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Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_qspi.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 0:9b334a45a8ff

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_qspi.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief QSPI HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the QuadSPI interface (QSPI).
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + Indirect functional mode management
<>	144:ef7eb2e8f9f7	12	* + Memory-mapped functional mode management
<>	144:ef7eb2e8f9f7	13	* + Auto-polling functional mode management
<>	144:ef7eb2e8f9f7	14	* + Interrupts and flags management
<>	144:ef7eb2e8f9f7	15	* + DMA channel configuration for indirect functional mode
<>	144:ef7eb2e8f9f7	16	* + Errors management and abort functionality
<>	144:ef7eb2e8f9f7	17	*
<>	144:ef7eb2e8f9f7	18	*
<>	144:ef7eb2e8f9f7	19	@verbatim
<>	144:ef7eb2e8f9f7	20	===============================================================================
<>	144:ef7eb2e8f9f7	21	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	22	===============================================================================
<>	144:ef7eb2e8f9f7	23	[..]
<>	144:ef7eb2e8f9f7	24	* Initialization *
<>	144:ef7eb2e8f9f7	25	======================
<>	144:ef7eb2e8f9f7	26	[..]
<>	144:ef7eb2e8f9f7	27	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
<>	144:ef7eb2e8f9f7	28	(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
<>	144:ef7eb2e8f9f7	29	(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
<>	144:ef7eb2e8f9f7	30	(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
<>	144:ef7eb2e8f9f7	31	(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
<>	144:ef7eb2e8f9f7	32	(++) If interrupt mode is used, enable and configure QuadSPI global
<>	144:ef7eb2e8f9f7	33	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<>	144:ef7eb2e8f9f7	34	(++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
<>	144:ef7eb2e8f9f7	35	with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
<>	144:ef7eb2e8f9f7	36	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
<>	144:ef7eb2e8f9f7	37	DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<>	144:ef7eb2e8f9f7	38	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
<>	144:ef7eb2e8f9f7	39	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
<>	144:ef7eb2e8f9f7	40
<>	144:ef7eb2e8f9f7	41	* Indirect functional mode *
<>	144:ef7eb2e8f9f7	42	================================
<>	144:ef7eb2e8f9f7	43	[..]
<>	144:ef7eb2e8f9f7	44	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
<>	144:ef7eb2e8f9f7	45	functions :
<>	144:ef7eb2e8f9f7	46	(++) Instruction phase : the mode used and if present the instruction opcode.
<>	144:ef7eb2e8f9f7	47	(++) Address phase : the mode used and if present the size and the address value.
<>	144:ef7eb2e8f9f7	48	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
<>	144:ef7eb2e8f9f7	49	bytes values.
<>	144:ef7eb2e8f9f7	50	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
<>	144:ef7eb2e8f9f7	51	(++) Data phase : the mode used and if present the number of bytes.
<>	144:ef7eb2e8f9f7	52	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
<>	144:ef7eb2e8f9f7	53	if activated.
<>	144:ef7eb2e8f9f7	54	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
<>	144:ef7eb2e8f9f7	55	(#) If no data is required for the command, it is sent directly to the memory :
<>	144:ef7eb2e8f9f7	56	(++) In polling mode, the output of the function is done when the transfer is complete.
<>	144:ef7eb2e8f9f7	57	(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	58	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
<>	144:ef7eb2e8f9f7	59	HAL_QSPI_Transmit_IT() after the command configuration :
<>	144:ef7eb2e8f9f7	60	(++) In polling mode, the output of the function is done when the transfer is complete.
<>	144:ef7eb2e8f9f7	61	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
<>	144:ef7eb2e8f9f7	62	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	63	(++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
<>	144:ef7eb2e8f9f7	64	HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	65	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
<>	144:ef7eb2e8f9f7	66	HAL_QSPI_Receive_IT() after the command configuration :
<>	144:ef7eb2e8f9f7	67	(++) In polling mode, the output of the function is done when the transfer is complete.
<>	144:ef7eb2e8f9f7	68	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
<>	144:ef7eb2e8f9f7	69	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	70	(++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
<>	144:ef7eb2e8f9f7	71	HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	* Auto-polling functional mode *
<>	144:ef7eb2e8f9f7	74	====================================
<>	144:ef7eb2e8f9f7	75	[..]
<>	144:ef7eb2e8f9f7	76	(#) Configure the command sequence and the auto-polling functional mode using the
<>	144:ef7eb2e8f9f7	77	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
<>	144:ef7eb2e8f9f7	78	(++) Instruction phase : the mode used and if present the instruction opcode.
<>	144:ef7eb2e8f9f7	79	(++) Address phase : the mode used and if present the size and the address value.
<>	144:ef7eb2e8f9f7	80	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
<>	144:ef7eb2e8f9f7	81	bytes values.
<>	144:ef7eb2e8f9f7	82	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
<>	144:ef7eb2e8f9f7	83	(++) Data phase : the mode used.
<>	144:ef7eb2e8f9f7	84	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
<>	144:ef7eb2e8f9f7	85	if activated.
<>	144:ef7eb2e8f9f7	86	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
<>	144:ef7eb2e8f9f7	87	(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
<>	144:ef7eb2e8f9f7	88	the polling interval and the automatic stop activation.
<>	144:ef7eb2e8f9f7	89	(#) After the configuration :
<>	144:ef7eb2e8f9f7	90	(++) In polling mode, the output of the function is done when the status match is reached. The
<>	144:ef7eb2e8f9f7	91	automatic stop is activated to avoid an infinite loop.
<>	144:ef7eb2e8f9f7	92	(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	* Memory-mapped functional mode *
<>	144:ef7eb2e8f9f7	95	=====================================
<>	144:ef7eb2e8f9f7	96	[..]
<>	144:ef7eb2e8f9f7	97	(#) Configure the command sequence and the memory-mapped functional mode using the
<>	144:ef7eb2e8f9f7	98	HAL_QSPI_MemoryMapped() functions :
<>	144:ef7eb2e8f9f7	99	(++) Instruction phase : the mode used and if present the instruction opcode.
<>	144:ef7eb2e8f9f7	100	(++) Address phase : the mode used and the size.
<>	144:ef7eb2e8f9f7	101	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
<>	144:ef7eb2e8f9f7	102	bytes values.
<>	144:ef7eb2e8f9f7	103	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
<>	144:ef7eb2e8f9f7	104	(++) Data phase : the mode used.
<>	144:ef7eb2e8f9f7	105	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
<>	144:ef7eb2e8f9f7	106	if activated.
<>	144:ef7eb2e8f9f7	107	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
<>	144:ef7eb2e8f9f7	108	(++) The timeout activation and the timeout period.
<>	144:ef7eb2e8f9f7	109	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
<>	144:ef7eb2e8f9f7	110	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
<>	144:ef7eb2e8f9f7	111
<>	144:ef7eb2e8f9f7	112	* Errors management and abort functionality *
<>	144:ef7eb2e8f9f7	113	=================================================
<>	144:ef7eb2e8f9f7	114	[..]
<>	144:ef7eb2e8f9f7	115	(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
<>	144:ef7eb2e8f9f7	116	(#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
<>	144:ef7eb2e8f9f7	117	flushes the fifo :
<>	144:ef7eb2e8f9f7	118	(++) In polling mode, the output of the function is done when the transfer
<>	144:ef7eb2e8f9f7	119	complete bit is set and the busy bit cleared.
<>	144:ef7eb2e8f9f7	120	(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
<>	144:ef7eb2e8f9f7	121	the transfer complete bi is set.
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	* Control functions *
<>	144:ef7eb2e8f9f7	124	=========================
<>	144:ef7eb2e8f9f7	125	[..]
<>	144:ef7eb2e8f9f7	126	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
<>	144:ef7eb2e8f9f7	127	(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
<>	144:ef7eb2e8f9f7	128	(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
<>	144:ef7eb2e8f9f7	129	(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	* Workarounds linked to Silicon Limitation *
<>	144:ef7eb2e8f9f7	132	====================================================
<>	144:ef7eb2e8f9f7	133	[..]
<>	144:ef7eb2e8f9f7	134	(#) Workarounds Implemented inside HAL Driver
<>	144:ef7eb2e8f9f7	135	(++) Extra data written in the FIFO at the end of a read transfer
<>	144:ef7eb2e8f9f7	136
<>	144:ef7eb2e8f9f7	137	@endverbatim
<>	144:ef7eb2e8f9f7	138	******************************************************************************
<>	144:ef7eb2e8f9f7	139	* @attention
<>	144:ef7eb2e8f9f7	140	*
<>	144:ef7eb2e8f9f7	141	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	142	*
<>	144:ef7eb2e8f9f7	143	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	144	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	145	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	146	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	147	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	148	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	149	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	150	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	151	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	152	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	153	*
<>	144:ef7eb2e8f9f7	154	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	155	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	156	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	157	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	158	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	159	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	160	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	161	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	162	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	163	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	164	*
<>	144:ef7eb2e8f9f7	165	******************************************************************************
<>	144:ef7eb2e8f9f7	166	*/
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	169	#include "stm32l4xx_hal.h"
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	172	* @{
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	/** @defgroup QSPI QSPI
<>	144:ef7eb2e8f9f7	176	* @brief QSPI HAL module driver
<>	144:ef7eb2e8f9f7	177	* @{
<>	144:ef7eb2e8f9f7	178	*/
<>	144:ef7eb2e8f9f7	179	#ifdef HAL_QSPI_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	184	/** @defgroup QSPI_Private_Constants QSPI Private Constants
<>	144:ef7eb2e8f9f7	185	* @{
<>	144:ef7eb2e8f9f7	186	*/
<>	144:ef7eb2e8f9f7	187	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /!<Indirect write mode/
<>	144:ef7eb2e8f9f7	188	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
<>	144:ef7eb2e8f9f7	189	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
<>	144:ef7eb2e8f9f7	190	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
<>	144:ef7eb2e8f9f7	191	/**
<>	144:ef7eb2e8f9f7	192	* @}
<>	144:ef7eb2e8f9f7	193	*/
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	196	/** @defgroup QSPI_Private_Macros QSPI Private Macros
<>	144:ef7eb2e8f9f7	197	* @{
<>	144:ef7eb2e8f9f7	198	*/
<>	144:ef7eb2e8f9f7	199	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
<>	144:ef7eb2e8f9f7	200	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
<>	144:ef7eb2e8f9f7	201	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
<>	144:ef7eb2e8f9f7	202	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
<>	144:ef7eb2e8f9f7	203	/**
<>	144:ef7eb2e8f9f7	204	* @}
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	208
<>	144:ef7eb2e8f9f7	209	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	210	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	211	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	212	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	213	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	214	static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	215	static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	216	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	217	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
<>	144:ef7eb2e8f9f7	218
<>	144:ef7eb2e8f9f7	219	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	220
<>	144:ef7eb2e8f9f7	221	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
<>	144:ef7eb2e8f9f7	222	* @{
<>	144:ef7eb2e8f9f7	223	*/
<>	144:ef7eb2e8f9f7	224
<>	144:ef7eb2e8f9f7	225	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
<>	144:ef7eb2e8f9f7	226	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	227	*
<>	144:ef7eb2e8f9f7	228	@verbatim
<>	144:ef7eb2e8f9f7	229	===============================================================================
<>	144:ef7eb2e8f9f7	230	##### Initialization and Configuration functions #####
<>	144:ef7eb2e8f9f7	231	===============================================================================
<>	144:ef7eb2e8f9f7	232	[..]
<>	144:ef7eb2e8f9f7	233	This subsection provides a set of functions allowing to :
<>	144:ef7eb2e8f9f7	234	(+) Initialize the QuadSPI.
<>	144:ef7eb2e8f9f7	235	(+) De-initialize the QuadSPI.
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	@endverbatim
<>	144:ef7eb2e8f9f7	238	* @{
<>	144:ef7eb2e8f9f7	239	*/
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	/**
<>	144:ef7eb2e8f9f7	242	* @brief Initialize the QSPI mode according to the specified parameters
<>	144:ef7eb2e8f9f7	243	* in the QSPI_InitTypeDef and initialize the associated handle.
<>	144:ef7eb2e8f9f7	244	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	245	* @retval HAL status
<>	144:ef7eb2e8f9f7	246	*/
<>	144:ef7eb2e8f9f7	247	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	248	{
<>	144:ef7eb2e8f9f7	249	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	250	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	251
<>	144:ef7eb2e8f9f7	252	/* Check the QSPI handle allocation */
<>	144:ef7eb2e8f9f7	253	if(hqspi == NULL)
<>	144:ef7eb2e8f9f7	254	{
<>	144:ef7eb2e8f9f7	255	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	256	}
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	/* Check the parameters */
<>	144:ef7eb2e8f9f7	259	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
<>	144:ef7eb2e8f9f7	260	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
<>	144:ef7eb2e8f9f7	261	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
<>	144:ef7eb2e8f9f7	262	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
<>	144:ef7eb2e8f9f7	263	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
<>	144:ef7eb2e8f9f7	264	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
<>	144:ef7eb2e8f9f7	265	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
<>	144:ef7eb2e8f9f7	266	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| defined(STM32L443xx)
<>	144:ef7eb2e8f9f7	267	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
<>	144:ef7eb2e8f9f7	268
<>	144:ef7eb2e8f9f7	269	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
<>	144:ef7eb2e8f9f7	270	{
<>	144:ef7eb2e8f9f7	271	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
<>	144:ef7eb2e8f9f7	272	}
<>	144:ef7eb2e8f9f7	273	#endif
<>	144:ef7eb2e8f9f7	274
<>	144:ef7eb2e8f9f7	275	/* Process locked */
<>	144:ef7eb2e8f9f7	276	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278	if(hqspi->State == HAL_QSPI_STATE_RESET)
<>	144:ef7eb2e8f9f7	279	{
<>	144:ef7eb2e8f9f7	280	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	281	hqspi->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283	/* Init the low level hardware : GPIO, CLOCK */
<>	144:ef7eb2e8f9f7	284	HAL_QSPI_MspInit(hqspi);
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/* Configure the default timeout for the QSPI memory access */
<>	144:ef7eb2e8f9f7	287	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
<>	144:ef7eb2e8f9f7	288	}
<>	144:ef7eb2e8f9f7	289
<>	144:ef7eb2e8f9f7	290	/* Configure QSPI FIFO Threshold */
<>	144:ef7eb2e8f9f7	291	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
<>	144:ef7eb2e8f9f7	292	((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	295	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297	if(status == HAL_OK)
<>	144:ef7eb2e8f9f7	298	{
<>	144:ef7eb2e8f9f7	299	/* Configure QSPI Clock Prescaler and Sample Shift */
<>	144:ef7eb2e8f9f7	300	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| defined(STM32L443xx)
<>	144:ef7eb2e8f9f7	301	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM),
<>	144:ef7eb2e8f9f7	302	((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) \|
<>	144:ef7eb2e8f9f7	303	hqspi->Init.SampleShifting \| hqspi->Init.FlashID \| hqspi->Init.DualFlash));
<>	144:ef7eb2e8f9f7	304	#else
<>	144:ef7eb2e8f9f7	305	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT),
<>	144:ef7eb2e8f9f7	306	((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) \|
<>	144:ef7eb2e8f9f7	307	hqspi->Init.SampleShifting));
<>	144:ef7eb2e8f9f7	308	#endif
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
<>	144:ef7eb2e8f9f7	311	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
<>	144:ef7eb2e8f9f7	312	((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) \|
<>	144:ef7eb2e8f9f7	313	hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
<>	144:ef7eb2e8f9f7	314
<>	144:ef7eb2e8f9f7	315	/* Enable the QSPI peripheral */
<>	144:ef7eb2e8f9f7	316	__HAL_QSPI_ENABLE(hqspi);
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/* Set QSPI error code to none */
<>	144:ef7eb2e8f9f7	319	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	/* Initialize the QSPI state */
<>	144:ef7eb2e8f9f7	322	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	323	}
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/* Release Lock */
<>	144:ef7eb2e8f9f7	326	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/* Return function status */
<>	144:ef7eb2e8f9f7	329	return status;
<>	144:ef7eb2e8f9f7	330	}
<>	144:ef7eb2e8f9f7	331
<>	144:ef7eb2e8f9f7	332	/**
<>	144:ef7eb2e8f9f7	333	* @brief De-Initialize the QSPI peripheral.
<>	144:ef7eb2e8f9f7	334	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	335	* @retval HAL status
<>	144:ef7eb2e8f9f7	336	*/
<>	144:ef7eb2e8f9f7	337	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	338	{
<>	144:ef7eb2e8f9f7	339	/* Check the QSPI handle allocation */
<>	144:ef7eb2e8f9f7	340	if(hqspi == NULL)
<>	144:ef7eb2e8f9f7	341	{
<>	144:ef7eb2e8f9f7	342	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	343	}
<>	144:ef7eb2e8f9f7	344
<>	144:ef7eb2e8f9f7	345	/* Process locked */
<>	144:ef7eb2e8f9f7	346	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/* Disable the QSPI Peripheral Clock */
<>	144:ef7eb2e8f9f7	349	__HAL_QSPI_DISABLE(hqspi);
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<>	144:ef7eb2e8f9f7	352	HAL_QSPI_MspDeInit(hqspi);
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	/* Set QSPI error code to none */
<>	144:ef7eb2e8f9f7	355	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/* Initialize the QSPI state */
<>	144:ef7eb2e8f9f7	358	hqspi->State = HAL_QSPI_STATE_RESET;
<>	144:ef7eb2e8f9f7	359
<>	144:ef7eb2e8f9f7	360	/* Release Lock */
<>	144:ef7eb2e8f9f7	361	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	362
<>	144:ef7eb2e8f9f7	363	return HAL_OK;
<>	144:ef7eb2e8f9f7	364	}
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/**
<>	144:ef7eb2e8f9f7	367	* @brief Initialize the QSPI MSP.
<>	144:ef7eb2e8f9f7	368	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	369	* @retval None
<>	144:ef7eb2e8f9f7	370	*/
<>	144:ef7eb2e8f9f7	371	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	372	{
<>	144:ef7eb2e8f9f7	373	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	374	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	377	the HAL_QSPI_MspInit can be implemented in the user file
<>	144:ef7eb2e8f9f7	378	*/
<>	144:ef7eb2e8f9f7	379	}
<>	144:ef7eb2e8f9f7	380
<>	144:ef7eb2e8f9f7	381	/**
<>	144:ef7eb2e8f9f7	382	* @brief DeInitialize the QSPI MSP.
<>	144:ef7eb2e8f9f7	383	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	384	* @retval None
<>	144:ef7eb2e8f9f7	385	*/
<>	144:ef7eb2e8f9f7	386	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	387	{
<>	144:ef7eb2e8f9f7	388	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	389	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	392	the HAL_QSPI_MspDeInit can be implemented in the user file
<>	144:ef7eb2e8f9f7	393	*/
<>	144:ef7eb2e8f9f7	394	}
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/**
<>	144:ef7eb2e8f9f7	397	* @}
<>	144:ef7eb2e8f9f7	398	*/
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
<>	144:ef7eb2e8f9f7	401	* @brief QSPI Transmit/Receive functions
<>	144:ef7eb2e8f9f7	402	*
<>	144:ef7eb2e8f9f7	403	@verbatim
<>	144:ef7eb2e8f9f7	404	===============================================================================
<>	144:ef7eb2e8f9f7	405	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	406	===============================================================================
<>	144:ef7eb2e8f9f7	407	[..]
<>	144:ef7eb2e8f9f7	408	This subsection provides a set of functions allowing to :
<>	144:ef7eb2e8f9f7	409	(+) Handle the interrupts.
<>	144:ef7eb2e8f9f7	410	(+) Handle the command sequence.
<>	144:ef7eb2e8f9f7	411	(+) Transmit data in blocking, interrupt or DMA mode.
<>	144:ef7eb2e8f9f7	412	(+) Receive data in blocking, interrupt or DMA mode.
<>	144:ef7eb2e8f9f7	413	(+) Manage the auto-polling functional mode.
<>	144:ef7eb2e8f9f7	414	(+) Manage the memory-mapped functional mode.
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	@endverbatim
<>	144:ef7eb2e8f9f7	417	* @{
<>	144:ef7eb2e8f9f7	418	*/
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	/**
<>	144:ef7eb2e8f9f7	421	* @brief Handle QSPI interrupt request.
<>	144:ef7eb2e8f9f7	422	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	423	* @retval None
<>	144:ef7eb2e8f9f7	424	*/
<>	144:ef7eb2e8f9f7	425	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	426	{
<>	144:ef7eb2e8f9f7	427	__IO uint32_t *data_reg;
<>	144:ef7eb2e8f9f7	428	uint32_t flag = READ_REG(hqspi->Instance->SR);
<>	144:ef7eb2e8f9f7	429	uint32_t itsource = READ_REG(hqspi->Instance->CR);
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
<>	144:ef7eb2e8f9f7	432	if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT))
<>	144:ef7eb2e8f9f7	433	{
<>	144:ef7eb2e8f9f7	434	data_reg = &hqspi->Instance->DR;
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
<>	144:ef7eb2e8f9f7	437	{
<>	144:ef7eb2e8f9f7	438	/* Transmission process */
<>	144:ef7eb2e8f9f7	439	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
<>	144:ef7eb2e8f9f7	440	{
<>	144:ef7eb2e8f9f7	441	if (hqspi->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	442	{
<>	144:ef7eb2e8f9f7	443	/* Fill the FIFO until the threshold is reached */
<>	144:ef7eb2e8f9f7	444	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
<>	144:ef7eb2e8f9f7	445	hqspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	446	}
<>	144:ef7eb2e8f9f7	447	else
<>	144:ef7eb2e8f9f7	448	{
<>	144:ef7eb2e8f9f7	449	/* No more data available for the transfer */
<>	144:ef7eb2e8f9f7	450	/* Disable the QSPI FIFO Threshold Interrupt */
<>	144:ef7eb2e8f9f7	451	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
<>	144:ef7eb2e8f9f7	452	break;
<>	144:ef7eb2e8f9f7	453	}
<>	144:ef7eb2e8f9f7	454	}
<>	144:ef7eb2e8f9f7	455	}
<>	144:ef7eb2e8f9f7	456	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
<>	144:ef7eb2e8f9f7	457	{
<>	144:ef7eb2e8f9f7	458	/* Receiving Process */
<>	144:ef7eb2e8f9f7	459	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
<>	144:ef7eb2e8f9f7	460	{
<>	144:ef7eb2e8f9f7	461	if (hqspi->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	462	{
<>	144:ef7eb2e8f9f7	463	/* Read the FIFO until the threshold is reached */
<>	144:ef7eb2e8f9f7	464	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
<>	144:ef7eb2e8f9f7	465	hqspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	466	}
<>	144:ef7eb2e8f9f7	467	else
<>	144:ef7eb2e8f9f7	468	{
<>	144:ef7eb2e8f9f7	469	/* All data have been received for the transfer */
<>	144:ef7eb2e8f9f7	470	/* Disable the QSPI FIFO Threshold Interrupt */
<>	144:ef7eb2e8f9f7	471	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
<>	144:ef7eb2e8f9f7	472	break;
<>	144:ef7eb2e8f9f7	473	}
<>	144:ef7eb2e8f9f7	474	}
<>	144:ef7eb2e8f9f7	475	}
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	/* FIFO Threshold callback */
<>	144:ef7eb2e8f9f7	478	HAL_QSPI_FifoThresholdCallback(hqspi);
<>	144:ef7eb2e8f9f7	479	}
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
<>	144:ef7eb2e8f9f7	482	else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC))
<>	144:ef7eb2e8f9f7	483	{
<>	144:ef7eb2e8f9f7	484	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	485	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	486
<>	144:ef7eb2e8f9f7	487	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
<>	144:ef7eb2e8f9f7	488	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
<>	144:ef7eb2e8f9f7	489
<>	144:ef7eb2e8f9f7	490	/* Transfer complete callback */
<>	144:ef7eb2e8f9f7	491	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
<>	144:ef7eb2e8f9f7	492	{
<>	144:ef7eb2e8f9f7	493	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
<>	144:ef7eb2e8f9f7	494	{
<>	144:ef7eb2e8f9f7	495	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	496	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/* Disable the DMA channel */
<>	144:ef7eb2e8f9f7	499	__HAL_DMA_DISABLE(hqspi->hdma);
<>	144:ef7eb2e8f9f7	500	}
<>	144:ef7eb2e8f9f7	501
<>	144:ef7eb2e8f9f7	502	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
<>	144:ef7eb2e8f9f7	503	/* Clear Busy bit */
<>	144:ef7eb2e8f9f7	504	HAL_QSPI_Abort_IT(hqspi);
<>	144:ef7eb2e8f9f7	505	#endif
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	508	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	509
<>	144:ef7eb2e8f9f7	510	/* TX Complete callback */
<>	144:ef7eb2e8f9f7	511	HAL_QSPI_TxCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	512	}
<>	144:ef7eb2e8f9f7	513	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
<>	144:ef7eb2e8f9f7	514	{
<>	144:ef7eb2e8f9f7	515	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
<>	144:ef7eb2e8f9f7	516	{
<>	144:ef7eb2e8f9f7	517	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	518	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	519
<>	144:ef7eb2e8f9f7	520	/* Disable the DMA channel */
<>	144:ef7eb2e8f9f7	521	__HAL_DMA_DISABLE(hqspi->hdma);
<>	144:ef7eb2e8f9f7	522	}
<>	144:ef7eb2e8f9f7	523	else
<>	144:ef7eb2e8f9f7	524	{
<>	144:ef7eb2e8f9f7	525	data_reg = &hqspi->Instance->DR;
<>	144:ef7eb2e8f9f7	526	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
<>	144:ef7eb2e8f9f7	527	{
<>	144:ef7eb2e8f9f7	528	if (hqspi->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	529	{
<>	144:ef7eb2e8f9f7	530	/* Read the last data received in the FIFO until it is empty */
<>	144:ef7eb2e8f9f7	531	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
<>	144:ef7eb2e8f9f7	532	hqspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	533	}
<>	144:ef7eb2e8f9f7	534	else
<>	144:ef7eb2e8f9f7	535	{
<>	144:ef7eb2e8f9f7	536	/* All data have been received for the transfer */
<>	144:ef7eb2e8f9f7	537	break;
<>	144:ef7eb2e8f9f7	538	}
<>	144:ef7eb2e8f9f7	539	}
<>	144:ef7eb2e8f9f7	540	}
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
<>	144:ef7eb2e8f9f7	543	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
<>	144:ef7eb2e8f9f7	544	HAL_QSPI_Abort_IT(hqspi);
<>	144:ef7eb2e8f9f7	545	#endif
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	548	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	/* RX Complete callback */
<>	144:ef7eb2e8f9f7	551	HAL_QSPI_RxCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	552	}
<>	144:ef7eb2e8f9f7	553	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
<>	144:ef7eb2e8f9f7	554	{
<>	144:ef7eb2e8f9f7	555	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	556	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	/* Command Complete callback */
<>	144:ef7eb2e8f9f7	559	HAL_QSPI_CmdCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	560	}
<>	144:ef7eb2e8f9f7	561	else if(hqspi->State == HAL_QSPI_STATE_ABORT)
<>	144:ef7eb2e8f9f7	562	{
<>	144:ef7eb2e8f9f7	563	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	564	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	567	{
<>	144:ef7eb2e8f9f7	568	/* Abort called by the user */
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	/* Abort Complete callback */
<>	144:ef7eb2e8f9f7	571	HAL_QSPI_AbortCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	572	}
<>	144:ef7eb2e8f9f7	573	else
<>	144:ef7eb2e8f9f7	574	{
<>	144:ef7eb2e8f9f7	575	/* Abort due to an error (eg : DMA error) */
<>	144:ef7eb2e8f9f7	576
<>	144:ef7eb2e8f9f7	577	/* Error callback */
<>	144:ef7eb2e8f9f7	578	HAL_QSPI_ErrorCallback(hqspi);
<>	144:ef7eb2e8f9f7	579	}
<>	144:ef7eb2e8f9f7	580	}
<>	144:ef7eb2e8f9f7	581	}
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	/* QSPI Status Match interrupt occurred ------------------------------------*/
<>	144:ef7eb2e8f9f7	584	else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM))
<>	144:ef7eb2e8f9f7	585	{
<>	144:ef7eb2e8f9f7	586	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	587	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/* Check if the automatic poll mode stop is activated */
<>	144:ef7eb2e8f9f7	590	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
<>	144:ef7eb2e8f9f7	591	{
<>	144:ef7eb2e8f9f7	592	/* Disable the QSPI Transfer Error and Status Match Interrupts */
<>	144:ef7eb2e8f9f7	593	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	596	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	597	}
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/* Status match callback */
<>	144:ef7eb2e8f9f7	600	HAL_QSPI_StatusMatchCallback(hqspi);
<>	144:ef7eb2e8f9f7	601	}
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
<>	144:ef7eb2e8f9f7	604	else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE))
<>	144:ef7eb2e8f9f7	605	{
<>	144:ef7eb2e8f9f7	606	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	607	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
<>	144:ef7eb2e8f9f7	608
<>	144:ef7eb2e8f9f7	609	/* Disable all the QSPI Interrupts */
<>	144:ef7eb2e8f9f7	610	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/* Set error code */
<>	144:ef7eb2e8f9f7	613	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
<>	144:ef7eb2e8f9f7	614
<>	144:ef7eb2e8f9f7	615	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
<>	144:ef7eb2e8f9f7	616	{
<>	144:ef7eb2e8f9f7	617	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	618	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620	/* Disable the DMA channel */
<>	144:ef7eb2e8f9f7	621	hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
<>	144:ef7eb2e8f9f7	622	HAL_DMA_Abort_IT(hqspi->hdma);
<>	144:ef7eb2e8f9f7	623	}
<>	144:ef7eb2e8f9f7	624	else
<>	144:ef7eb2e8f9f7	625	{
<>	144:ef7eb2e8f9f7	626	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	627	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	628
<>	144:ef7eb2e8f9f7	629	/* Error callback */
<>	144:ef7eb2e8f9f7	630	HAL_QSPI_ErrorCallback(hqspi);
<>	144:ef7eb2e8f9f7	631	}
<>	144:ef7eb2e8f9f7	632	}
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	/* QSPI Timeout interrupt occurred -----------------------------------------*/
<>	144:ef7eb2e8f9f7	635	else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO))
<>	144:ef7eb2e8f9f7	636	{
<>	144:ef7eb2e8f9f7	637	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	638	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640	/* Timeout callback */
<>	144:ef7eb2e8f9f7	641	HAL_QSPI_TimeOutCallback(hqspi);
<>	144:ef7eb2e8f9f7	642	}
<>	144:ef7eb2e8f9f7	643	}
<>	144:ef7eb2e8f9f7	644
<>	144:ef7eb2e8f9f7	645	/**
<>	144:ef7eb2e8f9f7	646	* @brief Set the command configuration.
<>	144:ef7eb2e8f9f7	647	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	648	* @param cmd : structure that contains the command configuration information
<>	144:ef7eb2e8f9f7	649	* @param Timeout : Timeout duration
<>	144:ef7eb2e8f9f7	650	* @note This function is used only in Indirect Read or Write Modes
<>	144:ef7eb2e8f9f7	651	* @retval HAL status
<>	144:ef7eb2e8f9f7	652	*/
<>	144:ef7eb2e8f9f7	653	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	654	{
<>	144:ef7eb2e8f9f7	655	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	656	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	657
<>	144:ef7eb2e8f9f7	658	/* Check the parameters */
<>	144:ef7eb2e8f9f7	659	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	660	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	661	{
<>	144:ef7eb2e8f9f7	662	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	663	}
<>	144:ef7eb2e8f9f7	664
<>	144:ef7eb2e8f9f7	665	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	666	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	667	{
<>	144:ef7eb2e8f9f7	668	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	669	}
<>	144:ef7eb2e8f9f7	670
<>	144:ef7eb2e8f9f7	671	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	672	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	673	{
<>	144:ef7eb2e8f9f7	674	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	675	}
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	678	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	681	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	682	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	/* Process locked */
<>	144:ef7eb2e8f9f7	685	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	686
<>	144:ef7eb2e8f9f7	687	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	688	{
<>	144:ef7eb2e8f9f7	689	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	692	hqspi->State = HAL_QSPI_STATE_BUSY;
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	695	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	696
<>	144:ef7eb2e8f9f7	697	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	698	{
<>	144:ef7eb2e8f9f7	699	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	700	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702	if (cmd->DataMode == QSPI_DATA_NONE)
<>	144:ef7eb2e8f9f7	703	{
<>	144:ef7eb2e8f9f7	704	/* When there is no data phase, the transfer start as soon as the configuration is done
<>	144:ef7eb2e8f9f7	705	so wait until TC flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	706	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	707
<>	144:ef7eb2e8f9f7	708	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	709	{
<>	144:ef7eb2e8f9f7	710	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	711
<>	144:ef7eb2e8f9f7	712	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	713	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	714	}
<>	144:ef7eb2e8f9f7	715	}
<>	144:ef7eb2e8f9f7	716	else
<>	144:ef7eb2e8f9f7	717	{
<>	144:ef7eb2e8f9f7	718	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	719	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	720	}
<>	144:ef7eb2e8f9f7	721	}
<>	144:ef7eb2e8f9f7	722	}
<>	144:ef7eb2e8f9f7	723	else
<>	144:ef7eb2e8f9f7	724	{
<>	144:ef7eb2e8f9f7	725	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	726	}
<>	144:ef7eb2e8f9f7	727
<>	144:ef7eb2e8f9f7	728	/* Process unlocked */
<>	144:ef7eb2e8f9f7	729	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	/* Return function status */
<>	144:ef7eb2e8f9f7	732	return status;
<>	144:ef7eb2e8f9f7	733	}
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	/**
<>	144:ef7eb2e8f9f7	736	* @brief Set the command configuration in interrupt mode.
<>	144:ef7eb2e8f9f7	737	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	738	* @param cmd : structure that contains the command configuration information
<>	144:ef7eb2e8f9f7	739	* @note This function is used only in Indirect Read or Write Modes
<>	144:ef7eb2e8f9f7	740	* @retval HAL status
<>	144:ef7eb2e8f9f7	741	*/
<>	144:ef7eb2e8f9f7	742	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
<>	144:ef7eb2e8f9f7	743	{
<>	144:ef7eb2e8f9f7	744	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	745	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	/* Check the parameters */
<>	144:ef7eb2e8f9f7	748	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	749	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	750	{
<>	144:ef7eb2e8f9f7	751	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	752	}
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	755	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	756	{
<>	144:ef7eb2e8f9f7	757	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	758	}
<>	144:ef7eb2e8f9f7	759
<>	144:ef7eb2e8f9f7	760	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	761	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	762	{
<>	144:ef7eb2e8f9f7	763	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	764	}
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	767	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	768
<>	144:ef7eb2e8f9f7	769	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	770	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	771	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	772
<>	144:ef7eb2e8f9f7	773	/* Process locked */
<>	144:ef7eb2e8f9f7	774	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	775
<>	144:ef7eb2e8f9f7	776	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	777	{
<>	144:ef7eb2e8f9f7	778	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	781	hqspi->State = HAL_QSPI_STATE_BUSY;
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	784	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	787	{
<>	144:ef7eb2e8f9f7	788	if (cmd->DataMode == QSPI_DATA_NONE)
<>	144:ef7eb2e8f9f7	789	{
<>	144:ef7eb2e8f9f7	790	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	791	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	792	}
<>	144:ef7eb2e8f9f7	793
<>	144:ef7eb2e8f9f7	794	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	795	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	796
<>	144:ef7eb2e8f9f7	797	if (cmd->DataMode == QSPI_DATA_NONE)
<>	144:ef7eb2e8f9f7	798	{
<>	144:ef7eb2e8f9f7	799	/* When there is no data phase, the transfer start as soon as the configuration is done
<>	144:ef7eb2e8f9f7	800	so activate TC and TE interrupts */
<>	144:ef7eb2e8f9f7	801	/* Process unlocked */
<>	144:ef7eb2e8f9f7	802	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	803
<>	144:ef7eb2e8f9f7	804	/* Enable the QSPI Transfer Error Interrupt */
<>	144:ef7eb2e8f9f7	805	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	806	}
<>	144:ef7eb2e8f9f7	807	else
<>	144:ef7eb2e8f9f7	808	{
<>	144:ef7eb2e8f9f7	809	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	810	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/* Process unlocked */
<>	144:ef7eb2e8f9f7	813	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815	}
<>	144:ef7eb2e8f9f7	816	else
<>	144:ef7eb2e8f9f7	817	{
<>	144:ef7eb2e8f9f7	818	/* Process unlocked */
<>	144:ef7eb2e8f9f7	819	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	820	}
<>	144:ef7eb2e8f9f7	821	}
<>	144:ef7eb2e8f9f7	822	else
<>	144:ef7eb2e8f9f7	823	{
<>	144:ef7eb2e8f9f7	824	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	825
<>	144:ef7eb2e8f9f7	826	/* Process unlocked */
<>	144:ef7eb2e8f9f7	827	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	828	}
<>	144:ef7eb2e8f9f7	829
<>	144:ef7eb2e8f9f7	830	/* Return function status */
<>	144:ef7eb2e8f9f7	831	return status;
<>	144:ef7eb2e8f9f7	832	}
<>	144:ef7eb2e8f9f7	833
<>	144:ef7eb2e8f9f7	834	/**
<>	144:ef7eb2e8f9f7	835	* @brief Transmit an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	836	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	837	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	838	* @param Timeout : Timeout duration
<>	144:ef7eb2e8f9f7	839	* @note This function is used only in Indirect Write Mode
<>	144:ef7eb2e8f9f7	840	* @retval HAL status
<>	144:ef7eb2e8f9f7	841	*/
<>	144:ef7eb2e8f9f7	842	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	843	{
<>	144:ef7eb2e8f9f7	844	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	845	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	846	__IO uint32_t *data_reg = &hqspi->Instance->DR;
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848	/* Process locked */
<>	144:ef7eb2e8f9f7	849	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	850
<>	144:ef7eb2e8f9f7	851	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	852	{
<>	144:ef7eb2e8f9f7	853	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	if(pData != NULL )
<>	144:ef7eb2e8f9f7	856	{
<>	144:ef7eb2e8f9f7	857	/* Update state */
<>	144:ef7eb2e8f9f7	858	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/* Configure counters and size of the handle */
<>	144:ef7eb2e8f9f7	861	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	862	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	863	hqspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	864
<>	144:ef7eb2e8f9f7	865	/* Configure QSPI: CCR register with functional as indirect write */
<>	144:ef7eb2e8f9f7	866	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	while(hqspi->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	869	{
<>	144:ef7eb2e8f9f7	870	/* Wait until FT flag is set to send data */
<>	144:ef7eb2e8f9f7	871	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	872
<>	144:ef7eb2e8f9f7	873	if (status != HAL_OK)
<>	144:ef7eb2e8f9f7	874	{
<>	144:ef7eb2e8f9f7	875	break;
<>	144:ef7eb2e8f9f7	876	}
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
<>	144:ef7eb2e8f9f7	879	hqspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	880	}
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	883	{
<>	144:ef7eb2e8f9f7	884	/* Wait until TC flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	885	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	888	{
<>	144:ef7eb2e8f9f7	889	/* Clear Transfer Complete bit */
<>	144:ef7eb2e8f9f7	890	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
<>	144:ef7eb2e8f9f7	893	/* Clear Busy bit */
<>	144:ef7eb2e8f9f7	894	status = HAL_QSPI_Abort(hqspi);
<>	144:ef7eb2e8f9f7	895	#endif
<>	144:ef7eb2e8f9f7	896	}
<>	144:ef7eb2e8f9f7	897	}
<>	144:ef7eb2e8f9f7	898
<>	144:ef7eb2e8f9f7	899	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	900	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	901	}
<>	144:ef7eb2e8f9f7	902	else
<>	144:ef7eb2e8f9f7	903	{
<>	144:ef7eb2e8f9f7	904	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	905	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	906	}
<>	144:ef7eb2e8f9f7	907	}
<>	144:ef7eb2e8f9f7	908	else
<>	144:ef7eb2e8f9f7	909	{
<>	144:ef7eb2e8f9f7	910	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	911	}
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	/* Process unlocked */
<>	144:ef7eb2e8f9f7	914	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	return status;
<>	144:ef7eb2e8f9f7	917	}
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	/**
<>	144:ef7eb2e8f9f7	921	* @brief Receive an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	922	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	923	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	924	* @param Timeout : Timeout duration
<>	144:ef7eb2e8f9f7	925	* @note This function is used only in Indirect Read Mode
<>	144:ef7eb2e8f9f7	926	* @retval HAL status
<>	144:ef7eb2e8f9f7	927	*/
<>	144:ef7eb2e8f9f7	928	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	929	{
<>	144:ef7eb2e8f9f7	930	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	931	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	932	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
<>	144:ef7eb2e8f9f7	933	__IO uint32_t *data_reg = &hqspi->Instance->DR;
<>	144:ef7eb2e8f9f7	934
<>	144:ef7eb2e8f9f7	935	/* Process locked */
<>	144:ef7eb2e8f9f7	936	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	937
<>	144:ef7eb2e8f9f7	938	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	939	{
<>	144:ef7eb2e8f9f7	940	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	941
<>	144:ef7eb2e8f9f7	942	if(pData != NULL )
<>	144:ef7eb2e8f9f7	943	{
<>	144:ef7eb2e8f9f7	944	/* Update state */
<>	144:ef7eb2e8f9f7	945	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/* Configure counters and size of the handle */
<>	144:ef7eb2e8f9f7	948	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	949	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	950	hqspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	951
<>	144:ef7eb2e8f9f7	952	/* Configure QSPI: CCR register with functional as indirect read */
<>	144:ef7eb2e8f9f7	953	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
<>	144:ef7eb2e8f9f7	954
<>	144:ef7eb2e8f9f7	955	/* Start the transfer by re-writing the address in AR register */
<>	144:ef7eb2e8f9f7	956	WRITE_REG(hqspi->Instance->AR, addr_reg);
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	while(hqspi->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	959	{
<>	144:ef7eb2e8f9f7	960	/* Wait until FT or TC flag is set to read received data */
<>	144:ef7eb2e8f9f7	961	status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	if (status != HAL_OK)
<>	144:ef7eb2e8f9f7	964	{
<>	144:ef7eb2e8f9f7	965	break;
<>	144:ef7eb2e8f9f7	966	}
<>	144:ef7eb2e8f9f7	967
<>	144:ef7eb2e8f9f7	968	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
<>	144:ef7eb2e8f9f7	969	hqspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	970	}
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	973	{
<>	144:ef7eb2e8f9f7	974	/* Wait until TC flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	975	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	976
<>	144:ef7eb2e8f9f7	977	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	978	{
<>	144:ef7eb2e8f9f7	979	/* Clear Transfer Complete bit */
<>	144:ef7eb2e8f9f7	980	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
<>	144:ef7eb2e8f9f7	983	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
<>	144:ef7eb2e8f9f7	984	status = HAL_QSPI_Abort(hqspi);
<>	144:ef7eb2e8f9f7	985	#endif
<>	144:ef7eb2e8f9f7	986	}
<>	144:ef7eb2e8f9f7	987	}
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	990	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	991	}
<>	144:ef7eb2e8f9f7	992	else
<>	144:ef7eb2e8f9f7	993	{
<>	144:ef7eb2e8f9f7	994	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	995	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	996	}
<>	144:ef7eb2e8f9f7	997	}
<>	144:ef7eb2e8f9f7	998	else
<>	144:ef7eb2e8f9f7	999	{
<>	144:ef7eb2e8f9f7	1000	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1001	}
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1004	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	return status;
<>	144:ef7eb2e8f9f7	1007	}
<>	144:ef7eb2e8f9f7	1008
<>	144:ef7eb2e8f9f7	1009	/**
<>	144:ef7eb2e8f9f7	1010	* @brief Send an amount of data in non-blocking mode with interrupt.
<>	144:ef7eb2e8f9f7	1011	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1012	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1013	* @note This function is used only in Indirect Write Mode
<>	144:ef7eb2e8f9f7	1014	* @retval HAL status
<>	144:ef7eb2e8f9f7	1015	*/
<>	144:ef7eb2e8f9f7	1016	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
<>	144:ef7eb2e8f9f7	1017	{
<>	144:ef7eb2e8f9f7	1018	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/* Process locked */
<>	144:ef7eb2e8f9f7	1021	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1024	{
<>	144:ef7eb2e8f9f7	1025	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1026
<>	144:ef7eb2e8f9f7	1027	if(pData != NULL )
<>	144:ef7eb2e8f9f7	1028	{
<>	144:ef7eb2e8f9f7	1029	/* Update state */
<>	144:ef7eb2e8f9f7	1030	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/* Configure counters and size of the handle */
<>	144:ef7eb2e8f9f7	1033	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	1034	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	1035	hqspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/* Configure QSPI: CCR register with functional as indirect write */
<>	144:ef7eb2e8f9f7	1038	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	1039
<>	144:ef7eb2e8f9f7	1040	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1041	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	1042
<>	144:ef7eb2e8f9f7	1043	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1044	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1045
<>	144:ef7eb2e8f9f7	1046	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
<>	144:ef7eb2e8f9f7	1047	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	1048	}
<>	144:ef7eb2e8f9f7	1049	else
<>	144:ef7eb2e8f9f7	1050	{
<>	144:ef7eb2e8f9f7	1051	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1052	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1053
<>	144:ef7eb2e8f9f7	1054	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1055	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1056	}
<>	144:ef7eb2e8f9f7	1057	}
<>	144:ef7eb2e8f9f7	1058	else
<>	144:ef7eb2e8f9f7	1059	{
<>	144:ef7eb2e8f9f7	1060	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1061
<>	144:ef7eb2e8f9f7	1062	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1063	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1064	}
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	return status;
<>	144:ef7eb2e8f9f7	1067	}
<>	144:ef7eb2e8f9f7	1068
<>	144:ef7eb2e8f9f7	1069	/**
<>	144:ef7eb2e8f9f7	1070	* @brief Receive an amount of data in non-blocking mode with interrupt.
<>	144:ef7eb2e8f9f7	1071	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1072	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1073	* @note This function is used only in Indirect Read Mode
<>	144:ef7eb2e8f9f7	1074	* @retval HAL status
<>	144:ef7eb2e8f9f7	1075	*/
<>	144:ef7eb2e8f9f7	1076	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
<>	144:ef7eb2e8f9f7	1077	{
<>	144:ef7eb2e8f9f7	1078	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1079	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
<>	144:ef7eb2e8f9f7	1080
<>	144:ef7eb2e8f9f7	1081	/* Process locked */
<>	144:ef7eb2e8f9f7	1082	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1083
<>	144:ef7eb2e8f9f7	1084	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1085	{
<>	144:ef7eb2e8f9f7	1086	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1087
<>	144:ef7eb2e8f9f7	1088	if(pData != NULL )
<>	144:ef7eb2e8f9f7	1089	{
<>	144:ef7eb2e8f9f7	1090	/* Update state */
<>	144:ef7eb2e8f9f7	1091	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
<>	144:ef7eb2e8f9f7	1092
<>	144:ef7eb2e8f9f7	1093	/* Configure counters and size of the handle */
<>	144:ef7eb2e8f9f7	1094	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	1095	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	1096	hqspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1097
<>	144:ef7eb2e8f9f7	1098	/* Configure QSPI: CCR register with functional as indirect read */
<>	144:ef7eb2e8f9f7	1099	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
<>	144:ef7eb2e8f9f7	1100
<>	144:ef7eb2e8f9f7	1101	/* Start the transfer by re-writing the address in AR register */
<>	144:ef7eb2e8f9f7	1102	WRITE_REG(hqspi->Instance->AR, addr_reg);
<>	144:ef7eb2e8f9f7	1103
<>	144:ef7eb2e8f9f7	1104	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1105	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	1106
<>	144:ef7eb2e8f9f7	1107	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1108	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1109
<>	144:ef7eb2e8f9f7	1110	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
<>	144:ef7eb2e8f9f7	1111	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	1112	}
<>	144:ef7eb2e8f9f7	1113	else
<>	144:ef7eb2e8f9f7	1114	{
<>	144:ef7eb2e8f9f7	1115	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1116	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1117
<>	144:ef7eb2e8f9f7	1118	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1119	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1120	}
<>	144:ef7eb2e8f9f7	1121	}
<>	144:ef7eb2e8f9f7	1122	else
<>	144:ef7eb2e8f9f7	1123	{
<>	144:ef7eb2e8f9f7	1124	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1127	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1128	}
<>	144:ef7eb2e8f9f7	1129
<>	144:ef7eb2e8f9f7	1130	return status;
<>	144:ef7eb2e8f9f7	1131	}
<>	144:ef7eb2e8f9f7	1132
<>	144:ef7eb2e8f9f7	1133	/**
<>	144:ef7eb2e8f9f7	1134	* @brief Send an amount of data in non-blocking mode with DMA.
<>	144:ef7eb2e8f9f7	1135	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1136	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1137	* @note This function is used only in Indirect Write Mode
<>	144:ef7eb2e8f9f7	1138	* @note If DMA peripheral access is configured as halfword, the number
<>	144:ef7eb2e8f9f7	1139	* of data and the fifo threshold should be aligned on halfword
<>	144:ef7eb2e8f9f7	1140	* @note If DMA peripheral access is configured as word, the number
<>	144:ef7eb2e8f9f7	1141	* of data and the fifo threshold should be aligned on word
<>	144:ef7eb2e8f9f7	1142	* @retval HAL status
<>	144:ef7eb2e8f9f7	1143	*/
<>	144:ef7eb2e8f9f7	1144	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
<>	144:ef7eb2e8f9f7	1145	{
<>	144:ef7eb2e8f9f7	1146	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1147	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	1148	uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	/* Process locked */
<>	144:ef7eb2e8f9f7	1151	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1152
<>	144:ef7eb2e8f9f7	1153	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1154	{
<>	144:ef7eb2e8f9f7	1155	/* Clear the error code */
<>	144:ef7eb2e8f9f7	1156	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	if(pData != NULL )
<>	144:ef7eb2e8f9f7	1159	{
<>	144:ef7eb2e8f9f7	1160	/* Configure counters of the handle */
<>	144:ef7eb2e8f9f7	1161	if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
<>	144:ef7eb2e8f9f7	1162	{
<>	144:ef7eb2e8f9f7	1163	hqspi->TxXferCount = data_size;
<>	144:ef7eb2e8f9f7	1164	}
<>	144:ef7eb2e8f9f7	1165	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
<>	144:ef7eb2e8f9f7	1166	{
<>	144:ef7eb2e8f9f7	1167	if (((data_size % 2) != 0) \|\| ((hqspi->Init.FifoThreshold % 2) != 0))
<>	144:ef7eb2e8f9f7	1168	{
<>	144:ef7eb2e8f9f7	1169	/* The number of data or the fifo threshold is not aligned on halfword
<>	144:ef7eb2e8f9f7	1170	=> no transfer possible with DMA peripheral access configured as halfword */
<>	144:ef7eb2e8f9f7	1171	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1172	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1173
<>	144:ef7eb2e8f9f7	1174	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1175	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1176	}
<>	144:ef7eb2e8f9f7	1177	else
<>	144:ef7eb2e8f9f7	1178	{
<>	144:ef7eb2e8f9f7	1179	hqspi->TxXferCount = (data_size >> 1);
<>	144:ef7eb2e8f9f7	1180	}
<>	144:ef7eb2e8f9f7	1181	}
<>	144:ef7eb2e8f9f7	1182	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
<>	144:ef7eb2e8f9f7	1183	{
<>	144:ef7eb2e8f9f7	1184	if (((data_size % 4) != 0) \|\| ((hqspi->Init.FifoThreshold % 4) != 0))
<>	144:ef7eb2e8f9f7	1185	{
<>	144:ef7eb2e8f9f7	1186	/* The number of data or the fifo threshold is not aligned on word
<>	144:ef7eb2e8f9f7	1187	=> no transfer possible with DMA peripheral access configured as word */
<>	144:ef7eb2e8f9f7	1188	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1189	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1192	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1193	}
<>	144:ef7eb2e8f9f7	1194	else
<>	144:ef7eb2e8f9f7	1195	{
<>	144:ef7eb2e8f9f7	1196	hqspi->TxXferCount = (data_size >> 2);
<>	144:ef7eb2e8f9f7	1197	}
<>	144:ef7eb2e8f9f7	1198	}
<>	144:ef7eb2e8f9f7	1199
<>	144:ef7eb2e8f9f7	1200	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1201	{
<>	144:ef7eb2e8f9f7	1202	/* Update state */
<>	144:ef7eb2e8f9f7	1203	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1206	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
<>	144:ef7eb2e8f9f7	1207
<>	144:ef7eb2e8f9f7	1208	/* Configure size and pointer of the handle */
<>	144:ef7eb2e8f9f7	1209	hqspi->TxXferSize = hqspi->TxXferCount;
<>	144:ef7eb2e8f9f7	1210	hqspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	/* Configure QSPI: CCR register with functional mode as indirect write */
<>	144:ef7eb2e8f9f7	1213	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	1214
<>	144:ef7eb2e8f9f7	1215	/* Set the QSPI DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1216	hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	/* Set the QSPI DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1219	hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1222	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
<>	144:ef7eb2e8f9f7	1223
<>	144:ef7eb2e8f9f7	1224	/* Clear the DMA abort callback */
<>	144:ef7eb2e8f9f7	1225	hqspi->hdma->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	/* Configure the direction of the DMA */
<>	144:ef7eb2e8f9f7	1228	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
<>	144:ef7eb2e8f9f7	1229	MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	/* Enable the QSPI transmit DMA Channel */
<>	144:ef7eb2e8f9f7	1232	tmp = (uint32_t*)&pData;
<>	144:ef7eb2e8f9f7	1233	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
<>	144:ef7eb2e8f9f7	1234
<>	144:ef7eb2e8f9f7	1235	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1236	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1237
<>	144:ef7eb2e8f9f7	1238	/* Enable the QSPI transfer error Interrupt */
<>	144:ef7eb2e8f9f7	1239	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
<>	144:ef7eb2e8f9f7	1240
<>	144:ef7eb2e8f9f7	1241	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	1242	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	1243	}
<>	144:ef7eb2e8f9f7	1244	}
<>	144:ef7eb2e8f9f7	1245	else
<>	144:ef7eb2e8f9f7	1246	{
<>	144:ef7eb2e8f9f7	1247	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1248	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1249
<>	144:ef7eb2e8f9f7	1250	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1251	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1252	}
<>	144:ef7eb2e8f9f7	1253	}
<>	144:ef7eb2e8f9f7	1254	else
<>	144:ef7eb2e8f9f7	1255	{
<>	144:ef7eb2e8f9f7	1256	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1259	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1260	}
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	return status;
<>	144:ef7eb2e8f9f7	1263	}
<>	144:ef7eb2e8f9f7	1264
<>	144:ef7eb2e8f9f7	1265	/**
<>	144:ef7eb2e8f9f7	1266	* @brief Receive an amount of data in non-blocking mode with DMA.
<>	144:ef7eb2e8f9f7	1267	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1268	* @param pData: pointer to data buffer.
<>	144:ef7eb2e8f9f7	1269	* @note This function is used only in Indirect Read Mode
<>	144:ef7eb2e8f9f7	1270	* @note If DMA peripheral access is configured as halfword, the number
<>	144:ef7eb2e8f9f7	1271	* of data and the fifo threshold should be aligned on halfword
<>	144:ef7eb2e8f9f7	1272	* @note If DMA peripheral access is configured as word, the number
<>	144:ef7eb2e8f9f7	1273	* of data and the fifo threshold should be aligned on word
<>	144:ef7eb2e8f9f7	1274	* @retval HAL status
<>	144:ef7eb2e8f9f7	1275	*/
<>	144:ef7eb2e8f9f7	1276	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
<>	144:ef7eb2e8f9f7	1277	{
<>	144:ef7eb2e8f9f7	1278	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1279	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	1280	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
<>	144:ef7eb2e8f9f7	1281	uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
<>	144:ef7eb2e8f9f7	1282
<>	144:ef7eb2e8f9f7	1283	/* Process locked */
<>	144:ef7eb2e8f9f7	1284	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1285
<>	144:ef7eb2e8f9f7	1286	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1287	{
<>	144:ef7eb2e8f9f7	1288	/* Clear the error code */
<>	144:ef7eb2e8f9f7	1289	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	if(pData != NULL)
<>	144:ef7eb2e8f9f7	1292	{
<>	144:ef7eb2e8f9f7	1293	/* Configure counters of the handle */
<>	144:ef7eb2e8f9f7	1294	if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
<>	144:ef7eb2e8f9f7	1295	{
<>	144:ef7eb2e8f9f7	1296	hqspi->RxXferCount = data_size;
<>	144:ef7eb2e8f9f7	1297	}
<>	144:ef7eb2e8f9f7	1298	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
<>	144:ef7eb2e8f9f7	1299	{
<>	144:ef7eb2e8f9f7	1300	if (((data_size % 2) != 0) \|\| ((hqspi->Init.FifoThreshold % 2) != 0))
<>	144:ef7eb2e8f9f7	1301	{
<>	144:ef7eb2e8f9f7	1302	/* The number of data or the fifo threshold is not aligned on halfword
<>	144:ef7eb2e8f9f7	1303	=> no transfer possible with DMA peripheral access configured as halfword */
<>	144:ef7eb2e8f9f7	1304	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1305	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1306
<>	144:ef7eb2e8f9f7	1307	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1308	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1309	}
<>	144:ef7eb2e8f9f7	1310	else
<>	144:ef7eb2e8f9f7	1311	{
<>	144:ef7eb2e8f9f7	1312	hqspi->RxXferCount = (data_size >> 1);
<>	144:ef7eb2e8f9f7	1313	}
<>	144:ef7eb2e8f9f7	1314	}
<>	144:ef7eb2e8f9f7	1315	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
<>	144:ef7eb2e8f9f7	1316	{
<>	144:ef7eb2e8f9f7	1317	if (((data_size % 4) != 0) \|\| ((hqspi->Init.FifoThreshold % 4) != 0))
<>	144:ef7eb2e8f9f7	1318	{
<>	144:ef7eb2e8f9f7	1319	/* The number of data or the fifo threshold is not aligned on word
<>	144:ef7eb2e8f9f7	1320	=> no transfer possible with DMA peripheral access configured as word */
<>	144:ef7eb2e8f9f7	1321	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1322	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1325	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1326	}
<>	144:ef7eb2e8f9f7	1327	else
<>	144:ef7eb2e8f9f7	1328	{
<>	144:ef7eb2e8f9f7	1329	hqspi->RxXferCount = (data_size >> 2);
<>	144:ef7eb2e8f9f7	1330	}
<>	144:ef7eb2e8f9f7	1331	}
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1334	{
<>	144:ef7eb2e8f9f7	1335	/* Update state */
<>	144:ef7eb2e8f9f7	1336	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
<>	144:ef7eb2e8f9f7	1337
<>	144:ef7eb2e8f9f7	1338	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1339	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
<>	144:ef7eb2e8f9f7	1340
<>	144:ef7eb2e8f9f7	1341	/* Configure size and pointer of the handle */
<>	144:ef7eb2e8f9f7	1342	hqspi->RxXferSize = hqspi->RxXferCount;
<>	144:ef7eb2e8f9f7	1343	hqspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1344
<>	144:ef7eb2e8f9f7	1345	/* Set the QSPI DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1346	hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/* Set the QSPI DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1349	hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
<>	144:ef7eb2e8f9f7	1350
<>	144:ef7eb2e8f9f7	1351	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1352	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
<>	144:ef7eb2e8f9f7	1353
<>	144:ef7eb2e8f9f7	1354	/* Clear the DMA abort callback */
<>	144:ef7eb2e8f9f7	1355	hqspi->hdma->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1356
<>	144:ef7eb2e8f9f7	1357	/* Configure the direction of the DMA */
<>	144:ef7eb2e8f9f7	1358	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
<>	144:ef7eb2e8f9f7	1359	MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
<>	144:ef7eb2e8f9f7	1360
<>	144:ef7eb2e8f9f7	1361	/* Enable the DMA Channel */
<>	144:ef7eb2e8f9f7	1362	tmp = (uint32_t*)&pData;
<>	144:ef7eb2e8f9f7	1363	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365	/* Configure QSPI: CCR register with functional as indirect read */
<>	144:ef7eb2e8f9f7	1366	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
<>	144:ef7eb2e8f9f7	1367
<>	144:ef7eb2e8f9f7	1368	/* Start the transfer by re-writing the address in AR register */
<>	144:ef7eb2e8f9f7	1369	WRITE_REG(hqspi->Instance->AR, addr_reg);
<>	144:ef7eb2e8f9f7	1370
<>	144:ef7eb2e8f9f7	1371	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1372	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1373
<>	144:ef7eb2e8f9f7	1374	/* Enable the QSPI transfer error Interrupt */
<>	144:ef7eb2e8f9f7	1375	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	1378	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	1379	}
<>	144:ef7eb2e8f9f7	1380	}
<>	144:ef7eb2e8f9f7	1381	else
<>	144:ef7eb2e8f9f7	1382	{
<>	144:ef7eb2e8f9f7	1383	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1384	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1385
<>	144:ef7eb2e8f9f7	1386	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1387	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1388	}
<>	144:ef7eb2e8f9f7	1389	}
<>	144:ef7eb2e8f9f7	1390	else
<>	144:ef7eb2e8f9f7	1391	{
<>	144:ef7eb2e8f9f7	1392	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1393
<>	144:ef7eb2e8f9f7	1394	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1395	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1396	}
<>	144:ef7eb2e8f9f7	1397
<>	144:ef7eb2e8f9f7	1398	return status;
<>	144:ef7eb2e8f9f7	1399	}
<>	144:ef7eb2e8f9f7	1400
<>	144:ef7eb2e8f9f7	1401	/**
<>	144:ef7eb2e8f9f7	1402	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
<>	144:ef7eb2e8f9f7	1403	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1404	* @param cmd: structure that contains the command configuration information.
<>	144:ef7eb2e8f9f7	1405	* @param cfg: structure that contains the polling configuration information.
<>	144:ef7eb2e8f9f7	1406	* @param Timeout : Timeout duration
<>	144:ef7eb2e8f9f7	1407	* @note This function is used only in Automatic Polling Mode
<>	144:ef7eb2e8f9f7	1408	* @retval HAL status
<>	144:ef7eb2e8f9f7	1409	*/
<>	144:ef7eb2e8f9f7	1410	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1411	{
<>	144:ef7eb2e8f9f7	1412	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1413	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1414
<>	144:ef7eb2e8f9f7	1415	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1416	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	1417	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	1418	{
<>	144:ef7eb2e8f9f7	1419	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	1420	}
<>	144:ef7eb2e8f9f7	1421
<>	144:ef7eb2e8f9f7	1422	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	1423	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	1424	{
<>	144:ef7eb2e8f9f7	1425	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	1426	}
<>	144:ef7eb2e8f9f7	1427
<>	144:ef7eb2e8f9f7	1428	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	1429	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	1430	{
<>	144:ef7eb2e8f9f7	1431	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	1432	}
<>	144:ef7eb2e8f9f7	1433
<>	144:ef7eb2e8f9f7	1434	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	1435	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	1436
<>	144:ef7eb2e8f9f7	1437	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	1438	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	1439	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
<>	144:ef7eb2e8f9f7	1442	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
<>	144:ef7eb2e8f9f7	1443	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
<>	144:ef7eb2e8f9f7	1444
<>	144:ef7eb2e8f9f7	1445	/* Process locked */
<>	144:ef7eb2e8f9f7	1446	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1447
<>	144:ef7eb2e8f9f7	1448	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1449	{
<>	144:ef7eb2e8f9f7	1450	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1451
<>	144:ef7eb2e8f9f7	1452	/* Update state */
<>	144:ef7eb2e8f9f7	1453	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
<>	144:ef7eb2e8f9f7	1454
<>	144:ef7eb2e8f9f7	1455	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	1456	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	1457
<>	144:ef7eb2e8f9f7	1458	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1459	{
<>	144:ef7eb2e8f9f7	1460	/* Configure QSPI: PSMAR register with the status match value */
<>	144:ef7eb2e8f9f7	1461	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
<>	144:ef7eb2e8f9f7	1462
<>	144:ef7eb2e8f9f7	1463	/* Configure QSPI: PSMKR register with the status mask value */
<>	144:ef7eb2e8f9f7	1464	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	/* Configure QSPI: PIR register with the interval value */
<>	144:ef7eb2e8f9f7	1467	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
<>	144:ef7eb2e8f9f7	1468
<>	144:ef7eb2e8f9f7	1469	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
<>	144:ef7eb2e8f9f7	1470	(otherwise there will be an infinite loop in blocking mode) */
<>	144:ef7eb2e8f9f7	1471	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
<>	144:ef7eb2e8f9f7	1472	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
<>	144:ef7eb2e8f9f7	1473
<>	144:ef7eb2e8f9f7	1474	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	1475	cmd->NbData = cfg->StatusBytesSize;
<>	144:ef7eb2e8f9f7	1476	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
<>	144:ef7eb2e8f9f7	1477
<>	144:ef7eb2e8f9f7	1478	/* Wait until SM flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	1479	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	1480
<>	144:ef7eb2e8f9f7	1481	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1482	{
<>	144:ef7eb2e8f9f7	1483	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
<>	144:ef7eb2e8f9f7	1484
<>	144:ef7eb2e8f9f7	1485	/* Update state */
<>	144:ef7eb2e8f9f7	1486	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1487	}
<>	144:ef7eb2e8f9f7	1488	}
<>	144:ef7eb2e8f9f7	1489	}
<>	144:ef7eb2e8f9f7	1490	else
<>	144:ef7eb2e8f9f7	1491	{
<>	144:ef7eb2e8f9f7	1492	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1493	}
<>	144:ef7eb2e8f9f7	1494
<>	144:ef7eb2e8f9f7	1495	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1496	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	/* Return function status */
<>	144:ef7eb2e8f9f7	1499	return status;
<>	144:ef7eb2e8f9f7	1500	}
<>	144:ef7eb2e8f9f7	1501
<>	144:ef7eb2e8f9f7	1502	/**
<>	144:ef7eb2e8f9f7	1503	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
<>	144:ef7eb2e8f9f7	1504	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1505	* @param cmd: structure that contains the command configuration information.
<>	144:ef7eb2e8f9f7	1506	* @param cfg: structure that contains the polling configuration information.
<>	144:ef7eb2e8f9f7	1507	* @note This function is used only in Automatic Polling Mode
<>	144:ef7eb2e8f9f7	1508	* @retval HAL status
<>	144:ef7eb2e8f9f7	1509	*/
<>	144:ef7eb2e8f9f7	1510	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
<>	144:ef7eb2e8f9f7	1511	{
<>	144:ef7eb2e8f9f7	1512	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1513	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1514
<>	144:ef7eb2e8f9f7	1515	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1516	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	1517	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	1518	{
<>	144:ef7eb2e8f9f7	1519	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	1520	}
<>	144:ef7eb2e8f9f7	1521
<>	144:ef7eb2e8f9f7	1522	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	1523	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	1524	{
<>	144:ef7eb2e8f9f7	1525	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	1526	}
<>	144:ef7eb2e8f9f7	1527
<>	144:ef7eb2e8f9f7	1528	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	1529	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	1530	{
<>	144:ef7eb2e8f9f7	1531	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	1532	}
<>	144:ef7eb2e8f9f7	1533
<>	144:ef7eb2e8f9f7	1534	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	1535	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	1536
<>	144:ef7eb2e8f9f7	1537	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	1538	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	1539	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	1540
<>	144:ef7eb2e8f9f7	1541	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
<>	144:ef7eb2e8f9f7	1542	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
<>	144:ef7eb2e8f9f7	1543	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
<>	144:ef7eb2e8f9f7	1544	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/* Process locked */
<>	144:ef7eb2e8f9f7	1547	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1550	{
<>	144:ef7eb2e8f9f7	1551	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1552
<>	144:ef7eb2e8f9f7	1553	/* Update state */
<>	144:ef7eb2e8f9f7	1554	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
<>	144:ef7eb2e8f9f7	1555
<>	144:ef7eb2e8f9f7	1556	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	1557	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	1558
<>	144:ef7eb2e8f9f7	1559	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1560	{
<>	144:ef7eb2e8f9f7	1561	/* Configure QSPI: PSMAR register with the status match value */
<>	144:ef7eb2e8f9f7	1562	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
<>	144:ef7eb2e8f9f7	1563
<>	144:ef7eb2e8f9f7	1564	/* Configure QSPI: PSMKR register with the status mask value */
<>	144:ef7eb2e8f9f7	1565	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
<>	144:ef7eb2e8f9f7	1566
<>	144:ef7eb2e8f9f7	1567	/* Configure QSPI: PIR register with the interval value */
<>	144:ef7eb2e8f9f7	1568	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
<>	144:ef7eb2e8f9f7	1569
<>	144:ef7eb2e8f9f7	1570	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
<>	144:ef7eb2e8f9f7	1571	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
<>	144:ef7eb2e8f9f7	1572	(cfg->MatchMode \| cfg->AutomaticStop));
<>	144:ef7eb2e8f9f7	1573
<>	144:ef7eb2e8f9f7	1574	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1575	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_SM);
<>	144:ef7eb2e8f9f7	1576
<>	144:ef7eb2e8f9f7	1577	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	1578	cmd->NbData = cfg->StatusBytesSize;
<>	144:ef7eb2e8f9f7	1579	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1582	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1583
<>	144:ef7eb2e8f9f7	1584	/* Enable the QSPI Transfer Error and status match Interrupt */
<>	144:ef7eb2e8f9f7	1585	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
<>	144:ef7eb2e8f9f7	1586
<>	144:ef7eb2e8f9f7	1587	}
<>	144:ef7eb2e8f9f7	1588	else
<>	144:ef7eb2e8f9f7	1589	{
<>	144:ef7eb2e8f9f7	1590	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1591	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1592	}
<>	144:ef7eb2e8f9f7	1593	}
<>	144:ef7eb2e8f9f7	1594	else
<>	144:ef7eb2e8f9f7	1595	{
<>	144:ef7eb2e8f9f7	1596	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1597
<>	144:ef7eb2e8f9f7	1598	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1599	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1600	}
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	/* Return function status */
<>	144:ef7eb2e8f9f7	1603	return status;
<>	144:ef7eb2e8f9f7	1604	}
<>	144:ef7eb2e8f9f7	1605
<>	144:ef7eb2e8f9f7	1606	/**
<>	144:ef7eb2e8f9f7	1607	* @brief Configure the Memory Mapped mode.
<>	144:ef7eb2e8f9f7	1608	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1609	* @param cmd: structure that contains the command configuration information.
<>	144:ef7eb2e8f9f7	1610	* @param cfg: structure that contains the memory mapped configuration information.
<>	144:ef7eb2e8f9f7	1611	* @note This function is used only in Memory mapped Mode
<>	144:ef7eb2e8f9f7	1612	* @retval HAL status
<>	144:ef7eb2e8f9f7	1613	*/
<>	144:ef7eb2e8f9f7	1614	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
<>	144:ef7eb2e8f9f7	1615	{
<>	144:ef7eb2e8f9f7	1616	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1617	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1618
<>	144:ef7eb2e8f9f7	1619	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1620	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	1621	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	1622	{
<>	144:ef7eb2e8f9f7	1623	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	1624	}
<>	144:ef7eb2e8f9f7	1625
<>	144:ef7eb2e8f9f7	1626	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	1627	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	1628	{
<>	144:ef7eb2e8f9f7	1629	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	1630	}
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	1633	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	1634	{
<>	144:ef7eb2e8f9f7	1635	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	1636	}
<>	144:ef7eb2e8f9f7	1637
<>	144:ef7eb2e8f9f7	1638	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	1639	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	1640
<>	144:ef7eb2e8f9f7	1641	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	1642	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	1643	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	1644
<>	144:ef7eb2e8f9f7	1645	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
<>	144:ef7eb2e8f9f7	1646
<>	144:ef7eb2e8f9f7	1647	/* Process locked */
<>	144:ef7eb2e8f9f7	1648	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1649
<>	144:ef7eb2e8f9f7	1650	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1651	{
<>	144:ef7eb2e8f9f7	1652	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1653
<>	144:ef7eb2e8f9f7	1654	/* Update state */
<>	144:ef7eb2e8f9f7	1655	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
<>	144:ef7eb2e8f9f7	1656
<>	144:ef7eb2e8f9f7	1657	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	1658	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	1659
<>	144:ef7eb2e8f9f7	1660	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1661	{
<>	144:ef7eb2e8f9f7	1662	/* Configure QSPI: CR register with timeout counter enable */
<>	144:ef7eb2e8f9f7	1663	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
<>	144:ef7eb2e8f9f7	1664
<>	144:ef7eb2e8f9f7	1665	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
<>	144:ef7eb2e8f9f7	1666	{
<>	144:ef7eb2e8f9f7	1667	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
<>	144:ef7eb2e8f9f7	1668
<>	144:ef7eb2e8f9f7	1669	/* Configure QSPI: LPTR register with the low-power timeout value */
<>	144:ef7eb2e8f9f7	1670	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1673	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
<>	144:ef7eb2e8f9f7	1674
<>	144:ef7eb2e8f9f7	1675	/* Enable the QSPI TimeOut Interrupt */
<>	144:ef7eb2e8f9f7	1676	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
<>	144:ef7eb2e8f9f7	1677	}
<>	144:ef7eb2e8f9f7	1678
<>	144:ef7eb2e8f9f7	1679	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	1680	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
<>	144:ef7eb2e8f9f7	1681	}
<>	144:ef7eb2e8f9f7	1682	}
<>	144:ef7eb2e8f9f7	1683	else
<>	144:ef7eb2e8f9f7	1684	{
<>	144:ef7eb2e8f9f7	1685	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1686	}
<>	144:ef7eb2e8f9f7	1687
<>	144:ef7eb2e8f9f7	1688	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1689	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1690
<>	144:ef7eb2e8f9f7	1691	/* Return function status */
<>	144:ef7eb2e8f9f7	1692	return status;
<>	144:ef7eb2e8f9f7	1693	}
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/**
<>	144:ef7eb2e8f9f7	1696	* @brief Transfer Error callback.
<>	144:ef7eb2e8f9f7	1697	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1698	* @retval None
<>	144:ef7eb2e8f9f7	1699	*/
<>	144:ef7eb2e8f9f7	1700	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1701	{
<>	144:ef7eb2e8f9f7	1702	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1703	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1704
<>	144:ef7eb2e8f9f7	1705	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1706	the HAL_QSPI_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1707	*/
<>	144:ef7eb2e8f9f7	1708	}
<>	144:ef7eb2e8f9f7	1709
<>	144:ef7eb2e8f9f7	1710	/**
<>	144:ef7eb2e8f9f7	1711	* @brief Abort completed callback.
<>	144:ef7eb2e8f9f7	1712	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1713	* @retval None
<>	144:ef7eb2e8f9f7	1714	*/
<>	144:ef7eb2e8f9f7	1715	__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1716	{
<>	144:ef7eb2e8f9f7	1717	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1718	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1719
<>	144:ef7eb2e8f9f7	1720	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1721	the HAL_QSPI_AbortCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1722	*/
<>	144:ef7eb2e8f9f7	1723	}
<>	144:ef7eb2e8f9f7	1724
<>	144:ef7eb2e8f9f7	1725	/**
<>	144:ef7eb2e8f9f7	1726	* @brief Command completed callback.
<>	144:ef7eb2e8f9f7	1727	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1728	* @retval None
<>	144:ef7eb2e8f9f7	1729	*/
<>	144:ef7eb2e8f9f7	1730	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1731	{
<>	144:ef7eb2e8f9f7	1732	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1733	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1734
<>	144:ef7eb2e8f9f7	1735	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1736	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1737	*/
<>	144:ef7eb2e8f9f7	1738	}
<>	144:ef7eb2e8f9f7	1739
<>	144:ef7eb2e8f9f7	1740	/**
<>	144:ef7eb2e8f9f7	1741	* @brief Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	1742	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1743	* @retval None
<>	144:ef7eb2e8f9f7	1744	*/
<>	144:ef7eb2e8f9f7	1745	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1746	{
<>	144:ef7eb2e8f9f7	1747	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1748	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1749
<>	144:ef7eb2e8f9f7	1750	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1751	the HAL_QSPI_RxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1752	*/
<>	144:ef7eb2e8f9f7	1753	}
<>	144:ef7eb2e8f9f7	1754
<>	144:ef7eb2e8f9f7	1755	/**
<>	144:ef7eb2e8f9f7	1756	* @brief Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	1757	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1758	* @retval None
<>	144:ef7eb2e8f9f7	1759	*/
<>	144:ef7eb2e8f9f7	1760	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1761	{
<>	144:ef7eb2e8f9f7	1762	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1763	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1764
<>	144:ef7eb2e8f9f7	1765	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1766	the HAL_QSPI_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1767	*/
<>	144:ef7eb2e8f9f7	1768	}
<>	144:ef7eb2e8f9f7	1769
<>	144:ef7eb2e8f9f7	1770	/**
<>	144:ef7eb2e8f9f7	1771	* @brief Rx Half Transfer completed callback.
<>	144:ef7eb2e8f9f7	1772	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1773	* @retval None
<>	144:ef7eb2e8f9f7	1774	*/
<>	144:ef7eb2e8f9f7	1775	__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1776	{
<>	144:ef7eb2e8f9f7	1777	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1778	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1781	the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1782	*/
<>	144:ef7eb2e8f9f7	1783	}
<>	144:ef7eb2e8f9f7	1784
<>	144:ef7eb2e8f9f7	1785	/**
<>	144:ef7eb2e8f9f7	1786	* @brief Tx Half Transfer completed callback.
<>	144:ef7eb2e8f9f7	1787	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1788	* @retval None
<>	144:ef7eb2e8f9f7	1789	*/
<>	144:ef7eb2e8f9f7	1790	__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1791	{
<>	144:ef7eb2e8f9f7	1792	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1793	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1794
<>	144:ef7eb2e8f9f7	1795	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1796	the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1797	*/
<>	144:ef7eb2e8f9f7	1798	}
<>	144:ef7eb2e8f9f7	1799
<>	144:ef7eb2e8f9f7	1800	/**
<>	144:ef7eb2e8f9f7	1801	* @brief FIFO Threshold callback.
<>	144:ef7eb2e8f9f7	1802	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1803	* @retval None
<>	144:ef7eb2e8f9f7	1804	*/
<>	144:ef7eb2e8f9f7	1805	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1806	{
<>	144:ef7eb2e8f9f7	1807	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1808	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1809
<>	144:ef7eb2e8f9f7	1810	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1811	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1812	*/
<>	144:ef7eb2e8f9f7	1813	}
<>	144:ef7eb2e8f9f7	1814
<>	144:ef7eb2e8f9f7	1815	/**
<>	144:ef7eb2e8f9f7	1816	* @brief Status Match callback.
<>	144:ef7eb2e8f9f7	1817	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1818	* @retval None
<>	144:ef7eb2e8f9f7	1819	*/
<>	144:ef7eb2e8f9f7	1820	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1821	{
<>	144:ef7eb2e8f9f7	1822	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1823	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1824
<>	144:ef7eb2e8f9f7	1825	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1826	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1827	*/
<>	144:ef7eb2e8f9f7	1828	}
<>	144:ef7eb2e8f9f7	1829
<>	144:ef7eb2e8f9f7	1830	/**
<>	144:ef7eb2e8f9f7	1831	* @brief Timeout callback.
<>	144:ef7eb2e8f9f7	1832	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1833	* @retval None
<>	144:ef7eb2e8f9f7	1834	*/
<>	144:ef7eb2e8f9f7	1835	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1836	{
<>	144:ef7eb2e8f9f7	1837	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1838	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1839
<>	144:ef7eb2e8f9f7	1840	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1841	the HAL_QSPI_TimeOutCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1842	*/
<>	144:ef7eb2e8f9f7	1843	}
<>	144:ef7eb2e8f9f7	1844
<>	144:ef7eb2e8f9f7	1845	/**
<>	144:ef7eb2e8f9f7	1846	* @}
<>	144:ef7eb2e8f9f7	1847	*/
<>	144:ef7eb2e8f9f7	1848
<>	144:ef7eb2e8f9f7	1849	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
<>	144:ef7eb2e8f9f7	1850	* @brief QSPI control and State functions
<>	144:ef7eb2e8f9f7	1851	*
<>	144:ef7eb2e8f9f7	1852	@verbatim
<>	144:ef7eb2e8f9f7	1853	===============================================================================
<>	144:ef7eb2e8f9f7	1854	##### Peripheral Control and State functions #####
<>	144:ef7eb2e8f9f7	1855	===============================================================================
<>	144:ef7eb2e8f9f7	1856	[..]
<>	144:ef7eb2e8f9f7	1857	This subsection provides a set of functions allowing to :
<>	144:ef7eb2e8f9f7	1858	(+) Check in run-time the state of the driver.
<>	144:ef7eb2e8f9f7	1859	(+) Check the error code set during last operation.
<>	144:ef7eb2e8f9f7	1860	(+) Abort any operation.
<>	144:ef7eb2e8f9f7	1861
<>	144:ef7eb2e8f9f7	1862
<>	144:ef7eb2e8f9f7	1863	@endverbatim
<>	144:ef7eb2e8f9f7	1864	* @{
<>	144:ef7eb2e8f9f7	1865	*/
<>	144:ef7eb2e8f9f7	1866
<>	144:ef7eb2e8f9f7	1867	/**
<>	144:ef7eb2e8f9f7	1868	* @brief Return the QSPI handle state.
<>	144:ef7eb2e8f9f7	1869	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1870	* @retval HAL state
<>	144:ef7eb2e8f9f7	1871	*/
<>	144:ef7eb2e8f9f7	1872	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1873	{
<>	144:ef7eb2e8f9f7	1874	/* Return QSPI handle state */
<>	144:ef7eb2e8f9f7	1875	return hqspi->State;
<>	144:ef7eb2e8f9f7	1876	}
<>	144:ef7eb2e8f9f7	1877
<>	144:ef7eb2e8f9f7	1878	/**
<>	144:ef7eb2e8f9f7	1879	* @brief Return the QSPI error code.
<>	144:ef7eb2e8f9f7	1880	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1881	* @retval QSPI Error Code
<>	144:ef7eb2e8f9f7	1882	*/
<>	144:ef7eb2e8f9f7	1883	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1884	{
<>	144:ef7eb2e8f9f7	1885	return hqspi->ErrorCode;
<>	144:ef7eb2e8f9f7	1886	}
<>	144:ef7eb2e8f9f7	1887
<>	144:ef7eb2e8f9f7	1888	/**
<>	144:ef7eb2e8f9f7	1889	* @brief Abort the current transmission.
<>	144:ef7eb2e8f9f7	1890	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1891	* @retval HAL status
<>	144:ef7eb2e8f9f7	1892	*/
<>	144:ef7eb2e8f9f7	1893	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1894	{
<>	144:ef7eb2e8f9f7	1895	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1896	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1897
<>	144:ef7eb2e8f9f7	1898	/* Check if the state is in one of the busy states */
<>	144:ef7eb2e8f9f7	1899	if ((hqspi->State & 0x2) != 0)
<>	144:ef7eb2e8f9f7	1900	{
<>	144:ef7eb2e8f9f7	1901	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1902	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1903
<>	144:ef7eb2e8f9f7	1904	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
<>	144:ef7eb2e8f9f7	1905	{
<>	144:ef7eb2e8f9f7	1906	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	1907	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	1908
<>	144:ef7eb2e8f9f7	1909	/* Abort DMA channel */
<>	144:ef7eb2e8f9f7	1910	status = HAL_DMA_Abort(hqspi->hdma);
<>	144:ef7eb2e8f9f7	1911	if(status != HAL_OK)
<>	144:ef7eb2e8f9f7	1912	{
<>	144:ef7eb2e8f9f7	1913	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
<>	144:ef7eb2e8f9f7	1914	}
<>	144:ef7eb2e8f9f7	1915	}
<>	144:ef7eb2e8f9f7	1916
<>	144:ef7eb2e8f9f7	1917	/* Configure QSPI: CR register with Abort request */
<>	144:ef7eb2e8f9f7	1918	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
<>	144:ef7eb2e8f9f7	1919
<>	144:ef7eb2e8f9f7	1920	/* Wait until TC flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	1921	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	1922
<>	144:ef7eb2e8f9f7	1923	if(status == HAL_OK)
<>	144:ef7eb2e8f9f7	1924	{
<>	144:ef7eb2e8f9f7	1925	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	1926
<>	144:ef7eb2e8f9f7	1927	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1928	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	1929	}
<>	144:ef7eb2e8f9f7	1930
<>	144:ef7eb2e8f9f7	1931	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1932	{
<>	144:ef7eb2e8f9f7	1933	/* Update state */
<>	144:ef7eb2e8f9f7	1934	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1935	}
<>	144:ef7eb2e8f9f7	1936	}
<>	144:ef7eb2e8f9f7	1937
<>	144:ef7eb2e8f9f7	1938	return status;
<>	144:ef7eb2e8f9f7	1939	}
<>	144:ef7eb2e8f9f7	1940
<>	144:ef7eb2e8f9f7	1941	/**
<>	144:ef7eb2e8f9f7	1942	* @brief Abort the current transmission (non-blocking function)
<>	144:ef7eb2e8f9f7	1943	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1944	* @retval HAL status
<>	144:ef7eb2e8f9f7	1945	*/
<>	144:ef7eb2e8f9f7	1946	HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1947	{
<>	144:ef7eb2e8f9f7	1948	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1949
<>	144:ef7eb2e8f9f7	1950	/* Check if the state is in one of the busy states */
<>	144:ef7eb2e8f9f7	1951	if ((hqspi->State & 0x2) != 0)
<>	144:ef7eb2e8f9f7	1952	{
<>	144:ef7eb2e8f9f7	1953	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1954	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1955
<>	144:ef7eb2e8f9f7	1956	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	1957	hqspi->State = HAL_QSPI_STATE_ABORT;
<>	144:ef7eb2e8f9f7	1958
<>	144:ef7eb2e8f9f7	1959	/* Disable all interrupts */
<>	144:ef7eb2e8f9f7	1960	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO \| QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TC \| QSPI_IT_TE));
<>	144:ef7eb2e8f9f7	1961
<>	144:ef7eb2e8f9f7	1962	if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
<>	144:ef7eb2e8f9f7	1963	{
<>	144:ef7eb2e8f9f7	1964	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	1965	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	1966
<>	144:ef7eb2e8f9f7	1967	/* Abort DMA channel */
<>	144:ef7eb2e8f9f7	1968	hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
<>	144:ef7eb2e8f9f7	1969	HAL_DMA_Abort_IT(hqspi->hdma);
<>	144:ef7eb2e8f9f7	1970	}
<>	144:ef7eb2e8f9f7	1971	else
<>	144:ef7eb2e8f9f7	1972	{
<>	144:ef7eb2e8f9f7	1973	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1974	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	1975
<>	144:ef7eb2e8f9f7	1976	/* Enable the QSPI Transfer Complete Interrupt */
<>	144:ef7eb2e8f9f7	1977	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	1978
<>	144:ef7eb2e8f9f7	1979	/* Configure QSPI: CR register with Abort request */
<>	144:ef7eb2e8f9f7	1980	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
<>	144:ef7eb2e8f9f7	1981	}
<>	144:ef7eb2e8f9f7	1982	}
<>	144:ef7eb2e8f9f7	1983	return status;
<>	144:ef7eb2e8f9f7	1984	}
<>	144:ef7eb2e8f9f7	1985
<>	144:ef7eb2e8f9f7	1986	/** @brief Set QSPI timeout.
<>	144:ef7eb2e8f9f7	1987	* @param hqspi: QSPI handle.
<>	144:ef7eb2e8f9f7	1988	* @param Timeout: Timeout for the QSPI memory access.
<>	144:ef7eb2e8f9f7	1989	* @retval None
<>	144:ef7eb2e8f9f7	1990	*/
<>	144:ef7eb2e8f9f7	1991	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1992	{
<>	144:ef7eb2e8f9f7	1993	hqspi->Timeout = Timeout;
<>	144:ef7eb2e8f9f7	1994	}
<>	144:ef7eb2e8f9f7	1995
<>	144:ef7eb2e8f9f7	1996	/** @brief Set QSPI Fifo threshold.
<>	144:ef7eb2e8f9f7	1997	* @param hqspi: QSPI handle.
<>	144:ef7eb2e8f9f7	1998	* @param Threshold: Threshold of the Fifo (value between 1 and 16).
<>	144:ef7eb2e8f9f7	1999	* @retval HAL status
<>	144:ef7eb2e8f9f7	2000	*/
<>	144:ef7eb2e8f9f7	2001	HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
<>	144:ef7eb2e8f9f7	2002	{
<>	144:ef7eb2e8f9f7	2003	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	2004
<>	144:ef7eb2e8f9f7	2005	/* Process locked */
<>	144:ef7eb2e8f9f7	2006	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	2007
<>	144:ef7eb2e8f9f7	2008	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	2009	{
<>	144:ef7eb2e8f9f7	2010	/* Synchronize init structure with new FIFO threshold value */
<>	144:ef7eb2e8f9f7	2011	hqspi->Init.FifoThreshold = Threshold;
<>	144:ef7eb2e8f9f7	2012
<>	144:ef7eb2e8f9f7	2013	/* Configure QSPI FIFO Threshold */
<>	144:ef7eb2e8f9f7	2014	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
<>	144:ef7eb2e8f9f7	2015	((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
<>	144:ef7eb2e8f9f7	2016	}
<>	144:ef7eb2e8f9f7	2017	else
<>	144:ef7eb2e8f9f7	2018	{
<>	144:ef7eb2e8f9f7	2019	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	2020	}
<>	144:ef7eb2e8f9f7	2021
<>	144:ef7eb2e8f9f7	2022	/* Process unlocked */
<>	144:ef7eb2e8f9f7	2023	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	2024
<>	144:ef7eb2e8f9f7	2025	/* Return function status */
<>	144:ef7eb2e8f9f7	2026	return status;
<>	144:ef7eb2e8f9f7	2027	}
<>	144:ef7eb2e8f9f7	2028
<>	144:ef7eb2e8f9f7	2029	/** @brief Get QSPI Fifo threshold.
<>	144:ef7eb2e8f9f7	2030	* @param hqspi: QSPI handle.
<>	144:ef7eb2e8f9f7	2031	* @retval Fifo threshold (value between 1 and 16)
<>	144:ef7eb2e8f9f7	2032	*/
<>	144:ef7eb2e8f9f7	2033	uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	2034	{
<>	144:ef7eb2e8f9f7	2035	return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
<>	144:ef7eb2e8f9f7	2036	}
<>	144:ef7eb2e8f9f7	2037
<>	144:ef7eb2e8f9f7	2038	/**
<>	144:ef7eb2e8f9f7	2039	* @}
<>	144:ef7eb2e8f9f7	2040	*/
<>	144:ef7eb2e8f9f7	2041
<>	144:ef7eb2e8f9f7	2042	/**
<>	144:ef7eb2e8f9f7	2043	* @brief DMA QSPI receive process complete callback.
<>	144:ef7eb2e8f9f7	2044	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2045	* @retval None
<>	144:ef7eb2e8f9f7	2046	*/
<>	144:ef7eb2e8f9f7	2047	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2048	{
<>	144:ef7eb2e8f9f7	2049	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2050	hqspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2051
<>	144:ef7eb2e8f9f7	2052	/* Enable the QSPI transfer complete Interrupt */
<>	144:ef7eb2e8f9f7	2053	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	2054	}
<>	144:ef7eb2e8f9f7	2055
<>	144:ef7eb2e8f9f7	2056	/**
<>	144:ef7eb2e8f9f7	2057	* @brief DMA QSPI transmit process complete callback.
<>	144:ef7eb2e8f9f7	2058	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2059	* @retval None
<>	144:ef7eb2e8f9f7	2060	*/
<>	144:ef7eb2e8f9f7	2061	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2062	{
<>	144:ef7eb2e8f9f7	2063	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2064	hqspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2065
<>	144:ef7eb2e8f9f7	2066	/* Enable the QSPI transfer complete Interrupt */
<>	144:ef7eb2e8f9f7	2067	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	2068	}
<>	144:ef7eb2e8f9f7	2069
<>	144:ef7eb2e8f9f7	2070	/**
<>	144:ef7eb2e8f9f7	2071	* @brief DMA QSPI receive process half complete callback.
<>	144:ef7eb2e8f9f7	2072	* @param hdma : DMA handle
<>	144:ef7eb2e8f9f7	2073	* @retval None
<>	144:ef7eb2e8f9f7	2074	*/
<>	144:ef7eb2e8f9f7	2075	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2076	{
<>	144:ef7eb2e8f9f7	2077	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2078
<>	144:ef7eb2e8f9f7	2079	HAL_QSPI_RxHalfCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	2080	}
<>	144:ef7eb2e8f9f7	2081
<>	144:ef7eb2e8f9f7	2082	/**
<>	144:ef7eb2e8f9f7	2083	* @brief DMA QSPI transmit process half complete callback.
<>	144:ef7eb2e8f9f7	2084	* @param hdma : DMA handle
<>	144:ef7eb2e8f9f7	2085	* @retval None
<>	144:ef7eb2e8f9f7	2086	*/
<>	144:ef7eb2e8f9f7	2087	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2088	{
<>	144:ef7eb2e8f9f7	2089	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2090
<>	144:ef7eb2e8f9f7	2091	HAL_QSPI_TxHalfCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	2092	}
<>	144:ef7eb2e8f9f7	2093
<>	144:ef7eb2e8f9f7	2094	/**
<>	144:ef7eb2e8f9f7	2095	* @brief DMA QSPI communication error callback.
<>	144:ef7eb2e8f9f7	2096	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2097	* @retval None
<>	144:ef7eb2e8f9f7	2098	*/
<>	144:ef7eb2e8f9f7	2099	static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2100	{
<>	144:ef7eb2e8f9f7	2101	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2102
<>	144:ef7eb2e8f9f7	2103	hqspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2104	hqspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2105	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
<>	144:ef7eb2e8f9f7	2106
<>	144:ef7eb2e8f9f7	2107	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	2108	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	2109
<>	144:ef7eb2e8f9f7	2110	/* Abort the QSPI */
<>	144:ef7eb2e8f9f7	2111	HAL_QSPI_Abort_IT(hqspi);
<>	144:ef7eb2e8f9f7	2112	}
<>	144:ef7eb2e8f9f7	2113
<>	144:ef7eb2e8f9f7	2114	/**
<>	144:ef7eb2e8f9f7	2115	* @brief DMA QSPI abort complete callback.
<>	144:ef7eb2e8f9f7	2116	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2117	* @retval None
<>	144:ef7eb2e8f9f7	2118	*/
<>	144:ef7eb2e8f9f7	2119	static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2120	{
<>	144:ef7eb2e8f9f7	2121	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2122
<>	144:ef7eb2e8f9f7	2123	hqspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2124	hqspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2125
<>	144:ef7eb2e8f9f7	2126	if(hqspi->State == HAL_QSPI_STATE_ABORT)
<>	144:ef7eb2e8f9f7	2127	{
<>	144:ef7eb2e8f9f7	2128	/* DMA Abort called by QSPI abort */
<>	144:ef7eb2e8f9f7	2129	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	2130	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	2131
<>	144:ef7eb2e8f9f7	2132	/* Enable the QSPI Transfer Complete Interrupt */
<>	144:ef7eb2e8f9f7	2133	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	2134
<>	144:ef7eb2e8f9f7	2135	/* Configure QSPI: CR register with Abort request */
<>	144:ef7eb2e8f9f7	2136	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
<>	144:ef7eb2e8f9f7	2137	}
<>	144:ef7eb2e8f9f7	2138	else
<>	144:ef7eb2e8f9f7	2139	{
<>	144:ef7eb2e8f9f7	2140	/* DMA Abort called due to a transfer error interrupt */
<>	144:ef7eb2e8f9f7	2141	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	2142	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2143
<>	144:ef7eb2e8f9f7	2144	/* Error callback */
<>	144:ef7eb2e8f9f7	2145	HAL_QSPI_ErrorCallback(hqspi);
<>	144:ef7eb2e8f9f7	2146	}
<>	144:ef7eb2e8f9f7	2147	}
<>	144:ef7eb2e8f9f7	2148	/**
<>	144:ef7eb2e8f9f7	2149	* @brief Wait for a flag state until timeout.
<>	144:ef7eb2e8f9f7	2150	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	2151	* @param Flag: Flag checked
<>	144:ef7eb2e8f9f7	2152	* @param State: Value of the flag expected
<>	144:ef7eb2e8f9f7	2153	* @param Timeout: Duration of the timeout
<>	144:ef7eb2e8f9f7	2154	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	2155	* @retval HAL status
<>	144:ef7eb2e8f9f7	2156	*/
<>	144:ef7eb2e8f9f7	2157	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
<>	144:ef7eb2e8f9f7	2158	FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2159	{
<>	144:ef7eb2e8f9f7	2160	/* Wait until flag is in expected state */
<>	144:ef7eb2e8f9f7	2161	while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
<>	144:ef7eb2e8f9f7	2162	{
<>	144:ef7eb2e8f9f7	2163	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	2164	if (Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	2165	{
<>	144:ef7eb2e8f9f7	2166	if((Timeout == 0) \|\| ((HAL_GetTick() - Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	2167	{
<>	144:ef7eb2e8f9f7	2168	hqspi->State = HAL_QSPI_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2169	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	2170
<>	144:ef7eb2e8f9f7	2171	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2172	}
<>	144:ef7eb2e8f9f7	2173	}
<>	144:ef7eb2e8f9f7	2174	}
<>	144:ef7eb2e8f9f7	2175	return HAL_OK;
<>	144:ef7eb2e8f9f7	2176	}
<>	144:ef7eb2e8f9f7	2177
<>	144:ef7eb2e8f9f7	2178	/**
<>	144:ef7eb2e8f9f7	2179	* @brief Configure the communication registers.
<>	144:ef7eb2e8f9f7	2180	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	2181	* @param cmd: structure that contains the command configuration information
<>	144:ef7eb2e8f9f7	2182	* @param FunctionalMode: functional mode to configured
<>	144:ef7eb2e8f9f7	2183	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2184	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
<>	144:ef7eb2e8f9f7	2185	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
<>	144:ef7eb2e8f9f7	2186	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
<>	144:ef7eb2e8f9f7	2187	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
<>	144:ef7eb2e8f9f7	2188	* @retval None
<>	144:ef7eb2e8f9f7	2189	*/
<>	144:ef7eb2e8f9f7	2190	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
<>	144:ef7eb2e8f9f7	2191	{
<>	144:ef7eb2e8f9f7	2192	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
<>	144:ef7eb2e8f9f7	2193
<>	144:ef7eb2e8f9f7	2194	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
<>	144:ef7eb2e8f9f7	2195	{
<>	144:ef7eb2e8f9f7	2196	/* Configure QSPI: DLR register with the number of data to read or write */
<>	144:ef7eb2e8f9f7	2197	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
<>	144:ef7eb2e8f9f7	2198	}
<>	144:ef7eb2e8f9f7	2199
<>	144:ef7eb2e8f9f7	2200	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	2201	{
<>	144:ef7eb2e8f9f7	2202	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	2203	{
<>	144:ef7eb2e8f9f7	2204	/* Configure QSPI: ABR register with alternate bytes value */
<>	144:ef7eb2e8f9f7	2205	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
<>	144:ef7eb2e8f9f7	2206
<>	144:ef7eb2e8f9f7	2207	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	2208	{
<>	144:ef7eb2e8f9f7	2209	/---- Command with instruction, address and alternate bytes ----/
<>	144:ef7eb2e8f9f7	2210	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2211	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2212	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
<>	144:ef7eb2e8f9f7	2213	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
<>	144:ef7eb2e8f9f7	2214	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
<>	144:ef7eb2e8f9f7	2215	cmd->Instruction \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2216
<>	144:ef7eb2e8f9f7	2217	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
<>	144:ef7eb2e8f9f7	2218	{
<>	144:ef7eb2e8f9f7	2219	/* Configure QSPI: AR register with address value */
<>	144:ef7eb2e8f9f7	2220	WRITE_REG(hqspi->Instance->AR, cmd->Address);
<>	144:ef7eb2e8f9f7	2221	}
<>	144:ef7eb2e8f9f7	2222	}
<>	144:ef7eb2e8f9f7	2223	else
<>	144:ef7eb2e8f9f7	2224	{
<>	144:ef7eb2e8f9f7	2225	/---- Command with instruction and alternate bytes ----/
<>	144:ef7eb2e8f9f7	2226	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2227	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2228	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
<>	144:ef7eb2e8f9f7	2229	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
<>	144:ef7eb2e8f9f7	2230	cmd->AddressMode \| cmd->InstructionMode \|
<>	144:ef7eb2e8f9f7	2231	cmd->Instruction \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2232	}
<>	144:ef7eb2e8f9f7	2233	}
<>	144:ef7eb2e8f9f7	2234	else
<>	144:ef7eb2e8f9f7	2235	{
<>	144:ef7eb2e8f9f7	2236	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	2237	{
<>	144:ef7eb2e8f9f7	2238	/---- Command with instruction and address ----/
<>	144:ef7eb2e8f9f7	2239	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2240	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2241	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
<>	144:ef7eb2e8f9f7	2242	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
<>	144:ef7eb2e8f9f7	2243	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2244
<>	144:ef7eb2e8f9f7	2245	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
<>	144:ef7eb2e8f9f7	2246	{
<>	144:ef7eb2e8f9f7	2247	/* Configure QSPI: AR register with address value */
<>	144:ef7eb2e8f9f7	2248	WRITE_REG(hqspi->Instance->AR, cmd->Address);
<>	144:ef7eb2e8f9f7	2249	}
<>	144:ef7eb2e8f9f7	2250	}
<>	144:ef7eb2e8f9f7	2251	else
<>	144:ef7eb2e8f9f7	2252	{
<>	144:ef7eb2e8f9f7	2253	/---- Command with only instruction ----/
<>	144:ef7eb2e8f9f7	2254	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2255	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2256	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
<>	144:ef7eb2e8f9f7	2257	cmd->AlternateByteMode \| cmd->AddressMode \|
<>	144:ef7eb2e8f9f7	2258	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2259	}
<>	144:ef7eb2e8f9f7	2260	}
<>	144:ef7eb2e8f9f7	2261	}
<>	144:ef7eb2e8f9f7	2262	else
<>	144:ef7eb2e8f9f7	2263	{
<>	144:ef7eb2e8f9f7	2264	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	2265	{
<>	144:ef7eb2e8f9f7	2266	/* Configure QSPI: ABR register with alternate bytes value */
<>	144:ef7eb2e8f9f7	2267	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
<>	144:ef7eb2e8f9f7	2268
<>	144:ef7eb2e8f9f7	2269	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	2270	{
<>	144:ef7eb2e8f9f7	2271	/---- Command with address and alternate bytes ----/
<>	144:ef7eb2e8f9f7	2272	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2273	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2274	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
<>	144:ef7eb2e8f9f7	2275	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
<>	144:ef7eb2e8f9f7	2276	cmd->AddressSize \| cmd->AddressMode \|
<>	144:ef7eb2e8f9f7	2277	cmd->InstructionMode \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2278
<>	144:ef7eb2e8f9f7	2279	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
<>	144:ef7eb2e8f9f7	2280	{
<>	144:ef7eb2e8f9f7	2281	/* Configure QSPI: AR register with address value */
<>	144:ef7eb2e8f9f7	2282	WRITE_REG(hqspi->Instance->AR, cmd->Address);
<>	144:ef7eb2e8f9f7	2283	}
<>	144:ef7eb2e8f9f7	2284	}
<>	144:ef7eb2e8f9f7	2285	else
<>	144:ef7eb2e8f9f7	2286	{
<>	144:ef7eb2e8f9f7	2287	/---- Command with only alternate bytes ----/
<>	144:ef7eb2e8f9f7	2288	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2289	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2290	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
<>	144:ef7eb2e8f9f7	2291	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
<>	144:ef7eb2e8f9f7	2292	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2293	}
<>	144:ef7eb2e8f9f7	2294	}
<>	144:ef7eb2e8f9f7	2295	else
<>	144:ef7eb2e8f9f7	2296	{
<>	144:ef7eb2e8f9f7	2297	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	2298	{
<>	144:ef7eb2e8f9f7	2299	/---- Command with only address ----/
<>	144:ef7eb2e8f9f7	2300	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2301	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2302	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
<>	144:ef7eb2e8f9f7	2303	cmd->AlternateByteMode \| cmd->AddressSize \|
<>	144:ef7eb2e8f9f7	2304	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2305
<>	144:ef7eb2e8f9f7	2306	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
<>	144:ef7eb2e8f9f7	2307	{
<>	144:ef7eb2e8f9f7	2308	/* Configure QSPI: AR register with address value */
<>	144:ef7eb2e8f9f7	2309	WRITE_REG(hqspi->Instance->AR, cmd->Address);
<>	144:ef7eb2e8f9f7	2310	}
<>	144:ef7eb2e8f9f7	2311	}
<>	144:ef7eb2e8f9f7	2312	else
<>	144:ef7eb2e8f9f7	2313	{
<>	144:ef7eb2e8f9f7	2314	/---- Command with only data phase ----/
<>	144:ef7eb2e8f9f7	2315	if (cmd->DataMode != QSPI_DATA_NONE)
<>	144:ef7eb2e8f9f7	2316	{
<>	144:ef7eb2e8f9f7	2317	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2318	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2319	cmd->DataMode \| (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) \|
<>	144:ef7eb2e8f9f7	2320	cmd->AlternateByteMode \| cmd->AddressMode \|
<>	144:ef7eb2e8f9f7	2321	cmd->InstructionMode \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2322	}
<>	144:ef7eb2e8f9f7	2323	}
<>	144:ef7eb2e8f9f7	2324	}
<>	144:ef7eb2e8f9f7	2325	}
<>	144:ef7eb2e8f9f7	2326	}
<>	144:ef7eb2e8f9f7	2327
<>	144:ef7eb2e8f9f7	2328	/**
<>	144:ef7eb2e8f9f7	2329	* @}
<>	144:ef7eb2e8f9f7	2330	*/
<>	144:ef7eb2e8f9f7	2331
<>	144:ef7eb2e8f9f7	2332	#endif /* HAL_QSPI_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2333	/**
<>	144:ef7eb2e8f9f7	2334	* @}
<>	144:ef7eb2e8f9f7	2335	*/
<>	144:ef7eb2e8f9f7	2336
<>	144:ef7eb2e8f9f7	2337	/**
<>	144:ef7eb2e8f9f7	2338	* @}
<>	144:ef7eb2e8f9f7	2339	*/
<>	144:ef7eb2e8f9f7	2340
<>	144:ef7eb2e8f9f7	2341	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/