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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_flash_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_flash_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended FLASH HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the FLASH extended peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended programming operations functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 @verbatim
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14 ##### Flash Extended features #####
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 [..] Comparing to other previous devices, the FLASH interface for STM32L4xx
<> 144:ef7eb2e8f9f7 18 devices contains the following additional features
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
<> 144:ef7eb2e8f9f7 21 capability (RWW)
<> 144:ef7eb2e8f9f7 22 (+) Dual bank memory organization
<> 144:ef7eb2e8f9f7 23 (+) PCROP protection for all banks
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 26 ==============================================================================
<> 144:ef7eb2e8f9f7 27 [..] This driver provides functions to configure and program the FLASH memory
<> 144:ef7eb2e8f9f7 28 of all STM32L4xx devices. It includes
<> 144:ef7eb2e8f9f7 29 (#) Flash Memory Erase functions:
<> 144:ef7eb2e8f9f7 30 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
<> 144:ef7eb2e8f9f7 31 HAL_FLASH_Lock() functions
<> 144:ef7eb2e8f9f7 32 (++) Erase function: Erase page, erase all sectors
<> 144:ef7eb2e8f9f7 33 (++) There are two modes of erase :
<> 144:ef7eb2e8f9f7 34 (+++) Polling Mode using HAL_FLASHEx_Erase()
<> 144:ef7eb2e8f9f7 35 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
<> 144:ef7eb2e8f9f7 38 (++) Set/Reset the write protection
<> 144:ef7eb2e8f9f7 39 (++) Set the Read protection Level
<> 144:ef7eb2e8f9f7 40 (++) Program the user Option Bytes
<> 144:ef7eb2e8f9f7 41 (++) Configure the PCROP protection
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
<> 144:ef7eb2e8f9f7 44 (++) Get the value of a write protection area
<> 144:ef7eb2e8f9f7 45 (++) Know if the read protection is activated
<> 144:ef7eb2e8f9f7 46 (++) Get the value of the user Option Bytes
<> 144:ef7eb2e8f9f7 47 (++) Get the value of a PCROP area
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 @endverbatim
<> 144:ef7eb2e8f9f7 50 ******************************************************************************
<> 144:ef7eb2e8f9f7 51 * @attention
<> 144:ef7eb2e8f9f7 52 *
<> 144:ef7eb2e8f9f7 53 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 54 *
<> 144:ef7eb2e8f9f7 55 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 56 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 57 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 58 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 59 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 60 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 61 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 63 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 64 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 ******************************************************************************
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 84 * @{
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup FLASHEx FLASHEx
<> 144:ef7eb2e8f9f7 88 * @brief FALSH Extended HAL module driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #ifdef HAL_FLASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 97 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 /** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 extern FLASH_ProcessTypeDef pFlash;
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @}
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 107 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
<> 144:ef7eb2e8f9f7 111 void FLASH_PageErase(uint32_t Page, uint32_t Banks);
<> 144:ef7eb2e8f9f7 112 static void FLASH_MassErase(uint32_t Banks);
<> 144:ef7eb2e8f9f7 113 void FLASH_FlushCaches(void);
<> 144:ef7eb2e8f9f7 114 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
<> 144:ef7eb2e8f9f7 115 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
<> 144:ef7eb2e8f9f7 116 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
<> 144:ef7eb2e8f9f7 117 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
<> 144:ef7eb2e8f9f7 118 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
<> 144:ef7eb2e8f9f7 119 static uint32_t FLASH_OB_GetRDP(void);
<> 144:ef7eb2e8f9f7 120 static uint32_t FLASH_OB_GetUser(void);
<> 144:ef7eb2e8f9f7 121 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @}
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Exported functions -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
<> 144:ef7eb2e8f9f7 132 * @brief Extended IO operation functions
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 @verbatim
<> 144:ef7eb2e8f9f7 135 ===============================================================================
<> 144:ef7eb2e8f9f7 136 ##### Extended programming operation functions #####
<> 144:ef7eb2e8f9f7 137 ===============================================================================
<> 144:ef7eb2e8f9f7 138 [..]
<> 144:ef7eb2e8f9f7 139 This subsection provides a set of functions allowing to manage the Extended FLASH
<> 144:ef7eb2e8f9f7 140 programming operations Operations.
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 @endverbatim
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 /**
<> 144:ef7eb2e8f9f7 146 * @brief Perform a mass erase or erase the specified FLASH memory pages.
<> 144:ef7eb2e8f9f7 147 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
<> 144:ef7eb2e8f9f7 148 * contains the configuration information for the erasing.
<> 144:ef7eb2e8f9f7 149 *
<> 144:ef7eb2e8f9f7 150 * @param[out] PageError : pointer to variable that contains the configuration
<> 144:ef7eb2e8f9f7 151 * information on faulty page in case of error (0xFFFFFFFF means that all
<> 144:ef7eb2e8f9f7 152 * the pages have been correctly erased)
<> 144:ef7eb2e8f9f7 153 *
<> 144:ef7eb2e8f9f7 154 * @retval HAL Status
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 159 uint32_t page_index = 0;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /* Process Locked */
<> 144:ef7eb2e8f9f7 162 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Check the parameters */
<> 144:ef7eb2e8f9f7 165 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 168 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 if (status == HAL_OK)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 /* Mass erase to be done */
<> 144:ef7eb2e8f9f7 177 FLASH_MassErase(pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 180 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 183 /* If the erase operation is completed, disable the MER1 and MER2 Bits */
<> 144:ef7eb2e8f9f7 184 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
<> 144:ef7eb2e8f9f7 185 #else
<> 144:ef7eb2e8f9f7 186 /* If the erase operation is completed, disable the MER1 Bit */
<> 144:ef7eb2e8f9f7 187 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
<> 144:ef7eb2e8f9f7 188 #endif
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190 else
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /*Initialization of PageError variable*/
<> 144:ef7eb2e8f9f7 193 *PageError = 0xFFFFFFFF;
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 FLASH_PageErase(page_index, pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 200 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* If the erase operation is completed, disable the PER Bit */
<> 144:ef7eb2e8f9f7 203 CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 if (status != HAL_OK)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 /* In case of error, stop erase procedure and return the faulty address */
<> 144:ef7eb2e8f9f7 208 *PageError = page_index;
<> 144:ef7eb2e8f9f7 209 break;
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Flush the caches to be sure of the data consistency */
<> 144:ef7eb2e8f9f7 215 FLASH_FlushCaches();
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 219 __HAL_UNLOCK(&pFlash);
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 return status;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
<> 144:ef7eb2e8f9f7 226 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
<> 144:ef7eb2e8f9f7 227 * contains the configuration information for the erasing.
<> 144:ef7eb2e8f9f7 228 *
<> 144:ef7eb2e8f9f7 229 * @retval HAL Status
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Process Locked */
<> 144:ef7eb2e8f9f7 236 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Check the parameters */
<> 144:ef7eb2e8f9f7 239 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Enable End of Operation and Error interrupts */
<> 144:ef7eb2e8f9f7 244 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 pFlash.Bank = pEraseInit->Banks;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
<> 144:ef7eb2e8f9f7 249 {
<> 144:ef7eb2e8f9f7 250 /* Mass erase to be done */
<> 144:ef7eb2e8f9f7 251 pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
<> 144:ef7eb2e8f9f7 252 FLASH_MassErase(pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254 else
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 /* Erase by page to be done */
<> 144:ef7eb2e8f9f7 257 pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
<> 144:ef7eb2e8f9f7 258 pFlash.NbPagesToErase = pEraseInit->NbPages;
<> 144:ef7eb2e8f9f7 259 pFlash.Page = pEraseInit->Page;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /*Erase 1st page and wait for IT */
<> 144:ef7eb2e8f9f7 262 FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 return status;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @brief Program Option bytes.
<> 144:ef7eb2e8f9f7 270 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
<> 144:ef7eb2e8f9f7 271 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 272 *
<> 144:ef7eb2e8f9f7 273 * @retval HAL Status
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Process Locked */
<> 144:ef7eb2e8f9f7 280 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Check the parameters */
<> 144:ef7eb2e8f9f7 283 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Write protection configuration */
<> 144:ef7eb2e8f9f7 288 if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET)
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 /* Configure of Write protection on the selected area */
<> 144:ef7eb2e8f9f7 291 status = FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Read protection configuration */
<> 144:ef7eb2e8f9f7 295 if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Configure the Read protection level */
<> 144:ef7eb2e8f9f7 298 status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* User Configuration */
<> 144:ef7eb2e8f9f7 302 if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* Configure the user option bytes */
<> 144:ef7eb2e8f9f7 305 status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* PCROP Configuration */
<> 144:ef7eb2e8f9f7 309 if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 /* Configure the Proprietary code readout protection */
<> 144:ef7eb2e8f9f7 312 status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr);
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 316 __HAL_UNLOCK(&pFlash);
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 return status;
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @brief Get the Option bytes configuration.
<> 144:ef7eb2e8f9f7 323 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the
<> 144:ef7eb2e8f9f7 324 * configuration information. The fields pOBInit->WRPArea and
<> 144:ef7eb2e8f9f7 325 * pOBInit->PCROPConfig should indicate which area is requested
<> 144:ef7eb2e8f9f7 326 * for the WRP and PCROP
<> 144:ef7eb2e8f9f7 327 *
<> 144:ef7eb2e8f9f7 328 * @retval None
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 pOBInit->OptionType = (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP);
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Get write protection on the selected area */
<> 144:ef7eb2e8f9f7 335 FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Get Read protection level */
<> 144:ef7eb2e8f9f7 338 pOBInit->RDPLevel = FLASH_OB_GetRDP();
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Get the user option bytes */
<> 144:ef7eb2e8f9f7 341 pOBInit->USERConfig = FLASH_OB_GetUser();
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Get the Proprietary code readout protection */
<> 144:ef7eb2e8f9f7 344 FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @}
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /**
<> 144:ef7eb2e8f9f7 353 * @}
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /** @addtogroup FLASHEx_Private_Functions
<> 144:ef7eb2e8f9f7 359 * @{
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @brief Mass erase of FLASH memory.
<> 144:ef7eb2e8f9f7 363 * @param Banks: Banks to be erased
<> 144:ef7eb2e8f9f7 364 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 365 * @arg FLASH_BANK_1: Bank1 to be erased
<> 144:ef7eb2e8f9f7 366 * @arg FLASH_BANK_2: Bank2 to be erased
<> 144:ef7eb2e8f9f7 367 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 static void FLASH_MassErase(uint32_t Banks)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 /* Check the parameters */
<> 144:ef7eb2e8f9f7 373 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Set the Mass Erase Bit for the bank 1 if requested */
<> 144:ef7eb2e8f9f7 376 if((Banks & FLASH_BANK_1) != RESET)
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 SET_BIT(FLASH->CR, FLASH_CR_MER1);
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 382 /* Set the Mass Erase Bit for the bank 2 if requested */
<> 144:ef7eb2e8f9f7 383 if((Banks & FLASH_BANK_2) != RESET)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 SET_BIT(FLASH->CR, FLASH_CR_MER2);
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387 #endif
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Proceed to erase all sectors */
<> 144:ef7eb2e8f9f7 390 SET_BIT(FLASH->CR, FLASH_CR_STRT);
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @brief Erase the specified FLASH memory page.
<> 144:ef7eb2e8f9f7 395 * @param Page: FLASH page to erase
<> 144:ef7eb2e8f9f7 396 * This parameter must be a value between 0 and (max number of pages in the bank - 1)
<> 144:ef7eb2e8f9f7 397 * @param Banks: Bank(s) where the page will be erased
<> 144:ef7eb2e8f9f7 398 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 399 * @arg FLASH_BANK_1: Page in bank 1 to be erased
<> 144:ef7eb2e8f9f7 400 * @arg FLASH_BANK_2: Page in bank 2 to be erased
<> 144:ef7eb2e8f9f7 401 * @retval None
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 /* Check the parameters */
<> 144:ef7eb2e8f9f7 406 assert_param(IS_FLASH_PAGE(Page));
<> 144:ef7eb2e8f9f7 407 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 410 if((Banks & FLASH_BANK_1) != RESET)
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 else
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 SET_BIT(FLASH->CR, FLASH_CR_BKER);
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418 #endif
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Proceed to erase the page */
<> 144:ef7eb2e8f9f7 421 MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << 3));
<> 144:ef7eb2e8f9f7 422 SET_BIT(FLASH->CR, FLASH_CR_PER);
<> 144:ef7eb2e8f9f7 423 SET_BIT(FLASH->CR, FLASH_CR_STRT);
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @brief Flush the instruction and data caches.
<> 144:ef7eb2e8f9f7 428 * @retval None
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430 void FLASH_FlushCaches(void)
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 /* Flush instruction cache */
<> 144:ef7eb2e8f9f7 433 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 /* Disable instruction cache */
<> 144:ef7eb2e8f9f7 436 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
<> 144:ef7eb2e8f9f7 437 /* Reset instruction cache */
<> 144:ef7eb2e8f9f7 438 __HAL_FLASH_INSTRUCTION_CACHE_RESET();
<> 144:ef7eb2e8f9f7 439 /* Enable instruction cache */
<> 144:ef7eb2e8f9f7 440 __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Flush data cache */
<> 144:ef7eb2e8f9f7 444 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 /* Disable data cache */
<> 144:ef7eb2e8f9f7 447 __HAL_FLASH_DATA_CACHE_DISABLE();
<> 144:ef7eb2e8f9f7 448 /* Reset data cache */
<> 144:ef7eb2e8f9f7 449 __HAL_FLASH_DATA_CACHE_RESET();
<> 144:ef7eb2e8f9f7 450 /* Enable data cache */
<> 144:ef7eb2e8f9f7 451 __HAL_FLASH_DATA_CACHE_ENABLE();
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @brief Configure the write protection of the desired pages.
<> 144:ef7eb2e8f9f7 457 *
<> 144:ef7eb2e8f9f7 458 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 459 * it is not possible to program or erase Flash memory if the CPU debug
<> 144:ef7eb2e8f9f7 460 * features are connected (JTAG or single wire) or boot code is being
<> 144:ef7eb2e8f9f7 461 * executed from RAM or System flash, even if WRP is not activated.
<> 144:ef7eb2e8f9f7 462 * @note To configure the WRP options, the option lock bit OPTLOCK must be
<> 144:ef7eb2e8f9f7 463 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
<> 144:ef7eb2e8f9f7 464 * @note To validate the WRP options, the option bytes must be reloaded
<> 144:ef7eb2e8f9f7 465 * through the call of the HAL_FLASH_OB_Launch() function.
<> 144:ef7eb2e8f9f7 466 *
<> 144:ef7eb2e8f9f7 467 * @param WRPArea: specifies the area to be configured.
<> 144:ef7eb2e8f9f7 468 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 469 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
<> 144:ef7eb2e8f9f7 470 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
<> 144:ef7eb2e8f9f7 471 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices)
<> 144:ef7eb2e8f9f7 472 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices)
<> 144:ef7eb2e8f9f7 473 *
<> 144:ef7eb2e8f9f7 474 * @param WRPStartOffset: specifies the start page of the write protected area
<> 144:ef7eb2e8f9f7 475 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
<> 144:ef7eb2e8f9f7 476 *
<> 144:ef7eb2e8f9f7 477 * @param WRDPEndOffset: specifies the end page of the write protected area
<> 144:ef7eb2e8f9f7 478 * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
<> 144:ef7eb2e8f9f7 479 *
<> 144:ef7eb2e8f9f7 480 * @retval HAL Status
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /* Check the parameters */
<> 144:ef7eb2e8f9f7 487 assert_param(IS_OB_WRPAREA(WRPArea));
<> 144:ef7eb2e8f9f7 488 assert_param(IS_FLASH_PAGE(WRPStartOffset));
<> 144:ef7eb2e8f9f7 489 assert_param(IS_FLASH_PAGE(WRDPEndOffset));
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 492 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 /* Configure the write protected area */
<> 144:ef7eb2e8f9f7 497 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
<> 144:ef7eb2e8f9f7 500 (WRPStartOffset | (WRDPEndOffset << 16)));
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
<> 144:ef7eb2e8f9f7 505 (WRPStartOffset | (WRDPEndOffset << 16)));
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 508 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
<> 144:ef7eb2e8f9f7 511 (WRPStartOffset | (WRDPEndOffset << 16)));
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),
<> 144:ef7eb2e8f9f7 516 (WRPStartOffset | (WRDPEndOffset << 16)));
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518 #endif
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Set OPTSTRT Bit */
<> 144:ef7eb2e8f9f7 521 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 524 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
<> 144:ef7eb2e8f9f7 527 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 return status;
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @brief Set the read protection level.
<> 144:ef7eb2e8f9f7 535 *
<> 144:ef7eb2e8f9f7 536 * @note To configure the RDP level, the option lock bit OPTLOCK must be
<> 144:ef7eb2e8f9f7 537 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
<> 144:ef7eb2e8f9f7 538 * @note To validate the RDP level, the option bytes must be reloaded
<> 144:ef7eb2e8f9f7 539 * through the call of the HAL_FLASH_OB_Launch() function.
<> 144:ef7eb2e8f9f7 540 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
<> 144:ef7eb2e8f9f7 541 * to go back to level 1 or 0 !!!
<> 144:ef7eb2e8f9f7 542 *
<> 144:ef7eb2e8f9f7 543 * @param RDPLevel: specifies the read protection level.
<> 144:ef7eb2e8f9f7 544 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 545 * @arg OB_RDP_LEVEL_0: No protection
<> 144:ef7eb2e8f9f7 546 * @arg OB_RDP_LEVEL_1: Read protection of the memory
<> 144:ef7eb2e8f9f7 547 * @arg OB_RDP_LEVEL_2: Full chip protection
<> 144:ef7eb2e8f9f7 548 *
<> 144:ef7eb2e8f9f7 549 * @retval HAL status
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Check the parameters */
<> 144:ef7eb2e8f9f7 556 assert_param(IS_OB_RDP_LEVEL(RDPLevel));
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 559 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 /* Configure the RDP level in the option bytes register */
<> 144:ef7eb2e8f9f7 564 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Set OPTSTRT Bit */
<> 144:ef7eb2e8f9f7 567 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 570 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
<> 144:ef7eb2e8f9f7 573 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 return status;
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /**
<> 144:ef7eb2e8f9f7 580 * @brief Program the FLASH User Option Byte.
<> 144:ef7eb2e8f9f7 581 *
<> 144:ef7eb2e8f9f7 582 * @note To configure the user option bytes, the option lock bit OPTLOCK must
<> 144:ef7eb2e8f9f7 583 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
<> 144:ef7eb2e8f9f7 584 * @note To validate the user option bytes, the option bytes must be reloaded
<> 144:ef7eb2e8f9f7 585 * through the call of the HAL_FLASH_OB_Launch() function.
<> 144:ef7eb2e8f9f7 586 *
<> 144:ef7eb2e8f9f7 587 * @param UserType: The FLASH User Option Bytes to be modified
<> 144:ef7eb2e8f9f7 588 * @param UserConfig: The FLASH User Option Bytes values:
<> 144:ef7eb2e8f9f7 589 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
<> 144:ef7eb2e8f9f7 590 * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20),
<> 144:ef7eb2e8f9f7 591 * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
<> 144:ef7eb2e8f9f7 592 *
<> 144:ef7eb2e8f9f7 593 * @retval HAL status
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
<> 144:ef7eb2e8f9f7 596 {
<> 144:ef7eb2e8f9f7 597 uint32_t optr_reg_val = 0;
<> 144:ef7eb2e8f9f7 598 uint32_t optr_reg_mask = 0;
<> 144:ef7eb2e8f9f7 599 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Check the parameters */
<> 144:ef7eb2e8f9f7 602 assert_param(IS_OB_USER_TYPE(UserType));
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 605 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 if((UserType & OB_USER_BOR_LEV) != RESET)
<> 144:ef7eb2e8f9f7 610 {
<> 144:ef7eb2e8f9f7 611 /* BOR level option byte should be modified */
<> 144:ef7eb2e8f9f7 612 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /* Set value and mask for BOR level option byte */
<> 144:ef7eb2e8f9f7 615 optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
<> 144:ef7eb2e8f9f7 616 optr_reg_mask |= FLASH_OPTR_BOR_LEV;
<> 144:ef7eb2e8f9f7 617 }
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 if((UserType & OB_USER_nRST_STOP) != RESET)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 /* nRST_STOP option byte should be modified */
<> 144:ef7eb2e8f9f7 622 assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Set value and mask for nRST_STOP option byte */
<> 144:ef7eb2e8f9f7 625 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
<> 144:ef7eb2e8f9f7 626 optr_reg_mask |= FLASH_OPTR_nRST_STOP;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 if((UserType & OB_USER_nRST_STDBY) != RESET)
<> 144:ef7eb2e8f9f7 630 {
<> 144:ef7eb2e8f9f7 631 /* nRST_STDBY option byte should be modified */
<> 144:ef7eb2e8f9f7 632 assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Set value and mask for nRST_STDBY option byte */
<> 144:ef7eb2e8f9f7 635 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
<> 144:ef7eb2e8f9f7 636 optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 if((UserType & OB_USER_nRST_SHDW) != RESET)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 /* nRST_SHDW option byte should be modified */
<> 144:ef7eb2e8f9f7 642 assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /* Set value and mask for nRST_SHDW option byte */
<> 144:ef7eb2e8f9f7 645 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
<> 144:ef7eb2e8f9f7 646 optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 if((UserType & OB_USER_IWDG_SW) != RESET)
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 /* IWDG_SW option byte should be modified */
<> 144:ef7eb2e8f9f7 652 assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Set value and mask for IWDG_SW option byte */
<> 144:ef7eb2e8f9f7 655 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
<> 144:ef7eb2e8f9f7 656 optr_reg_mask |= FLASH_OPTR_IWDG_SW;
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 if((UserType & OB_USER_IWDG_STOP) != RESET)
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 /* IWDG_STOP option byte should be modified */
<> 144:ef7eb2e8f9f7 662 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Set value and mask for IWDG_STOP option byte */
<> 144:ef7eb2e8f9f7 665 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
<> 144:ef7eb2e8f9f7 666 optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 if((UserType & OB_USER_IWDG_STDBY) != RESET)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* IWDG_STDBY option byte should be modified */
<> 144:ef7eb2e8f9f7 672 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Set value and mask for IWDG_STDBY option byte */
<> 144:ef7eb2e8f9f7 675 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
<> 144:ef7eb2e8f9f7 676 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 if((UserType & OB_USER_WWDG_SW) != RESET)
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 /* WWDG_SW option byte should be modified */
<> 144:ef7eb2e8f9f7 682 assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Set value and mask for WWDG_SW option byte */
<> 144:ef7eb2e8f9f7 685 optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
<> 144:ef7eb2e8f9f7 686 optr_reg_mask |= FLASH_OPTR_WWDG_SW;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 690 if((UserType & OB_USER_BFB2) != RESET)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 /* BFB2 option byte should be modified */
<> 144:ef7eb2e8f9f7 693 assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Set value and mask for BFB2 option byte */
<> 144:ef7eb2e8f9f7 696 optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
<> 144:ef7eb2e8f9f7 697 optr_reg_mask |= FLASH_OPTR_BFB2;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 if((UserType & OB_USER_DUALBANK) != RESET)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 /* DUALBANK option byte should be modified */
<> 144:ef7eb2e8f9f7 703 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Set value and mask for DUALBANK option byte */
<> 144:ef7eb2e8f9f7 706 optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
<> 144:ef7eb2e8f9f7 707 optr_reg_mask |= FLASH_OPTR_DUALBANK;
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 #endif
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 if((UserType & OB_USER_nBOOT1) != RESET)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 /* nBOOT1 option byte should be modified */
<> 144:ef7eb2e8f9f7 714 assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /* Set value and mask for nBOOT1 option byte */
<> 144:ef7eb2e8f9f7 717 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
<> 144:ef7eb2e8f9f7 718 optr_reg_mask |= FLASH_OPTR_nBOOT1;
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 if((UserType & OB_USER_SRAM2_PE) != RESET)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 /* SRAM2_PE option byte should be modified */
<> 144:ef7eb2e8f9f7 724 assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Set value and mask for SRAM2_PE option byte */
<> 144:ef7eb2e8f9f7 727 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
<> 144:ef7eb2e8f9f7 728 optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 if((UserType & OB_USER_SRAM2_RST) != RESET)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 /* SRAM2_RST option byte should be modified */
<> 144:ef7eb2e8f9f7 734 assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Set value and mask for SRAM2_RST option byte */
<> 144:ef7eb2e8f9f7 737 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
<> 144:ef7eb2e8f9f7 738 optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
<> 144:ef7eb2e8f9f7 739 }
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
<> 144:ef7eb2e8f9f7 742 if((UserType & OB_USER_nSWBOOT0) != RESET)
<> 144:ef7eb2e8f9f7 743 {
<> 144:ef7eb2e8f9f7 744 /* nSWBOOT0 option byte should be modified */
<> 144:ef7eb2e8f9f7 745 assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /* Set value and mask for nSWBOOT0 option byte */
<> 144:ef7eb2e8f9f7 748 optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
<> 144:ef7eb2e8f9f7 749 optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
<> 144:ef7eb2e8f9f7 750 }
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 if((UserType & OB_USER_nBOOT0) != RESET)
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 /* nBOOT0 option byte should be modified */
<> 144:ef7eb2e8f9f7 755 assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Set value and mask for nBOOT0 option byte */
<> 144:ef7eb2e8f9f7 758 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
<> 144:ef7eb2e8f9f7 759 optr_reg_mask |= FLASH_OPTR_nBOOT0;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 #endif
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Configure the option bytes register */
<> 144:ef7eb2e8f9f7 764 MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Set OPTSTRT Bit */
<> 144:ef7eb2e8f9f7 767 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 770 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
<> 144:ef7eb2e8f9f7 773 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 return status;
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /**
<> 144:ef7eb2e8f9f7 780 * @brief Configure the Proprietary code readout protection of the desired addresses.
<> 144:ef7eb2e8f9f7 781 *
<> 144:ef7eb2e8f9f7 782 * @note To configure the PCROP options, the option lock bit OPTLOCK must be
<> 144:ef7eb2e8f9f7 783 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
<> 144:ef7eb2e8f9f7 784 * @note To validate the PCROP options, the option bytes must be reloaded
<> 144:ef7eb2e8f9f7 785 * through the call of the HAL_FLASH_OB_Launch() function.
<> 144:ef7eb2e8f9f7 786 *
<> 144:ef7eb2e8f9f7 787 * @param PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).
<> 144:ef7eb2e8f9f7 788 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
<> 144:ef7eb2e8f9f7 789 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
<> 144:ef7eb2e8f9f7 790 *
<> 144:ef7eb2e8f9f7 791 * @param PCROPStartAddr: specifies the start address of the Proprietary code readout protection
<> 144:ef7eb2e8f9f7 792 * This parameter can be an address between begin and end of the bank
<> 144:ef7eb2e8f9f7 793 *
<> 144:ef7eb2e8f9f7 794 * @param PCROPEndAddr: specifies the end address of the Proprietary code readout protection
<> 144:ef7eb2e8f9f7 795 * This parameter can be an address between PCROPStartAddr and end of the bank
<> 144:ef7eb2e8f9f7 796 *
<> 144:ef7eb2e8f9f7 797 * @retval HAL Status
<> 144:ef7eb2e8f9f7 798 */
<> 144:ef7eb2e8f9f7 799 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 802 uint32_t reg_value = 0;
<> 144:ef7eb2e8f9f7 803 uint32_t bank1_addr;
<> 144:ef7eb2e8f9f7 804 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 805 uint32_t bank2_addr;
<> 144:ef7eb2e8f9f7 806 #endif
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /* Check the parameters */
<> 144:ef7eb2e8f9f7 809 assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
<> 144:ef7eb2e8f9f7 810 assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
<> 144:ef7eb2e8f9f7 811 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
<> 144:ef7eb2e8f9f7 812 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 815 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 820 /* Get the information about the bank swapping */
<> 144:ef7eb2e8f9f7 821 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 bank1_addr = FLASH_BASE;
<> 144:ef7eb2e8f9f7 824 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 else
<> 144:ef7eb2e8f9f7 827 {
<> 144:ef7eb2e8f9f7 828 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
<> 144:ef7eb2e8f9f7 829 bank2_addr = FLASH_BASE;
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831 #else
<> 144:ef7eb2e8f9f7 832 bank1_addr = FLASH_BASE;
<> 144:ef7eb2e8f9f7 833 #endif
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /* Configure the Proprietary code readout protection */
<> 144:ef7eb2e8f9f7 836 if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
<> 144:ef7eb2e8f9f7 839 MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
<> 144:ef7eb2e8f9f7 842 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 845 else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
<> 144:ef7eb2e8f9f7 848 MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
<> 144:ef7eb2e8f9f7 851 MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853 #endif
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Set OPTSTRT Bit */
<> 144:ef7eb2e8f9f7 858 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 861 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
<> 144:ef7eb2e8f9f7 864 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
<> 144:ef7eb2e8f9f7 865 }
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 return status;
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /**
<> 144:ef7eb2e8f9f7 871 * @brief Return the FLASH Write Protection Option Bytes value.
<> 144:ef7eb2e8f9f7 872 *
<> 144:ef7eb2e8f9f7 873 * @param[in] WRPArea: specifies the area to be returned.
<> 144:ef7eb2e8f9f7 874 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 875 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
<> 144:ef7eb2e8f9f7 876 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
<> 144:ef7eb2e8f9f7 877 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)
<> 144:ef7eb2e8f9f7 878 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)
<> 144:ef7eb2e8f9f7 879 *
<> 144:ef7eb2e8f9f7 880 * @param[out] WRPStartOffset: specifies the address where to copied the start page
<> 144:ef7eb2e8f9f7 881 * of the write protected area
<> 144:ef7eb2e8f9f7 882 *
<> 144:ef7eb2e8f9f7 883 * @param[out] WRDPEndOffset: specifies the address where to copied the end page of
<> 144:ef7eb2e8f9f7 884 * the write protected area
<> 144:ef7eb2e8f9f7 885 *
<> 144:ef7eb2e8f9f7 886 * @retval None
<> 144:ef7eb2e8f9f7 887 */
<> 144:ef7eb2e8f9f7 888 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 /* Check the parameters */
<> 144:ef7eb2e8f9f7 891 assert_param(IS_OB_WRPAREA(WRPArea));
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /* Get the configuration of the write protected area */
<> 144:ef7eb2e8f9f7 894 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
<> 144:ef7eb2e8f9f7 895 {
<> 144:ef7eb2e8f9f7 896 *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
<> 144:ef7eb2e8f9f7 897 *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
<> 144:ef7eb2e8f9f7 898 }
<> 144:ef7eb2e8f9f7 899 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
<> 144:ef7eb2e8f9f7 902 *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
<> 144:ef7eb2e8f9f7 903 }
<> 144:ef7eb2e8f9f7 904 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 905 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
<> 144:ef7eb2e8f9f7 908 *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
<> 144:ef7eb2e8f9f7 911 {
<> 144:ef7eb2e8f9f7 912 *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
<> 144:ef7eb2e8f9f7 913 *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915 #endif
<> 144:ef7eb2e8f9f7 916 }
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /**
<> 144:ef7eb2e8f9f7 919 * @brief Return the FLASH Read Protection level.
<> 144:ef7eb2e8f9f7 920 * @retval FLASH ReadOut Protection Status:
<> 144:ef7eb2e8f9f7 921 * This return value can be one of the following values:
<> 144:ef7eb2e8f9f7 922 * @arg OB_RDP_LEVEL_0: No protection
<> 144:ef7eb2e8f9f7 923 * @arg OB_RDP_LEVEL_1: Read protection of the memory
<> 144:ef7eb2e8f9f7 924 * @arg OB_RDP_LEVEL_2: Full chip protection
<> 144:ef7eb2e8f9f7 925 */
<> 144:ef7eb2e8f9f7 926 static uint32_t FLASH_OB_GetRDP(void)
<> 144:ef7eb2e8f9f7 927 {
<> 144:ef7eb2e8f9f7 928 if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) &&
<> 144:ef7eb2e8f9f7 929 (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2))
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 return (OB_RDP_LEVEL_1);
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 else
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /**
<> 144:ef7eb2e8f9f7 940 * @brief Return the FLASH User Option Byte value.
<> 144:ef7eb2e8f9f7 941 * @retval The FLASH User Option Bytes values:
<> 144:ef7eb2e8f9f7 942 * For STM32L47x/STM32L48x devices :
<> 144:ef7eb2e8f9f7 943 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
<> 144:ef7eb2e8f9f7 944 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
<> 144:ef7eb2e8f9f7 945 * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
<> 144:ef7eb2e8f9f7 946 * For STM32L43x/STM32L44x devices :
<> 144:ef7eb2e8f9f7 947 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
<> 144:ef7eb2e8f9f7 948 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
<> 144:ef7eb2e8f9f7 949 * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).
<> 144:ef7eb2e8f9f7 950 */
<> 144:ef7eb2e8f9f7 951 static uint32_t FLASH_OB_GetUser(void)
<> 144:ef7eb2e8f9f7 952 {
<> 144:ef7eb2e8f9f7 953 uint32_t user_config = READ_REG(FLASH->OPTR);
<> 144:ef7eb2e8f9f7 954 CLEAR_BIT(user_config, FLASH_OPTR_RDP);
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 return user_config;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /**
<> 144:ef7eb2e8f9f7 960 * @brief Return the FLASH Write Protection Option Bytes value.
<> 144:ef7eb2e8f9f7 961 *
<> 144:ef7eb2e8f9f7 962 * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
<> 144:ef7eb2e8f9f7 963 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
<> 144:ef7eb2e8f9f7 964 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
<> 144:ef7eb2e8f9f7 965 *
<> 144:ef7eb2e8f9f7 966 * @param PCROPStartAddr [out]: specifies the address where to copied the start address
<> 144:ef7eb2e8f9f7 967 * of the Proprietary code readout protection
<> 144:ef7eb2e8f9f7 968 *
<> 144:ef7eb2e8f9f7 969 * @param PCROPEndAddr [out]: specifies the address where to copied the end address of
<> 144:ef7eb2e8f9f7 970 * the Proprietary code readout protection
<> 144:ef7eb2e8f9f7 971 *
<> 144:ef7eb2e8f9f7 972 * @retval None
<> 144:ef7eb2e8f9f7 973 */
<> 144:ef7eb2e8f9f7 974 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 uint32_t reg_value = 0;
<> 144:ef7eb2e8f9f7 977 uint32_t bank1_addr;
<> 144:ef7eb2e8f9f7 978 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 979 uint32_t bank2_addr;
<> 144:ef7eb2e8f9f7 980 #endif
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* Check the parameters */
<> 144:ef7eb2e8f9f7 983 assert_param(IS_FLASH_BANK_EXCLUSIVE((*PCROPConfig) & FLASH_BANK_BOTH));
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 986 /* Get the information about the bank swapping */
<> 144:ef7eb2e8f9f7 987 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 bank1_addr = FLASH_BASE;
<> 144:ef7eb2e8f9f7 990 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992 else
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
<> 144:ef7eb2e8f9f7 995 bank2_addr = FLASH_BASE;
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 #else
<> 144:ef7eb2e8f9f7 998 bank1_addr = FLASH_BASE;
<> 144:ef7eb2e8f9f7 999 #endif
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
<> 144:ef7eb2e8f9f7 1002 {
<> 144:ef7eb2e8f9f7 1003 reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
<> 144:ef7eb2e8f9f7 1004 *PCROPStartAddr = (reg_value << 3) + bank1_addr;
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
<> 144:ef7eb2e8f9f7 1007 *PCROPEndAddr = (reg_value << 3) + bank1_addr;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
<> 144:ef7eb2e8f9f7 1010 else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
<> 144:ef7eb2e8f9f7 1013 *PCROPStartAddr = (reg_value << 3) + bank2_addr;
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
<> 144:ef7eb2e8f9f7 1016 *PCROPEndAddr = (reg_value << 3) + bank2_addr;
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 #endif
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022 /**
<> 144:ef7eb2e8f9f7 1023 * @}
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /**
<> 144:ef7eb2e8f9f7 1027 * @}
<> 144:ef7eb2e8f9f7 1028 */
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 #endif /* HAL_FLASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /**
<> 144:ef7eb2e8f9f7 1033 * @}
<> 144:ef7eb2e8f9f7 1034 */
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 /**
<> 144:ef7eb2e8f9f7 1037 * @}
<> 144:ef7eb2e8f9f7 1038 */
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/