mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_adc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f2xx_hal_adc.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.1.3 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 29-June-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 8 | * functionalities of the Analog to Digital Convertor (ADC) peripheral: |
<> | 144:ef7eb2e8f9f7 | 9 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 10 | * + IO operation functions |
<> | 144:ef7eb2e8f9f7 | 11 | * + State and errors functions |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 14 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 15 | ##### ADC Peripheral features ##### |
<> | 144:ef7eb2e8f9f7 | 16 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 17 | [..] |
<> | 144:ef7eb2e8f9f7 | 18 | (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. |
<> | 144:ef7eb2e8f9f7 | 19 | (#) Interrupt generation at the end of conversion, end of injected conversion, |
<> | 144:ef7eb2e8f9f7 | 20 | and in case of analog watchdog or overrun events |
<> | 144:ef7eb2e8f9f7 | 21 | (#) Single and continuous conversion modes. |
<> | 144:ef7eb2e8f9f7 | 22 | (#) Scan mode for automatic conversion of channel 0 to channel x. |
<> | 144:ef7eb2e8f9f7 | 23 | (#) Data alignment with in-built data coherency. |
<> | 144:ef7eb2e8f9f7 | 24 | (#) Channel-wise programmable sampling time. |
<> | 144:ef7eb2e8f9f7 | 25 | (#) External trigger option with configurable polarity for both regular and |
<> | 144:ef7eb2e8f9f7 | 26 | injected conversion. |
<> | 144:ef7eb2e8f9f7 | 27 | (#) Dual/Triple mode (on devices with 2 ADCs or more). |
<> | 144:ef7eb2e8f9f7 | 28 | (#) Configurable DMA data storage in Dual/Triple ADC mode. |
<> | 144:ef7eb2e8f9f7 | 29 | (#) Configurable delay between conversions in Dual/Triple interleaved mode. |
<> | 144:ef7eb2e8f9f7 | 30 | (#) ADC conversion type (refer to the datasheets). |
<> | 144:ef7eb2e8f9f7 | 31 | (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
<> | 144:ef7eb2e8f9f7 | 32 | slower speed. |
<> | 144:ef7eb2e8f9f7 | 33 | (#) ADC input range: VREF(minus) = VIN = VREF(plus). |
<> | 144:ef7eb2e8f9f7 | 34 | (#) DMA request generation during regular channel conversion. |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 38 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 39 | [..] |
<> | 144:ef7eb2e8f9f7 | 40 | (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): |
<> | 144:ef7eb2e8f9f7 | 41 | (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 42 | (##) ADC pins configuration |
<> | 144:ef7eb2e8f9f7 | 43 | (+++) Enable the clock for the ADC GPIOs using the following function: |
<> | 144:ef7eb2e8f9f7 | 44 | __HAL_RCC_GPIOx_CLK_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 45 | (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() |
<> | 144:ef7eb2e8f9f7 | 46 | (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) |
<> | 144:ef7eb2e8f9f7 | 47 | (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() |
<> | 144:ef7eb2e8f9f7 | 48 | (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() |
<> | 144:ef7eb2e8f9f7 | 49 | (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 50 | (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) |
<> | 144:ef7eb2e8f9f7 | 51 | (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 52 | (+++) Configure and enable two DMA streams stream for managing data |
<> | 144:ef7eb2e8f9f7 | 53 | transfer from peripheral to memory (output stream) |
<> | 144:ef7eb2e8f9f7 | 54 | (+++) Associate the initialized DMA handle to the CRYP DMA handle |
<> | 144:ef7eb2e8f9f7 | 55 | using __HAL_LINKDMA() |
<> | 144:ef7eb2e8f9f7 | 56 | (+++) Configure the priority and enable the NVIC for the transfer complete |
<> | 144:ef7eb2e8f9f7 | 57 | interrupt on the two DMA Streams. The output stream should have higher |
<> | 144:ef7eb2e8f9f7 | 58 | priority than the input stream. |
<> | 144:ef7eb2e8f9f7 | 59 | |
<> | 144:ef7eb2e8f9f7 | 60 | *** Configuration of ADC, groups regular/injected, channels parameters *** |
<> | 144:ef7eb2e8f9f7 | 61 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 62 | [..] |
<> | 144:ef7eb2e8f9f7 | 63 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
<> | 144:ef7eb2e8f9f7 | 64 | and regular group parameters (conversion trigger, sequencer, ...) |
<> | 144:ef7eb2e8f9f7 | 65 | using function HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 66 | |
<> | 144:ef7eb2e8f9f7 | 67 | (#) Configure the channels for regular group parameters (channel number, |
<> | 144:ef7eb2e8f9f7 | 68 | channel rank into sequencer, ..., into regular group) |
<> | 144:ef7eb2e8f9f7 | 69 | using function HAL_ADC_ConfigChannel(). |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | (#) Optionally, configure the injected group parameters (conversion trigger, |
<> | 144:ef7eb2e8f9f7 | 72 | sequencer, ..., of injected group) |
<> | 144:ef7eb2e8f9f7 | 73 | and the channels for injected group parameters (channel number, |
<> | 144:ef7eb2e8f9f7 | 74 | channel rank into sequencer, ..., into injected group) |
<> | 144:ef7eb2e8f9f7 | 75 | using function HAL_ADCEx_InjectedConfigChannel(). |
<> | 144:ef7eb2e8f9f7 | 76 | |
<> | 144:ef7eb2e8f9f7 | 77 | (#) Optionally, configure the analog watchdog parameters (channels |
<> | 144:ef7eb2e8f9f7 | 78 | monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | (#) Optionally, for devices with several ADC instances: configure the |
<> | 144:ef7eb2e8f9f7 | 81 | multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). |
<> | 144:ef7eb2e8f9f7 | 82 | |
<> | 144:ef7eb2e8f9f7 | 83 | *** Execution of ADC conversions *** |
<> | 144:ef7eb2e8f9f7 | 84 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 85 | [..] |
<> | 144:ef7eb2e8f9f7 | 86 | (#) ADC driver can be used among three modes: polling, interruption, |
<> | 144:ef7eb2e8f9f7 | 87 | transfer by DMA. |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | *** Polling mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 90 | ================================= |
<> | 144:ef7eb2e8f9f7 | 91 | [..] |
<> | 144:ef7eb2e8f9f7 | 92 | (+) Start the ADC peripheral using HAL_ADC_Start() |
<> | 144:ef7eb2e8f9f7 | 93 | (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage |
<> | 144:ef7eb2e8f9f7 | 94 | user can specify the value of timeout according to his end application |
<> | 144:ef7eb2e8f9f7 | 95 | (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. |
<> | 144:ef7eb2e8f9f7 | 96 | (+) Stop the ADC peripheral using HAL_ADC_Stop() |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | *** Interrupt mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 99 | =================================== |
<> | 144:ef7eb2e8f9f7 | 100 | [..] |
<> | 144:ef7eb2e8f9f7 | 101 | (+) Start the ADC peripheral using HAL_ADC_Start_IT() |
<> | 144:ef7eb2e8f9f7 | 102 | (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine |
<> | 144:ef7eb2e8f9f7 | 103 | (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 104 | add his own code by customization of function pointer HAL_ADC_ConvCpltCallback |
<> | 144:ef7eb2e8f9f7 | 105 | (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 106 | add his own code by customization of function pointer HAL_ADC_ErrorCallback |
<> | 144:ef7eb2e8f9f7 | 107 | (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | *** DMA mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 110 | ============================== |
<> | 144:ef7eb2e8f9f7 | 111 | [..] |
<> | 144:ef7eb2e8f9f7 | 112 | (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length |
<> | 144:ef7eb2e8f9f7 | 113 | of data to be transferred at each end of conversion |
<> | 144:ef7eb2e8f9f7 | 114 | (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 115 | add his own code by customization of function pointer HAL_ADC_ConvCpltCallback |
<> | 144:ef7eb2e8f9f7 | 116 | (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 117 | add his own code by customization of function pointer HAL_ADC_ErrorCallback |
<> | 144:ef7eb2e8f9f7 | 118 | (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | *** ADC HAL driver macros list *** |
<> | 144:ef7eb2e8f9f7 | 121 | ============================================= |
<> | 144:ef7eb2e8f9f7 | 122 | [..] |
<> | 144:ef7eb2e8f9f7 | 123 | Below the list of most used macros in ADC HAL driver. |
<> | 144:ef7eb2e8f9f7 | 124 | |
<> | 144:ef7eb2e8f9f7 | 125 | (+) __HAL_ADC_ENABLE : Enable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 126 | (+) __HAL_ADC_DISABLE : Disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 127 | (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt |
<> | 144:ef7eb2e8f9f7 | 128 | (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt |
<> | 144:ef7eb2e8f9f7 | 129 | (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled |
<> | 144:ef7eb2e8f9f7 | 130 | (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags |
<> | 144:ef7eb2e8f9f7 | 131 | (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status |
<> | 144:ef7eb2e8f9f7 | 132 | (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | [..] |
<> | 144:ef7eb2e8f9f7 | 135 | (@) You can refer to the ADC HAL driver header file for more useful macros |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | *** Deinitialization of ADC *** |
<> | 144:ef7eb2e8f9f7 | 138 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 139 | [..] |
<> | 144:ef7eb2e8f9f7 | 140 | (#) Disable the ADC interface |
<> | 144:ef7eb2e8f9f7 | 141 | (++) ADC clock can be hard reset and disabled at RCC top level. |
<> | 144:ef7eb2e8f9f7 | 142 | (++) Hard reset of ADC peripherals |
<> | 144:ef7eb2e8f9f7 | 143 | using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). |
<> | 144:ef7eb2e8f9f7 | 144 | (++) ADC clock disable using the equivalent macro/functions as configuration step. |
<> | 144:ef7eb2e8f9f7 | 145 | (+++) Example: |
<> | 144:ef7eb2e8f9f7 | 146 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
<> | 144:ef7eb2e8f9f7 | 147 | other device clock parameters configuration: |
<> | 144:ef7eb2e8f9f7 | 148 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
<> | 144:ef7eb2e8f9f7 | 149 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
<> | 144:ef7eb2e8f9f7 | 150 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) |
<> | 144:ef7eb2e8f9f7 | 151 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | (#) ADC pins configuration |
<> | 144:ef7eb2e8f9f7 | 154 | (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
<> | 144:ef7eb2e8f9f7 | 155 | |
<> | 144:ef7eb2e8f9f7 | 156 | (#) Optionally, in case of usage of ADC with interruptions: |
<> | 144:ef7eb2e8f9f7 | 157 | (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | (#) Optionally, in case of usage of DMA: |
<> | 144:ef7eb2e8f9f7 | 160 | (++) Deinitialize the DMA using function HAL_DMA_DeInit(). |
<> | 144:ef7eb2e8f9f7 | 161 | (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 164 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 165 | * @attention |
<> | 144:ef7eb2e8f9f7 | 166 | * |
<> | 144:ef7eb2e8f9f7 | 167 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 168 | * |
<> | 144:ef7eb2e8f9f7 | 169 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 170 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 171 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 172 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 173 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 174 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 175 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 176 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 177 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 178 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 179 | * |
<> | 144:ef7eb2e8f9f7 | 180 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 181 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 182 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 183 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 184 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 185 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 186 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 187 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 188 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 189 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 190 | * |
<> | 144:ef7eb2e8f9f7 | 191 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 192 | */ |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 195 | #include "stm32f2xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 196 | |
<> | 144:ef7eb2e8f9f7 | 197 | /** @addtogroup STM32F2xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 198 | * @{ |
<> | 144:ef7eb2e8f9f7 | 199 | */ |
<> | 144:ef7eb2e8f9f7 | 200 | |
<> | 144:ef7eb2e8f9f7 | 201 | /** @defgroup ADC ADC |
<> | 144:ef7eb2e8f9f7 | 202 | * @brief ADC driver modules |
<> | 144:ef7eb2e8f9f7 | 203 | * @{ |
<> | 144:ef7eb2e8f9f7 | 204 | */ |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | #ifdef HAL_ADC_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 209 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 210 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 211 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 212 | /** @addtogroup ADC_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 213 | * @{ |
<> | 144:ef7eb2e8f9f7 | 214 | */ |
<> | 144:ef7eb2e8f9f7 | 215 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 216 | static void ADC_Init(ADC_HandleTypeDef* hadc); |
<> | 144:ef7eb2e8f9f7 | 217 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 218 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 219 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 220 | /** |
<> | 144:ef7eb2e8f9f7 | 221 | * @} |
<> | 144:ef7eb2e8f9f7 | 222 | */ |
<> | 144:ef7eb2e8f9f7 | 223 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 224 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
<> | 144:ef7eb2e8f9f7 | 225 | * @{ |
<> | 144:ef7eb2e8f9f7 | 226 | */ |
<> | 144:ef7eb2e8f9f7 | 227 | |
<> | 144:ef7eb2e8f9f7 | 228 | /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 229 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 230 | * |
<> | 144:ef7eb2e8f9f7 | 231 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 232 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 233 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 234 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 235 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 236 | (+) Initialize and configure the ADC. |
<> | 144:ef7eb2e8f9f7 | 237 | (+) De-initialize the ADC. |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 240 | * @{ |
<> | 144:ef7eb2e8f9f7 | 241 | */ |
<> | 144:ef7eb2e8f9f7 | 242 | |
<> | 144:ef7eb2e8f9f7 | 243 | /** |
<> | 144:ef7eb2e8f9f7 | 244 | * @brief Initializes the ADCx peripheral according to the specified parameters |
<> | 144:ef7eb2e8f9f7 | 245 | * in the ADC_InitStruct and initializes the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 246 | * |
<> | 144:ef7eb2e8f9f7 | 247 | * @note This function is used to configure the global features of the ADC ( |
<> | 144:ef7eb2e8f9f7 | 248 | * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, |
<> | 144:ef7eb2e8f9f7 | 249 | * the rest of the configuration parameters are specific to the regular |
<> | 144:ef7eb2e8f9f7 | 250 | * channels group (scan mode activation, continuous mode activation, |
<> | 144:ef7eb2e8f9f7 | 251 | * External trigger source and edge, DMA continuous request after the |
<> | 144:ef7eb2e8f9f7 | 252 | * last transfer and End of conversion selection). |
<> | 144:ef7eb2e8f9f7 | 253 | * |
<> | 144:ef7eb2e8f9f7 | 254 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 255 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 256 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 257 | */ |
<> | 144:ef7eb2e8f9f7 | 258 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 259 | { |
<> | 144:ef7eb2e8f9f7 | 260 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | /* Check ADC handle */ |
<> | 144:ef7eb2e8f9f7 | 263 | if(hadc == NULL) |
<> | 144:ef7eb2e8f9f7 | 264 | { |
<> | 144:ef7eb2e8f9f7 | 265 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 269 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 270 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
<> | 144:ef7eb2e8f9f7 | 271 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
<> | 144:ef7eb2e8f9f7 | 272 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode)); |
<> | 144:ef7eb2e8f9f7 | 273 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 274 | assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); |
<> | 144:ef7eb2e8f9f7 | 275 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
<> | 144:ef7eb2e8f9f7 | 276 | assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); |
<> | 144:ef7eb2e8f9f7 | 277 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
<> | 144:ef7eb2e8f9f7 | 278 | assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); |
<> | 144:ef7eb2e8f9f7 | 279 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 280 | |
<> | 144:ef7eb2e8f9f7 | 281 | if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
<> | 144:ef7eb2e8f9f7 | 282 | { |
<> | 144:ef7eb2e8f9f7 | 283 | assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
<> | 144:ef7eb2e8f9f7 | 284 | } |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | if(hadc->State == HAL_ADC_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 287 | { |
<> | 144:ef7eb2e8f9f7 | 288 | /* Initialize ADC error code */ |
<> | 144:ef7eb2e8f9f7 | 289 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 292 | hadc->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 293 | |
<> | 144:ef7eb2e8f9f7 | 294 | /* Init the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 295 | HAL_ADC_MspInit(hadc); |
<> | 144:ef7eb2e8f9f7 | 296 | } |
<> | 144:ef7eb2e8f9f7 | 297 | |
<> | 144:ef7eb2e8f9f7 | 298 | /* Configuration of ADC parameters if previous preliminary actions are */ |
<> | 144:ef7eb2e8f9f7 | 299 | /* correctly completed. */ |
<> | 144:ef7eb2e8f9f7 | 300 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
<> | 144:ef7eb2e8f9f7 | 301 | { |
<> | 144:ef7eb2e8f9f7 | 302 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 303 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 304 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
<> | 144:ef7eb2e8f9f7 | 305 | HAL_ADC_STATE_BUSY_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 306 | |
<> | 144:ef7eb2e8f9f7 | 307 | /* Set ADC parameters */ |
<> | 144:ef7eb2e8f9f7 | 308 | ADC_Init(hadc); |
<> | 144:ef7eb2e8f9f7 | 309 | |
<> | 144:ef7eb2e8f9f7 | 310 | /* Set ADC error code to none */ |
<> | 144:ef7eb2e8f9f7 | 311 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 312 | |
<> | 144:ef7eb2e8f9f7 | 313 | /* Set the ADC state */ |
<> | 144:ef7eb2e8f9f7 | 314 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 315 | HAL_ADC_STATE_BUSY_INTERNAL, |
<> | 144:ef7eb2e8f9f7 | 316 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 317 | } |
<> | 144:ef7eb2e8f9f7 | 318 | else |
<> | 144:ef7eb2e8f9f7 | 319 | { |
<> | 144:ef7eb2e8f9f7 | 320 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 321 | } |
<> | 144:ef7eb2e8f9f7 | 322 | |
<> | 144:ef7eb2e8f9f7 | 323 | /* Release Lock */ |
<> | 144:ef7eb2e8f9f7 | 324 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 325 | |
<> | 144:ef7eb2e8f9f7 | 326 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 327 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 328 | } |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | /** |
<> | 144:ef7eb2e8f9f7 | 331 | * @brief Deinitializes the ADCx peripheral registers to their default reset values. |
<> | 144:ef7eb2e8f9f7 | 332 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 333 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 334 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 335 | */ |
<> | 144:ef7eb2e8f9f7 | 336 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 337 | { |
<> | 144:ef7eb2e8f9f7 | 338 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /* Check ADC handle */ |
<> | 144:ef7eb2e8f9f7 | 341 | if(hadc == NULL) |
<> | 144:ef7eb2e8f9f7 | 342 | { |
<> | 144:ef7eb2e8f9f7 | 343 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 344 | } |
<> | 144:ef7eb2e8f9f7 | 345 | |
<> | 144:ef7eb2e8f9f7 | 346 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 347 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 350 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 351 | |
<> | 144:ef7eb2e8f9f7 | 352 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 353 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 354 | __HAL_ADC_DISABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 355 | |
<> | 144:ef7eb2e8f9f7 | 356 | /* Configuration of ADC parameters if previous preliminary actions are */ |
<> | 144:ef7eb2e8f9f7 | 357 | /* correctly completed. */ |
<> | 144:ef7eb2e8f9f7 | 358 | if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) |
<> | 144:ef7eb2e8f9f7 | 359 | { |
<> | 144:ef7eb2e8f9f7 | 360 | /* DeInit the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 361 | HAL_ADC_MspDeInit(hadc); |
<> | 144:ef7eb2e8f9f7 | 362 | |
<> | 144:ef7eb2e8f9f7 | 363 | /* Set ADC error code to none */ |
<> | 144:ef7eb2e8f9f7 | 364 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 365 | |
<> | 144:ef7eb2e8f9f7 | 366 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 367 | hadc->State = HAL_ADC_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 368 | } |
<> | 144:ef7eb2e8f9f7 | 369 | |
<> | 144:ef7eb2e8f9f7 | 370 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 371 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 372 | |
<> | 144:ef7eb2e8f9f7 | 373 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 374 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 375 | } |
<> | 144:ef7eb2e8f9f7 | 376 | |
<> | 144:ef7eb2e8f9f7 | 377 | /** |
<> | 144:ef7eb2e8f9f7 | 378 | * @brief Initializes the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 379 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 380 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 381 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 382 | */ |
<> | 144:ef7eb2e8f9f7 | 383 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 384 | { |
<> | 144:ef7eb2e8f9f7 | 385 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 386 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 387 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 388 | the HAL_ADC_MspInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 389 | */ |
<> | 144:ef7eb2e8f9f7 | 390 | } |
<> | 144:ef7eb2e8f9f7 | 391 | |
<> | 144:ef7eb2e8f9f7 | 392 | /** |
<> | 144:ef7eb2e8f9f7 | 393 | * @brief DeInitializes the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 394 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 395 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 396 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 397 | */ |
<> | 144:ef7eb2e8f9f7 | 398 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 399 | { |
<> | 144:ef7eb2e8f9f7 | 400 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 401 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 402 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 403 | the HAL_ADC_MspDeInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 404 | */ |
<> | 144:ef7eb2e8f9f7 | 405 | } |
<> | 144:ef7eb2e8f9f7 | 406 | |
<> | 144:ef7eb2e8f9f7 | 407 | /** |
<> | 144:ef7eb2e8f9f7 | 408 | * @} |
<> | 144:ef7eb2e8f9f7 | 409 | */ |
<> | 144:ef7eb2e8f9f7 | 410 | |
<> | 144:ef7eb2e8f9f7 | 411 | /** @defgroup ADC_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 412 | * @brief IO operation functions |
<> | 144:ef7eb2e8f9f7 | 413 | * |
<> | 144:ef7eb2e8f9f7 | 414 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 415 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 416 | ##### IO operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 417 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 418 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 419 | (+) Start conversion of regular channel. |
<> | 144:ef7eb2e8f9f7 | 420 | (+) Stop conversion of regular channel. |
<> | 144:ef7eb2e8f9f7 | 421 | (+) Start conversion of regular channel and enable interrupt. |
<> | 144:ef7eb2e8f9f7 | 422 | (+) Stop conversion of regular channel and disable interrupt. |
<> | 144:ef7eb2e8f9f7 | 423 | (+) Start conversion of regular channel and enable DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 424 | (+) Stop conversion of regular channel and disable DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 425 | (+) Handle ADC interrupt request. |
<> | 144:ef7eb2e8f9f7 | 426 | |
<> | 144:ef7eb2e8f9f7 | 427 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 428 | * @{ |
<> | 144:ef7eb2e8f9f7 | 429 | */ |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | /** |
<> | 144:ef7eb2e8f9f7 | 432 | * @brief Enables ADC and starts conversion of the regular channels. |
<> | 144:ef7eb2e8f9f7 | 433 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 434 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 435 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 436 | */ |
<> | 144:ef7eb2e8f9f7 | 437 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 438 | { |
<> | 144:ef7eb2e8f9f7 | 439 | __IO uint32_t counter = 0U; |
<> | 144:ef7eb2e8f9f7 | 440 | |
<> | 144:ef7eb2e8f9f7 | 441 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 442 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 443 | assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
<> | 144:ef7eb2e8f9f7 | 444 | |
<> | 144:ef7eb2e8f9f7 | 445 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 446 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 447 | |
<> | 144:ef7eb2e8f9f7 | 448 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 449 | /* Check if ADC peripheral is disabled in order to enable it and wait during |
<> | 144:ef7eb2e8f9f7 | 450 | Tstab time the ADC's stabilization */ |
<> | 144:ef7eb2e8f9f7 | 451 | if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) |
<> | 144:ef7eb2e8f9f7 | 452 | { |
<> | 144:ef7eb2e8f9f7 | 453 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 454 | __HAL_ADC_ENABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 455 | |
<> | 144:ef7eb2e8f9f7 | 456 | /* Delay for ADC stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 457 | /* Compute number of CPU cycles to wait for */ |
<> | 144:ef7eb2e8f9f7 | 458 | counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); |
<> | 144:ef7eb2e8f9f7 | 459 | while(counter != 0U) |
<> | 144:ef7eb2e8f9f7 | 460 | { |
<> | 144:ef7eb2e8f9f7 | 461 | counter--; |
<> | 144:ef7eb2e8f9f7 | 462 | } |
<> | 144:ef7eb2e8f9f7 | 463 | } |
<> | 144:ef7eb2e8f9f7 | 464 | |
<> | 144:ef7eb2e8f9f7 | 465 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 466 | if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) |
<> | 144:ef7eb2e8f9f7 | 467 | { |
<> | 144:ef7eb2e8f9f7 | 468 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 469 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 470 | /* - Set state bitfield related to regular group operation */ |
<> | 144:ef7eb2e8f9f7 | 471 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 472 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
<> | 144:ef7eb2e8f9f7 | 473 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 474 | |
<> | 144:ef7eb2e8f9f7 | 475 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 476 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 477 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
<> | 144:ef7eb2e8f9f7 | 478 | { |
<> | 144:ef7eb2e8f9f7 | 479 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 480 | } |
<> | 144:ef7eb2e8f9f7 | 481 | |
<> | 144:ef7eb2e8f9f7 | 482 | /* State machine update: Check if an injected conversion is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 483 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 484 | { |
<> | 144:ef7eb2e8f9f7 | 485 | /* Reset ADC error code fields related to conversions on group regular */ |
<> | 144:ef7eb2e8f9f7 | 486 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
<> | 144:ef7eb2e8f9f7 | 487 | } |
<> | 144:ef7eb2e8f9f7 | 488 | else |
<> | 144:ef7eb2e8f9f7 | 489 | { |
<> | 144:ef7eb2e8f9f7 | 490 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 491 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 492 | } |
<> | 144:ef7eb2e8f9f7 | 493 | |
<> | 144:ef7eb2e8f9f7 | 494 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 495 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 496 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 497 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 498 | |
<> | 144:ef7eb2e8f9f7 | 499 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 500 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
<> | 144:ef7eb2e8f9f7 | 501 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 502 | |
<> | 144:ef7eb2e8f9f7 | 503 | /* Check if Multimode enabled */ |
<> | 144:ef7eb2e8f9f7 | 504 | if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) |
<> | 144:ef7eb2e8f9f7 | 505 | { |
<> | 144:ef7eb2e8f9f7 | 506 | /* if no external trigger present enable software conversion of regular channels */ |
<> | 144:ef7eb2e8f9f7 | 507 | if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) |
<> | 144:ef7eb2e8f9f7 | 508 | { |
<> | 144:ef7eb2e8f9f7 | 509 | /* Enable the selected ADC software conversion for regular group */ |
<> | 144:ef7eb2e8f9f7 | 510 | hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; |
<> | 144:ef7eb2e8f9f7 | 511 | } |
<> | 144:ef7eb2e8f9f7 | 512 | } |
<> | 144:ef7eb2e8f9f7 | 513 | else |
<> | 144:ef7eb2e8f9f7 | 514 | { |
<> | 144:ef7eb2e8f9f7 | 515 | /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ |
<> | 144:ef7eb2e8f9f7 | 516 | if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) |
<> | 144:ef7eb2e8f9f7 | 517 | { |
<> | 144:ef7eb2e8f9f7 | 518 | /* Enable the selected ADC software conversion for regular group */ |
<> | 144:ef7eb2e8f9f7 | 519 | hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; |
<> | 144:ef7eb2e8f9f7 | 520 | } |
<> | 144:ef7eb2e8f9f7 | 521 | } |
<> | 144:ef7eb2e8f9f7 | 522 | } |
<> | 144:ef7eb2e8f9f7 | 523 | |
<> | 144:ef7eb2e8f9f7 | 524 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 525 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 526 | } |
<> | 144:ef7eb2e8f9f7 | 527 | |
<> | 144:ef7eb2e8f9f7 | 528 | /** |
<> | 144:ef7eb2e8f9f7 | 529 | * @brief Disables ADC and stop conversion of regular channels. |
<> | 144:ef7eb2e8f9f7 | 530 | * |
<> | 144:ef7eb2e8f9f7 | 531 | * @note Caution: This function will stop also injected channels. |
<> | 144:ef7eb2e8f9f7 | 532 | * |
<> | 144:ef7eb2e8f9f7 | 533 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 534 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 535 | * |
<> | 144:ef7eb2e8f9f7 | 536 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 537 | */ |
<> | 144:ef7eb2e8f9f7 | 538 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 539 | { |
<> | 144:ef7eb2e8f9f7 | 540 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 541 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 542 | |
<> | 144:ef7eb2e8f9f7 | 543 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 544 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 545 | |
<> | 144:ef7eb2e8f9f7 | 546 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 547 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 548 | __HAL_ADC_DISABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 549 | |
<> | 144:ef7eb2e8f9f7 | 550 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 551 | if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) |
<> | 144:ef7eb2e8f9f7 | 552 | { |
<> | 144:ef7eb2e8f9f7 | 553 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 554 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 555 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
<> | 144:ef7eb2e8f9f7 | 556 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 557 | } |
<> | 144:ef7eb2e8f9f7 | 558 | |
<> | 144:ef7eb2e8f9f7 | 559 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 560 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 561 | |
<> | 144:ef7eb2e8f9f7 | 562 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 563 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 564 | } |
<> | 144:ef7eb2e8f9f7 | 565 | |
<> | 144:ef7eb2e8f9f7 | 566 | /** |
<> | 144:ef7eb2e8f9f7 | 567 | * @brief Poll for regular conversion complete |
<> | 144:ef7eb2e8f9f7 | 568 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
<> | 144:ef7eb2e8f9f7 | 569 | * conversion) are cleared by this function. |
<> | 144:ef7eb2e8f9f7 | 570 | * @note This function cannot be used in a particular setup: ADC configured |
<> | 144:ef7eb2e8f9f7 | 571 | * in DMA mode and polling for end of each conversion (ADC init |
<> | 144:ef7eb2e8f9f7 | 572 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
<> | 144:ef7eb2e8f9f7 | 573 | * In this case, DMA resets the flag EOC and polling cannot be |
<> | 144:ef7eb2e8f9f7 | 574 | * performed on each conversion. Nevertheless, polling can still |
<> | 144:ef7eb2e8f9f7 | 575 | * be performed on the complete sequence. |
<> | 144:ef7eb2e8f9f7 | 576 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 577 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 578 | * @param Timeout: Timeout value in millisecond. |
<> | 144:ef7eb2e8f9f7 | 579 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 580 | */ |
<> | 144:ef7eb2e8f9f7 | 581 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 582 | { |
<> | 144:ef7eb2e8f9f7 | 583 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 584 | |
<> | 144:ef7eb2e8f9f7 | 585 | /* Verification that ADC configuration is compliant with polling for */ |
<> | 144:ef7eb2e8f9f7 | 586 | /* each conversion: */ |
<> | 144:ef7eb2e8f9f7 | 587 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
<> | 144:ef7eb2e8f9f7 | 588 | /* several ranks and polling for end of each conversion. */ |
<> | 144:ef7eb2e8f9f7 | 589 | /* For code simplicity sake, this particular case is generalized to */ |
<> | 144:ef7eb2e8f9f7 | 590 | /* ADC configured in DMA mode and polling for end of each conversion. */ |
<> | 144:ef7eb2e8f9f7 | 591 | if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && |
<> | 144:ef7eb2e8f9f7 | 592 | HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) |
<> | 144:ef7eb2e8f9f7 | 593 | { |
<> | 144:ef7eb2e8f9f7 | 594 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 595 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 596 | |
<> | 144:ef7eb2e8f9f7 | 597 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 598 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 144:ef7eb2e8f9f7 | 600 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 601 | } |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 604 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 605 | |
<> | 144:ef7eb2e8f9f7 | 606 | /* Check End of conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 607 | while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) |
<> | 144:ef7eb2e8f9f7 | 608 | { |
<> | 144:ef7eb2e8f9f7 | 609 | /* Check if timeout is disabled (set to infinite wait) */ |
<> | 144:ef7eb2e8f9f7 | 610 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 611 | { |
<> | 144:ef7eb2e8f9f7 | 612 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 613 | { |
<> | 144:ef7eb2e8f9f7 | 614 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 615 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 616 | |
<> | 144:ef7eb2e8f9f7 | 617 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 618 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 619 | |
<> | 144:ef7eb2e8f9f7 | 620 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 621 | } |
<> | 144:ef7eb2e8f9f7 | 622 | } |
<> | 144:ef7eb2e8f9f7 | 623 | } |
<> | 144:ef7eb2e8f9f7 | 624 | |
<> | 144:ef7eb2e8f9f7 | 625 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 626 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
<> | 144:ef7eb2e8f9f7 | 627 | |
<> | 144:ef7eb2e8f9f7 | 628 | /* Update ADC state machine */ |
<> | 144:ef7eb2e8f9f7 | 629 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 630 | |
<> | 144:ef7eb2e8f9f7 | 631 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 632 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 633 | /* Note: On STM32F2, there is no independent flag of end of sequence. */ |
<> | 144:ef7eb2e8f9f7 | 634 | /* The test of scan sequence on going is done either with scan */ |
<> | 144:ef7eb2e8f9f7 | 635 | /* sequence disabled or with end of conversion flag set to */ |
<> | 144:ef7eb2e8f9f7 | 636 | /* of end of sequence. */ |
<> | 144:ef7eb2e8f9f7 | 637 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 638 | (hadc->Init.ContinuousConvMode == DISABLE) && |
<> | 144:ef7eb2e8f9f7 | 639 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
<> | 144:ef7eb2e8f9f7 | 640 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
<> | 144:ef7eb2e8f9f7 | 641 | { |
<> | 144:ef7eb2e8f9f7 | 642 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 643 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 644 | |
<> | 144:ef7eb2e8f9f7 | 645 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 646 | { |
<> | 144:ef7eb2e8f9f7 | 647 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 648 | } |
<> | 144:ef7eb2e8f9f7 | 649 | } |
<> | 144:ef7eb2e8f9f7 | 650 | |
<> | 144:ef7eb2e8f9f7 | 651 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 652 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 653 | } |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | /** |
<> | 144:ef7eb2e8f9f7 | 656 | * @brief Poll for conversion event |
<> | 144:ef7eb2e8f9f7 | 657 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 658 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 659 | * @param EventType: the ADC event type. |
<> | 144:ef7eb2e8f9f7 | 660 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 661 | * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. |
<> | 144:ef7eb2e8f9f7 | 662 | * @arg ADC_OVR_EVENT: ADC Overrun event. |
<> | 144:ef7eb2e8f9f7 | 663 | * @param Timeout: Timeout value in millisecond. |
<> | 144:ef7eb2e8f9f7 | 664 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 665 | */ |
<> | 144:ef7eb2e8f9f7 | 666 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 667 | { |
<> | 144:ef7eb2e8f9f7 | 668 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 669 | |
<> | 144:ef7eb2e8f9f7 | 670 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 671 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 672 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
<> | 144:ef7eb2e8f9f7 | 673 | |
<> | 144:ef7eb2e8f9f7 | 674 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 675 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 676 | |
<> | 144:ef7eb2e8f9f7 | 677 | /* Check selected event flag */ |
<> | 144:ef7eb2e8f9f7 | 678 | while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) |
<> | 144:ef7eb2e8f9f7 | 679 | { |
<> | 144:ef7eb2e8f9f7 | 680 | /* Check for the Timeout */ |
<> | 144:ef7eb2e8f9f7 | 681 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 682 | { |
<> | 144:ef7eb2e8f9f7 | 683 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 684 | { |
<> | 144:ef7eb2e8f9f7 | 685 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 686 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 687 | |
<> | 144:ef7eb2e8f9f7 | 688 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 689 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 690 | |
<> | 144:ef7eb2e8f9f7 | 691 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 692 | } |
<> | 144:ef7eb2e8f9f7 | 693 | } |
<> | 144:ef7eb2e8f9f7 | 694 | } |
<> | 144:ef7eb2e8f9f7 | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | /* Analog watchdog (level out of window) event */ |
<> | 144:ef7eb2e8f9f7 | 697 | if(EventType == ADC_AWD_EVENT) |
<> | 144:ef7eb2e8f9f7 | 698 | { |
<> | 144:ef7eb2e8f9f7 | 699 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 700 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
<> | 144:ef7eb2e8f9f7 | 701 | |
<> | 144:ef7eb2e8f9f7 | 702 | /* Clear ADC analog watchdog flag */ |
<> | 144:ef7eb2e8f9f7 | 703 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 704 | } |
<> | 144:ef7eb2e8f9f7 | 705 | /* Overrun event */ |
<> | 144:ef7eb2e8f9f7 | 706 | else |
<> | 144:ef7eb2e8f9f7 | 707 | { |
<> | 144:ef7eb2e8f9f7 | 708 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 709 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
<> | 144:ef7eb2e8f9f7 | 710 | /* Set ADC error code to overrun */ |
<> | 144:ef7eb2e8f9f7 | 711 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
<> | 144:ef7eb2e8f9f7 | 712 | |
<> | 144:ef7eb2e8f9f7 | 713 | /* Clear ADC overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 714 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 715 | } |
<> | 144:ef7eb2e8f9f7 | 716 | |
<> | 144:ef7eb2e8f9f7 | 717 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 718 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 719 | } |
<> | 144:ef7eb2e8f9f7 | 720 | |
<> | 144:ef7eb2e8f9f7 | 721 | |
<> | 144:ef7eb2e8f9f7 | 722 | /** |
<> | 144:ef7eb2e8f9f7 | 723 | * @brief Enables the interrupt and starts ADC conversion of regular channels. |
<> | 144:ef7eb2e8f9f7 | 724 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 725 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 726 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 727 | */ |
<> | 144:ef7eb2e8f9f7 | 728 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 729 | { |
<> | 144:ef7eb2e8f9f7 | 730 | __IO uint32_t counter = 0U; |
<> | 144:ef7eb2e8f9f7 | 731 | |
<> | 144:ef7eb2e8f9f7 | 732 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 733 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 734 | assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
<> | 144:ef7eb2e8f9f7 | 735 | |
<> | 144:ef7eb2e8f9f7 | 736 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 737 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 738 | |
<> | 144:ef7eb2e8f9f7 | 739 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 740 | /* Check if ADC peripheral is disabled in order to enable it and wait during |
<> | 144:ef7eb2e8f9f7 | 741 | Tstab time the ADC's stabilization */ |
<> | 144:ef7eb2e8f9f7 | 742 | if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) |
<> | 144:ef7eb2e8f9f7 | 743 | { |
<> | 144:ef7eb2e8f9f7 | 744 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 745 | __HAL_ADC_ENABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 746 | |
<> | 144:ef7eb2e8f9f7 | 747 | /* Delay for ADC stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 748 | /* Compute number of CPU cycles to wait for */ |
<> | 144:ef7eb2e8f9f7 | 749 | counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); |
<> | 144:ef7eb2e8f9f7 | 750 | while(counter != 0U) |
<> | 144:ef7eb2e8f9f7 | 751 | { |
<> | 144:ef7eb2e8f9f7 | 752 | counter--; |
<> | 144:ef7eb2e8f9f7 | 753 | } |
<> | 144:ef7eb2e8f9f7 | 754 | } |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 757 | if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) |
<> | 144:ef7eb2e8f9f7 | 758 | { |
<> | 144:ef7eb2e8f9f7 | 759 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 760 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 761 | /* - Set state bitfield related to regular group operation */ |
<> | 144:ef7eb2e8f9f7 | 762 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 763 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
<> | 144:ef7eb2e8f9f7 | 764 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 765 | |
<> | 144:ef7eb2e8f9f7 | 766 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 767 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 768 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
<> | 144:ef7eb2e8f9f7 | 769 | { |
<> | 144:ef7eb2e8f9f7 | 770 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 771 | } |
<> | 144:ef7eb2e8f9f7 | 772 | |
<> | 144:ef7eb2e8f9f7 | 773 | /* State machine update: Check if an injected conversion is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 774 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 775 | { |
<> | 144:ef7eb2e8f9f7 | 776 | /* Reset ADC error code fields related to conversions on group regular */ |
<> | 144:ef7eb2e8f9f7 | 777 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
<> | 144:ef7eb2e8f9f7 | 778 | } |
<> | 144:ef7eb2e8f9f7 | 779 | else |
<> | 144:ef7eb2e8f9f7 | 780 | { |
<> | 144:ef7eb2e8f9f7 | 781 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 782 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 783 | } |
<> | 144:ef7eb2e8f9f7 | 784 | |
<> | 144:ef7eb2e8f9f7 | 785 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 786 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 787 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 788 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 789 | |
<> | 144:ef7eb2e8f9f7 | 790 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 791 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
<> | 144:ef7eb2e8f9f7 | 792 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 793 | |
<> | 144:ef7eb2e8f9f7 | 794 | /* Enable end of conversion interrupt for regular group */ |
<> | 144:ef7eb2e8f9f7 | 795 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); |
<> | 144:ef7eb2e8f9f7 | 796 | |
<> | 144:ef7eb2e8f9f7 | 797 | /* Check if Multimode enabled */ |
<> | 144:ef7eb2e8f9f7 | 798 | if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) |
<> | 144:ef7eb2e8f9f7 | 799 | { |
<> | 144:ef7eb2e8f9f7 | 800 | /* if no external trigger present enable software conversion of regular channels */ |
<> | 144:ef7eb2e8f9f7 | 801 | if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) |
<> | 144:ef7eb2e8f9f7 | 802 | { |
<> | 144:ef7eb2e8f9f7 | 803 | /* Enable the selected ADC software conversion for regular group */ |
<> | 144:ef7eb2e8f9f7 | 804 | hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; |
<> | 144:ef7eb2e8f9f7 | 805 | } |
<> | 144:ef7eb2e8f9f7 | 806 | } |
<> | 144:ef7eb2e8f9f7 | 807 | else |
<> | 144:ef7eb2e8f9f7 | 808 | { |
<> | 144:ef7eb2e8f9f7 | 809 | /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ |
<> | 144:ef7eb2e8f9f7 | 810 | if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) |
<> | 144:ef7eb2e8f9f7 | 811 | { |
<> | 144:ef7eb2e8f9f7 | 812 | /* Enable the selected ADC software conversion for regular group */ |
<> | 144:ef7eb2e8f9f7 | 813 | hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; |
<> | 144:ef7eb2e8f9f7 | 814 | } |
<> | 144:ef7eb2e8f9f7 | 815 | } |
<> | 144:ef7eb2e8f9f7 | 816 | } |
<> | 144:ef7eb2e8f9f7 | 817 | |
<> | 144:ef7eb2e8f9f7 | 818 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 819 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 820 | } |
<> | 144:ef7eb2e8f9f7 | 821 | |
<> | 144:ef7eb2e8f9f7 | 822 | /** |
<> | 144:ef7eb2e8f9f7 | 823 | * @brief Disables the interrupt and stop ADC conversion of regular channels. |
<> | 144:ef7eb2e8f9f7 | 824 | * |
<> | 144:ef7eb2e8f9f7 | 825 | * @note Caution: This function will stop also injected channels. |
<> | 144:ef7eb2e8f9f7 | 826 | * |
<> | 144:ef7eb2e8f9f7 | 827 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 828 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 829 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 830 | */ |
<> | 144:ef7eb2e8f9f7 | 831 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 832 | { |
<> | 144:ef7eb2e8f9f7 | 833 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 834 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 835 | |
<> | 144:ef7eb2e8f9f7 | 836 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 837 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 838 | |
<> | 144:ef7eb2e8f9f7 | 839 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 840 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 841 | __HAL_ADC_DISABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 842 | |
<> | 144:ef7eb2e8f9f7 | 843 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 844 | if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) |
<> | 144:ef7eb2e8f9f7 | 845 | { |
<> | 144:ef7eb2e8f9f7 | 846 | /* Disable ADC end of conversion interrupt for regular group */ |
<> | 144:ef7eb2e8f9f7 | 847 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); |
<> | 144:ef7eb2e8f9f7 | 848 | |
<> | 144:ef7eb2e8f9f7 | 849 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 850 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 851 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
<> | 144:ef7eb2e8f9f7 | 852 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 853 | } |
<> | 144:ef7eb2e8f9f7 | 854 | |
<> | 144:ef7eb2e8f9f7 | 855 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 856 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 857 | |
<> | 144:ef7eb2e8f9f7 | 858 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 859 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 860 | } |
<> | 144:ef7eb2e8f9f7 | 861 | |
<> | 144:ef7eb2e8f9f7 | 862 | /** |
<> | 144:ef7eb2e8f9f7 | 863 | * @brief Handles ADC interrupt request |
<> | 144:ef7eb2e8f9f7 | 864 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 865 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 866 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 867 | */ |
<> | 144:ef7eb2e8f9f7 | 868 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 869 | { |
<> | 144:ef7eb2e8f9f7 | 870 | uint32_t tmp1 = 0U, tmp2 = 0U; |
<> | 144:ef7eb2e8f9f7 | 871 | |
<> | 144:ef7eb2e8f9f7 | 872 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 873 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 874 | assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); |
<> | 144:ef7eb2e8f9f7 | 875 | assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); |
<> | 144:ef7eb2e8f9f7 | 876 | |
<> | 144:ef7eb2e8f9f7 | 877 | tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); |
<> | 144:ef7eb2e8f9f7 | 878 | tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); |
<> | 144:ef7eb2e8f9f7 | 879 | /* Check End of conversion flag for regular channels */ |
<> | 144:ef7eb2e8f9f7 | 880 | if(tmp1 && tmp2) |
<> | 144:ef7eb2e8f9f7 | 881 | { |
<> | 144:ef7eb2e8f9f7 | 882 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 883 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
<> | 144:ef7eb2e8f9f7 | 884 | { |
<> | 144:ef7eb2e8f9f7 | 885 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 886 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 887 | } |
<> | 144:ef7eb2e8f9f7 | 888 | |
<> | 144:ef7eb2e8f9f7 | 889 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 890 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 891 | /* Note: On STM32F2, there is no independent flag of end of sequence. */ |
<> | 144:ef7eb2e8f9f7 | 892 | /* The test of scan sequence on going is done either with scan */ |
<> | 144:ef7eb2e8f9f7 | 893 | /* sequence disabled or with end of conversion flag set to */ |
<> | 144:ef7eb2e8f9f7 | 894 | /* of end of sequence. */ |
<> | 144:ef7eb2e8f9f7 | 895 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 896 | (hadc->Init.ContinuousConvMode == DISABLE) && |
<> | 144:ef7eb2e8f9f7 | 897 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
<> | 144:ef7eb2e8f9f7 | 898 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
<> | 144:ef7eb2e8f9f7 | 899 | { |
<> | 144:ef7eb2e8f9f7 | 900 | /* Disable ADC end of single conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 901 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
<> | 144:ef7eb2e8f9f7 | 902 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
<> | 144:ef7eb2e8f9f7 | 903 | /* by overrun IRQ process below. */ |
<> | 144:ef7eb2e8f9f7 | 904 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
<> | 144:ef7eb2e8f9f7 | 905 | |
<> | 144:ef7eb2e8f9f7 | 906 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 907 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 908 | |
<> | 144:ef7eb2e8f9f7 | 909 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 910 | { |
<> | 144:ef7eb2e8f9f7 | 911 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 912 | } |
<> | 144:ef7eb2e8f9f7 | 913 | } |
<> | 144:ef7eb2e8f9f7 | 914 | |
<> | 144:ef7eb2e8f9f7 | 915 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 916 | HAL_ADC_ConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 917 | |
<> | 144:ef7eb2e8f9f7 | 918 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 919 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
<> | 144:ef7eb2e8f9f7 | 920 | } |
<> | 144:ef7eb2e8f9f7 | 921 | |
<> | 144:ef7eb2e8f9f7 | 922 | tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); |
<> | 144:ef7eb2e8f9f7 | 923 | tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); |
<> | 144:ef7eb2e8f9f7 | 924 | /* Check End of conversion flag for injected channels */ |
<> | 144:ef7eb2e8f9f7 | 925 | if(tmp1 && tmp2) |
<> | 144:ef7eb2e8f9f7 | 926 | { |
<> | 144:ef7eb2e8f9f7 | 927 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 928 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
<> | 144:ef7eb2e8f9f7 | 929 | { |
<> | 144:ef7eb2e8f9f7 | 930 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 931 | SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); |
<> | 144:ef7eb2e8f9f7 | 932 | } |
<> | 144:ef7eb2e8f9f7 | 933 | |
<> | 144:ef7eb2e8f9f7 | 934 | /* Determine whether any further conversion upcoming on group injected */ |
<> | 144:ef7eb2e8f9f7 | 935 | /* by external trigger, scan sequence on going or by automatic injected */ |
<> | 144:ef7eb2e8f9f7 | 936 | /* conversion from group regular (same conditions as group regular */ |
<> | 144:ef7eb2e8f9f7 | 937 | /* interruption disabling above). */ |
<> | 144:ef7eb2e8f9f7 | 938 | if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
<> | 144:ef7eb2e8f9f7 | 939 | (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || |
<> | 144:ef7eb2e8f9f7 | 940 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && |
<> | 144:ef7eb2e8f9f7 | 941 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
<> | 144:ef7eb2e8f9f7 | 942 | (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 943 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
<> | 144:ef7eb2e8f9f7 | 944 | { |
<> | 144:ef7eb2e8f9f7 | 945 | /* Disable ADC end of single conversion interrupt on group injected */ |
<> | 144:ef7eb2e8f9f7 | 946 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
<> | 144:ef7eb2e8f9f7 | 947 | |
<> | 144:ef7eb2e8f9f7 | 948 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 949 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 950 | |
<> | 144:ef7eb2e8f9f7 | 951 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 952 | { |
<> | 144:ef7eb2e8f9f7 | 953 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 954 | } |
<> | 144:ef7eb2e8f9f7 | 955 | } |
<> | 144:ef7eb2e8f9f7 | 956 | |
<> | 144:ef7eb2e8f9f7 | 957 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 958 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 959 | |
<> | 144:ef7eb2e8f9f7 | 960 | /* Clear injected group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 961 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); |
<> | 144:ef7eb2e8f9f7 | 962 | } |
<> | 144:ef7eb2e8f9f7 | 963 | |
<> | 144:ef7eb2e8f9f7 | 964 | tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 965 | tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 966 | /* Check Analog watchdog flag */ |
<> | 144:ef7eb2e8f9f7 | 967 | if(tmp1 && tmp2) |
<> | 144:ef7eb2e8f9f7 | 968 | { |
<> | 144:ef7eb2e8f9f7 | 969 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) |
<> | 144:ef7eb2e8f9f7 | 970 | { |
<> | 144:ef7eb2e8f9f7 | 971 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 972 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
<> | 144:ef7eb2e8f9f7 | 973 | |
<> | 144:ef7eb2e8f9f7 | 974 | /* Level out of window callback */ |
<> | 144:ef7eb2e8f9f7 | 975 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 976 | |
<> | 144:ef7eb2e8f9f7 | 977 | /* Clear the ADC analog watchdog flag */ |
<> | 144:ef7eb2e8f9f7 | 978 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 979 | } |
<> | 144:ef7eb2e8f9f7 | 980 | } |
<> | 144:ef7eb2e8f9f7 | 981 | |
<> | 144:ef7eb2e8f9f7 | 982 | tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 983 | tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); |
<> | 144:ef7eb2e8f9f7 | 984 | /* Check Overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 985 | if(tmp1 && tmp2) |
<> | 144:ef7eb2e8f9f7 | 986 | { |
<> | 144:ef7eb2e8f9f7 | 987 | /* Note: On STM32F2, ADC overrun can be set through other parameters */ |
<> | 144:ef7eb2e8f9f7 | 988 | /* refer to description of parameter "EOCSelection" for more */ |
<> | 144:ef7eb2e8f9f7 | 989 | /* details. */ |
<> | 144:ef7eb2e8f9f7 | 990 | |
<> | 144:ef7eb2e8f9f7 | 991 | /* Set ADC error code to overrun */ |
<> | 144:ef7eb2e8f9f7 | 992 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
<> | 144:ef7eb2e8f9f7 | 993 | |
<> | 144:ef7eb2e8f9f7 | 994 | /* Clear ADC overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 995 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 996 | |
<> | 144:ef7eb2e8f9f7 | 997 | /* Error callback */ |
<> | 144:ef7eb2e8f9f7 | 998 | HAL_ADC_ErrorCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 999 | |
<> | 144:ef7eb2e8f9f7 | 1000 | /* Clear the Overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1001 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1002 | } |
<> | 144:ef7eb2e8f9f7 | 1003 | } |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | /** |
<> | 144:ef7eb2e8f9f7 | 1006 | * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 1007 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1008 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1009 | * @param pData: The destination Buffer address. |
<> | 144:ef7eb2e8f9f7 | 1010 | * @param Length: The length of data to be transferred from ADC peripheral to memory. |
<> | 144:ef7eb2e8f9f7 | 1011 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1012 | */ |
<> | 144:ef7eb2e8f9f7 | 1013 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
<> | 144:ef7eb2e8f9f7 | 1014 | { |
<> | 144:ef7eb2e8f9f7 | 1015 | __IO uint32_t counter = 0U; |
<> | 144:ef7eb2e8f9f7 | 1016 | |
<> | 144:ef7eb2e8f9f7 | 1017 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1018 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 1019 | assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
<> | 144:ef7eb2e8f9f7 | 1020 | |
<> | 144:ef7eb2e8f9f7 | 1021 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1022 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1023 | |
<> | 144:ef7eb2e8f9f7 | 1024 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1025 | /* Check if ADC peripheral is disabled in order to enable it and wait during |
<> | 144:ef7eb2e8f9f7 | 1026 | Tstab time the ADC's stabilization */ |
<> | 144:ef7eb2e8f9f7 | 1027 | if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) |
<> | 144:ef7eb2e8f9f7 | 1028 | { |
<> | 144:ef7eb2e8f9f7 | 1029 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1030 | __HAL_ADC_ENABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1031 | |
<> | 144:ef7eb2e8f9f7 | 1032 | /* Delay for ADC stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 1033 | /* Compute number of CPU cycles to wait for */ |
<> | 144:ef7eb2e8f9f7 | 1034 | counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); |
<> | 144:ef7eb2e8f9f7 | 1035 | while(counter != 0U) |
<> | 144:ef7eb2e8f9f7 | 1036 | { |
<> | 144:ef7eb2e8f9f7 | 1037 | counter--; |
<> | 144:ef7eb2e8f9f7 | 1038 | } |
<> | 144:ef7eb2e8f9f7 | 1039 | } |
<> | 144:ef7eb2e8f9f7 | 1040 | |
<> | 144:ef7eb2e8f9f7 | 1041 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1042 | if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) |
<> | 144:ef7eb2e8f9f7 | 1043 | { |
<> | 144:ef7eb2e8f9f7 | 1044 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1045 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 1046 | /* - Set state bitfield related to regular group operation */ |
<> | 144:ef7eb2e8f9f7 | 1047 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1048 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
<> | 144:ef7eb2e8f9f7 | 1049 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1050 | |
<> | 144:ef7eb2e8f9f7 | 1051 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 1052 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 1053 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1054 | { |
<> | 144:ef7eb2e8f9f7 | 1055 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1056 | } |
<> | 144:ef7eb2e8f9f7 | 1057 | |
<> | 144:ef7eb2e8f9f7 | 1058 | /* State machine update: Check if an injected conversion is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 1059 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 1060 | { |
<> | 144:ef7eb2e8f9f7 | 1061 | /* Reset ADC error code fields related to conversions on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1062 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
<> | 144:ef7eb2e8f9f7 | 1063 | } |
<> | 144:ef7eb2e8f9f7 | 1064 | else |
<> | 144:ef7eb2e8f9f7 | 1065 | { |
<> | 144:ef7eb2e8f9f7 | 1066 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 1067 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1068 | } |
<> | 144:ef7eb2e8f9f7 | 1069 | |
<> | 144:ef7eb2e8f9f7 | 1070 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1071 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 1072 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 1073 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1074 | |
<> | 144:ef7eb2e8f9f7 | 1075 | /* Set the DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1076 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
<> | 144:ef7eb2e8f9f7 | 1077 | |
<> | 144:ef7eb2e8f9f7 | 1078 | /* Set the DMA half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1079 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
<> | 144:ef7eb2e8f9f7 | 1080 | |
<> | 144:ef7eb2e8f9f7 | 1081 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1082 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1083 | |
<> | 144:ef7eb2e8f9f7 | 1084 | |
<> | 144:ef7eb2e8f9f7 | 1085 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
<> | 144:ef7eb2e8f9f7 | 1086 | /* start (in case of SW start): */ |
<> | 144:ef7eb2e8f9f7 | 1087 | |
<> | 144:ef7eb2e8f9f7 | 1088 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1089 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
<> | 144:ef7eb2e8f9f7 | 1090 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1091 | |
<> | 144:ef7eb2e8f9f7 | 1092 | /* Enable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1093 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
<> | 144:ef7eb2e8f9f7 | 1094 | |
<> | 144:ef7eb2e8f9f7 | 1095 | /* Enable ADC DMA mode */ |
<> | 144:ef7eb2e8f9f7 | 1096 | hadc->Instance->CR2 |= ADC_CR2_DMA; |
<> | 144:ef7eb2e8f9f7 | 1097 | |
<> | 144:ef7eb2e8f9f7 | 1098 | /* Start the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1099 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
<> | 144:ef7eb2e8f9f7 | 1100 | |
<> | 144:ef7eb2e8f9f7 | 1101 | /* Check if Multimode enabled */ |
<> | 144:ef7eb2e8f9f7 | 1102 | if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) |
<> | 144:ef7eb2e8f9f7 | 1103 | { |
<> | 144:ef7eb2e8f9f7 | 1104 | /* if no external trigger present enable software conversion of regular channels */ |
<> | 144:ef7eb2e8f9f7 | 1105 | if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1106 | { |
<> | 144:ef7eb2e8f9f7 | 1107 | /* Enable the selected ADC software conversion for regular group */ |
<> | 144:ef7eb2e8f9f7 | 1108 | hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; |
<> | 144:ef7eb2e8f9f7 | 1109 | } |
<> | 144:ef7eb2e8f9f7 | 1110 | } |
<> | 144:ef7eb2e8f9f7 | 1111 | else |
<> | 144:ef7eb2e8f9f7 | 1112 | { |
<> | 144:ef7eb2e8f9f7 | 1113 | /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ |
<> | 144:ef7eb2e8f9f7 | 1114 | if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) |
<> | 144:ef7eb2e8f9f7 | 1115 | { |
<> | 144:ef7eb2e8f9f7 | 1116 | /* Enable the selected ADC software conversion for regular group */ |
<> | 144:ef7eb2e8f9f7 | 1117 | hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; |
<> | 144:ef7eb2e8f9f7 | 1118 | } |
<> | 144:ef7eb2e8f9f7 | 1119 | } |
<> | 144:ef7eb2e8f9f7 | 1120 | } |
<> | 144:ef7eb2e8f9f7 | 1121 | |
<> | 144:ef7eb2e8f9f7 | 1122 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1123 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1124 | } |
<> | 144:ef7eb2e8f9f7 | 1125 | |
<> | 144:ef7eb2e8f9f7 | 1126 | /** |
<> | 144:ef7eb2e8f9f7 | 1127 | * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 1128 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1129 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1130 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1131 | */ |
<> | 144:ef7eb2e8f9f7 | 1132 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1133 | { |
<> | 144:ef7eb2e8f9f7 | 1134 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1135 | |
<> | 144:ef7eb2e8f9f7 | 1136 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1137 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1138 | |
<> | 144:ef7eb2e8f9f7 | 1139 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1140 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1141 | |
<> | 144:ef7eb2e8f9f7 | 1142 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 1143 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1144 | __HAL_ADC_DISABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1145 | |
<> | 144:ef7eb2e8f9f7 | 1146 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1147 | if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) |
<> | 144:ef7eb2e8f9f7 | 1148 | { |
<> | 144:ef7eb2e8f9f7 | 1149 | /* Disable the selected ADC DMA mode */ |
<> | 144:ef7eb2e8f9f7 | 1150 | hadc->Instance->CR2 &= ~ADC_CR2_DMA; |
<> | 144:ef7eb2e8f9f7 | 1151 | |
<> | 144:ef7eb2e8f9f7 | 1152 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
<> | 144:ef7eb2e8f9f7 | 1153 | /* DMA transfer is on going) */ |
<> | 144:ef7eb2e8f9f7 | 1154 | tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); |
<> | 144:ef7eb2e8f9f7 | 1155 | |
<> | 144:ef7eb2e8f9f7 | 1156 | /* Disable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1157 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
<> | 144:ef7eb2e8f9f7 | 1158 | |
<> | 144:ef7eb2e8f9f7 | 1159 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1160 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1161 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1162 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1163 | } |
<> | 144:ef7eb2e8f9f7 | 1164 | |
<> | 144:ef7eb2e8f9f7 | 1165 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1166 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1167 | |
<> | 144:ef7eb2e8f9f7 | 1168 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1169 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1170 | } |
<> | 144:ef7eb2e8f9f7 | 1171 | |
<> | 144:ef7eb2e8f9f7 | 1172 | /** |
<> | 144:ef7eb2e8f9f7 | 1173 | * @brief Gets the converted value from data register of regular channel. |
<> | 144:ef7eb2e8f9f7 | 1174 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1175 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1176 | * @retval Converted value |
<> | 144:ef7eb2e8f9f7 | 1177 | */ |
<> | 144:ef7eb2e8f9f7 | 1178 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1179 | { |
<> | 144:ef7eb2e8f9f7 | 1180 | /* Return the selected ADC converted value */ |
<> | 144:ef7eb2e8f9f7 | 1181 | return hadc->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 1182 | } |
<> | 144:ef7eb2e8f9f7 | 1183 | |
<> | 144:ef7eb2e8f9f7 | 1184 | /** |
<> | 144:ef7eb2e8f9f7 | 1185 | * @brief Regular conversion complete callback in non blocking mode |
<> | 144:ef7eb2e8f9f7 | 1186 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1187 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1188 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1189 | */ |
<> | 144:ef7eb2e8f9f7 | 1190 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1191 | { |
<> | 144:ef7eb2e8f9f7 | 1192 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1193 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1194 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1195 | the HAL_ADC_ConvCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1196 | */ |
<> | 144:ef7eb2e8f9f7 | 1197 | } |
<> | 144:ef7eb2e8f9f7 | 1198 | |
<> | 144:ef7eb2e8f9f7 | 1199 | /** |
<> | 144:ef7eb2e8f9f7 | 1200 | * @brief Regular conversion half DMA transfer callback in non blocking mode |
<> | 144:ef7eb2e8f9f7 | 1201 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1202 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1203 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1204 | */ |
<> | 144:ef7eb2e8f9f7 | 1205 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1206 | { |
<> | 144:ef7eb2e8f9f7 | 1207 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1208 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1209 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1210 | the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1211 | */ |
<> | 144:ef7eb2e8f9f7 | 1212 | } |
<> | 144:ef7eb2e8f9f7 | 1213 | |
<> | 144:ef7eb2e8f9f7 | 1214 | /** |
<> | 144:ef7eb2e8f9f7 | 1215 | * @brief Analog watchdog callback in non blocking mode |
<> | 144:ef7eb2e8f9f7 | 1216 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1217 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1218 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1219 | */ |
<> | 144:ef7eb2e8f9f7 | 1220 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1221 | { |
<> | 144:ef7eb2e8f9f7 | 1222 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1223 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1224 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1225 | the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1226 | */ |
<> | 144:ef7eb2e8f9f7 | 1227 | } |
<> | 144:ef7eb2e8f9f7 | 1228 | |
<> | 144:ef7eb2e8f9f7 | 1229 | /** |
<> | 144:ef7eb2e8f9f7 | 1230 | * @brief Error ADC callback. |
<> | 144:ef7eb2e8f9f7 | 1231 | * @note In case of error due to overrun when using ADC with DMA transfer |
<> | 144:ef7eb2e8f9f7 | 1232 | * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): |
<> | 144:ef7eb2e8f9f7 | 1233 | * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". |
<> | 144:ef7eb2e8f9f7 | 1234 | * - If needed, restart a new ADC conversion using function |
<> | 144:ef7eb2e8f9f7 | 1235 | * "HAL_ADC_Start_DMA()" |
<> | 144:ef7eb2e8f9f7 | 1236 | * (this function is also clearing overrun flag) |
<> | 144:ef7eb2e8f9f7 | 1237 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1238 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1239 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1240 | */ |
<> | 144:ef7eb2e8f9f7 | 1241 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
<> | 144:ef7eb2e8f9f7 | 1242 | { |
<> | 144:ef7eb2e8f9f7 | 1243 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1244 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1245 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1246 | the HAL_ADC_ErrorCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1247 | */ |
<> | 144:ef7eb2e8f9f7 | 1248 | } |
<> | 144:ef7eb2e8f9f7 | 1249 | |
<> | 144:ef7eb2e8f9f7 | 1250 | /** |
<> | 144:ef7eb2e8f9f7 | 1251 | * @} |
<> | 144:ef7eb2e8f9f7 | 1252 | */ |
<> | 144:ef7eb2e8f9f7 | 1253 | |
<> | 144:ef7eb2e8f9f7 | 1254 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 1255 | * @brief Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 1256 | * |
<> | 144:ef7eb2e8f9f7 | 1257 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1258 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1259 | ##### Peripheral Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 1260 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1261 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 1262 | (+) Configure regular channels. |
<> | 144:ef7eb2e8f9f7 | 1263 | (+) Configure injected channels. |
<> | 144:ef7eb2e8f9f7 | 1264 | (+) Configure multimode. |
<> | 144:ef7eb2e8f9f7 | 1265 | (+) Configure the analog watch dog. |
<> | 144:ef7eb2e8f9f7 | 1266 | |
<> | 144:ef7eb2e8f9f7 | 1267 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1268 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1269 | */ |
<> | 144:ef7eb2e8f9f7 | 1270 | |
<> | 144:ef7eb2e8f9f7 | 1271 | /** |
<> | 144:ef7eb2e8f9f7 | 1272 | * @brief Configures for the selected ADC regular channel its corresponding |
<> | 144:ef7eb2e8f9f7 | 1273 | * rank in the sequencer and its sample time. |
<> | 144:ef7eb2e8f9f7 | 1274 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1275 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1276 | * @param sConfig: ADC configuration structure. |
<> | 144:ef7eb2e8f9f7 | 1277 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1278 | */ |
<> | 144:ef7eb2e8f9f7 | 1279 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
<> | 144:ef7eb2e8f9f7 | 1280 | { |
<> | 144:ef7eb2e8f9f7 | 1281 | __IO uint32_t counter = 0U; |
<> | 144:ef7eb2e8f9f7 | 1282 | |
<> | 144:ef7eb2e8f9f7 | 1283 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1284 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1285 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
<> | 144:ef7eb2e8f9f7 | 1286 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
<> | 144:ef7eb2e8f9f7 | 1287 | |
<> | 144:ef7eb2e8f9f7 | 1288 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1289 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1290 | |
<> | 144:ef7eb2e8f9f7 | 1291 | /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ |
<> | 144:ef7eb2e8f9f7 | 1292 | if (sConfig->Channel > ADC_CHANNEL_9) |
<> | 144:ef7eb2e8f9f7 | 1293 | { |
<> | 144:ef7eb2e8f9f7 | 1294 | /* Clear the old sample time */ |
<> | 144:ef7eb2e8f9f7 | 1295 | hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); |
<> | 144:ef7eb2e8f9f7 | 1296 | |
<> | 144:ef7eb2e8f9f7 | 1297 | /* Set the new sample time */ |
<> | 144:ef7eb2e8f9f7 | 1298 | hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); |
<> | 144:ef7eb2e8f9f7 | 1299 | } |
<> | 144:ef7eb2e8f9f7 | 1300 | else /* ADC_Channel include in ADC_Channel_[0..9] */ |
<> | 144:ef7eb2e8f9f7 | 1301 | { |
<> | 144:ef7eb2e8f9f7 | 1302 | /* Clear the old sample time */ |
<> | 144:ef7eb2e8f9f7 | 1303 | hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); |
<> | 144:ef7eb2e8f9f7 | 1304 | |
<> | 144:ef7eb2e8f9f7 | 1305 | /* Set the new sample time */ |
<> | 144:ef7eb2e8f9f7 | 1306 | hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); |
<> | 144:ef7eb2e8f9f7 | 1307 | } |
<> | 144:ef7eb2e8f9f7 | 1308 | |
<> | 144:ef7eb2e8f9f7 | 1309 | /* For Rank 1 to 6 */ |
<> | 144:ef7eb2e8f9f7 | 1310 | if (sConfig->Rank < 7U) |
<> | 144:ef7eb2e8f9f7 | 1311 | { |
<> | 144:ef7eb2e8f9f7 | 1312 | /* Clear the old SQx bits for the selected rank */ |
<> | 144:ef7eb2e8f9f7 | 1313 | hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); |
<> | 144:ef7eb2e8f9f7 | 1314 | |
<> | 144:ef7eb2e8f9f7 | 1315 | /* Set the SQx bits for the selected rank */ |
<> | 144:ef7eb2e8f9f7 | 1316 | hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); |
<> | 144:ef7eb2e8f9f7 | 1317 | } |
<> | 144:ef7eb2e8f9f7 | 1318 | /* For Rank 7 to 12 */ |
<> | 144:ef7eb2e8f9f7 | 1319 | else if (sConfig->Rank < 13U) |
<> | 144:ef7eb2e8f9f7 | 1320 | { |
<> | 144:ef7eb2e8f9f7 | 1321 | /* Clear the old SQx bits for the selected rank */ |
<> | 144:ef7eb2e8f9f7 | 1322 | hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); |
<> | 144:ef7eb2e8f9f7 | 1323 | |
<> | 144:ef7eb2e8f9f7 | 1324 | /* Set the SQx bits for the selected rank */ |
<> | 144:ef7eb2e8f9f7 | 1325 | hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); |
<> | 144:ef7eb2e8f9f7 | 1326 | } |
<> | 144:ef7eb2e8f9f7 | 1327 | /* For Rank 13 to 16 */ |
<> | 144:ef7eb2e8f9f7 | 1328 | else |
<> | 144:ef7eb2e8f9f7 | 1329 | { |
<> | 144:ef7eb2e8f9f7 | 1330 | /* Clear the old SQx bits for the selected rank */ |
<> | 144:ef7eb2e8f9f7 | 1331 | hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); |
<> | 144:ef7eb2e8f9f7 | 1332 | |
<> | 144:ef7eb2e8f9f7 | 1333 | /* Set the SQx bits for the selected rank */ |
<> | 144:ef7eb2e8f9f7 | 1334 | hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); |
<> | 144:ef7eb2e8f9f7 | 1335 | } |
<> | 144:ef7eb2e8f9f7 | 1336 | |
<> | 144:ef7eb2e8f9f7 | 1337 | /* if ADC1 Channel_18 is selected enable VBAT Channel */ |
<> | 144:ef7eb2e8f9f7 | 1338 | if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) |
<> | 144:ef7eb2e8f9f7 | 1339 | { |
<> | 144:ef7eb2e8f9f7 | 1340 | /* Enable the VBAT channel*/ |
<> | 144:ef7eb2e8f9f7 | 1341 | ADC->CCR |= ADC_CCR_VBATE; |
<> | 144:ef7eb2e8f9f7 | 1342 | } |
<> | 144:ef7eb2e8f9f7 | 1343 | |
<> | 144:ef7eb2e8f9f7 | 1344 | /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ |
<> | 144:ef7eb2e8f9f7 | 1345 | if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) |
<> | 144:ef7eb2e8f9f7 | 1346 | { |
<> | 144:ef7eb2e8f9f7 | 1347 | /* Enable the TSVREFE channel*/ |
<> | 144:ef7eb2e8f9f7 | 1348 | ADC->CCR |= ADC_CCR_TSVREFE; |
<> | 144:ef7eb2e8f9f7 | 1349 | |
<> | 144:ef7eb2e8f9f7 | 1350 | if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) |
<> | 144:ef7eb2e8f9f7 | 1351 | { |
<> | 144:ef7eb2e8f9f7 | 1352 | /* Delay for temperature sensor stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 1353 | /* Compute number of CPU cycles to wait for */ |
<> | 144:ef7eb2e8f9f7 | 1354 | counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); |
<> | 144:ef7eb2e8f9f7 | 1355 | while(counter != 0U) |
<> | 144:ef7eb2e8f9f7 | 1356 | { |
<> | 144:ef7eb2e8f9f7 | 1357 | counter--; |
<> | 144:ef7eb2e8f9f7 | 1358 | } |
<> | 144:ef7eb2e8f9f7 | 1359 | } |
<> | 144:ef7eb2e8f9f7 | 1360 | } |
<> | 144:ef7eb2e8f9f7 | 1361 | |
<> | 144:ef7eb2e8f9f7 | 1362 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1363 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1364 | |
<> | 144:ef7eb2e8f9f7 | 1365 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1366 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1367 | } |
<> | 144:ef7eb2e8f9f7 | 1368 | |
<> | 144:ef7eb2e8f9f7 | 1369 | /** |
<> | 144:ef7eb2e8f9f7 | 1370 | * @brief Configures the analog watchdog. |
<> | 144:ef7eb2e8f9f7 | 1371 | * @note Analog watchdog thresholds can be modified while ADC conversion |
<> | 144:ef7eb2e8f9f7 | 1372 | * is on going. |
<> | 144:ef7eb2e8f9f7 | 1373 | * In this case, some constraints must be taken into account: |
<> | 144:ef7eb2e8f9f7 | 1374 | * The programmed threshold values are effective from the next |
<> | 144:ef7eb2e8f9f7 | 1375 | * ADC EOC (end of unitary conversion). |
<> | 144:ef7eb2e8f9f7 | 1376 | * Considering that registers write delay may happen due to |
<> | 144:ef7eb2e8f9f7 | 1377 | * bus activity, this might cause an uncertainty on the |
<> | 144:ef7eb2e8f9f7 | 1378 | * effective timing of the new programmed threshold values. |
<> | 144:ef7eb2e8f9f7 | 1379 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1380 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1381 | * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure |
<> | 144:ef7eb2e8f9f7 | 1382 | * that contains the configuration information of ADC analog watchdog. |
<> | 144:ef7eb2e8f9f7 | 1383 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1384 | */ |
<> | 144:ef7eb2e8f9f7 | 1385 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
<> | 144:ef7eb2e8f9f7 | 1386 | { |
<> | 144:ef7eb2e8f9f7 | 1387 | #ifdef USE_FULL_ASSERT |
<> | 144:ef7eb2e8f9f7 | 1388 | uint32_t tmp = 0U; |
<> | 144:ef7eb2e8f9f7 | 1389 | #endif /* USE_FULL_ASSERT */ |
<> | 144:ef7eb2e8f9f7 | 1390 | |
<> | 144:ef7eb2e8f9f7 | 1391 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1392 | assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); |
<> | 144:ef7eb2e8f9f7 | 1393 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1394 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
<> | 144:ef7eb2e8f9f7 | 1395 | |
<> | 144:ef7eb2e8f9f7 | 1396 | #ifdef USE_FULL_ASSERT |
<> | 144:ef7eb2e8f9f7 | 1397 | tmp = ADC_GET_RESOLUTION(hadc); |
<> | 144:ef7eb2e8f9f7 | 1398 | assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); |
<> | 144:ef7eb2e8f9f7 | 1399 | assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); |
<> | 144:ef7eb2e8f9f7 | 1400 | #endif /* USE_FULL_ASSERT */ |
<> | 144:ef7eb2e8f9f7 | 1401 | |
<> | 144:ef7eb2e8f9f7 | 1402 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1403 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1404 | |
<> | 144:ef7eb2e8f9f7 | 1405 | if(AnalogWDGConfig->ITMode == ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1406 | { |
<> | 144:ef7eb2e8f9f7 | 1407 | /* Enable the ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1408 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1409 | } |
<> | 144:ef7eb2e8f9f7 | 1410 | else |
<> | 144:ef7eb2e8f9f7 | 1411 | { |
<> | 144:ef7eb2e8f9f7 | 1412 | /* Disable the ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1413 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1414 | } |
<> | 144:ef7eb2e8f9f7 | 1415 | |
<> | 144:ef7eb2e8f9f7 | 1416 | /* Clear AWDEN, JAWDEN and AWDSGL bits */ |
<> | 144:ef7eb2e8f9f7 | 1417 | hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); |
<> | 144:ef7eb2e8f9f7 | 1418 | |
<> | 144:ef7eb2e8f9f7 | 1419 | /* Set the analog watchdog enable mode */ |
<> | 144:ef7eb2e8f9f7 | 1420 | hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; |
<> | 144:ef7eb2e8f9f7 | 1421 | |
<> | 144:ef7eb2e8f9f7 | 1422 | /* Set the high threshold */ |
<> | 144:ef7eb2e8f9f7 | 1423 | hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; |
<> | 144:ef7eb2e8f9f7 | 1424 | |
<> | 144:ef7eb2e8f9f7 | 1425 | /* Set the low threshold */ |
<> | 144:ef7eb2e8f9f7 | 1426 | hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; |
<> | 144:ef7eb2e8f9f7 | 1427 | |
<> | 144:ef7eb2e8f9f7 | 1428 | /* Clear the Analog watchdog channel select bits */ |
<> | 144:ef7eb2e8f9f7 | 1429 | hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; |
<> | 144:ef7eb2e8f9f7 | 1430 | |
<> | 144:ef7eb2e8f9f7 | 1431 | /* Set the Analog watchdog channel */ |
<> | 144:ef7eb2e8f9f7 | 1432 | hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1433 | |
<> | 144:ef7eb2e8f9f7 | 1434 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1435 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1436 | |
<> | 144:ef7eb2e8f9f7 | 1437 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1438 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1439 | } |
<> | 144:ef7eb2e8f9f7 | 1440 | |
<> | 144:ef7eb2e8f9f7 | 1441 | /** |
<> | 144:ef7eb2e8f9f7 | 1442 | * @} |
<> | 144:ef7eb2e8f9f7 | 1443 | */ |
<> | 144:ef7eb2e8f9f7 | 1444 | |
<> | 144:ef7eb2e8f9f7 | 1445 | /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1446 | * @brief ADC Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1447 | * |
<> | 144:ef7eb2e8f9f7 | 1448 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1449 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1450 | ##### Peripheral State and errors functions ##### |
<> | 144:ef7eb2e8f9f7 | 1451 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1452 | [..] |
<> | 144:ef7eb2e8f9f7 | 1453 | This subsection provides functions allowing to |
<> | 144:ef7eb2e8f9f7 | 1454 | (+) Check the ADC state |
<> | 144:ef7eb2e8f9f7 | 1455 | (+) Check the ADC Error |
<> | 144:ef7eb2e8f9f7 | 1456 | |
<> | 144:ef7eb2e8f9f7 | 1457 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1458 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1459 | */ |
<> | 144:ef7eb2e8f9f7 | 1460 | |
<> | 144:ef7eb2e8f9f7 | 1461 | /** |
<> | 144:ef7eb2e8f9f7 | 1462 | * @brief return the ADC state |
<> | 144:ef7eb2e8f9f7 | 1463 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1464 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1465 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 1466 | */ |
<> | 144:ef7eb2e8f9f7 | 1467 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1468 | { |
<> | 144:ef7eb2e8f9f7 | 1469 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1470 | return hadc->State; |
<> | 144:ef7eb2e8f9f7 | 1471 | } |
<> | 144:ef7eb2e8f9f7 | 1472 | |
<> | 144:ef7eb2e8f9f7 | 1473 | /** |
<> | 144:ef7eb2e8f9f7 | 1474 | * @brief Return the ADC error code |
<> | 144:ef7eb2e8f9f7 | 1475 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1476 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1477 | * @retval ADC Error Code |
<> | 144:ef7eb2e8f9f7 | 1478 | */ |
<> | 144:ef7eb2e8f9f7 | 1479 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
<> | 144:ef7eb2e8f9f7 | 1480 | { |
<> | 144:ef7eb2e8f9f7 | 1481 | return hadc->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1482 | } |
<> | 144:ef7eb2e8f9f7 | 1483 | |
<> | 144:ef7eb2e8f9f7 | 1484 | /** |
<> | 144:ef7eb2e8f9f7 | 1485 | * @} |
<> | 144:ef7eb2e8f9f7 | 1486 | */ |
<> | 144:ef7eb2e8f9f7 | 1487 | |
<> | 144:ef7eb2e8f9f7 | 1488 | /** @addtogroup ADC_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 1489 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1490 | */ |
<> | 144:ef7eb2e8f9f7 | 1491 | |
<> | 144:ef7eb2e8f9f7 | 1492 | /** |
<> | 144:ef7eb2e8f9f7 | 1493 | * @brief Initializes the ADCx peripheral according to the specified parameters |
<> | 144:ef7eb2e8f9f7 | 1494 | * in the ADC_InitStruct without initializing the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 1495 | * @param hadc: pointer to a ADC_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1496 | * the configuration information for the specified ADC. |
<> | 144:ef7eb2e8f9f7 | 1497 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1498 | */ |
<> | 144:ef7eb2e8f9f7 | 1499 | static void ADC_Init(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1500 | { |
<> | 144:ef7eb2e8f9f7 | 1501 | /* Set ADC parameters */ |
<> | 144:ef7eb2e8f9f7 | 1502 | /* Set the ADC clock prescaler */ |
<> | 144:ef7eb2e8f9f7 | 1503 | ADC->CCR &= ~(ADC_CCR_ADCPRE); |
<> | 144:ef7eb2e8f9f7 | 1504 | ADC->CCR |= hadc->Init.ClockPrescaler; |
<> | 144:ef7eb2e8f9f7 | 1505 | |
<> | 144:ef7eb2e8f9f7 | 1506 | /* Set ADC scan mode */ |
<> | 144:ef7eb2e8f9f7 | 1507 | hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); |
<> | 144:ef7eb2e8f9f7 | 1508 | hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); |
<> | 144:ef7eb2e8f9f7 | 1509 | |
<> | 144:ef7eb2e8f9f7 | 1510 | /* Set ADC resolution */ |
<> | 144:ef7eb2e8f9f7 | 1511 | hadc->Instance->CR1 &= ~(ADC_CR1_RES); |
<> | 144:ef7eb2e8f9f7 | 1512 | hadc->Instance->CR1 |= hadc->Init.Resolution; |
<> | 144:ef7eb2e8f9f7 | 1513 | |
<> | 144:ef7eb2e8f9f7 | 1514 | /* Set ADC data alignment */ |
<> | 144:ef7eb2e8f9f7 | 1515 | hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); |
<> | 144:ef7eb2e8f9f7 | 1516 | hadc->Instance->CR2 |= hadc->Init.DataAlign; |
<> | 144:ef7eb2e8f9f7 | 1517 | |
<> | 144:ef7eb2e8f9f7 | 1518 | /* Enable external trigger if trigger selection is different of software */ |
<> | 144:ef7eb2e8f9f7 | 1519 | /* start. */ |
<> | 144:ef7eb2e8f9f7 | 1520 | /* Note: This configuration keeps the hardware feature of parameter */ |
<> | 144:ef7eb2e8f9f7 | 1521 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
<> | 144:ef7eb2e8f9f7 | 1522 | /* software start. */ |
<> | 144:ef7eb2e8f9f7 | 1523 | if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
<> | 144:ef7eb2e8f9f7 | 1524 | { |
<> | 144:ef7eb2e8f9f7 | 1525 | /* Select external trigger to start conversion */ |
<> | 144:ef7eb2e8f9f7 | 1526 | hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); |
<> | 144:ef7eb2e8f9f7 | 1527 | hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; |
<> | 144:ef7eb2e8f9f7 | 1528 | |
<> | 144:ef7eb2e8f9f7 | 1529 | /* Select external trigger polarity */ |
<> | 144:ef7eb2e8f9f7 | 1530 | hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); |
<> | 144:ef7eb2e8f9f7 | 1531 | hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; |
<> | 144:ef7eb2e8f9f7 | 1532 | } |
<> | 144:ef7eb2e8f9f7 | 1533 | else |
<> | 144:ef7eb2e8f9f7 | 1534 | { |
<> | 144:ef7eb2e8f9f7 | 1535 | /* Reset the external trigger */ |
<> | 144:ef7eb2e8f9f7 | 1536 | hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); |
<> | 144:ef7eb2e8f9f7 | 1537 | hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); |
<> | 144:ef7eb2e8f9f7 | 1538 | } |
<> | 144:ef7eb2e8f9f7 | 1539 | |
<> | 144:ef7eb2e8f9f7 | 1540 | /* Enable or disable ADC continuous conversion mode */ |
<> | 144:ef7eb2e8f9f7 | 1541 | hadc->Instance->CR2 &= ~(ADC_CR2_CONT); |
<> | 144:ef7eb2e8f9f7 | 1542 | hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode); |
<> | 144:ef7eb2e8f9f7 | 1543 | |
<> | 144:ef7eb2e8f9f7 | 1544 | if(hadc->Init.DiscontinuousConvMode != DISABLE) |
<> | 144:ef7eb2e8f9f7 | 1545 | { |
<> | 144:ef7eb2e8f9f7 | 1546 | assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); |
<> | 144:ef7eb2e8f9f7 | 1547 | |
<> | 144:ef7eb2e8f9f7 | 1548 | /* Enable the selected ADC regular discontinuous mode */ |
<> | 144:ef7eb2e8f9f7 | 1549 | hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; |
<> | 144:ef7eb2e8f9f7 | 1550 | |
<> | 144:ef7eb2e8f9f7 | 1551 | /* Set the number of channels to be converted in discontinuous mode */ |
<> | 144:ef7eb2e8f9f7 | 1552 | hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); |
<> | 144:ef7eb2e8f9f7 | 1553 | hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); |
<> | 144:ef7eb2e8f9f7 | 1554 | } |
<> | 144:ef7eb2e8f9f7 | 1555 | else |
<> | 144:ef7eb2e8f9f7 | 1556 | { |
<> | 144:ef7eb2e8f9f7 | 1557 | /* Disable the selected ADC regular discontinuous mode */ |
<> | 144:ef7eb2e8f9f7 | 1558 | hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); |
<> | 144:ef7eb2e8f9f7 | 1559 | } |
<> | 144:ef7eb2e8f9f7 | 1560 | |
<> | 144:ef7eb2e8f9f7 | 1561 | /* Set ADC number of conversion */ |
<> | 144:ef7eb2e8f9f7 | 1562 | hadc->Instance->SQR1 &= ~(ADC_SQR1_L); |
<> | 144:ef7eb2e8f9f7 | 1563 | hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); |
<> | 144:ef7eb2e8f9f7 | 1564 | |
<> | 144:ef7eb2e8f9f7 | 1565 | /* Enable or disable ADC DMA continuous request */ |
<> | 144:ef7eb2e8f9f7 | 1566 | hadc->Instance->CR2 &= ~(ADC_CR2_DDS); |
<> | 144:ef7eb2e8f9f7 | 1567 | hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests); |
<> | 144:ef7eb2e8f9f7 | 1568 | |
<> | 144:ef7eb2e8f9f7 | 1569 | /* Enable or disable ADC end of conversion selection */ |
<> | 144:ef7eb2e8f9f7 | 1570 | hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); |
<> | 144:ef7eb2e8f9f7 | 1571 | hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); |
<> | 144:ef7eb2e8f9f7 | 1572 | } |
<> | 144:ef7eb2e8f9f7 | 1573 | |
<> | 144:ef7eb2e8f9f7 | 1574 | /** |
<> | 144:ef7eb2e8f9f7 | 1575 | * @brief DMA transfer complete callback. |
<> | 144:ef7eb2e8f9f7 | 1576 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1577 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1578 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1579 | */ |
<> | 144:ef7eb2e8f9f7 | 1580 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1581 | { |
<> | 144:ef7eb2e8f9f7 | 1582 | /* Retrieve ADC handle corresponding to current DMA handle */ |
<> | 144:ef7eb2e8f9f7 | 1583 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1584 | |
<> | 144:ef7eb2e8f9f7 | 1585 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 1586 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
<> | 144:ef7eb2e8f9f7 | 1587 | { |
<> | 144:ef7eb2e8f9f7 | 1588 | /* Update ADC state machine */ |
<> | 144:ef7eb2e8f9f7 | 1589 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1590 | |
<> | 144:ef7eb2e8f9f7 | 1591 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1592 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 1593 | /* Note: On STM32F2, there is no independent flag of end of sequence. */ |
<> | 144:ef7eb2e8f9f7 | 1594 | /* The test of scan sequence on going is done either with scan */ |
<> | 144:ef7eb2e8f9f7 | 1595 | /* sequence disabled or with end of conversion flag set to */ |
<> | 144:ef7eb2e8f9f7 | 1596 | /* of end of sequence. */ |
<> | 144:ef7eb2e8f9f7 | 1597 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 1598 | (hadc->Init.ContinuousConvMode == DISABLE) && |
<> | 144:ef7eb2e8f9f7 | 1599 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
<> | 144:ef7eb2e8f9f7 | 1600 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
<> | 144:ef7eb2e8f9f7 | 1601 | { |
<> | 144:ef7eb2e8f9f7 | 1602 | /* Disable ADC end of single conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1603 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
<> | 144:ef7eb2e8f9f7 | 1604 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
<> | 144:ef7eb2e8f9f7 | 1605 | /* by overrun IRQ process below. */ |
<> | 144:ef7eb2e8f9f7 | 1606 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
<> | 144:ef7eb2e8f9f7 | 1607 | |
<> | 144:ef7eb2e8f9f7 | 1608 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1609 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1610 | |
<> | 144:ef7eb2e8f9f7 | 1611 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 1612 | { |
<> | 144:ef7eb2e8f9f7 | 1613 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1614 | } |
<> | 144:ef7eb2e8f9f7 | 1615 | } |
<> | 144:ef7eb2e8f9f7 | 1616 | |
<> | 144:ef7eb2e8f9f7 | 1617 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1618 | HAL_ADC_ConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1619 | } |
<> | 144:ef7eb2e8f9f7 | 1620 | else |
<> | 144:ef7eb2e8f9f7 | 1621 | { |
<> | 144:ef7eb2e8f9f7 | 1622 | /* Call DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1623 | hadc->DMA_Handle->XferErrorCallback(hdma); |
<> | 144:ef7eb2e8f9f7 | 1624 | } |
<> | 144:ef7eb2e8f9f7 | 1625 | } |
<> | 144:ef7eb2e8f9f7 | 1626 | |
<> | 144:ef7eb2e8f9f7 | 1627 | /** |
<> | 144:ef7eb2e8f9f7 | 1628 | * @brief DMA half transfer complete callback. |
<> | 144:ef7eb2e8f9f7 | 1629 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1630 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1631 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1632 | */ |
<> | 144:ef7eb2e8f9f7 | 1633 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1634 | { |
<> | 144:ef7eb2e8f9f7 | 1635 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1636 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1637 | HAL_ADC_ConvHalfCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1638 | } |
<> | 144:ef7eb2e8f9f7 | 1639 | |
<> | 144:ef7eb2e8f9f7 | 1640 | /** |
<> | 144:ef7eb2e8f9f7 | 1641 | * @brief DMA error callback |
<> | 144:ef7eb2e8f9f7 | 1642 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1643 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1644 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1645 | */ |
<> | 144:ef7eb2e8f9f7 | 1646 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1647 | { |
<> | 144:ef7eb2e8f9f7 | 1648 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1649 | hadc->State= HAL_ADC_STATE_ERROR_DMA; |
<> | 144:ef7eb2e8f9f7 | 1650 | /* Set ADC error code to DMA error */ |
<> | 144:ef7eb2e8f9f7 | 1651 | hadc->ErrorCode |= HAL_ADC_ERROR_DMA; |
<> | 144:ef7eb2e8f9f7 | 1652 | HAL_ADC_ErrorCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1653 | } |
<> | 144:ef7eb2e8f9f7 | 1654 | |
<> | 144:ef7eb2e8f9f7 | 1655 | /** |
<> | 144:ef7eb2e8f9f7 | 1656 | * @} |
<> | 144:ef7eb2e8f9f7 | 1657 | */ |
<> | 144:ef7eb2e8f9f7 | 1658 | |
<> | 144:ef7eb2e8f9f7 | 1659 | /** |
<> | 144:ef7eb2e8f9f7 | 1660 | * @} |
<> | 144:ef7eb2e8f9f7 | 1661 | */ |
<> | 144:ef7eb2e8f9f7 | 1662 | |
<> | 144:ef7eb2e8f9f7 | 1663 | #endif /* HAL_ADC_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 1664 | /** |
<> | 144:ef7eb2e8f9f7 | 1665 | * @} |
<> | 144:ef7eb2e8f9f7 | 1666 | */ |
<> | 144:ef7eb2e8f9f7 | 1667 | |
<> | 144:ef7eb2e8f9f7 | 1668 | /** |
<> | 144:ef7eb2e8f9f7 | 1669 | * @} |
<> | 144:ef7eb2e8f9f7 | 1670 | */ |
<> | 144:ef7eb2e8f9f7 | 1671 | |
<> | 144:ef7eb2e8f9f7 | 1672 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |