mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
135:eec55f8ee438 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f072xb.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.3.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
<> 144:ef7eb2e8f9f7 8 * This file contains all the peripheral register's definitions, bits
<> 144:ef7eb2e8f9f7 9 * definitions and memory mapping for STM32F0xx devices.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * This file contains:
<> 144:ef7eb2e8f9f7 12 * - Data structures and the address mapping for all peripherals
<> 144:ef7eb2e8f9f7 13 * - Peripheral's registers declarations and bits definition
<> 144:ef7eb2e8f9f7 14 * - Macros to access peripheral’s registers hardware
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 ******************************************************************************
<> 144:ef7eb2e8f9f7 17 * @attention
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 22 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 23 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 24 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 26 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 27 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 29 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 30 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 ******************************************************************************
<> 144:ef7eb2e8f9f7 44 */
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup stm32f072xb
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 #ifndef __STM32F072xB_H
<> 144:ef7eb2e8f9f7 55 #define __STM32F072xB_H
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 58 extern "C" {
<> 144:ef7eb2e8f9f7 59 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** @addtogroup Configuration_section_for_CMSIS
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 #define __CM0_REV 0 /*!< Core Revision r0p0 */
<> 144:ef7eb2e8f9f7 68 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
<> 144:ef7eb2e8f9f7 69 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
<> 144:ef7eb2e8f9f7 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /**
<> 144:ef7eb2e8f9f7 73 * @}
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /** @addtogroup Peripheral_interrupt_number_definition
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /**
<> 144:ef7eb2e8f9f7 81 * @brief STM32F0xx Interrupt Number Definition, according to the selected device
<> 144:ef7eb2e8f9f7 82 * in @ref Library_configuration_section
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /*!< Interrupt Number Definition */
<> 144:ef7eb2e8f9f7 86 typedef enum
<> 144:ef7eb2e8f9f7 87 {
<> 144:ef7eb2e8f9f7 88 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
<> 144:ef7eb2e8f9f7 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 90 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
<> 144:ef7eb2e8f9f7 91 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 92 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 93 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /****** STM32F0 specific Interrupt Numbers ******************************************************************/
<> 144:ef7eb2e8f9f7 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 144:ef7eb2e8f9f7 97 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */
<> 144:ef7eb2e8f9f7 98 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
<> 144:ef7eb2e8f9f7 99 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
<> 144:ef7eb2e8f9f7 100 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */
<> 144:ef7eb2e8f9f7 101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */
<> 144:ef7eb2e8f9f7 102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */
<> 144:ef7eb2e8f9f7 103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */
<> 144:ef7eb2e8f9f7 104 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
<> 144:ef7eb2e8f9f7 105 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
<> 144:ef7eb2e8f9f7 106 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */
<> 144:ef7eb2e8f9f7 107 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupt */
<> 144:ef7eb2e8f9f7 108 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
<> 144:ef7eb2e8f9f7 109 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */
<> 144:ef7eb2e8f9f7 110 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
<> 144:ef7eb2e8f9f7 111 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
<> 144:ef7eb2e8f9f7 112 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
<> 144:ef7eb2e8f9f7 113 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupt */
<> 144:ef7eb2e8f9f7 114 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
<> 144:ef7eb2e8f9f7 115 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
<> 144:ef7eb2e8f9f7 116 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
<> 144:ef7eb2e8f9f7 117 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
<> 144:ef7eb2e8f9f7 118 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
<> 144:ef7eb2e8f9f7 119 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
<> 144:ef7eb2e8f9f7 120 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
<> 144:ef7eb2e8f9f7 121 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
<> 144:ef7eb2e8f9f7 122 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
<> 144:ef7eb2e8f9f7 123 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
<> 144:ef7eb2e8f9f7 124 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
<> 144:ef7eb2e8f9f7 125 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupt */
<> 144:ef7eb2e8f9f7 126 CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
<> 144:ef7eb2e8f9f7 127 USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */
<> 144:ef7eb2e8f9f7 128 } IRQn_Type;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /**
<> 144:ef7eb2e8f9f7 131 * @}
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
<> 144:ef7eb2e8f9f7 135 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
<> 144:ef7eb2e8f9f7 136 #include <stdint.h>
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** @addtogroup Peripheral_registers_structures
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @brief Analog to Digital Converter
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 typedef struct
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 149 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 150 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 151 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 152 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 153 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 154 uint32_t RESERVED1; /*!< Reserved, 0x18 */
<> 144:ef7eb2e8f9f7 155 uint32_t RESERVED2; /*!< Reserved, 0x1C */
<> 144:ef7eb2e8f9f7 156 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 157 uint32_t RESERVED3; /*!< Reserved, 0x24 */
<> 144:ef7eb2e8f9f7 158 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 159 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
<> 144:ef7eb2e8f9f7 160 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 161 } ADC_TypeDef;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 typedef struct
<> 144:ef7eb2e8f9f7 164 {
<> 144:ef7eb2e8f9f7 165 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
<> 144:ef7eb2e8f9f7 166 } ADC_Common_TypeDef;
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief Controller Area Network TxMailBox
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171 typedef struct
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
<> 144:ef7eb2e8f9f7 174 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
<> 144:ef7eb2e8f9f7 175 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
<> 144:ef7eb2e8f9f7 176 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
<> 144:ef7eb2e8f9f7 177 }CAN_TxMailBox_TypeDef;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief Controller Area Network FIFOMailBox
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 typedef struct
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
<> 144:ef7eb2e8f9f7 185 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
<> 144:ef7eb2e8f9f7 186 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
<> 144:ef7eb2e8f9f7 187 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
<> 144:ef7eb2e8f9f7 188 }CAN_FIFOMailBox_TypeDef;
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @brief Controller Area Network FilterRegister
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 typedef struct
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
<> 144:ef7eb2e8f9f7 196 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
<> 144:ef7eb2e8f9f7 197 }CAN_FilterRegister_TypeDef;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @brief Controller Area Network
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 typedef struct
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 205 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 206 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 207 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 208 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 209 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 210 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 212 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
<> 144:ef7eb2e8f9f7 213 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
<> 144:ef7eb2e8f9f7 214 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
<> 144:ef7eb2e8f9f7 215 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
<> 144:ef7eb2e8f9f7 216 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
<> 144:ef7eb2e8f9f7 217 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
<> 144:ef7eb2e8f9f7 218 uint32_t RESERVED2; /*!< Reserved, 0x208 */
<> 144:ef7eb2e8f9f7 219 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
<> 144:ef7eb2e8f9f7 220 uint32_t RESERVED3; /*!< Reserved, 0x210 */
<> 144:ef7eb2e8f9f7 221 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
<> 144:ef7eb2e8f9f7 222 uint32_t RESERVED4; /*!< Reserved, 0x218 */
<> 144:ef7eb2e8f9f7 223 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
<> 144:ef7eb2e8f9f7 224 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
<> 144:ef7eb2e8f9f7 225 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
<> 144:ef7eb2e8f9f7 226 }CAN_TypeDef;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @brief HDMI-CEC
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 typedef struct
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
<> 144:ef7eb2e8f9f7 235 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
<> 144:ef7eb2e8f9f7 236 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
<> 144:ef7eb2e8f9f7 237 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
<> 144:ef7eb2e8f9f7 238 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
<> 144:ef7eb2e8f9f7 239 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
<> 144:ef7eb2e8f9f7 240 }CEC_TypeDef;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @brief Comparator
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 typedef struct
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 __IO uint16_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 249 } COMP_TypeDef;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 typedef struct
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 254 } COMP_Common_TypeDef;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Legacy defines */
<> 144:ef7eb2e8f9f7 257 typedef struct
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 __IO uint32_t CSR; /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */
<> 144:ef7eb2e8f9f7 260 }COMP1_2_TypeDef;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief CRC calculation unit
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 typedef struct
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 269 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 270 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 144:ef7eb2e8f9f7 271 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 144:ef7eb2e8f9f7 272 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 273 uint32_t RESERVED2; /*!< Reserved, 0x0C */
<> 144:ef7eb2e8f9f7 274 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 275 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 276 } CRC_TypeDef;
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief Clock Recovery System
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 typedef struct
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 284 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 285 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 286 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 287 }CRS_TypeDef;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief Digital to Analog Converter
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 typedef struct
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 296 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 297 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 298 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 299 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 300 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 301 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 302 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 303 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 304 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 305 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 306 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 307 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 308 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 309 } DAC_TypeDef;
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @brief Debug MCU
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 typedef struct
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 318 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 319 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 320 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 321 }DBGMCU_TypeDef;
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @brief DMA Controller
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 typedef struct
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 __IO uint32_t CCR; /*!< DMA channel x configuration register */
<> 144:ef7eb2e8f9f7 330 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
<> 144:ef7eb2e8f9f7 331 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
<> 144:ef7eb2e8f9f7 332 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
<> 144:ef7eb2e8f9f7 333 } DMA_Channel_TypeDef;
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 typedef struct
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 338 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 339 } DMA_TypeDef;
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @brief External Interrupt/Event Controller
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 typedef struct
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 348 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 349 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 350 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 351 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 352 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 353 } EXTI_TypeDef;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @brief FLASH Registers
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 typedef struct
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 362 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 363 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 364 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 365 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 366 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
<> 144:ef7eb2e8f9f7 367 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 368 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 369 } FLASH_TypeDef;
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @brief Option Bytes Registers
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374 typedef struct
<> 144:ef7eb2e8f9f7 375 {
<> 144:ef7eb2e8f9f7 376 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 377 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
<> 144:ef7eb2e8f9f7 378 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 379 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
<> 144:ef7eb2e8f9f7 380 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 381 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
<> 144:ef7eb2e8f9f7 382 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 383 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
<> 144:ef7eb2e8f9f7 384 } OB_TypeDef;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @brief General Purpose I/O
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 typedef struct
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 393 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 394 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 395 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 396 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 397 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 398 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
<> 144:ef7eb2e8f9f7 399 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 400 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
<> 144:ef7eb2e8f9f7 401 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 402 } GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /**
<> 144:ef7eb2e8f9f7 405 * @brief SysTem Configuration
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 typedef struct
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 411 uint32_t RESERVED; /*!< Reserved, 0x04 */
<> 144:ef7eb2e8f9f7 412 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
<> 144:ef7eb2e8f9f7 413 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 414 } SYSCFG_TypeDef;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @brief Inter-integrated Circuit Interface
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 typedef struct
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 423 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 424 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 425 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 426 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 427 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 428 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 429 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 430 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 431 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 432 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 433 } I2C_TypeDef;
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @brief Independent WATCHDOG
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 typedef struct
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 442 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 443 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 444 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 445 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 446 } IWDG_TypeDef;
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /**
<> 144:ef7eb2e8f9f7 449 * @brief Power Control
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 typedef struct
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 455 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 456 } PWR_TypeDef;
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @brief Reset and Clock Control
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 typedef struct
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 465 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 466 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 467 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 468 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 469 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 470 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 471 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 472 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 473 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 474 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 476 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 477 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 478 } RCC_TypeDef;
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @brief Real-Time Clock
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 typedef struct
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 486 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 487 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 488 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 489 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 490 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 491 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 492 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 493 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 494 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 495 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 496 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 497 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 498 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 499 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 500 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 501 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 502 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 503 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 504 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 505 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 506 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 507 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 508 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 144:ef7eb2e8f9f7 509 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 510 } RTC_TypeDef;
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @brief Serial Peripheral Interface
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 typedef struct
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 519 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 520 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 521 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 522 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 523 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 524 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 525 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 526 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 527 } SPI_TypeDef;
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /**
<> 144:ef7eb2e8f9f7 530 * @brief TIM
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532 typedef struct
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 535 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 536 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 537 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 538 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 539 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 540 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 541 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 542 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 543 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 544 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 545 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 546 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 547 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 548 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 549 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 550 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 551 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 552 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 553 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 554 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 555 } TIM_TypeDef;
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @brief Touch Sensing Controller (TSC)
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 typedef struct
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 563 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 564 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 565 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 566 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 567 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 568 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 569 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 570 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 571 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 572 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 573 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 574 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 575 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
<> 144:ef7eb2e8f9f7 576 }TSC_TypeDef;
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /**
<> 144:ef7eb2e8f9f7 579 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 typedef struct
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 585 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 586 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 587 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 588 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 589 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 590 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 591 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 592 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 593 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 594 uint16_t RESERVED1; /*!< Reserved, 0x26 */
<> 144:ef7eb2e8f9f7 595 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 596 uint16_t RESERVED2; /*!< Reserved, 0x2A */
<> 144:ef7eb2e8f9f7 597 } USART_TypeDef;
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /**
<> 144:ef7eb2e8f9f7 600 * @brief Universal Serial Bus Full Speed Device
<> 144:ef7eb2e8f9f7 601 */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 typedef struct
<> 144:ef7eb2e8f9f7 604 {
<> 144:ef7eb2e8f9f7 605 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 606 __IO uint16_t RESERVED0; /*!< Reserved */
<> 144:ef7eb2e8f9f7 607 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 608 __IO uint16_t RESERVED1; /*!< Reserved */
<> 144:ef7eb2e8f9f7 609 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 610 __IO uint16_t RESERVED2; /*!< Reserved */
<> 144:ef7eb2e8f9f7 611 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 612 __IO uint16_t RESERVED3; /*!< Reserved */
<> 144:ef7eb2e8f9f7 613 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 614 __IO uint16_t RESERVED4; /*!< Reserved */
<> 144:ef7eb2e8f9f7 615 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 616 __IO uint16_t RESERVED5; /*!< Reserved */
<> 144:ef7eb2e8f9f7 617 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 618 __IO uint16_t RESERVED6; /*!< Reserved */
<> 144:ef7eb2e8f9f7 619 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 620 __IO uint16_t RESERVED7[17]; /*!< Reserved */
<> 144:ef7eb2e8f9f7 621 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 622 __IO uint16_t RESERVED8; /*!< Reserved */
<> 144:ef7eb2e8f9f7 623 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 624 __IO uint16_t RESERVED9; /*!< Reserved */
<> 144:ef7eb2e8f9f7 625 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 626 __IO uint16_t RESERVEDA; /*!< Reserved */
<> 144:ef7eb2e8f9f7 627 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 628 __IO uint16_t RESERVEDB; /*!< Reserved */
<> 144:ef7eb2e8f9f7 629 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 630 __IO uint16_t RESERVEDC; /*!< Reserved */
<> 144:ef7eb2e8f9f7 631 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 632 __IO uint16_t RESERVEDD; /*!< Reserved */
<> 144:ef7eb2e8f9f7 633 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 634 __IO uint16_t RESERVEDE; /*!< Reserved */
<> 144:ef7eb2e8f9f7 635 } USB_TypeDef;
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /**
<> 144:ef7eb2e8f9f7 638 * @brief Window WATCHDOG
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640 typedef struct
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 643 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 644 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 645 } WWDG_TypeDef;
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /**
<> 144:ef7eb2e8f9f7 648 * @}
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /** @addtogroup Peripheral_memory_map
<> 144:ef7eb2e8f9f7 652 * @{
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
<> 144:ef7eb2e8f9f7 656 #define FLASH_BANK1_END ((uint32_t)0x0801FFFFU) /*!< FLASH END address of bank1 */
<> 144:ef7eb2e8f9f7 657 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
<> 144:ef7eb2e8f9f7 658 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /*!< Peripheral memory map */
<> 144:ef7eb2e8f9f7 661 #define APBPERIPH_BASE PERIPH_BASE
<> 144:ef7eb2e8f9f7 662 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
<> 144:ef7eb2e8f9f7 663 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /*!< APB peripherals */
<> 144:ef7eb2e8f9f7 666 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
<> 144:ef7eb2e8f9f7 667 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
<> 144:ef7eb2e8f9f7 668 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
<> 144:ef7eb2e8f9f7 669 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
<> 144:ef7eb2e8f9f7 670 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
<> 144:ef7eb2e8f9f7 671 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
<> 144:ef7eb2e8f9f7 672 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
<> 144:ef7eb2e8f9f7 673 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
<> 144:ef7eb2e8f9f7 674 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
<> 144:ef7eb2e8f9f7 675 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
<> 144:ef7eb2e8f9f7 676 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
<> 144:ef7eb2e8f9f7 677 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
<> 144:ef7eb2e8f9f7 678 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
<> 144:ef7eb2e8f9f7 679 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
<> 144:ef7eb2e8f9f7 680 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
<> 144:ef7eb2e8f9f7 681 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
<> 144:ef7eb2e8f9f7 682 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
<> 144:ef7eb2e8f9f7 683 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
<> 144:ef7eb2e8f9f7 684 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
<> 144:ef7eb2e8f9f7 685 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
<> 144:ef7eb2e8f9f7 690 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
<> 144:ef7eb2e8f9f7 691 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
<> 144:ef7eb2e8f9f7 692 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
<> 144:ef7eb2e8f9f7 693 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
<> 144:ef7eb2e8f9f7 694 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
<> 144:ef7eb2e8f9f7 695 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
<> 144:ef7eb2e8f9f7 696 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
<> 144:ef7eb2e8f9f7 697 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
<> 144:ef7eb2e8f9f7 698 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
<> 144:ef7eb2e8f9f7 699 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
<> 144:ef7eb2e8f9f7 700 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /*!< AHB peripherals */
<> 144:ef7eb2e8f9f7 703 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
<> 144:ef7eb2e8f9f7 704 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
<> 144:ef7eb2e8f9f7 705 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
<> 144:ef7eb2e8f9f7 706 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
<> 144:ef7eb2e8f9f7 707 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
<> 144:ef7eb2e8f9f7 708 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
<> 144:ef7eb2e8f9f7 709 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
<> 144:ef7eb2e8f9f7 710 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
<> 144:ef7eb2e8f9f7 713 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
<> 144:ef7eb2e8f9f7 714 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< FLASH Option Bytes base address */
<> 144:ef7eb2e8f9f7 715 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
<> 144:ef7eb2e8f9f7 716 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
<> 144:ef7eb2e8f9f7 717 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
<> 144:ef7eb2e8f9f7 718 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /*!< AHB2 peripherals */
<> 144:ef7eb2e8f9f7 721 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
<> 144:ef7eb2e8f9f7 722 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
<> 144:ef7eb2e8f9f7 723 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
<> 144:ef7eb2e8f9f7 724 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
<> 144:ef7eb2e8f9f7 725 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
<> 144:ef7eb2e8f9f7 726 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @}
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /** @addtogroup Peripheral_declaration
<> 144:ef7eb2e8f9f7 733 * @{
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 144:ef7eb2e8f9f7 737 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 144:ef7eb2e8f9f7 738 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 144:ef7eb2e8f9f7 739 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 144:ef7eb2e8f9f7 740 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
<> 144:ef7eb2e8f9f7 741 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 144:ef7eb2e8f9f7 742 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 144:ef7eb2e8f9f7 743 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 144:ef7eb2e8f9f7 744 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 144:ef7eb2e8f9f7 745 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 144:ef7eb2e8f9f7 746 #define USART4 ((USART_TypeDef *) USART4_BASE)
<> 144:ef7eb2e8f9f7 747 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 144:ef7eb2e8f9f7 748 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 144:ef7eb2e8f9f7 749 #define CAN1 ((CAN_TypeDef *) CAN_BASE)
<> 144:ef7eb2e8f9f7 750 #define CRS ((CRS_TypeDef *) CRS_BASE)
<> 144:ef7eb2e8f9f7 751 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 144:ef7eb2e8f9f7 752 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
<> 144:ef7eb2e8f9f7 753 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
<> 144:ef7eb2e8f9f7 754 #define CEC ((CEC_TypeDef *) CEC_BASE)
<> 144:ef7eb2e8f9f7 755 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 144:ef7eb2e8f9f7 756 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
<> 144:ef7eb2e8f9f7 757 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
<> 144:ef7eb2e8f9f7 758 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE)
<> 144:ef7eb2e8f9f7 759 #define COMP ((COMP1_2_TypeDef *) COMP_BASE) /* Kept for legacy purpose */
<> 144:ef7eb2e8f9f7 760 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 144:ef7eb2e8f9f7 761 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 144:ef7eb2e8f9f7 762 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
<> 144:ef7eb2e8f9f7 763 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
<> 144:ef7eb2e8f9f7 764 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 144:ef7eb2e8f9f7 765 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 144:ef7eb2e8f9f7 766 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 144:ef7eb2e8f9f7 767 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 144:ef7eb2e8f9f7 768 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
<> 144:ef7eb2e8f9f7 769 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
<> 144:ef7eb2e8f9f7 770 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
<> 144:ef7eb2e8f9f7 771 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 144:ef7eb2e8f9f7 772 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 144:ef7eb2e8f9f7 773 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
<> 144:ef7eb2e8f9f7 774 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
<> 144:ef7eb2e8f9f7 775 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
<> 144:ef7eb2e8f9f7 776 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
<> 144:ef7eb2e8f9f7 777 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
<> 144:ef7eb2e8f9f7 778 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
<> 144:ef7eb2e8f9f7 779 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
<> 144:ef7eb2e8f9f7 780 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 144:ef7eb2e8f9f7 781 #define OB ((OB_TypeDef *) OB_BASE)
<> 144:ef7eb2e8f9f7 782 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 144:ef7eb2e8f9f7 783 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 144:ef7eb2e8f9f7 784 #define TSC ((TSC_TypeDef *) TSC_BASE)
<> 144:ef7eb2e8f9f7 785 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 144:ef7eb2e8f9f7 786 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 144:ef7eb2e8f9f7 787 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 144:ef7eb2e8f9f7 788 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 144:ef7eb2e8f9f7 789 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 144:ef7eb2e8f9f7 790 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
<> 144:ef7eb2e8f9f7 791 #define USB ((USB_TypeDef *) USB_BASE)
<> 144:ef7eb2e8f9f7 792 /**
<> 144:ef7eb2e8f9f7 793 * @}
<> 144:ef7eb2e8f9f7 794 */
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /** @addtogroup Exported_constants
<> 144:ef7eb2e8f9f7 797 * @{
<> 144:ef7eb2e8f9f7 798 */
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 144:ef7eb2e8f9f7 801 * @{
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /******************************************************************************/
<> 144:ef7eb2e8f9f7 805 /* Peripheral Registers Bits Definition */
<> 144:ef7eb2e8f9f7 806 /******************************************************************************/
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /******************************************************************************/
<> 144:ef7eb2e8f9f7 809 /* */
<> 144:ef7eb2e8f9f7 810 /* Analog to Digital Converter (ADC) */
<> 144:ef7eb2e8f9f7 811 /* */
<> 144:ef7eb2e8f9f7 812 /******************************************************************************/
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /*
<> 144:ef7eb2e8f9f7 815 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 144:ef7eb2e8f9f7 816 */
<> 144:ef7eb2e8f9f7 817 #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /******************** Bits definition for ADC_ISR register ******************/
<> 144:ef7eb2e8f9f7 820 #define ADC_ISR_ADRDY_Pos (0U)
<> 144:ef7eb2e8f9f7 821 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 822 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
<> 144:ef7eb2e8f9f7 823 #define ADC_ISR_EOSMP_Pos (1U)
<> 144:ef7eb2e8f9f7 824 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 825 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
<> 144:ef7eb2e8f9f7 826 #define ADC_ISR_EOC_Pos (2U)
<> 144:ef7eb2e8f9f7 827 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 828 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
<> 144:ef7eb2e8f9f7 829 #define ADC_ISR_EOS_Pos (3U)
<> 144:ef7eb2e8f9f7 830 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 831 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
<> 144:ef7eb2e8f9f7 832 #define ADC_ISR_OVR_Pos (4U)
<> 144:ef7eb2e8f9f7 833 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 834 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
<> 144:ef7eb2e8f9f7 835 #define ADC_ISR_AWD1_Pos (7U)
<> 144:ef7eb2e8f9f7 836 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 837 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Legacy defines */
<> 144:ef7eb2e8f9f7 840 #define ADC_ISR_AWD (ADC_ISR_AWD1)
<> 144:ef7eb2e8f9f7 841 #define ADC_ISR_EOSEQ (ADC_ISR_EOS)
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /******************** Bits definition for ADC_IER register ******************/
<> 144:ef7eb2e8f9f7 844 #define ADC_IER_ADRDYIE_Pos (0U)
<> 144:ef7eb2e8f9f7 845 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 846 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
<> 144:ef7eb2e8f9f7 847 #define ADC_IER_EOSMPIE_Pos (1U)
<> 144:ef7eb2e8f9f7 848 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 849 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
<> 144:ef7eb2e8f9f7 850 #define ADC_IER_EOCIE_Pos (2U)
<> 144:ef7eb2e8f9f7 851 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 852 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
<> 144:ef7eb2e8f9f7 853 #define ADC_IER_EOSIE_Pos (3U)
<> 144:ef7eb2e8f9f7 854 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 855 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
<> 144:ef7eb2e8f9f7 856 #define ADC_IER_OVRIE_Pos (4U)
<> 144:ef7eb2e8f9f7 857 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 858 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
<> 144:ef7eb2e8f9f7 859 #define ADC_IER_AWD1IE_Pos (7U)
<> 144:ef7eb2e8f9f7 860 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 861 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /* Legacy defines */
<> 144:ef7eb2e8f9f7 864 #define ADC_IER_AWDIE (ADC_IER_AWD1IE)
<> 144:ef7eb2e8f9f7 865 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /******************** Bits definition for ADC_CR register *******************/
<> 144:ef7eb2e8f9f7 868 #define ADC_CR_ADEN_Pos (0U)
<> 144:ef7eb2e8f9f7 869 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 870 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
<> 144:ef7eb2e8f9f7 871 #define ADC_CR_ADDIS_Pos (1U)
<> 144:ef7eb2e8f9f7 872 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 873 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
<> 144:ef7eb2e8f9f7 874 #define ADC_CR_ADSTART_Pos (2U)
<> 144:ef7eb2e8f9f7 875 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 876 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
<> 144:ef7eb2e8f9f7 877 #define ADC_CR_ADSTP_Pos (4U)
<> 144:ef7eb2e8f9f7 878 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 879 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
<> 144:ef7eb2e8f9f7 880 #define ADC_CR_ADCAL_Pos (31U)
<> 144:ef7eb2e8f9f7 881 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 882 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /******************* Bits definition for ADC_CFGR1 register *****************/
<> 144:ef7eb2e8f9f7 885 #define ADC_CFGR1_DMAEN_Pos (0U)
<> 144:ef7eb2e8f9f7 886 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 887 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
<> 144:ef7eb2e8f9f7 888 #define ADC_CFGR1_DMACFG_Pos (1U)
<> 144:ef7eb2e8f9f7 889 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 890 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
<> 144:ef7eb2e8f9f7 891 #define ADC_CFGR1_SCANDIR_Pos (2U)
<> 144:ef7eb2e8f9f7 892 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 893 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 #define ADC_CFGR1_RES_Pos (3U)
<> 144:ef7eb2e8f9f7 896 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
<> 144:ef7eb2e8f9f7 897 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
<> 144:ef7eb2e8f9f7 898 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 899 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 #define ADC_CFGR1_ALIGN_Pos (5U)
<> 144:ef7eb2e8f9f7 902 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 903 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 #define ADC_CFGR1_EXTSEL_Pos (6U)
<> 144:ef7eb2e8f9f7 906 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
<> 144:ef7eb2e8f9f7 907 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
<> 144:ef7eb2e8f9f7 908 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 909 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 910 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 #define ADC_CFGR1_EXTEN_Pos (10U)
<> 144:ef7eb2e8f9f7 913 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
<> 144:ef7eb2e8f9f7 914 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
<> 144:ef7eb2e8f9f7 915 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 916 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 #define ADC_CFGR1_OVRMOD_Pos (12U)
<> 144:ef7eb2e8f9f7 919 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 920 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
<> 144:ef7eb2e8f9f7 921 #define ADC_CFGR1_CONT_Pos (13U)
<> 144:ef7eb2e8f9f7 922 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 923 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
<> 144:ef7eb2e8f9f7 924 #define ADC_CFGR1_WAIT_Pos (14U)
<> 144:ef7eb2e8f9f7 925 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 926 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
<> 144:ef7eb2e8f9f7 927 #define ADC_CFGR1_AUTOFF_Pos (15U)
<> 144:ef7eb2e8f9f7 928 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 929 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
<> 144:ef7eb2e8f9f7 930 #define ADC_CFGR1_DISCEN_Pos (16U)
<> 144:ef7eb2e8f9f7 931 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 932 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 #define ADC_CFGR1_AWD1SGL_Pos (22U)
<> 144:ef7eb2e8f9f7 935 #define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 936 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
<> 144:ef7eb2e8f9f7 937 #define ADC_CFGR1_AWD1EN_Pos (23U)
<> 144:ef7eb2e8f9f7 938 #define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 939 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 #define ADC_CFGR1_AWD1CH_Pos (26U)
<> 144:ef7eb2e8f9f7 942 #define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
<> 144:ef7eb2e8f9f7 943 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
<> 144:ef7eb2e8f9f7 944 #define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 945 #define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 946 #define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 947 #define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 948 #define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Legacy defines */
<> 144:ef7eb2e8f9f7 951 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
<> 144:ef7eb2e8f9f7 952 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
<> 144:ef7eb2e8f9f7 953 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
<> 144:ef7eb2e8f9f7 954 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
<> 144:ef7eb2e8f9f7 955 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
<> 144:ef7eb2e8f9f7 956 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
<> 144:ef7eb2e8f9f7 957 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
<> 144:ef7eb2e8f9f7 958 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
<> 144:ef7eb2e8f9f7 959 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 /******************* Bits definition for ADC_CFGR2 register *****************/
<> 144:ef7eb2e8f9f7 962 #define ADC_CFGR2_CKMODE_Pos (30U)
<> 144:ef7eb2e8f9f7 963 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
<> 144:ef7eb2e8f9f7 964 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
<> 144:ef7eb2e8f9f7 965 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 966 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /* Legacy defines */
<> 144:ef7eb2e8f9f7 969 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */
<> 144:ef7eb2e8f9f7 970 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /****************** Bit definition for ADC_SMPR register ********************/
<> 144:ef7eb2e8f9f7 973 #define ADC_SMPR_SMP_Pos (0U)
<> 144:ef7eb2e8f9f7 974 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
<> 144:ef7eb2e8f9f7 975 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */
<> 144:ef7eb2e8f9f7 976 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 977 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 978 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 /* Legacy defines */
<> 144:ef7eb2e8f9f7 981 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */
<> 144:ef7eb2e8f9f7 982 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */
<> 144:ef7eb2e8f9f7 983 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */
<> 144:ef7eb2e8f9f7 984 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 /******************* Bit definition for ADC_TR register ********************/
<> 144:ef7eb2e8f9f7 987 #define ADC_TR1_LT1_Pos (0U)
<> 144:ef7eb2e8f9f7 988 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 989 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
<> 144:ef7eb2e8f9f7 990 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 991 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 992 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 993 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 994 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 995 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 996 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 997 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 998 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 999 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1000 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1001 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 #define ADC_TR1_HT1_Pos (16U)
<> 144:ef7eb2e8f9f7 1004 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
<> 144:ef7eb2e8f9f7 1005 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
<> 144:ef7eb2e8f9f7 1006 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1007 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1008 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 1009 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 1010 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 1011 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 1012 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 1013 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 1014 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 1015 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 1016 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 1017 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1020 #define ADC_TR_HT (ADC_TR1_HT1)
<> 144:ef7eb2e8f9f7 1021 #define ADC_TR_LT (ADC_TR1_LT1)
<> 144:ef7eb2e8f9f7 1022 #define ADC_HTR_HT (ADC_TR1_HT1)
<> 144:ef7eb2e8f9f7 1023 #define ADC_LTR_LT (ADC_TR1_LT1)
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /****************** Bit definition for ADC_CHSELR register ******************/
<> 144:ef7eb2e8f9f7 1026 #define ADC_CHSELR_CHSEL_Pos (0U)
<> 144:ef7eb2e8f9f7 1027 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
<> 144:ef7eb2e8f9f7 1028 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1029 #define ADC_CHSELR_CHSEL18_Pos (18U)
<> 144:ef7eb2e8f9f7 1030 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 1031 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1032 #define ADC_CHSELR_CHSEL17_Pos (17U)
<> 144:ef7eb2e8f9f7 1033 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1034 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1035 #define ADC_CHSELR_CHSEL16_Pos (16U)
<> 144:ef7eb2e8f9f7 1036 #define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1037 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1038 #define ADC_CHSELR_CHSEL15_Pos (15U)
<> 144:ef7eb2e8f9f7 1039 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1040 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1041 #define ADC_CHSELR_CHSEL14_Pos (14U)
<> 144:ef7eb2e8f9f7 1042 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 1043 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1044 #define ADC_CHSELR_CHSEL13_Pos (13U)
<> 144:ef7eb2e8f9f7 1045 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 1046 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1047 #define ADC_CHSELR_CHSEL12_Pos (12U)
<> 144:ef7eb2e8f9f7 1048 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 1049 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1050 #define ADC_CHSELR_CHSEL11_Pos (11U)
<> 144:ef7eb2e8f9f7 1051 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1052 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1053 #define ADC_CHSELR_CHSEL10_Pos (10U)
<> 144:ef7eb2e8f9f7 1054 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1055 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1056 #define ADC_CHSELR_CHSEL9_Pos (9U)
<> 144:ef7eb2e8f9f7 1057 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1058 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1059 #define ADC_CHSELR_CHSEL8_Pos (8U)
<> 144:ef7eb2e8f9f7 1060 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1061 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1062 #define ADC_CHSELR_CHSEL7_Pos (7U)
<> 144:ef7eb2e8f9f7 1063 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 1064 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1065 #define ADC_CHSELR_CHSEL6_Pos (6U)
<> 144:ef7eb2e8f9f7 1066 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1067 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1068 #define ADC_CHSELR_CHSEL5_Pos (5U)
<> 144:ef7eb2e8f9f7 1069 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1070 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1071 #define ADC_CHSELR_CHSEL4_Pos (4U)
<> 144:ef7eb2e8f9f7 1072 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1073 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1074 #define ADC_CHSELR_CHSEL3_Pos (3U)
<> 144:ef7eb2e8f9f7 1075 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1076 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1077 #define ADC_CHSELR_CHSEL2_Pos (2U)
<> 144:ef7eb2e8f9f7 1078 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1079 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1080 #define ADC_CHSELR_CHSEL1_Pos (1U)
<> 144:ef7eb2e8f9f7 1081 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1082 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1083 #define ADC_CHSELR_CHSEL0_Pos (0U)
<> 144:ef7eb2e8f9f7 1084 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1085 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /******************** Bit definition for ADC_DR register ********************/
<> 144:ef7eb2e8f9f7 1088 #define ADC_DR_DATA_Pos (0U)
<> 144:ef7eb2e8f9f7 1089 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 1090 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
<> 144:ef7eb2e8f9f7 1091 #define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1092 #define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1093 #define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1094 #define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1095 #define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1096 #define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1097 #define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1098 #define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 1099 #define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1100 #define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1101 #define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1102 #define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1103 #define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 1104 #define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 1105 #define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 1106 #define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /************************* ADC Common registers *****************************/
<> 144:ef7eb2e8f9f7 1109 /******************* Bit definition for ADC_CCR register ********************/
<> 144:ef7eb2e8f9f7 1110 #define ADC_CCR_VREFEN_Pos (22U)
<> 144:ef7eb2e8f9f7 1111 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 1112 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
<> 144:ef7eb2e8f9f7 1113 #define ADC_CCR_TSEN_Pos (23U)
<> 144:ef7eb2e8f9f7 1114 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 1115 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 #define ADC_CCR_VBATEN_Pos (24U)
<> 144:ef7eb2e8f9f7 1118 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 1119 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1122 /* */
<> 144:ef7eb2e8f9f7 1123 /* Controller Area Network (CAN ) */
<> 144:ef7eb2e8f9f7 1124 /* */
<> 144:ef7eb2e8f9f7 1125 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1126 /*!<CAN control and status registers */
<> 144:ef7eb2e8f9f7 1127 /******************* Bit definition for CAN_MCR register ********************/
<> 144:ef7eb2e8f9f7 1128 #define CAN_MCR_INRQ_Pos (0U)
<> 144:ef7eb2e8f9f7 1129 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1130 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
<> 144:ef7eb2e8f9f7 1131 #define CAN_MCR_SLEEP_Pos (1U)
<> 144:ef7eb2e8f9f7 1132 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1133 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
<> 144:ef7eb2e8f9f7 1134 #define CAN_MCR_TXFP_Pos (2U)
<> 144:ef7eb2e8f9f7 1135 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1136 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
<> 144:ef7eb2e8f9f7 1137 #define CAN_MCR_RFLM_Pos (3U)
<> 144:ef7eb2e8f9f7 1138 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1139 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
<> 144:ef7eb2e8f9f7 1140 #define CAN_MCR_NART_Pos (4U)
<> 144:ef7eb2e8f9f7 1141 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1142 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
<> 144:ef7eb2e8f9f7 1143 #define CAN_MCR_AWUM_Pos (5U)
<> 144:ef7eb2e8f9f7 1144 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1145 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
<> 144:ef7eb2e8f9f7 1146 #define CAN_MCR_ABOM_Pos (6U)
<> 144:ef7eb2e8f9f7 1147 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1148 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
<> 144:ef7eb2e8f9f7 1149 #define CAN_MCR_TTCM_Pos (7U)
<> 144:ef7eb2e8f9f7 1150 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 1151 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
<> 144:ef7eb2e8f9f7 1152 #define CAN_MCR_RESET_Pos (15U)
<> 144:ef7eb2e8f9f7 1153 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1154 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /******************* Bit definition for CAN_MSR register ********************/
<> 144:ef7eb2e8f9f7 1157 #define CAN_MSR_INAK_Pos (0U)
<> 144:ef7eb2e8f9f7 1158 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1159 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
<> 144:ef7eb2e8f9f7 1160 #define CAN_MSR_SLAK_Pos (1U)
<> 144:ef7eb2e8f9f7 1161 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1162 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
<> 144:ef7eb2e8f9f7 1163 #define CAN_MSR_ERRI_Pos (2U)
<> 144:ef7eb2e8f9f7 1164 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1165 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
<> 144:ef7eb2e8f9f7 1166 #define CAN_MSR_WKUI_Pos (3U)
<> 144:ef7eb2e8f9f7 1167 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1168 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
<> 144:ef7eb2e8f9f7 1169 #define CAN_MSR_SLAKI_Pos (4U)
<> 144:ef7eb2e8f9f7 1170 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1171 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
<> 144:ef7eb2e8f9f7 1172 #define CAN_MSR_TXM_Pos (8U)
<> 144:ef7eb2e8f9f7 1173 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1174 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
<> 144:ef7eb2e8f9f7 1175 #define CAN_MSR_RXM_Pos (9U)
<> 144:ef7eb2e8f9f7 1176 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1177 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
<> 144:ef7eb2e8f9f7 1178 #define CAN_MSR_SAMP_Pos (10U)
<> 144:ef7eb2e8f9f7 1179 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1180 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
<> 144:ef7eb2e8f9f7 1181 #define CAN_MSR_RX_Pos (11U)
<> 144:ef7eb2e8f9f7 1182 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1183 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /******************* Bit definition for CAN_TSR register ********************/
<> 144:ef7eb2e8f9f7 1186 #define CAN_TSR_RQCP0_Pos (0U)
<> 144:ef7eb2e8f9f7 1187 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1188 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
<> 144:ef7eb2e8f9f7 1189 #define CAN_TSR_TXOK0_Pos (1U)
<> 144:ef7eb2e8f9f7 1190 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1191 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
<> 144:ef7eb2e8f9f7 1192 #define CAN_TSR_ALST0_Pos (2U)
<> 144:ef7eb2e8f9f7 1193 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1194 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
<> 144:ef7eb2e8f9f7 1195 #define CAN_TSR_TERR0_Pos (3U)
<> 144:ef7eb2e8f9f7 1196 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1197 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
<> 144:ef7eb2e8f9f7 1198 #define CAN_TSR_ABRQ0_Pos (7U)
<> 144:ef7eb2e8f9f7 1199 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 1200 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
<> 144:ef7eb2e8f9f7 1201 #define CAN_TSR_RQCP1_Pos (8U)
<> 144:ef7eb2e8f9f7 1202 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1203 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
<> 144:ef7eb2e8f9f7 1204 #define CAN_TSR_TXOK1_Pos (9U)
<> 144:ef7eb2e8f9f7 1205 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1206 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
<> 144:ef7eb2e8f9f7 1207 #define CAN_TSR_ALST1_Pos (10U)
<> 144:ef7eb2e8f9f7 1208 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1209 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
<> 144:ef7eb2e8f9f7 1210 #define CAN_TSR_TERR1_Pos (11U)
<> 144:ef7eb2e8f9f7 1211 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1212 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
<> 144:ef7eb2e8f9f7 1213 #define CAN_TSR_ABRQ1_Pos (15U)
<> 144:ef7eb2e8f9f7 1214 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1215 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
<> 144:ef7eb2e8f9f7 1216 #define CAN_TSR_RQCP2_Pos (16U)
<> 144:ef7eb2e8f9f7 1217 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1218 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
<> 144:ef7eb2e8f9f7 1219 #define CAN_TSR_TXOK2_Pos (17U)
<> 144:ef7eb2e8f9f7 1220 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1221 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
<> 144:ef7eb2e8f9f7 1222 #define CAN_TSR_ALST2_Pos (18U)
<> 144:ef7eb2e8f9f7 1223 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 1224 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
<> 144:ef7eb2e8f9f7 1225 #define CAN_TSR_TERR2_Pos (19U)
<> 144:ef7eb2e8f9f7 1226 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 1227 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
<> 144:ef7eb2e8f9f7 1228 #define CAN_TSR_ABRQ2_Pos (23U)
<> 144:ef7eb2e8f9f7 1229 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 1230 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
<> 144:ef7eb2e8f9f7 1231 #define CAN_TSR_CODE_Pos (24U)
<> 144:ef7eb2e8f9f7 1232 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
<> 144:ef7eb2e8f9f7 1233 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 #define CAN_TSR_TME_Pos (26U)
<> 144:ef7eb2e8f9f7 1236 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
<> 144:ef7eb2e8f9f7 1237 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
<> 144:ef7eb2e8f9f7 1238 #define CAN_TSR_TME0_Pos (26U)
<> 144:ef7eb2e8f9f7 1239 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 1240 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
<> 144:ef7eb2e8f9f7 1241 #define CAN_TSR_TME1_Pos (27U)
<> 144:ef7eb2e8f9f7 1242 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 1243 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
<> 144:ef7eb2e8f9f7 1244 #define CAN_TSR_TME2_Pos (28U)
<> 144:ef7eb2e8f9f7 1245 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 1246 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 #define CAN_TSR_LOW_Pos (29U)
<> 144:ef7eb2e8f9f7 1249 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
<> 144:ef7eb2e8f9f7 1250 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
<> 144:ef7eb2e8f9f7 1251 #define CAN_TSR_LOW0_Pos (29U)
<> 144:ef7eb2e8f9f7 1252 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 1253 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
<> 144:ef7eb2e8f9f7 1254 #define CAN_TSR_LOW1_Pos (30U)
<> 144:ef7eb2e8f9f7 1255 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 1256 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
<> 144:ef7eb2e8f9f7 1257 #define CAN_TSR_LOW2_Pos (31U)
<> 144:ef7eb2e8f9f7 1258 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 1259 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 /******************* Bit definition for CAN_RF0R register *******************/
<> 144:ef7eb2e8f9f7 1262 #define CAN_RF0R_FMP0_Pos (0U)
<> 144:ef7eb2e8f9f7 1263 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 1264 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
<> 144:ef7eb2e8f9f7 1265 #define CAN_RF0R_FULL0_Pos (3U)
<> 144:ef7eb2e8f9f7 1266 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1267 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
<> 144:ef7eb2e8f9f7 1268 #define CAN_RF0R_FOVR0_Pos (4U)
<> 144:ef7eb2e8f9f7 1269 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1270 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
<> 144:ef7eb2e8f9f7 1271 #define CAN_RF0R_RFOM0_Pos (5U)
<> 144:ef7eb2e8f9f7 1272 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1273 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /******************* Bit definition for CAN_RF1R register *******************/
<> 144:ef7eb2e8f9f7 1276 #define CAN_RF1R_FMP1_Pos (0U)
<> 144:ef7eb2e8f9f7 1277 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 1278 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
<> 144:ef7eb2e8f9f7 1279 #define CAN_RF1R_FULL1_Pos (3U)
<> 144:ef7eb2e8f9f7 1280 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1281 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
<> 144:ef7eb2e8f9f7 1282 #define CAN_RF1R_FOVR1_Pos (4U)
<> 144:ef7eb2e8f9f7 1283 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1284 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
<> 144:ef7eb2e8f9f7 1285 #define CAN_RF1R_RFOM1_Pos (5U)
<> 144:ef7eb2e8f9f7 1286 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1287 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 /******************** Bit definition for CAN_IER register *******************/
<> 144:ef7eb2e8f9f7 1290 #define CAN_IER_TMEIE_Pos (0U)
<> 144:ef7eb2e8f9f7 1291 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1292 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 1293 #define CAN_IER_FMPIE0_Pos (1U)
<> 144:ef7eb2e8f9f7 1294 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1295 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
<> 144:ef7eb2e8f9f7 1296 #define CAN_IER_FFIE0_Pos (2U)
<> 144:ef7eb2e8f9f7 1297 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1298 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
<> 144:ef7eb2e8f9f7 1299 #define CAN_IER_FOVIE0_Pos (3U)
<> 144:ef7eb2e8f9f7 1300 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1301 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
<> 144:ef7eb2e8f9f7 1302 #define CAN_IER_FMPIE1_Pos (4U)
<> 144:ef7eb2e8f9f7 1303 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1304 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
<> 144:ef7eb2e8f9f7 1305 #define CAN_IER_FFIE1_Pos (5U)
<> 144:ef7eb2e8f9f7 1306 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1307 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
<> 144:ef7eb2e8f9f7 1308 #define CAN_IER_FOVIE1_Pos (6U)
<> 144:ef7eb2e8f9f7 1309 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1310 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
<> 144:ef7eb2e8f9f7 1311 #define CAN_IER_EWGIE_Pos (8U)
<> 144:ef7eb2e8f9f7 1312 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1313 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
<> 144:ef7eb2e8f9f7 1314 #define CAN_IER_EPVIE_Pos (9U)
<> 144:ef7eb2e8f9f7 1315 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1316 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
<> 144:ef7eb2e8f9f7 1317 #define CAN_IER_BOFIE_Pos (10U)
<> 144:ef7eb2e8f9f7 1318 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1319 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
<> 144:ef7eb2e8f9f7 1320 #define CAN_IER_LECIE_Pos (11U)
<> 144:ef7eb2e8f9f7 1321 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1322 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
<> 144:ef7eb2e8f9f7 1323 #define CAN_IER_ERRIE_Pos (15U)
<> 144:ef7eb2e8f9f7 1324 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1325 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 1326 #define CAN_IER_WKUIE_Pos (16U)
<> 144:ef7eb2e8f9f7 1327 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1328 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
<> 144:ef7eb2e8f9f7 1329 #define CAN_IER_SLKIE_Pos (17U)
<> 144:ef7eb2e8f9f7 1330 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1331 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /******************** Bit definition for CAN_ESR register *******************/
<> 144:ef7eb2e8f9f7 1334 #define CAN_ESR_EWGF_Pos (0U)
<> 144:ef7eb2e8f9f7 1335 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1336 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
<> 144:ef7eb2e8f9f7 1337 #define CAN_ESR_EPVF_Pos (1U)
<> 144:ef7eb2e8f9f7 1338 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1339 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
<> 144:ef7eb2e8f9f7 1340 #define CAN_ESR_BOFF_Pos (2U)
<> 144:ef7eb2e8f9f7 1341 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1342 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 #define CAN_ESR_LEC_Pos (4U)
<> 144:ef7eb2e8f9f7 1345 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 1346 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
<> 144:ef7eb2e8f9f7 1347 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1348 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1349 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 #define CAN_ESR_TEC_Pos (16U)
<> 144:ef7eb2e8f9f7 1352 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1353 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
<> 144:ef7eb2e8f9f7 1354 #define CAN_ESR_REC_Pos (24U)
<> 144:ef7eb2e8f9f7 1355 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1356 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 /******************* Bit definition for CAN_BTR register ********************/
<> 144:ef7eb2e8f9f7 1359 #define CAN_BTR_BRP_Pos (0U)
<> 144:ef7eb2e8f9f7 1360 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
<> 144:ef7eb2e8f9f7 1361 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
<> 144:ef7eb2e8f9f7 1362 #define CAN_BTR_TS1_Pos (16U)
<> 144:ef7eb2e8f9f7 1363 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
<> 144:ef7eb2e8f9f7 1364 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
<> 144:ef7eb2e8f9f7 1365 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1366 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1367 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 1368 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 1369 #define CAN_BTR_TS2_Pos (20U)
<> 144:ef7eb2e8f9f7 1370 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
<> 144:ef7eb2e8f9f7 1371 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
<> 144:ef7eb2e8f9f7 1372 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 1373 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 1374 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 1375 #define CAN_BTR_SJW_Pos (24U)
<> 144:ef7eb2e8f9f7 1376 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
<> 144:ef7eb2e8f9f7 1377 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
<> 144:ef7eb2e8f9f7 1378 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 1379 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 1380 #define CAN_BTR_LBKM_Pos (30U)
<> 144:ef7eb2e8f9f7 1381 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 1382 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
<> 144:ef7eb2e8f9f7 1383 #define CAN_BTR_SILM_Pos (31U)
<> 144:ef7eb2e8f9f7 1384 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 1385 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /*!<Mailbox registers */
<> 144:ef7eb2e8f9f7 1388 /****************** Bit definition for CAN_TI0R register ********************/
<> 144:ef7eb2e8f9f7 1389 #define CAN_TI0R_TXRQ_Pos (0U)
<> 144:ef7eb2e8f9f7 1390 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1391 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1392 #define CAN_TI0R_RTR_Pos (1U)
<> 144:ef7eb2e8f9f7 1393 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1394 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1395 #define CAN_TI0R_IDE_Pos (2U)
<> 144:ef7eb2e8f9f7 1396 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1397 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1398 #define CAN_TI0R_EXID_Pos (3U)
<> 144:ef7eb2e8f9f7 1399 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
<> 144:ef7eb2e8f9f7 1400 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1401 #define CAN_TI0R_STID_Pos (21U)
<> 144:ef7eb2e8f9f7 1402 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
<> 144:ef7eb2e8f9f7 1403 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 /****************** Bit definition for CAN_TDT0R register *******************/
<> 144:ef7eb2e8f9f7 1406 #define CAN_TDT0R_DLC_Pos (0U)
<> 144:ef7eb2e8f9f7 1407 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 1408 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1409 #define CAN_TDT0R_TGT_Pos (8U)
<> 144:ef7eb2e8f9f7 1410 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1411 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1412 #define CAN_TDT0R_TIME_Pos (16U)
<> 144:ef7eb2e8f9f7 1413 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
<> 144:ef7eb2e8f9f7 1414 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /****************** Bit definition for CAN_TDL0R register *******************/
<> 144:ef7eb2e8f9f7 1417 #define CAN_TDL0R_DATA0_Pos (0U)
<> 144:ef7eb2e8f9f7 1418 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1419 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1420 #define CAN_TDL0R_DATA1_Pos (8U)
<> 144:ef7eb2e8f9f7 1421 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1422 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1423 #define CAN_TDL0R_DATA2_Pos (16U)
<> 144:ef7eb2e8f9f7 1424 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1425 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1426 #define CAN_TDL0R_DATA3_Pos (24U)
<> 144:ef7eb2e8f9f7 1427 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1428 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1429
<> 144:ef7eb2e8f9f7 1430 /****************** Bit definition for CAN_TDH0R register *******************/
<> 144:ef7eb2e8f9f7 1431 #define CAN_TDH0R_DATA4_Pos (0U)
<> 144:ef7eb2e8f9f7 1432 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1433 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1434 #define CAN_TDH0R_DATA5_Pos (8U)
<> 144:ef7eb2e8f9f7 1435 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1436 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1437 #define CAN_TDH0R_DATA6_Pos (16U)
<> 144:ef7eb2e8f9f7 1438 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1439 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1440 #define CAN_TDH0R_DATA7_Pos (24U)
<> 144:ef7eb2e8f9f7 1441 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1442 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /******************* Bit definition for CAN_TI1R register *******************/
<> 144:ef7eb2e8f9f7 1445 #define CAN_TI1R_TXRQ_Pos (0U)
<> 144:ef7eb2e8f9f7 1446 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1447 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1448 #define CAN_TI1R_RTR_Pos (1U)
<> 144:ef7eb2e8f9f7 1449 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1450 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1451 #define CAN_TI1R_IDE_Pos (2U)
<> 144:ef7eb2e8f9f7 1452 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1453 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1454 #define CAN_TI1R_EXID_Pos (3U)
<> 144:ef7eb2e8f9f7 1455 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
<> 144:ef7eb2e8f9f7 1456 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1457 #define CAN_TI1R_STID_Pos (21U)
<> 144:ef7eb2e8f9f7 1458 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
<> 144:ef7eb2e8f9f7 1459 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 /******************* Bit definition for CAN_TDT1R register ******************/
<> 144:ef7eb2e8f9f7 1462 #define CAN_TDT1R_DLC_Pos (0U)
<> 144:ef7eb2e8f9f7 1463 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 1464 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1465 #define CAN_TDT1R_TGT_Pos (8U)
<> 144:ef7eb2e8f9f7 1466 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1467 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1468 #define CAN_TDT1R_TIME_Pos (16U)
<> 144:ef7eb2e8f9f7 1469 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
<> 144:ef7eb2e8f9f7 1470 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1471
<> 144:ef7eb2e8f9f7 1472 /******************* Bit definition for CAN_TDL1R register ******************/
<> 144:ef7eb2e8f9f7 1473 #define CAN_TDL1R_DATA0_Pos (0U)
<> 144:ef7eb2e8f9f7 1474 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1475 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1476 #define CAN_TDL1R_DATA1_Pos (8U)
<> 144:ef7eb2e8f9f7 1477 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1478 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1479 #define CAN_TDL1R_DATA2_Pos (16U)
<> 144:ef7eb2e8f9f7 1480 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1481 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1482 #define CAN_TDL1R_DATA3_Pos (24U)
<> 144:ef7eb2e8f9f7 1483 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1484 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 /******************* Bit definition for CAN_TDH1R register ******************/
<> 144:ef7eb2e8f9f7 1487 #define CAN_TDH1R_DATA4_Pos (0U)
<> 144:ef7eb2e8f9f7 1488 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1489 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1490 #define CAN_TDH1R_DATA5_Pos (8U)
<> 144:ef7eb2e8f9f7 1491 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1492 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1493 #define CAN_TDH1R_DATA6_Pos (16U)
<> 144:ef7eb2e8f9f7 1494 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1495 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1496 #define CAN_TDH1R_DATA7_Pos (24U)
<> 144:ef7eb2e8f9f7 1497 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1498 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /******************* Bit definition for CAN_TI2R register *******************/
<> 144:ef7eb2e8f9f7 1501 #define CAN_TI2R_TXRQ_Pos (0U)
<> 144:ef7eb2e8f9f7 1502 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1503 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1504 #define CAN_TI2R_RTR_Pos (1U)
<> 144:ef7eb2e8f9f7 1505 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1506 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1507 #define CAN_TI2R_IDE_Pos (2U)
<> 144:ef7eb2e8f9f7 1508 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1509 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1510 #define CAN_TI2R_EXID_Pos (3U)
<> 144:ef7eb2e8f9f7 1511 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
<> 144:ef7eb2e8f9f7 1512 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
<> 144:ef7eb2e8f9f7 1513 #define CAN_TI2R_STID_Pos (21U)
<> 144:ef7eb2e8f9f7 1514 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
<> 144:ef7eb2e8f9f7 1515 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 /******************* Bit definition for CAN_TDT2R register ******************/
<> 144:ef7eb2e8f9f7 1518 #define CAN_TDT2R_DLC_Pos (0U)
<> 144:ef7eb2e8f9f7 1519 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 1520 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1521 #define CAN_TDT2R_TGT_Pos (8U)
<> 144:ef7eb2e8f9f7 1522 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1523 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1524 #define CAN_TDT2R_TIME_Pos (16U)
<> 144:ef7eb2e8f9f7 1525 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
<> 144:ef7eb2e8f9f7 1526 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 /******************* Bit definition for CAN_TDL2R register ******************/
<> 144:ef7eb2e8f9f7 1529 #define CAN_TDL2R_DATA0_Pos (0U)
<> 144:ef7eb2e8f9f7 1530 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1531 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1532 #define CAN_TDL2R_DATA1_Pos (8U)
<> 144:ef7eb2e8f9f7 1533 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1534 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1535 #define CAN_TDL2R_DATA2_Pos (16U)
<> 144:ef7eb2e8f9f7 1536 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1537 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1538 #define CAN_TDL2R_DATA3_Pos (24U)
<> 144:ef7eb2e8f9f7 1539 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1540 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 /******************* Bit definition for CAN_TDH2R register ******************/
<> 144:ef7eb2e8f9f7 1543 #define CAN_TDH2R_DATA4_Pos (0U)
<> 144:ef7eb2e8f9f7 1544 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1545 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1546 #define CAN_TDH2R_DATA5_Pos (8U)
<> 144:ef7eb2e8f9f7 1547 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1548 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1549 #define CAN_TDH2R_DATA6_Pos (16U)
<> 144:ef7eb2e8f9f7 1550 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1551 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1552 #define CAN_TDH2R_DATA7_Pos (24U)
<> 144:ef7eb2e8f9f7 1553 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1554 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /******************* Bit definition for CAN_RI0R register *******************/
<> 144:ef7eb2e8f9f7 1557 #define CAN_RI0R_RTR_Pos (1U)
<> 144:ef7eb2e8f9f7 1558 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1559 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1560 #define CAN_RI0R_IDE_Pos (2U)
<> 144:ef7eb2e8f9f7 1561 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1562 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1563 #define CAN_RI0R_EXID_Pos (3U)
<> 144:ef7eb2e8f9f7 1564 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
<> 144:ef7eb2e8f9f7 1565 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1566 #define CAN_RI0R_STID_Pos (21U)
<> 144:ef7eb2e8f9f7 1567 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
<> 144:ef7eb2e8f9f7 1568 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /******************* Bit definition for CAN_RDT0R register ******************/
<> 144:ef7eb2e8f9f7 1571 #define CAN_RDT0R_DLC_Pos (0U)
<> 144:ef7eb2e8f9f7 1572 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 1573 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1574 #define CAN_RDT0R_FMI_Pos (8U)
<> 144:ef7eb2e8f9f7 1575 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1576 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
<> 144:ef7eb2e8f9f7 1577 #define CAN_RDT0R_TIME_Pos (16U)
<> 144:ef7eb2e8f9f7 1578 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
<> 144:ef7eb2e8f9f7 1579 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 /******************* Bit definition for CAN_RDL0R register ******************/
<> 144:ef7eb2e8f9f7 1582 #define CAN_RDL0R_DATA0_Pos (0U)
<> 144:ef7eb2e8f9f7 1583 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1584 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1585 #define CAN_RDL0R_DATA1_Pos (8U)
<> 144:ef7eb2e8f9f7 1586 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1587 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1588 #define CAN_RDL0R_DATA2_Pos (16U)
<> 144:ef7eb2e8f9f7 1589 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1590 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1591 #define CAN_RDL0R_DATA3_Pos (24U)
<> 144:ef7eb2e8f9f7 1592 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1593 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /******************* Bit definition for CAN_RDH0R register ******************/
<> 144:ef7eb2e8f9f7 1596 #define CAN_RDH0R_DATA4_Pos (0U)
<> 144:ef7eb2e8f9f7 1597 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1598 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1599 #define CAN_RDH0R_DATA5_Pos (8U)
<> 144:ef7eb2e8f9f7 1600 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1601 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1602 #define CAN_RDH0R_DATA6_Pos (16U)
<> 144:ef7eb2e8f9f7 1603 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1604 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1605 #define CAN_RDH0R_DATA7_Pos (24U)
<> 144:ef7eb2e8f9f7 1606 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1607 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 /******************* Bit definition for CAN_RI1R register *******************/
<> 144:ef7eb2e8f9f7 1610 #define CAN_RI1R_RTR_Pos (1U)
<> 144:ef7eb2e8f9f7 1611 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1612 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1613 #define CAN_RI1R_IDE_Pos (2U)
<> 144:ef7eb2e8f9f7 1614 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1615 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1616 #define CAN_RI1R_EXID_Pos (3U)
<> 144:ef7eb2e8f9f7 1617 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
<> 144:ef7eb2e8f9f7 1618 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
<> 144:ef7eb2e8f9f7 1619 #define CAN_RI1R_STID_Pos (21U)
<> 144:ef7eb2e8f9f7 1620 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
<> 144:ef7eb2e8f9f7 1621 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1622
<> 144:ef7eb2e8f9f7 1623 /******************* Bit definition for CAN_RDT1R register ******************/
<> 144:ef7eb2e8f9f7 1624 #define CAN_RDT1R_DLC_Pos (0U)
<> 144:ef7eb2e8f9f7 1625 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 1626 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1627 #define CAN_RDT1R_FMI_Pos (8U)
<> 144:ef7eb2e8f9f7 1628 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1629 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
<> 144:ef7eb2e8f9f7 1630 #define CAN_RDT1R_TIME_Pos (16U)
<> 144:ef7eb2e8f9f7 1631 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
<> 144:ef7eb2e8f9f7 1632 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1633
<> 144:ef7eb2e8f9f7 1634 /******************* Bit definition for CAN_RDL1R register ******************/
<> 144:ef7eb2e8f9f7 1635 #define CAN_RDL1R_DATA0_Pos (0U)
<> 144:ef7eb2e8f9f7 1636 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1637 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1638 #define CAN_RDL1R_DATA1_Pos (8U)
<> 144:ef7eb2e8f9f7 1639 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1640 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1641 #define CAN_RDL1R_DATA2_Pos (16U)
<> 144:ef7eb2e8f9f7 1642 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1643 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1644 #define CAN_RDL1R_DATA3_Pos (24U)
<> 144:ef7eb2e8f9f7 1645 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1646 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 /******************* Bit definition for CAN_RDH1R register ******************/
<> 144:ef7eb2e8f9f7 1649 #define CAN_RDH1R_DATA4_Pos (0U)
<> 144:ef7eb2e8f9f7 1650 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 1651 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1652 #define CAN_RDH1R_DATA5_Pos (8U)
<> 144:ef7eb2e8f9f7 1653 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 1654 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1655 #define CAN_RDH1R_DATA6_Pos (16U)
<> 144:ef7eb2e8f9f7 1656 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 1657 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1658 #define CAN_RDH1R_DATA7_Pos (24U)
<> 144:ef7eb2e8f9f7 1659 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 1660 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 /*!<CAN filter registers */
<> 144:ef7eb2e8f9f7 1663 /******************* Bit definition for CAN_FMR register ********************/
<> 144:ef7eb2e8f9f7 1664 #define CAN_FMR_FINIT_Pos (0U)
<> 144:ef7eb2e8f9f7 1665 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1666 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
<> 144:ef7eb2e8f9f7 1667 #define CAN_FMR_CAN2SB_Pos (8U)
<> 144:ef7eb2e8f9f7 1668 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
<> 144:ef7eb2e8f9f7 1669 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
<> 144:ef7eb2e8f9f7 1670
<> 144:ef7eb2e8f9f7 1671 /******************* Bit definition for CAN_FM1R register *******************/
<> 144:ef7eb2e8f9f7 1672 #define CAN_FM1R_FBM_Pos (0U)
<> 144:ef7eb2e8f9f7 1673 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
<> 144:ef7eb2e8f9f7 1674 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
<> 144:ef7eb2e8f9f7 1675 #define CAN_FM1R_FBM0_Pos (0U)
<> 144:ef7eb2e8f9f7 1676 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1677 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
<> 144:ef7eb2e8f9f7 1678 #define CAN_FM1R_FBM1_Pos (1U)
<> 144:ef7eb2e8f9f7 1679 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1680 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
<> 144:ef7eb2e8f9f7 1681 #define CAN_FM1R_FBM2_Pos (2U)
<> 144:ef7eb2e8f9f7 1682 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1683 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
<> 144:ef7eb2e8f9f7 1684 #define CAN_FM1R_FBM3_Pos (3U)
<> 144:ef7eb2e8f9f7 1685 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1686 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
<> 144:ef7eb2e8f9f7 1687 #define CAN_FM1R_FBM4_Pos (4U)
<> 144:ef7eb2e8f9f7 1688 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1689 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
<> 144:ef7eb2e8f9f7 1690 #define CAN_FM1R_FBM5_Pos (5U)
<> 144:ef7eb2e8f9f7 1691 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1692 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
<> 144:ef7eb2e8f9f7 1693 #define CAN_FM1R_FBM6_Pos (6U)
<> 144:ef7eb2e8f9f7 1694 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1695 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
<> 144:ef7eb2e8f9f7 1696 #define CAN_FM1R_FBM7_Pos (7U)
<> 144:ef7eb2e8f9f7 1697 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 1698 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
<> 144:ef7eb2e8f9f7 1699 #define CAN_FM1R_FBM8_Pos (8U)
<> 144:ef7eb2e8f9f7 1700 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1701 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
<> 144:ef7eb2e8f9f7 1702 #define CAN_FM1R_FBM9_Pos (9U)
<> 144:ef7eb2e8f9f7 1703 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1704 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
<> 144:ef7eb2e8f9f7 1705 #define CAN_FM1R_FBM10_Pos (10U)
<> 144:ef7eb2e8f9f7 1706 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1707 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
<> 144:ef7eb2e8f9f7 1708 #define CAN_FM1R_FBM11_Pos (11U)
<> 144:ef7eb2e8f9f7 1709 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1710 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
<> 144:ef7eb2e8f9f7 1711 #define CAN_FM1R_FBM12_Pos (12U)
<> 144:ef7eb2e8f9f7 1712 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 1713 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
<> 144:ef7eb2e8f9f7 1714 #define CAN_FM1R_FBM13_Pos (13U)
<> 144:ef7eb2e8f9f7 1715 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 1716 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
<> 144:ef7eb2e8f9f7 1717 #define CAN_FM1R_FBM14_Pos (14U)
<> 144:ef7eb2e8f9f7 1718 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 1719 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
<> 144:ef7eb2e8f9f7 1720 #define CAN_FM1R_FBM15_Pos (15U)
<> 144:ef7eb2e8f9f7 1721 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1722 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
<> 144:ef7eb2e8f9f7 1723 #define CAN_FM1R_FBM16_Pos (16U)
<> 144:ef7eb2e8f9f7 1724 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1725 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
<> 144:ef7eb2e8f9f7 1726 #define CAN_FM1R_FBM17_Pos (17U)
<> 144:ef7eb2e8f9f7 1727 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1728 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
<> 144:ef7eb2e8f9f7 1729 #define CAN_FM1R_FBM18_Pos (18U)
<> 144:ef7eb2e8f9f7 1730 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 1731 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
<> 144:ef7eb2e8f9f7 1732 #define CAN_FM1R_FBM19_Pos (19U)
<> 144:ef7eb2e8f9f7 1733 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 1734 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
<> 144:ef7eb2e8f9f7 1735 #define CAN_FM1R_FBM20_Pos (20U)
<> 144:ef7eb2e8f9f7 1736 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 1737 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
<> 144:ef7eb2e8f9f7 1738 #define CAN_FM1R_FBM21_Pos (21U)
<> 144:ef7eb2e8f9f7 1739 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 1740 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
<> 144:ef7eb2e8f9f7 1741 #define CAN_FM1R_FBM22_Pos (22U)
<> 144:ef7eb2e8f9f7 1742 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 1743 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
<> 144:ef7eb2e8f9f7 1744 #define CAN_FM1R_FBM23_Pos (23U)
<> 144:ef7eb2e8f9f7 1745 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 1746 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
<> 144:ef7eb2e8f9f7 1747 #define CAN_FM1R_FBM24_Pos (24U)
<> 144:ef7eb2e8f9f7 1748 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 1749 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
<> 144:ef7eb2e8f9f7 1750 #define CAN_FM1R_FBM25_Pos (25U)
<> 144:ef7eb2e8f9f7 1751 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 1752 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
<> 144:ef7eb2e8f9f7 1753 #define CAN_FM1R_FBM26_Pos (26U)
<> 144:ef7eb2e8f9f7 1754 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 1755 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
<> 144:ef7eb2e8f9f7 1756 #define CAN_FM1R_FBM27_Pos (27U)
<> 144:ef7eb2e8f9f7 1757 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 1758 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
<> 144:ef7eb2e8f9f7 1759
<> 144:ef7eb2e8f9f7 1760 /******************* Bit definition for CAN_FS1R register *******************/
<> 144:ef7eb2e8f9f7 1761 #define CAN_FS1R_FSC_Pos (0U)
<> 144:ef7eb2e8f9f7 1762 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
<> 144:ef7eb2e8f9f7 1763 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
<> 144:ef7eb2e8f9f7 1764 #define CAN_FS1R_FSC0_Pos (0U)
<> 144:ef7eb2e8f9f7 1765 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1766 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
<> 144:ef7eb2e8f9f7 1767 #define CAN_FS1R_FSC1_Pos (1U)
<> 144:ef7eb2e8f9f7 1768 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1769 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
<> 144:ef7eb2e8f9f7 1770 #define CAN_FS1R_FSC2_Pos (2U)
<> 144:ef7eb2e8f9f7 1771 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1772 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
<> 144:ef7eb2e8f9f7 1773 #define CAN_FS1R_FSC3_Pos (3U)
<> 144:ef7eb2e8f9f7 1774 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1775 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
<> 144:ef7eb2e8f9f7 1776 #define CAN_FS1R_FSC4_Pos (4U)
<> 144:ef7eb2e8f9f7 1777 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1778 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
<> 144:ef7eb2e8f9f7 1779 #define CAN_FS1R_FSC5_Pos (5U)
<> 144:ef7eb2e8f9f7 1780 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1781 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
<> 144:ef7eb2e8f9f7 1782 #define CAN_FS1R_FSC6_Pos (6U)
<> 144:ef7eb2e8f9f7 1783 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1784 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
<> 144:ef7eb2e8f9f7 1785 #define CAN_FS1R_FSC7_Pos (7U)
<> 144:ef7eb2e8f9f7 1786 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 1787 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
<> 144:ef7eb2e8f9f7 1788 #define CAN_FS1R_FSC8_Pos (8U)
<> 144:ef7eb2e8f9f7 1789 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1790 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
<> 144:ef7eb2e8f9f7 1791 #define CAN_FS1R_FSC9_Pos (9U)
<> 144:ef7eb2e8f9f7 1792 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1793 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
<> 144:ef7eb2e8f9f7 1794 #define CAN_FS1R_FSC10_Pos (10U)
<> 144:ef7eb2e8f9f7 1795 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1796 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
<> 144:ef7eb2e8f9f7 1797 #define CAN_FS1R_FSC11_Pos (11U)
<> 144:ef7eb2e8f9f7 1798 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1799 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
<> 144:ef7eb2e8f9f7 1800 #define CAN_FS1R_FSC12_Pos (12U)
<> 144:ef7eb2e8f9f7 1801 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 1802 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
<> 144:ef7eb2e8f9f7 1803 #define CAN_FS1R_FSC13_Pos (13U)
<> 144:ef7eb2e8f9f7 1804 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 1805 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
<> 144:ef7eb2e8f9f7 1806 #define CAN_FS1R_FSC14_Pos (14U)
<> 144:ef7eb2e8f9f7 1807 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 1808 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
<> 144:ef7eb2e8f9f7 1809 #define CAN_FS1R_FSC15_Pos (15U)
<> 144:ef7eb2e8f9f7 1810 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1811 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
<> 144:ef7eb2e8f9f7 1812 #define CAN_FS1R_FSC16_Pos (16U)
<> 144:ef7eb2e8f9f7 1813 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1814 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
<> 144:ef7eb2e8f9f7 1815 #define CAN_FS1R_FSC17_Pos (17U)
<> 144:ef7eb2e8f9f7 1816 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1817 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
<> 144:ef7eb2e8f9f7 1818 #define CAN_FS1R_FSC18_Pos (18U)
<> 144:ef7eb2e8f9f7 1819 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 1820 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
<> 144:ef7eb2e8f9f7 1821 #define CAN_FS1R_FSC19_Pos (19U)
<> 144:ef7eb2e8f9f7 1822 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 1823 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
<> 144:ef7eb2e8f9f7 1824 #define CAN_FS1R_FSC20_Pos (20U)
<> 144:ef7eb2e8f9f7 1825 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 1826 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
<> 144:ef7eb2e8f9f7 1827 #define CAN_FS1R_FSC21_Pos (21U)
<> 144:ef7eb2e8f9f7 1828 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 1829 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
<> 144:ef7eb2e8f9f7 1830 #define CAN_FS1R_FSC22_Pos (22U)
<> 144:ef7eb2e8f9f7 1831 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 1832 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
<> 144:ef7eb2e8f9f7 1833 #define CAN_FS1R_FSC23_Pos (23U)
<> 144:ef7eb2e8f9f7 1834 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 1835 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
<> 144:ef7eb2e8f9f7 1836 #define CAN_FS1R_FSC24_Pos (24U)
<> 144:ef7eb2e8f9f7 1837 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 1838 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
<> 144:ef7eb2e8f9f7 1839 #define CAN_FS1R_FSC25_Pos (25U)
<> 144:ef7eb2e8f9f7 1840 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 1841 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
<> 144:ef7eb2e8f9f7 1842 #define CAN_FS1R_FSC26_Pos (26U)
<> 144:ef7eb2e8f9f7 1843 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 1844 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
<> 144:ef7eb2e8f9f7 1845 #define CAN_FS1R_FSC27_Pos (27U)
<> 144:ef7eb2e8f9f7 1846 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 1847 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
<> 144:ef7eb2e8f9f7 1848
<> 144:ef7eb2e8f9f7 1849 /****************** Bit definition for CAN_FFA1R register *******************/
<> 144:ef7eb2e8f9f7 1850 #define CAN_FFA1R_FFA_Pos (0U)
<> 144:ef7eb2e8f9f7 1851 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
<> 144:ef7eb2e8f9f7 1852 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
<> 144:ef7eb2e8f9f7 1853 #define CAN_FFA1R_FFA0_Pos (0U)
<> 144:ef7eb2e8f9f7 1854 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1855 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
<> 144:ef7eb2e8f9f7 1856 #define CAN_FFA1R_FFA1_Pos (1U)
<> 144:ef7eb2e8f9f7 1857 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1858 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
<> 144:ef7eb2e8f9f7 1859 #define CAN_FFA1R_FFA2_Pos (2U)
<> 144:ef7eb2e8f9f7 1860 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1861 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
<> 144:ef7eb2e8f9f7 1862 #define CAN_FFA1R_FFA3_Pos (3U)
<> 144:ef7eb2e8f9f7 1863 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1864 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
<> 144:ef7eb2e8f9f7 1865 #define CAN_FFA1R_FFA4_Pos (4U)
<> 144:ef7eb2e8f9f7 1866 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1867 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
<> 144:ef7eb2e8f9f7 1868 #define CAN_FFA1R_FFA5_Pos (5U)
<> 144:ef7eb2e8f9f7 1869 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1870 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
<> 144:ef7eb2e8f9f7 1871 #define CAN_FFA1R_FFA6_Pos (6U)
<> 144:ef7eb2e8f9f7 1872 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1873 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
<> 144:ef7eb2e8f9f7 1874 #define CAN_FFA1R_FFA7_Pos (7U)
<> 144:ef7eb2e8f9f7 1875 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 1876 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
<> 144:ef7eb2e8f9f7 1877 #define CAN_FFA1R_FFA8_Pos (8U)
<> 144:ef7eb2e8f9f7 1878 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1879 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
<> 144:ef7eb2e8f9f7 1880 #define CAN_FFA1R_FFA9_Pos (9U)
<> 144:ef7eb2e8f9f7 1881 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1882 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
<> 144:ef7eb2e8f9f7 1883 #define CAN_FFA1R_FFA10_Pos (10U)
<> 144:ef7eb2e8f9f7 1884 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1885 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
<> 144:ef7eb2e8f9f7 1886 #define CAN_FFA1R_FFA11_Pos (11U)
<> 144:ef7eb2e8f9f7 1887 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1888 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
<> 144:ef7eb2e8f9f7 1889 #define CAN_FFA1R_FFA12_Pos (12U)
<> 144:ef7eb2e8f9f7 1890 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 1891 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
<> 144:ef7eb2e8f9f7 1892 #define CAN_FFA1R_FFA13_Pos (13U)
<> 144:ef7eb2e8f9f7 1893 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 1894 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
<> 144:ef7eb2e8f9f7 1895 #define CAN_FFA1R_FFA14_Pos (14U)
<> 144:ef7eb2e8f9f7 1896 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 1897 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
<> 144:ef7eb2e8f9f7 1898 #define CAN_FFA1R_FFA15_Pos (15U)
<> 144:ef7eb2e8f9f7 1899 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1900 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
<> 144:ef7eb2e8f9f7 1901 #define CAN_FFA1R_FFA16_Pos (16U)
<> 144:ef7eb2e8f9f7 1902 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1903 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
<> 144:ef7eb2e8f9f7 1904 #define CAN_FFA1R_FFA17_Pos (17U)
<> 144:ef7eb2e8f9f7 1905 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1906 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
<> 144:ef7eb2e8f9f7 1907 #define CAN_FFA1R_FFA18_Pos (18U)
<> 144:ef7eb2e8f9f7 1908 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 1909 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
<> 144:ef7eb2e8f9f7 1910 #define CAN_FFA1R_FFA19_Pos (19U)
<> 144:ef7eb2e8f9f7 1911 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 1912 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
<> 144:ef7eb2e8f9f7 1913 #define CAN_FFA1R_FFA20_Pos (20U)
<> 144:ef7eb2e8f9f7 1914 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 1915 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
<> 144:ef7eb2e8f9f7 1916 #define CAN_FFA1R_FFA21_Pos (21U)
<> 144:ef7eb2e8f9f7 1917 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 1918 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
<> 144:ef7eb2e8f9f7 1919 #define CAN_FFA1R_FFA22_Pos (22U)
<> 144:ef7eb2e8f9f7 1920 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 1921 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
<> 144:ef7eb2e8f9f7 1922 #define CAN_FFA1R_FFA23_Pos (23U)
<> 144:ef7eb2e8f9f7 1923 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 1924 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
<> 144:ef7eb2e8f9f7 1925 #define CAN_FFA1R_FFA24_Pos (24U)
<> 144:ef7eb2e8f9f7 1926 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 1927 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
<> 144:ef7eb2e8f9f7 1928 #define CAN_FFA1R_FFA25_Pos (25U)
<> 144:ef7eb2e8f9f7 1929 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 1930 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
<> 144:ef7eb2e8f9f7 1931 #define CAN_FFA1R_FFA26_Pos (26U)
<> 144:ef7eb2e8f9f7 1932 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 1933 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
<> 144:ef7eb2e8f9f7 1934 #define CAN_FFA1R_FFA27_Pos (27U)
<> 144:ef7eb2e8f9f7 1935 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 1936 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
<> 144:ef7eb2e8f9f7 1937
<> 144:ef7eb2e8f9f7 1938 /******************* Bit definition for CAN_FA1R register *******************/
<> 144:ef7eb2e8f9f7 1939 #define CAN_FA1R_FACT_Pos (0U)
<> 144:ef7eb2e8f9f7 1940 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
<> 144:ef7eb2e8f9f7 1941 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
<> 144:ef7eb2e8f9f7 1942 #define CAN_FA1R_FACT0_Pos (0U)
<> 144:ef7eb2e8f9f7 1943 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 1944 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
<> 144:ef7eb2e8f9f7 1945 #define CAN_FA1R_FACT1_Pos (1U)
<> 144:ef7eb2e8f9f7 1946 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 1947 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
<> 144:ef7eb2e8f9f7 1948 #define CAN_FA1R_FACT2_Pos (2U)
<> 144:ef7eb2e8f9f7 1949 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 1950 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
<> 144:ef7eb2e8f9f7 1951 #define CAN_FA1R_FACT3_Pos (3U)
<> 144:ef7eb2e8f9f7 1952 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 1953 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
<> 144:ef7eb2e8f9f7 1954 #define CAN_FA1R_FACT4_Pos (4U)
<> 144:ef7eb2e8f9f7 1955 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 1956 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
<> 144:ef7eb2e8f9f7 1957 #define CAN_FA1R_FACT5_Pos (5U)
<> 144:ef7eb2e8f9f7 1958 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 1959 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
<> 144:ef7eb2e8f9f7 1960 #define CAN_FA1R_FACT6_Pos (6U)
<> 144:ef7eb2e8f9f7 1961 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 1962 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
<> 144:ef7eb2e8f9f7 1963 #define CAN_FA1R_FACT7_Pos (7U)
<> 144:ef7eb2e8f9f7 1964 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 1965 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
<> 144:ef7eb2e8f9f7 1966 #define CAN_FA1R_FACT8_Pos (8U)
<> 144:ef7eb2e8f9f7 1967 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 1968 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
<> 144:ef7eb2e8f9f7 1969 #define CAN_FA1R_FACT9_Pos (9U)
<> 144:ef7eb2e8f9f7 1970 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 1971 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
<> 144:ef7eb2e8f9f7 1972 #define CAN_FA1R_FACT10_Pos (10U)
<> 144:ef7eb2e8f9f7 1973 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 1974 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
<> 144:ef7eb2e8f9f7 1975 #define CAN_FA1R_FACT11_Pos (11U)
<> 144:ef7eb2e8f9f7 1976 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 1977 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
<> 144:ef7eb2e8f9f7 1978 #define CAN_FA1R_FACT12_Pos (12U)
<> 144:ef7eb2e8f9f7 1979 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 1980 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
<> 144:ef7eb2e8f9f7 1981 #define CAN_FA1R_FACT13_Pos (13U)
<> 144:ef7eb2e8f9f7 1982 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 1983 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
<> 144:ef7eb2e8f9f7 1984 #define CAN_FA1R_FACT14_Pos (14U)
<> 144:ef7eb2e8f9f7 1985 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 1986 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
<> 144:ef7eb2e8f9f7 1987 #define CAN_FA1R_FACT15_Pos (15U)
<> 144:ef7eb2e8f9f7 1988 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 1989 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
<> 144:ef7eb2e8f9f7 1990 #define CAN_FA1R_FACT16_Pos (16U)
<> 144:ef7eb2e8f9f7 1991 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 1992 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
<> 144:ef7eb2e8f9f7 1993 #define CAN_FA1R_FACT17_Pos (17U)
<> 144:ef7eb2e8f9f7 1994 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 1995 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
<> 144:ef7eb2e8f9f7 1996 #define CAN_FA1R_FACT18_Pos (18U)
<> 144:ef7eb2e8f9f7 1997 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 1998 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
<> 144:ef7eb2e8f9f7 1999 #define CAN_FA1R_FACT19_Pos (19U)
<> 144:ef7eb2e8f9f7 2000 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2001 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
<> 144:ef7eb2e8f9f7 2002 #define CAN_FA1R_FACT20_Pos (20U)
<> 144:ef7eb2e8f9f7 2003 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2004 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
<> 144:ef7eb2e8f9f7 2005 #define CAN_FA1R_FACT21_Pos (21U)
<> 144:ef7eb2e8f9f7 2006 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2007 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
<> 144:ef7eb2e8f9f7 2008 #define CAN_FA1R_FACT22_Pos (22U)
<> 144:ef7eb2e8f9f7 2009 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2010 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
<> 144:ef7eb2e8f9f7 2011 #define CAN_FA1R_FACT23_Pos (23U)
<> 144:ef7eb2e8f9f7 2012 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2013 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
<> 144:ef7eb2e8f9f7 2014 #define CAN_FA1R_FACT24_Pos (24U)
<> 144:ef7eb2e8f9f7 2015 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2016 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
<> 144:ef7eb2e8f9f7 2017 #define CAN_FA1R_FACT25_Pos (25U)
<> 144:ef7eb2e8f9f7 2018 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2019 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
<> 144:ef7eb2e8f9f7 2020 #define CAN_FA1R_FACT26_Pos (26U)
<> 144:ef7eb2e8f9f7 2021 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2022 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
<> 144:ef7eb2e8f9f7 2023 #define CAN_FA1R_FACT27_Pos (27U)
<> 144:ef7eb2e8f9f7 2024 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2025 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
<> 144:ef7eb2e8f9f7 2026
<> 144:ef7eb2e8f9f7 2027 /******************* Bit definition for CAN_F0R1 register *******************/
<> 144:ef7eb2e8f9f7 2028 #define CAN_F0R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2029 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2030 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2031 #define CAN_F0R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2032 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2033 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2034 #define CAN_F0R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2035 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2036 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2037 #define CAN_F0R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2038 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2039 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2040 #define CAN_F0R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2041 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2042 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2043 #define CAN_F0R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2044 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2045 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2046 #define CAN_F0R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2047 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2048 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2049 #define CAN_F0R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2050 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2051 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2052 #define CAN_F0R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2053 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2054 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2055 #define CAN_F0R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2056 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2057 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2058 #define CAN_F0R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2059 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2060 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2061 #define CAN_F0R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2062 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2063 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2064 #define CAN_F0R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2065 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2066 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2067 #define CAN_F0R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2068 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2069 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2070 #define CAN_F0R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2071 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2072 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2073 #define CAN_F0R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2074 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2075 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2076 #define CAN_F0R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2077 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2078 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2079 #define CAN_F0R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2080 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2081 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2082 #define CAN_F0R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2083 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2084 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2085 #define CAN_F0R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2086 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2087 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2088 #define CAN_F0R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2089 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2090 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2091 #define CAN_F0R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2092 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2093 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2094 #define CAN_F0R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2095 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2096 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2097 #define CAN_F0R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2098 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2099 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2100 #define CAN_F0R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2101 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2102 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2103 #define CAN_F0R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2104 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2105 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2106 #define CAN_F0R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2107 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2108 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2109 #define CAN_F0R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2110 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2111 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2112 #define CAN_F0R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2113 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2114 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2115 #define CAN_F0R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2116 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2117 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2118 #define CAN_F0R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2119 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2120 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2121 #define CAN_F0R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2122 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2123 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2124
<> 144:ef7eb2e8f9f7 2125 /******************* Bit definition for CAN_F1R1 register *******************/
<> 144:ef7eb2e8f9f7 2126 #define CAN_F1R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2127 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2128 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2129 #define CAN_F1R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2130 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2131 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2132 #define CAN_F1R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2133 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2134 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2135 #define CAN_F1R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2136 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2137 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2138 #define CAN_F1R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2139 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2140 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2141 #define CAN_F1R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2142 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2143 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2144 #define CAN_F1R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2145 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2146 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2147 #define CAN_F1R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2148 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2149 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2150 #define CAN_F1R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2151 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2152 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2153 #define CAN_F1R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2154 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2155 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2156 #define CAN_F1R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2157 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2158 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2159 #define CAN_F1R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2160 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2161 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2162 #define CAN_F1R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2163 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2164 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2165 #define CAN_F1R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2166 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2167 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2168 #define CAN_F1R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2169 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2170 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2171 #define CAN_F1R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2172 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2173 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2174 #define CAN_F1R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2175 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2176 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2177 #define CAN_F1R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2178 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2179 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2180 #define CAN_F1R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2181 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2182 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2183 #define CAN_F1R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2184 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2185 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2186 #define CAN_F1R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2187 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2188 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2189 #define CAN_F1R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2190 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2191 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2192 #define CAN_F1R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2193 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2194 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2195 #define CAN_F1R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2196 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2197 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2198 #define CAN_F1R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2199 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2200 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2201 #define CAN_F1R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2202 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2203 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2204 #define CAN_F1R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2205 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2206 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2207 #define CAN_F1R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2208 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2209 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2210 #define CAN_F1R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2211 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2212 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2213 #define CAN_F1R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2214 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2215 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2216 #define CAN_F1R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2217 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2218 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2219 #define CAN_F1R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2220 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2221 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2222
<> 144:ef7eb2e8f9f7 2223 /******************* Bit definition for CAN_F2R1 register *******************/
<> 144:ef7eb2e8f9f7 2224 #define CAN_F2R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2225 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2226 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2227 #define CAN_F2R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2228 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2229 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2230 #define CAN_F2R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2231 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2232 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2233 #define CAN_F2R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2234 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2235 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2236 #define CAN_F2R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2237 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2238 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2239 #define CAN_F2R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2240 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2241 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2242 #define CAN_F2R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2243 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2244 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2245 #define CAN_F2R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2246 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2247 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2248 #define CAN_F2R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2249 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2250 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2251 #define CAN_F2R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2252 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2253 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2254 #define CAN_F2R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2255 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2256 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2257 #define CAN_F2R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2258 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2259 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2260 #define CAN_F2R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2261 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2262 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2263 #define CAN_F2R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2264 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2265 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2266 #define CAN_F2R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2267 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2268 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2269 #define CAN_F2R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2270 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2271 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2272 #define CAN_F2R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2273 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2274 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2275 #define CAN_F2R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2276 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2277 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2278 #define CAN_F2R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2279 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2280 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2281 #define CAN_F2R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2282 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2283 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2284 #define CAN_F2R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2285 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2286 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2287 #define CAN_F2R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2288 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2289 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2290 #define CAN_F2R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2291 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2292 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2293 #define CAN_F2R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2294 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2295 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2296 #define CAN_F2R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2297 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2298 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2299 #define CAN_F2R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2300 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2301 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2302 #define CAN_F2R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2303 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2304 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2305 #define CAN_F2R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2306 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2307 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2308 #define CAN_F2R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2309 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2310 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2311 #define CAN_F2R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2312 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2313 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2314 #define CAN_F2R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2315 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2316 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2317 #define CAN_F2R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2318 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2319 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2320
<> 144:ef7eb2e8f9f7 2321 /******************* Bit definition for CAN_F3R1 register *******************/
<> 144:ef7eb2e8f9f7 2322 #define CAN_F3R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2323 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2324 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2325 #define CAN_F3R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2326 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2327 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2328 #define CAN_F3R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2329 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2330 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2331 #define CAN_F3R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2332 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2333 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2334 #define CAN_F3R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2335 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2336 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2337 #define CAN_F3R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2338 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2339 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2340 #define CAN_F3R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2341 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2342 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2343 #define CAN_F3R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2344 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2345 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2346 #define CAN_F3R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2347 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2348 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2349 #define CAN_F3R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2350 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2351 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2352 #define CAN_F3R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2353 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2354 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2355 #define CAN_F3R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2356 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2357 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2358 #define CAN_F3R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2359 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2360 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2361 #define CAN_F3R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2362 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2363 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2364 #define CAN_F3R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2365 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2366 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2367 #define CAN_F3R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2368 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2369 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2370 #define CAN_F3R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2371 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2372 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2373 #define CAN_F3R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2374 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2375 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2376 #define CAN_F3R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2377 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2378 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2379 #define CAN_F3R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2380 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2381 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2382 #define CAN_F3R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2383 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2384 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2385 #define CAN_F3R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2386 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2387 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2388 #define CAN_F3R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2389 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2390 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2391 #define CAN_F3R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2392 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2393 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2394 #define CAN_F3R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2395 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2396 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2397 #define CAN_F3R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2398 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2399 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2400 #define CAN_F3R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2401 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2402 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2403 #define CAN_F3R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2404 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2405 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2406 #define CAN_F3R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2407 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2408 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2409 #define CAN_F3R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2410 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2411 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2412 #define CAN_F3R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2413 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2414 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2415 #define CAN_F3R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2416 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2417 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2418
<> 144:ef7eb2e8f9f7 2419 /******************* Bit definition for CAN_F4R1 register *******************/
<> 144:ef7eb2e8f9f7 2420 #define CAN_F4R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2421 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2422 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2423 #define CAN_F4R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2424 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2425 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2426 #define CAN_F4R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2427 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2428 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2429 #define CAN_F4R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2430 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2431 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2432 #define CAN_F4R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2433 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2434 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2435 #define CAN_F4R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2436 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2437 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2438 #define CAN_F4R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2439 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2440 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2441 #define CAN_F4R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2442 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2443 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2444 #define CAN_F4R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2445 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2446 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2447 #define CAN_F4R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2448 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2449 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2450 #define CAN_F4R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2451 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2452 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2453 #define CAN_F4R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2454 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2455 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2456 #define CAN_F4R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2457 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2458 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2459 #define CAN_F4R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2460 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2461 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2462 #define CAN_F4R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2463 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2464 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2465 #define CAN_F4R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2466 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2467 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2468 #define CAN_F4R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2469 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2470 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2471 #define CAN_F4R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2472 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2473 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2474 #define CAN_F4R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2475 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2476 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2477 #define CAN_F4R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2478 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2479 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2480 #define CAN_F4R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2481 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2482 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2483 #define CAN_F4R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2484 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2485 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2486 #define CAN_F4R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2487 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2488 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2489 #define CAN_F4R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2490 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2491 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2492 #define CAN_F4R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2493 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2494 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2495 #define CAN_F4R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2496 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2497 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2498 #define CAN_F4R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2499 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2500 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2501 #define CAN_F4R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2502 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2503 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2504 #define CAN_F4R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2505 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2506 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2507 #define CAN_F4R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2508 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2509 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2510 #define CAN_F4R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2511 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2512 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2513 #define CAN_F4R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2514 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2515 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2516
<> 144:ef7eb2e8f9f7 2517 /******************* Bit definition for CAN_F5R1 register *******************/
<> 144:ef7eb2e8f9f7 2518 #define CAN_F5R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2519 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2520 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2521 #define CAN_F5R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2522 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2523 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2524 #define CAN_F5R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2525 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2526 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2527 #define CAN_F5R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2528 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2529 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2530 #define CAN_F5R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2531 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2532 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2533 #define CAN_F5R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2534 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2535 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2536 #define CAN_F5R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2537 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2538 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2539 #define CAN_F5R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2540 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2541 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2542 #define CAN_F5R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2543 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2544 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2545 #define CAN_F5R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2546 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2547 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2548 #define CAN_F5R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2549 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2550 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2551 #define CAN_F5R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2552 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2553 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2554 #define CAN_F5R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2555 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2556 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2557 #define CAN_F5R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2558 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2559 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2560 #define CAN_F5R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2561 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2562 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2563 #define CAN_F5R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2564 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2565 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2566 #define CAN_F5R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2567 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2568 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2569 #define CAN_F5R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2570 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2571 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2572 #define CAN_F5R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2573 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2574 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2575 #define CAN_F5R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2576 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2577 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2578 #define CAN_F5R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2579 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2580 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2581 #define CAN_F5R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2582 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2583 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2584 #define CAN_F5R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2585 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2586 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2587 #define CAN_F5R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2588 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2589 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2590 #define CAN_F5R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2591 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2592 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2593 #define CAN_F5R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2594 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2595 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2596 #define CAN_F5R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2597 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2598 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2599 #define CAN_F5R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2600 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2601 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2602 #define CAN_F5R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2603 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2604 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2605 #define CAN_F5R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2606 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2607 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2608 #define CAN_F5R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2609 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2610 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2611 #define CAN_F5R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2612 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2613 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2614
<> 144:ef7eb2e8f9f7 2615 /******************* Bit definition for CAN_F6R1 register *******************/
<> 144:ef7eb2e8f9f7 2616 #define CAN_F6R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2617 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2618 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2619 #define CAN_F6R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2620 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2621 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2622 #define CAN_F6R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2623 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2624 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2625 #define CAN_F6R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2626 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2627 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2628 #define CAN_F6R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2629 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2630 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2631 #define CAN_F6R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2632 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2633 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2634 #define CAN_F6R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2635 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2636 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2637 #define CAN_F6R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2638 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2639 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2640 #define CAN_F6R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2641 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2642 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2643 #define CAN_F6R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2644 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2645 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2646 #define CAN_F6R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2647 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2648 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2649 #define CAN_F6R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2650 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2651 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2652 #define CAN_F6R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2653 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2654 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2655 #define CAN_F6R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2656 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2657 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2658 #define CAN_F6R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2659 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2660 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2661 #define CAN_F6R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2662 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2663 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2664 #define CAN_F6R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2665 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2666 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2667 #define CAN_F6R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2668 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2669 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2670 #define CAN_F6R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2671 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2672 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2673 #define CAN_F6R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2674 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2675 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2676 #define CAN_F6R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2677 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2678 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2679 #define CAN_F6R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2680 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2681 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2682 #define CAN_F6R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2683 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2684 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2685 #define CAN_F6R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2686 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2687 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2688 #define CAN_F6R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2689 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2690 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2691 #define CAN_F6R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2692 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2693 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2694 #define CAN_F6R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2695 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2696 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2697 #define CAN_F6R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2698 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2699 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2700 #define CAN_F6R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2701 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2702 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2703 #define CAN_F6R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2704 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2705 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2706 #define CAN_F6R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2707 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2708 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2709 #define CAN_F6R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2710 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2711 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2712
<> 144:ef7eb2e8f9f7 2713 /******************* Bit definition for CAN_F7R1 register *******************/
<> 144:ef7eb2e8f9f7 2714 #define CAN_F7R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2715 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2716 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2717 #define CAN_F7R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2718 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2719 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2720 #define CAN_F7R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2721 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2722 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2723 #define CAN_F7R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2724 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2725 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2726 #define CAN_F7R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2727 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2728 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2729 #define CAN_F7R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2730 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2731 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2732 #define CAN_F7R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2733 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2734 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2735 #define CAN_F7R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2736 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2737 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2738 #define CAN_F7R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2739 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2740 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2741 #define CAN_F7R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2742 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2743 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2744 #define CAN_F7R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2745 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2746 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2747 #define CAN_F7R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2748 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2749 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2750 #define CAN_F7R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2751 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2752 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2753 #define CAN_F7R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2754 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2755 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2756 #define CAN_F7R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2757 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2758 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2759 #define CAN_F7R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2760 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2761 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2762 #define CAN_F7R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2763 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2764 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2765 #define CAN_F7R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2766 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2767 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2768 #define CAN_F7R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2769 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2770 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2771 #define CAN_F7R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2772 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2773 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2774 #define CAN_F7R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2775 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2776 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2777 #define CAN_F7R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2778 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2779 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2780 #define CAN_F7R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2781 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2782 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2783 #define CAN_F7R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2784 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2785 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2786 #define CAN_F7R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2787 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2788 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2789 #define CAN_F7R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2790 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2791 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2792 #define CAN_F7R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2793 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2794 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2795 #define CAN_F7R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2796 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2797 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2798 #define CAN_F7R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2799 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2800 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2801 #define CAN_F7R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2802 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2803 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2804 #define CAN_F7R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2805 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2806 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2807 #define CAN_F7R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2808 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2809 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2810
<> 144:ef7eb2e8f9f7 2811 /******************* Bit definition for CAN_F8R1 register *******************/
<> 144:ef7eb2e8f9f7 2812 #define CAN_F8R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2813 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2814 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2815 #define CAN_F8R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2816 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2817 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2818 #define CAN_F8R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2819 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2820 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2821 #define CAN_F8R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2822 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2823 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2824 #define CAN_F8R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2825 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2826 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2827 #define CAN_F8R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2828 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2829 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2830 #define CAN_F8R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2831 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2832 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2833 #define CAN_F8R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2834 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2835 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2836 #define CAN_F8R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2837 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2838 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2839 #define CAN_F8R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2840 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2841 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2842 #define CAN_F8R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2843 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2844 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2845 #define CAN_F8R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2846 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2847 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2848 #define CAN_F8R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2849 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2850 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2851 #define CAN_F8R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2852 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2853 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2854 #define CAN_F8R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2855 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2856 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2857 #define CAN_F8R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2858 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2859 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2860 #define CAN_F8R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2861 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2862 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2863 #define CAN_F8R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2864 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2865 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2866 #define CAN_F8R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2867 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2868 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2869 #define CAN_F8R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2870 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2871 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2872 #define CAN_F8R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2873 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2874 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2875 #define CAN_F8R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2876 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2877 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2878 #define CAN_F8R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2879 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2880 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2881 #define CAN_F8R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2882 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2883 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2884 #define CAN_F8R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2885 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2886 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2887 #define CAN_F8R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2888 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2889 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2890 #define CAN_F8R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2891 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2892 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2893 #define CAN_F8R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2894 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2895 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2896 #define CAN_F8R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2897 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2898 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2899 #define CAN_F8R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2900 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2901 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2902 #define CAN_F8R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 2903 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 2904 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2905 #define CAN_F8R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 2906 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 2907 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2908
<> 144:ef7eb2e8f9f7 2909 /******************* Bit definition for CAN_F9R1 register *******************/
<> 144:ef7eb2e8f9f7 2910 #define CAN_F9R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 2911 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 2912 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2913 #define CAN_F9R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 2914 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 2915 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2916 #define CAN_F9R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 2917 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 2918 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2919 #define CAN_F9R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 2920 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 2921 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2922 #define CAN_F9R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 2923 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 2924 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2925 #define CAN_F9R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 2926 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 2927 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2928 #define CAN_F9R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 2929 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 2930 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2931 #define CAN_F9R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 2932 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 2933 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2934 #define CAN_F9R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 2935 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 2936 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2937 #define CAN_F9R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 2938 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 2939 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2940 #define CAN_F9R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 2941 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 2942 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2943 #define CAN_F9R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 2944 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 2945 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2946 #define CAN_F9R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 2947 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 2948 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2949 #define CAN_F9R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 2950 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 2951 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2952 #define CAN_F9R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 2953 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 2954 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2955 #define CAN_F9R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 2956 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 2957 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2958 #define CAN_F9R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 2959 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 2960 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2961 #define CAN_F9R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 2962 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 2963 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2964 #define CAN_F9R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 2965 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 2966 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2967 #define CAN_F9R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 2968 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 2969 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2970 #define CAN_F9R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 2971 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 2972 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2973 #define CAN_F9R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 2974 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2975 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2976 #define CAN_F9R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 2977 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 2978 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2979 #define CAN_F9R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 2980 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 2981 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2982 #define CAN_F9R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 2983 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 2984 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2985 #define CAN_F9R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 2986 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 2987 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2988 #define CAN_F9R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 2989 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 2990 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2991 #define CAN_F9R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 2992 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 2993 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2994 #define CAN_F9R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 2995 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 2996 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2997 #define CAN_F9R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 2998 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2999 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3000 #define CAN_F9R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3001 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3002 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3003 #define CAN_F9R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3004 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3005 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3006
<> 144:ef7eb2e8f9f7 3007 /******************* Bit definition for CAN_F10R1 register ******************/
<> 144:ef7eb2e8f9f7 3008 #define CAN_F10R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3009 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3010 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3011 #define CAN_F10R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3012 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3013 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3014 #define CAN_F10R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3015 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3016 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3017 #define CAN_F10R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3018 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3019 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3020 #define CAN_F10R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3021 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3022 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3023 #define CAN_F10R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3024 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3025 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3026 #define CAN_F10R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3027 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3028 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3029 #define CAN_F10R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3030 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3031 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3032 #define CAN_F10R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3033 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3034 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3035 #define CAN_F10R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3036 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3037 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3038 #define CAN_F10R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3039 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3040 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3041 #define CAN_F10R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3042 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3043 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3044 #define CAN_F10R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3045 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3046 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3047 #define CAN_F10R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3048 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3049 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3050 #define CAN_F10R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3051 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3052 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3053 #define CAN_F10R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3054 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3055 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3056 #define CAN_F10R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3057 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3058 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3059 #define CAN_F10R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3060 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3061 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3062 #define CAN_F10R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3063 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3064 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3065 #define CAN_F10R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3066 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3067 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3068 #define CAN_F10R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3069 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3070 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3071 #define CAN_F10R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3072 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3073 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3074 #define CAN_F10R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3075 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3076 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3077 #define CAN_F10R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3078 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3079 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3080 #define CAN_F10R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3081 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3082 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3083 #define CAN_F10R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3084 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3085 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3086 #define CAN_F10R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3087 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3088 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3089 #define CAN_F10R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3090 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3091 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3092 #define CAN_F10R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3093 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3094 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3095 #define CAN_F10R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3096 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3097 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3098 #define CAN_F10R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3099 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3100 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3101 #define CAN_F10R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3102 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3103 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3104
<> 144:ef7eb2e8f9f7 3105 /******************* Bit definition for CAN_F11R1 register ******************/
<> 144:ef7eb2e8f9f7 3106 #define CAN_F11R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3107 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3108 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3109 #define CAN_F11R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3110 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3111 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3112 #define CAN_F11R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3113 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3114 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3115 #define CAN_F11R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3116 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3117 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3118 #define CAN_F11R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3119 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3120 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3121 #define CAN_F11R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3122 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3123 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3124 #define CAN_F11R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3125 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3126 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3127 #define CAN_F11R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3128 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3129 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3130 #define CAN_F11R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3131 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3132 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3133 #define CAN_F11R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3134 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3135 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3136 #define CAN_F11R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3137 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3138 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3139 #define CAN_F11R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3140 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3141 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3142 #define CAN_F11R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3143 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3144 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3145 #define CAN_F11R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3146 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3147 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3148 #define CAN_F11R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3149 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3150 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3151 #define CAN_F11R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3152 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3153 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3154 #define CAN_F11R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3155 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3156 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3157 #define CAN_F11R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3158 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3159 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3160 #define CAN_F11R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3161 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3162 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3163 #define CAN_F11R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3164 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3165 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3166 #define CAN_F11R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3167 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3168 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3169 #define CAN_F11R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3170 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3171 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3172 #define CAN_F11R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3173 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3174 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3175 #define CAN_F11R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3176 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3177 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3178 #define CAN_F11R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3179 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3180 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3181 #define CAN_F11R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3182 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3183 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3184 #define CAN_F11R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3185 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3186 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3187 #define CAN_F11R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3188 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3189 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3190 #define CAN_F11R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3191 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3192 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3193 #define CAN_F11R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3194 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3195 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3196 #define CAN_F11R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3197 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3198 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3199 #define CAN_F11R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3200 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3201 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3202
<> 144:ef7eb2e8f9f7 3203 /******************* Bit definition for CAN_F12R1 register ******************/
<> 144:ef7eb2e8f9f7 3204 #define CAN_F12R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3205 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3206 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3207 #define CAN_F12R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3208 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3209 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3210 #define CAN_F12R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3211 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3212 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3213 #define CAN_F12R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3214 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3215 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3216 #define CAN_F12R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3217 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3218 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3219 #define CAN_F12R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3220 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3221 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3222 #define CAN_F12R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3223 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3224 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3225 #define CAN_F12R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3226 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3227 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3228 #define CAN_F12R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3229 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3230 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3231 #define CAN_F12R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3232 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3233 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3234 #define CAN_F12R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3235 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3236 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3237 #define CAN_F12R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3238 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3239 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3240 #define CAN_F12R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3241 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3242 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3243 #define CAN_F12R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3244 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3245 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3246 #define CAN_F12R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3247 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3248 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3249 #define CAN_F12R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3250 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3251 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3252 #define CAN_F12R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3253 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3254 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3255 #define CAN_F12R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3256 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3257 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3258 #define CAN_F12R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3259 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3260 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3261 #define CAN_F12R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3262 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3263 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3264 #define CAN_F12R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3265 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3266 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3267 #define CAN_F12R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3268 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3269 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3270 #define CAN_F12R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3271 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3272 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3273 #define CAN_F12R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3274 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3275 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3276 #define CAN_F12R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3277 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3278 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3279 #define CAN_F12R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3280 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3281 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3282 #define CAN_F12R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3283 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3284 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3285 #define CAN_F12R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3286 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3287 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3288 #define CAN_F12R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3289 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3290 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3291 #define CAN_F12R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3292 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3293 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3294 #define CAN_F12R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3295 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3296 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3297 #define CAN_F12R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3298 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3299 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3300
<> 144:ef7eb2e8f9f7 3301 /******************* Bit definition for CAN_F13R1 register ******************/
<> 144:ef7eb2e8f9f7 3302 #define CAN_F13R1_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3303 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3304 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3305 #define CAN_F13R1_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3306 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3307 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3308 #define CAN_F13R1_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3309 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3310 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3311 #define CAN_F13R1_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3312 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3313 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3314 #define CAN_F13R1_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3315 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3316 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3317 #define CAN_F13R1_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3318 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3319 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3320 #define CAN_F13R1_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3321 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3322 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3323 #define CAN_F13R1_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3324 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3325 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3326 #define CAN_F13R1_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3327 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3328 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3329 #define CAN_F13R1_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3330 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3331 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3332 #define CAN_F13R1_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3333 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3334 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3335 #define CAN_F13R1_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3336 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3337 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3338 #define CAN_F13R1_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3339 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3340 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3341 #define CAN_F13R1_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3342 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3343 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3344 #define CAN_F13R1_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3345 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3346 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3347 #define CAN_F13R1_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3348 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3349 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3350 #define CAN_F13R1_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3351 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3352 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3353 #define CAN_F13R1_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3354 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3355 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3356 #define CAN_F13R1_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3357 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3358 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3359 #define CAN_F13R1_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3360 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3361 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3362 #define CAN_F13R1_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3363 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3364 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3365 #define CAN_F13R1_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3366 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3367 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3368 #define CAN_F13R1_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3369 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3370 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3371 #define CAN_F13R1_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3372 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3373 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3374 #define CAN_F13R1_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3375 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3376 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3377 #define CAN_F13R1_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3378 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3379 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3380 #define CAN_F13R1_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3381 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3382 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3383 #define CAN_F13R1_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3384 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3385 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3386 #define CAN_F13R1_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3387 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3388 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3389 #define CAN_F13R1_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3390 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3391 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3392 #define CAN_F13R1_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3393 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3394 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3395 #define CAN_F13R1_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3396 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3397 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3398
<> 144:ef7eb2e8f9f7 3399 /******************* Bit definition for CAN_F0R2 register *******************/
<> 144:ef7eb2e8f9f7 3400 #define CAN_F0R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3401 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3402 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3403 #define CAN_F0R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3404 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3405 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3406 #define CAN_F0R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3407 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3408 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3409 #define CAN_F0R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3410 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3411 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3412 #define CAN_F0R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3413 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3414 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3415 #define CAN_F0R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3416 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3417 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3418 #define CAN_F0R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3419 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3420 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3421 #define CAN_F0R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3422 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3423 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3424 #define CAN_F0R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3425 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3426 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3427 #define CAN_F0R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3428 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3429 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3430 #define CAN_F0R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3431 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3432 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3433 #define CAN_F0R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3434 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3435 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3436 #define CAN_F0R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3437 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3438 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3439 #define CAN_F0R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3440 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3441 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3442 #define CAN_F0R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3443 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3444 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3445 #define CAN_F0R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3446 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3447 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3448 #define CAN_F0R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3449 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3450 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3451 #define CAN_F0R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3452 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3453 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3454 #define CAN_F0R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3455 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3456 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3457 #define CAN_F0R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3458 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3459 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3460 #define CAN_F0R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3461 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3462 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3463 #define CAN_F0R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3464 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3465 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3466 #define CAN_F0R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3467 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3468 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3469 #define CAN_F0R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3470 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3471 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3472 #define CAN_F0R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3473 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3474 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3475 #define CAN_F0R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3476 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3477 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3478 #define CAN_F0R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3479 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3480 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3481 #define CAN_F0R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3482 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3483 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3484 #define CAN_F0R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3485 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3486 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3487 #define CAN_F0R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3488 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3489 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3490 #define CAN_F0R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3491 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3492 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3493 #define CAN_F0R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3494 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3495 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3496
<> 144:ef7eb2e8f9f7 3497 /******************* Bit definition for CAN_F1R2 register *******************/
<> 144:ef7eb2e8f9f7 3498 #define CAN_F1R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3499 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3500 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3501 #define CAN_F1R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3502 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3503 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3504 #define CAN_F1R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3505 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3506 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3507 #define CAN_F1R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3508 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3509 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3510 #define CAN_F1R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3511 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3512 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3513 #define CAN_F1R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3514 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3515 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3516 #define CAN_F1R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3517 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3518 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3519 #define CAN_F1R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3520 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3521 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3522 #define CAN_F1R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3523 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3524 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3525 #define CAN_F1R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3526 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3527 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3528 #define CAN_F1R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3529 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3530 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3531 #define CAN_F1R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3532 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3533 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3534 #define CAN_F1R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3535 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3536 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3537 #define CAN_F1R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3538 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3539 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3540 #define CAN_F1R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3541 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3542 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3543 #define CAN_F1R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3544 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3545 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3546 #define CAN_F1R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3547 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3548 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3549 #define CAN_F1R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3550 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3551 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3552 #define CAN_F1R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3553 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3554 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3555 #define CAN_F1R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3556 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3557 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3558 #define CAN_F1R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3559 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3560 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3561 #define CAN_F1R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3562 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3563 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3564 #define CAN_F1R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3565 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3566 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3567 #define CAN_F1R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3568 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3569 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3570 #define CAN_F1R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3571 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3572 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3573 #define CAN_F1R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3574 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3575 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3576 #define CAN_F1R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3577 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3578 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3579 #define CAN_F1R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3580 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3581 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3582 #define CAN_F1R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3583 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3584 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3585 #define CAN_F1R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3586 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3587 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3588 #define CAN_F1R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3589 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3590 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3591 #define CAN_F1R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3592 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3593 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3594
<> 144:ef7eb2e8f9f7 3595 /******************* Bit definition for CAN_F2R2 register *******************/
<> 144:ef7eb2e8f9f7 3596 #define CAN_F2R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3597 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3598 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3599 #define CAN_F2R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3600 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3601 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3602 #define CAN_F2R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3603 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3604 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3605 #define CAN_F2R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3606 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3607 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3608 #define CAN_F2R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3609 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3610 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3611 #define CAN_F2R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3612 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3613 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3614 #define CAN_F2R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3615 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3616 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3617 #define CAN_F2R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3618 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3619 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3620 #define CAN_F2R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3621 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3622 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3623 #define CAN_F2R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3624 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3625 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3626 #define CAN_F2R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3627 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3628 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3629 #define CAN_F2R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3630 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3631 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3632 #define CAN_F2R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3633 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3634 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3635 #define CAN_F2R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3636 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3637 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3638 #define CAN_F2R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3639 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3640 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3641 #define CAN_F2R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3642 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3643 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3644 #define CAN_F2R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3645 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3646 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3647 #define CAN_F2R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3648 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3649 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3650 #define CAN_F2R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3651 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3652 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3653 #define CAN_F2R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3654 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3655 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3656 #define CAN_F2R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3657 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3658 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3659 #define CAN_F2R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3660 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3661 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3662 #define CAN_F2R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3663 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3664 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3665 #define CAN_F2R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3666 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3667 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3668 #define CAN_F2R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3669 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3670 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3671 #define CAN_F2R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3672 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3673 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3674 #define CAN_F2R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3675 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3676 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3677 #define CAN_F2R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3678 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3679 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3680 #define CAN_F2R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3681 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3682 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3683 #define CAN_F2R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3684 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3685 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3686 #define CAN_F2R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3687 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3688 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3689 #define CAN_F2R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3690 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3691 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3692
<> 144:ef7eb2e8f9f7 3693 /******************* Bit definition for CAN_F3R2 register *******************/
<> 144:ef7eb2e8f9f7 3694 #define CAN_F3R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3695 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3696 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3697 #define CAN_F3R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3698 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3699 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3700 #define CAN_F3R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3701 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3702 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3703 #define CAN_F3R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3704 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3705 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3706 #define CAN_F3R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3707 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3708 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3709 #define CAN_F3R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3710 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3711 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3712 #define CAN_F3R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3713 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3714 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3715 #define CAN_F3R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3716 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3717 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3718 #define CAN_F3R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3719 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3720 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3721 #define CAN_F3R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3722 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3723 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3724 #define CAN_F3R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3725 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3726 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3727 #define CAN_F3R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3728 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3729 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3730 #define CAN_F3R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3731 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3732 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3733 #define CAN_F3R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3734 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3735 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3736 #define CAN_F3R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3737 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3738 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3739 #define CAN_F3R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3740 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3741 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3742 #define CAN_F3R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3743 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3744 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3745 #define CAN_F3R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3746 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3747 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3748 #define CAN_F3R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3749 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3750 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3751 #define CAN_F3R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3752 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3753 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3754 #define CAN_F3R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3755 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3756 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3757 #define CAN_F3R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3758 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3759 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3760 #define CAN_F3R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3761 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3762 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3763 #define CAN_F3R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3764 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3765 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3766 #define CAN_F3R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3767 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3768 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3769 #define CAN_F3R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3770 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3771 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3772 #define CAN_F3R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3773 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3774 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3775 #define CAN_F3R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3776 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3777 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3778 #define CAN_F3R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3779 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3780 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3781 #define CAN_F3R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3782 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3783 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3784 #define CAN_F3R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3785 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3786 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3787 #define CAN_F3R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3788 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3789 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3790
<> 144:ef7eb2e8f9f7 3791 /******************* Bit definition for CAN_F4R2 register *******************/
<> 144:ef7eb2e8f9f7 3792 #define CAN_F4R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3793 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3794 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3795 #define CAN_F4R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3796 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3797 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3798 #define CAN_F4R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3799 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3800 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3801 #define CAN_F4R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3802 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3803 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3804 #define CAN_F4R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3805 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3806 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3807 #define CAN_F4R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3808 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3809 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3810 #define CAN_F4R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3811 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3812 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3813 #define CAN_F4R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3814 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3815 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3816 #define CAN_F4R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3817 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3818 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3819 #define CAN_F4R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3820 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3821 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3822 #define CAN_F4R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3823 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3824 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3825 #define CAN_F4R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3826 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3827 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3828 #define CAN_F4R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3829 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3830 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3831 #define CAN_F4R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3832 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3833 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3834 #define CAN_F4R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3835 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3836 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3837 #define CAN_F4R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3838 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3839 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3840 #define CAN_F4R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3841 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3842 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3843 #define CAN_F4R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3844 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3845 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3846 #define CAN_F4R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3847 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3848 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3849 #define CAN_F4R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3850 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3851 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3852 #define CAN_F4R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3853 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3854 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3855 #define CAN_F4R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3856 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3857 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3858 #define CAN_F4R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3859 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3860 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3861 #define CAN_F4R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3862 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3863 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3864 #define CAN_F4R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3865 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3866 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3867 #define CAN_F4R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3868 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3869 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3870 #define CAN_F4R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3871 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3872 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3873 #define CAN_F4R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3874 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3875 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3876 #define CAN_F4R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3877 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3878 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3879 #define CAN_F4R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3880 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3881 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3882 #define CAN_F4R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3883 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3884 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3885 #define CAN_F4R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3886 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3887 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3888
<> 144:ef7eb2e8f9f7 3889 /******************* Bit definition for CAN_F5R2 register *******************/
<> 144:ef7eb2e8f9f7 3890 #define CAN_F5R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3891 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3892 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3893 #define CAN_F5R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3894 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3895 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3896 #define CAN_F5R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3897 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3898 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3899 #define CAN_F5R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3900 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3901 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3902 #define CAN_F5R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 3903 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 3904 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3905 #define CAN_F5R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 3906 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 3907 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3908 #define CAN_F5R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 3909 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 3910 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3911 #define CAN_F5R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 3912 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 3913 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3914 #define CAN_F5R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 3915 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 3916 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3917 #define CAN_F5R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 3918 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 3919 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3920 #define CAN_F5R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 3921 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 3922 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3923 #define CAN_F5R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 3924 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 3925 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3926 #define CAN_F5R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 3927 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 3928 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3929 #define CAN_F5R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 3930 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 3931 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3932 #define CAN_F5R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 3933 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 3934 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3935 #define CAN_F5R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 3936 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 3937 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3938 #define CAN_F5R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 3939 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 3940 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3941 #define CAN_F5R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 3942 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 3943 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3944 #define CAN_F5R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 3945 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 3946 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3947 #define CAN_F5R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 3948 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 3949 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3950 #define CAN_F5R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 3951 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 3952 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3953 #define CAN_F5R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 3954 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 3955 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3956 #define CAN_F5R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 3957 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 3958 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3959 #define CAN_F5R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 3960 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 3961 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3962 #define CAN_F5R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 3963 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 3964 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3965 #define CAN_F5R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 3966 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 3967 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3968 #define CAN_F5R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 3969 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 3970 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3971 #define CAN_F5R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 3972 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 3973 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3974 #define CAN_F5R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 3975 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 3976 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3977 #define CAN_F5R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 3978 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 3979 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3980 #define CAN_F5R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 3981 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 3982 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3983 #define CAN_F5R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 3984 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 3985 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3986
<> 144:ef7eb2e8f9f7 3987 /******************* Bit definition for CAN_F6R2 register *******************/
<> 144:ef7eb2e8f9f7 3988 #define CAN_F6R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 3989 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 3990 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3991 #define CAN_F6R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 3992 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 3993 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3994 #define CAN_F6R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 3995 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 3996 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3997 #define CAN_F6R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 3998 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 3999 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 4000 #define CAN_F6R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 4001 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4002 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 4003 #define CAN_F6R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 4004 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4005 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 4006 #define CAN_F6R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 4007 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4008 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 4009 #define CAN_F6R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 4010 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4011 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 4012 #define CAN_F6R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 4013 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4014 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 4015 #define CAN_F6R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 4016 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4017 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 4018 #define CAN_F6R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 4019 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4020 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 4021 #define CAN_F6R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 4022 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4023 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 4024 #define CAN_F6R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 4025 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4026 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 4027 #define CAN_F6R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 4028 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4029 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 4030 #define CAN_F6R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 4031 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4032 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 4033 #define CAN_F6R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 4034 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4035 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 4036 #define CAN_F6R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 4037 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4038 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 4039 #define CAN_F6R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 4040 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 4041 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 4042 #define CAN_F6R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 4043 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4044 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 4045 #define CAN_F6R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 4046 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4047 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 4048 #define CAN_F6R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 4049 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4050 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 4051 #define CAN_F6R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 4052 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4053 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 4054 #define CAN_F6R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 4055 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4056 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 4057 #define CAN_F6R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 4058 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4059 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 4060 #define CAN_F6R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 4061 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4062 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 4063 #define CAN_F6R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 4064 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4065 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 4066 #define CAN_F6R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 4067 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4068 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 4069 #define CAN_F6R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 4070 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4071 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 4072 #define CAN_F6R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 4073 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4074 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 4075 #define CAN_F6R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 4076 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4077 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 4078 #define CAN_F6R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 4079 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4080 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 4081 #define CAN_F6R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 4082 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4083 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4084
<> 144:ef7eb2e8f9f7 4085 /******************* Bit definition for CAN_F7R2 register *******************/
<> 144:ef7eb2e8f9f7 4086 #define CAN_F7R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 4087 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4088 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 4089 #define CAN_F7R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 4090 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4091 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 4092 #define CAN_F7R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 4093 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4094 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 4095 #define CAN_F7R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 4096 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4097 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 4098 #define CAN_F7R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 4099 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4100 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 4101 #define CAN_F7R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 4102 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4103 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 4104 #define CAN_F7R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 4105 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4106 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 4107 #define CAN_F7R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 4108 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4109 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 4110 #define CAN_F7R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 4111 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4112 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 4113 #define CAN_F7R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 4114 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4115 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 4116 #define CAN_F7R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 4117 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4118 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 4119 #define CAN_F7R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 4120 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4121 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 4122 #define CAN_F7R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 4123 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4124 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 4125 #define CAN_F7R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 4126 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4127 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 4128 #define CAN_F7R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 4129 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4130 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 4131 #define CAN_F7R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 4132 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4133 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 4134 #define CAN_F7R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 4135 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4136 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 4137 #define CAN_F7R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 4138 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 4139 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 4140 #define CAN_F7R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 4141 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4142 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 4143 #define CAN_F7R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 4144 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4145 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 4146 #define CAN_F7R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 4147 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4148 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 4149 #define CAN_F7R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 4150 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4151 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 4152 #define CAN_F7R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 4153 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4154 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 4155 #define CAN_F7R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 4156 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4157 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 4158 #define CAN_F7R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 4159 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4160 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 4161 #define CAN_F7R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 4162 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4163 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 4164 #define CAN_F7R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 4165 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4166 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 4167 #define CAN_F7R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 4168 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4169 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 4170 #define CAN_F7R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 4171 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4172 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 4173 #define CAN_F7R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 4174 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4175 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 4176 #define CAN_F7R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 4177 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4178 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 4179 #define CAN_F7R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 4180 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4181 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4182
<> 144:ef7eb2e8f9f7 4183 /******************* Bit definition for CAN_F8R2 register *******************/
<> 144:ef7eb2e8f9f7 4184 #define CAN_F8R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 4185 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4186 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 4187 #define CAN_F8R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 4188 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4189 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 4190 #define CAN_F8R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 4191 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4192 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 4193 #define CAN_F8R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 4194 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4195 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 4196 #define CAN_F8R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 4197 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4198 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 4199 #define CAN_F8R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 4200 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4201 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 4202 #define CAN_F8R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 4203 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4204 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 4205 #define CAN_F8R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 4206 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4207 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 4208 #define CAN_F8R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 4209 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4210 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 4211 #define CAN_F8R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 4212 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4213 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 4214 #define CAN_F8R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 4215 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4216 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 4217 #define CAN_F8R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 4218 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4219 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 4220 #define CAN_F8R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 4221 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4222 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 4223 #define CAN_F8R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 4224 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4225 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 4226 #define CAN_F8R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 4227 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4228 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 4229 #define CAN_F8R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 4230 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4231 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 4232 #define CAN_F8R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 4233 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4234 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 4235 #define CAN_F8R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 4236 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 4237 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 4238 #define CAN_F8R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 4239 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4240 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 4241 #define CAN_F8R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 4242 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4243 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 4244 #define CAN_F8R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 4245 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4246 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 4247 #define CAN_F8R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 4248 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4249 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 4250 #define CAN_F8R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 4251 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4252 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 4253 #define CAN_F8R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 4254 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4255 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 4256 #define CAN_F8R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 4257 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4258 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 4259 #define CAN_F8R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 4260 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4261 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 4262 #define CAN_F8R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 4263 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4264 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 4265 #define CAN_F8R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 4266 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4267 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 4268 #define CAN_F8R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 4269 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4270 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 4271 #define CAN_F8R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 4272 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4273 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 4274 #define CAN_F8R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 4275 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4276 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 4277 #define CAN_F8R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 4278 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4279 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4280
<> 144:ef7eb2e8f9f7 4281 /******************* Bit definition for CAN_F9R2 register *******************/
<> 144:ef7eb2e8f9f7 4282 #define CAN_F9R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 4283 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4284 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 4285 #define CAN_F9R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 4286 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4287 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 4288 #define CAN_F9R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 4289 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4290 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 4291 #define CAN_F9R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 4292 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4293 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 4294 #define CAN_F9R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 4295 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4296 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 4297 #define CAN_F9R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 4298 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4299 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 4300 #define CAN_F9R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 4301 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4302 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 4303 #define CAN_F9R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 4304 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4305 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 4306 #define CAN_F9R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 4307 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4308 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 4309 #define CAN_F9R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 4310 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4311 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 4312 #define CAN_F9R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 4313 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4314 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 4315 #define CAN_F9R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 4316 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4317 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 4318 #define CAN_F9R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 4319 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4320 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 4321 #define CAN_F9R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 4322 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4323 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 4324 #define CAN_F9R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 4325 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4326 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 4327 #define CAN_F9R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 4328 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4329 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 4330 #define CAN_F9R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 4331 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4332 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 4333 #define CAN_F9R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 4334 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 4335 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 4336 #define CAN_F9R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 4337 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4338 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 4339 #define CAN_F9R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 4340 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4341 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 4342 #define CAN_F9R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 4343 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4344 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 4345 #define CAN_F9R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 4346 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4347 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 4348 #define CAN_F9R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 4349 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4350 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 4351 #define CAN_F9R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 4352 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4353 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 4354 #define CAN_F9R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 4355 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4356 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 4357 #define CAN_F9R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 4358 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4359 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 4360 #define CAN_F9R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 4361 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4362 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 4363 #define CAN_F9R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 4364 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4365 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 4366 #define CAN_F9R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 4367 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4368 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 4369 #define CAN_F9R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 4370 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4371 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 4372 #define CAN_F9R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 4373 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4374 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 4375 #define CAN_F9R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 4376 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4377 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4378
<> 144:ef7eb2e8f9f7 4379 /******************* Bit definition for CAN_F10R2 register ******************/
<> 144:ef7eb2e8f9f7 4380 #define CAN_F10R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 4381 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4382 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 4383 #define CAN_F10R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 4384 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4385 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 4386 #define CAN_F10R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 4387 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4388 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 4389 #define CAN_F10R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 4390 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4391 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 4392 #define CAN_F10R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 4393 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4394 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 4395 #define CAN_F10R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 4396 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4397 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 4398 #define CAN_F10R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 4399 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4400 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 4401 #define CAN_F10R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 4402 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4403 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 4404 #define CAN_F10R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 4405 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4406 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 4407 #define CAN_F10R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 4408 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4409 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 4410 #define CAN_F10R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 4411 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4412 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 4413 #define CAN_F10R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 4414 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4415 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 4416 #define CAN_F10R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 4417 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4418 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 4419 #define CAN_F10R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 4420 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4421 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 4422 #define CAN_F10R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 4423 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4424 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 4425 #define CAN_F10R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 4426 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4427 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 4428 #define CAN_F10R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 4429 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4430 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 4431 #define CAN_F10R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 4432 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 4433 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 4434 #define CAN_F10R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 4435 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4436 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 4437 #define CAN_F10R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 4438 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4439 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 4440 #define CAN_F10R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 4441 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4442 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 4443 #define CAN_F10R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 4444 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4445 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 4446 #define CAN_F10R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 4447 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4448 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 4449 #define CAN_F10R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 4450 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4451 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 4452 #define CAN_F10R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 4453 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4454 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 4455 #define CAN_F10R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 4456 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4457 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 4458 #define CAN_F10R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 4459 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4460 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 4461 #define CAN_F10R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 4462 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4463 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 4464 #define CAN_F10R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 4465 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4466 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 4467 #define CAN_F10R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 4468 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4469 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 4470 #define CAN_F10R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 4471 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4472 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 4473 #define CAN_F10R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 4474 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4475 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4476
<> 144:ef7eb2e8f9f7 4477 /******************* Bit definition for CAN_F11R2 register ******************/
<> 144:ef7eb2e8f9f7 4478 #define CAN_F11R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 4479 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4480 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 4481 #define CAN_F11R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 4482 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4483 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 4484 #define CAN_F11R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 4485 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4486 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 4487 #define CAN_F11R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 4488 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4489 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 4490 #define CAN_F11R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 4491 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4492 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 4493 #define CAN_F11R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 4494 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4495 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 4496 #define CAN_F11R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 4497 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4498 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 4499 #define CAN_F11R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 4500 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4501 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 4502 #define CAN_F11R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 4503 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4504 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 4505 #define CAN_F11R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 4506 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4507 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 4508 #define CAN_F11R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 4509 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4510 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 4511 #define CAN_F11R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 4512 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4513 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 4514 #define CAN_F11R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 4515 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4516 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 4517 #define CAN_F11R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 4518 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4519 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 4520 #define CAN_F11R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 4521 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4522 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 4523 #define CAN_F11R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 4524 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4525 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 4526 #define CAN_F11R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 4527 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4528 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 4529 #define CAN_F11R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 4530 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 4531 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 4532 #define CAN_F11R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 4533 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4534 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 4535 #define CAN_F11R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 4536 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4537 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 4538 #define CAN_F11R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 4539 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4540 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 4541 #define CAN_F11R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 4542 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4543 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 4544 #define CAN_F11R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 4545 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4546 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 4547 #define CAN_F11R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 4548 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4549 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 4550 #define CAN_F11R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 4551 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4552 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 4553 #define CAN_F11R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 4554 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4555 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 4556 #define CAN_F11R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 4557 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4558 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 4559 #define CAN_F11R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 4560 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4561 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 4562 #define CAN_F11R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 4563 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4564 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 4565 #define CAN_F11R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 4566 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4567 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 4568 #define CAN_F11R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 4569 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4570 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 4571 #define CAN_F11R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 4572 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4573 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4574
<> 144:ef7eb2e8f9f7 4575 /******************* Bit definition for CAN_F12R2 register ******************/
<> 144:ef7eb2e8f9f7 4576 #define CAN_F12R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 4577 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4578 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 4579 #define CAN_F12R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 4580 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4581 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 4582 #define CAN_F12R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 4583 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4584 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 4585 #define CAN_F12R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 4586 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4587 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 4588 #define CAN_F12R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 4589 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4590 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 4591 #define CAN_F12R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 4592 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4593 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 4594 #define CAN_F12R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 4595 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4596 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 4597 #define CAN_F12R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 4598 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4599 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 4600 #define CAN_F12R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 4601 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4602 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 4603 #define CAN_F12R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 4604 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4605 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 4606 #define CAN_F12R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 4607 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4608 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 4609 #define CAN_F12R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 4610 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4611 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 4612 #define CAN_F12R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 4613 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4614 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 4615 #define CAN_F12R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 4616 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4617 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 4618 #define CAN_F12R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 4619 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4620 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 4621 #define CAN_F12R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 4622 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4623 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 4624 #define CAN_F12R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 4625 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4626 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 4627 #define CAN_F12R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 4628 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 4629 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 4630 #define CAN_F12R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 4631 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4632 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 4633 #define CAN_F12R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 4634 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4635 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 4636 #define CAN_F12R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 4637 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4638 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 4639 #define CAN_F12R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 4640 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4641 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 4642 #define CAN_F12R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 4643 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4644 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 4645 #define CAN_F12R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 4646 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4647 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 4648 #define CAN_F12R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 4649 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4650 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 4651 #define CAN_F12R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 4652 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4653 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 4654 #define CAN_F12R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 4655 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4656 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 4657 #define CAN_F12R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 4658 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4659 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 4660 #define CAN_F12R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 4661 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4662 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 4663 #define CAN_F12R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 4664 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4665 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 4666 #define CAN_F12R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 4667 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4668 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 4669 #define CAN_F12R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 4670 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4671 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4672
<> 144:ef7eb2e8f9f7 4673 /******************* Bit definition for CAN_F13R2 register ******************/
<> 144:ef7eb2e8f9f7 4674 #define CAN_F13R2_FB0_Pos (0U)
<> 144:ef7eb2e8f9f7 4675 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4676 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 4677 #define CAN_F13R2_FB1_Pos (1U)
<> 144:ef7eb2e8f9f7 4678 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4679 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 4680 #define CAN_F13R2_FB2_Pos (2U)
<> 144:ef7eb2e8f9f7 4681 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4682 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 4683 #define CAN_F13R2_FB3_Pos (3U)
<> 144:ef7eb2e8f9f7 4684 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4685 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 4686 #define CAN_F13R2_FB4_Pos (4U)
<> 144:ef7eb2e8f9f7 4687 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4688 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 4689 #define CAN_F13R2_FB5_Pos (5U)
<> 144:ef7eb2e8f9f7 4690 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4691 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 4692 #define CAN_F13R2_FB6_Pos (6U)
<> 144:ef7eb2e8f9f7 4693 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4694 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 4695 #define CAN_F13R2_FB7_Pos (7U)
<> 144:ef7eb2e8f9f7 4696 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4697 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 4698 #define CAN_F13R2_FB8_Pos (8U)
<> 144:ef7eb2e8f9f7 4699 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4700 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 4701 #define CAN_F13R2_FB9_Pos (9U)
<> 144:ef7eb2e8f9f7 4702 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4703 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 4704 #define CAN_F13R2_FB10_Pos (10U)
<> 144:ef7eb2e8f9f7 4705 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4706 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 4707 #define CAN_F13R2_FB11_Pos (11U)
<> 144:ef7eb2e8f9f7 4708 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4709 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 4710 #define CAN_F13R2_FB12_Pos (12U)
<> 144:ef7eb2e8f9f7 4711 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4712 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 4713 #define CAN_F13R2_FB13_Pos (13U)
<> 144:ef7eb2e8f9f7 4714 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4715 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 4716 #define CAN_F13R2_FB14_Pos (14U)
<> 144:ef7eb2e8f9f7 4717 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4718 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 4719 #define CAN_F13R2_FB15_Pos (15U)
<> 144:ef7eb2e8f9f7 4720 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4721 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 4722 #define CAN_F13R2_FB16_Pos (16U)
<> 144:ef7eb2e8f9f7 4723 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4724 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 4725 #define CAN_F13R2_FB17_Pos (17U)
<> 144:ef7eb2e8f9f7 4726 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 4727 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 4728 #define CAN_F13R2_FB18_Pos (18U)
<> 144:ef7eb2e8f9f7 4729 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4730 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 4731 #define CAN_F13R2_FB19_Pos (19U)
<> 144:ef7eb2e8f9f7 4732 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4733 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 4734 #define CAN_F13R2_FB20_Pos (20U)
<> 144:ef7eb2e8f9f7 4735 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4736 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 4737 #define CAN_F13R2_FB21_Pos (21U)
<> 144:ef7eb2e8f9f7 4738 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4739 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 4740 #define CAN_F13R2_FB22_Pos (22U)
<> 144:ef7eb2e8f9f7 4741 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4742 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 4743 #define CAN_F13R2_FB23_Pos (23U)
<> 144:ef7eb2e8f9f7 4744 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4745 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 4746 #define CAN_F13R2_FB24_Pos (24U)
<> 144:ef7eb2e8f9f7 4747 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4748 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 4749 #define CAN_F13R2_FB25_Pos (25U)
<> 144:ef7eb2e8f9f7 4750 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4751 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 4752 #define CAN_F13R2_FB26_Pos (26U)
<> 144:ef7eb2e8f9f7 4753 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4754 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 4755 #define CAN_F13R2_FB27_Pos (27U)
<> 144:ef7eb2e8f9f7 4756 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4757 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 4758 #define CAN_F13R2_FB28_Pos (28U)
<> 144:ef7eb2e8f9f7 4759 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4760 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 4761 #define CAN_F13R2_FB29_Pos (29U)
<> 144:ef7eb2e8f9f7 4762 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4763 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 4764 #define CAN_F13R2_FB30_Pos (30U)
<> 144:ef7eb2e8f9f7 4765 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4766 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 4767 #define CAN_F13R2_FB31_Pos (31U)
<> 144:ef7eb2e8f9f7 4768 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4769 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4770
<> 144:ef7eb2e8f9f7 4771 /******************************************************************************/
<> 144:ef7eb2e8f9f7 4772 /* */
<> 144:ef7eb2e8f9f7 4773 /* HDMI-CEC (CEC) */
<> 144:ef7eb2e8f9f7 4774 /* */
<> 144:ef7eb2e8f9f7 4775 /******************************************************************************/
<> 144:ef7eb2e8f9f7 4776
<> 144:ef7eb2e8f9f7 4777 /******************* Bit definition for CEC_CR register *********************/
<> 144:ef7eb2e8f9f7 4778 #define CEC_CR_CECEN_Pos (0U)
<> 144:ef7eb2e8f9f7 4779 #define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4780 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
<> 144:ef7eb2e8f9f7 4781 #define CEC_CR_TXSOM_Pos (1U)
<> 144:ef7eb2e8f9f7 4782 #define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4783 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
<> 144:ef7eb2e8f9f7 4784 #define CEC_CR_TXEOM_Pos (2U)
<> 144:ef7eb2e8f9f7 4785 #define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4786 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
<> 144:ef7eb2e8f9f7 4787
<> 144:ef7eb2e8f9f7 4788 /******************* Bit definition for CEC_CFGR register *******************/
<> 144:ef7eb2e8f9f7 4789 #define CEC_CFGR_SFT_Pos (0U)
<> 144:ef7eb2e8f9f7 4790 #define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
<> 144:ef7eb2e8f9f7 4791 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
<> 144:ef7eb2e8f9f7 4792 #define CEC_CFGR_RXTOL_Pos (3U)
<> 144:ef7eb2e8f9f7 4793 #define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4794 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
<> 144:ef7eb2e8f9f7 4795 #define CEC_CFGR_BRESTP_Pos (4U)
<> 144:ef7eb2e8f9f7 4796 #define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4797 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
<> 144:ef7eb2e8f9f7 4798 #define CEC_CFGR_BREGEN_Pos (5U)
<> 144:ef7eb2e8f9f7 4799 #define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4800 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
<> 144:ef7eb2e8f9f7 4801 #define CEC_CFGR_LBPEGEN_Pos (6U)
<> 144:ef7eb2e8f9f7 4802 #define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4803 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */
<> 144:ef7eb2e8f9f7 4804 #define CEC_CFGR_BRDNOGEN_Pos (7U)
<> 144:ef7eb2e8f9f7 4805 #define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4806 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */
<> 144:ef7eb2e8f9f7 4807 #define CEC_CFGR_SFTOPT_Pos (8U)
<> 144:ef7eb2e8f9f7 4808 #define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4809 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
<> 144:ef7eb2e8f9f7 4810 #define CEC_CFGR_OAR_Pos (16U)
<> 144:ef7eb2e8f9f7 4811 #define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
<> 144:ef7eb2e8f9f7 4812 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
<> 144:ef7eb2e8f9f7 4813 #define CEC_CFGR_LSTN_Pos (31U)
<> 144:ef7eb2e8f9f7 4814 #define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4815 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
<> 144:ef7eb2e8f9f7 4816
<> 144:ef7eb2e8f9f7 4817 /******************* Bit definition for CEC_TXDR register *******************/
<> 144:ef7eb2e8f9f7 4818 #define CEC_TXDR_TXD_Pos (0U)
<> 144:ef7eb2e8f9f7 4819 #define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 4820 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
<> 144:ef7eb2e8f9f7 4821
<> 144:ef7eb2e8f9f7 4822 /******************* Bit definition for CEC_RXDR register *******************/
<> 144:ef7eb2e8f9f7 4823 #define CEC_TXDR_RXD_Pos (0U)
<> 144:ef7eb2e8f9f7 4824 #define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 4825 #define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
<> 144:ef7eb2e8f9f7 4826
<> 144:ef7eb2e8f9f7 4827 /******************* Bit definition for CEC_ISR register ********************/
<> 144:ef7eb2e8f9f7 4828 #define CEC_ISR_RXBR_Pos (0U)
<> 144:ef7eb2e8f9f7 4829 #define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4830 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
<> 144:ef7eb2e8f9f7 4831 #define CEC_ISR_RXEND_Pos (1U)
<> 144:ef7eb2e8f9f7 4832 #define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4833 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
<> 144:ef7eb2e8f9f7 4834 #define CEC_ISR_RXOVR_Pos (2U)
<> 144:ef7eb2e8f9f7 4835 #define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4836 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
<> 144:ef7eb2e8f9f7 4837 #define CEC_ISR_BRE_Pos (3U)
<> 144:ef7eb2e8f9f7 4838 #define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4839 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
<> 144:ef7eb2e8f9f7 4840 #define CEC_ISR_SBPE_Pos (4U)
<> 144:ef7eb2e8f9f7 4841 #define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4842 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
<> 144:ef7eb2e8f9f7 4843 #define CEC_ISR_LBPE_Pos (5U)
<> 144:ef7eb2e8f9f7 4844 #define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4845 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
<> 144:ef7eb2e8f9f7 4846 #define CEC_ISR_RXACKE_Pos (6U)
<> 144:ef7eb2e8f9f7 4847 #define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4848 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 4849 #define CEC_ISR_ARBLST_Pos (7U)
<> 144:ef7eb2e8f9f7 4850 #define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4851 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
<> 144:ef7eb2e8f9f7 4852 #define CEC_ISR_TXBR_Pos (8U)
<> 144:ef7eb2e8f9f7 4853 #define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4854 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
<> 144:ef7eb2e8f9f7 4855 #define CEC_ISR_TXEND_Pos (9U)
<> 144:ef7eb2e8f9f7 4856 #define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4857 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
<> 144:ef7eb2e8f9f7 4858 #define CEC_ISR_TXUDR_Pos (10U)
<> 144:ef7eb2e8f9f7 4859 #define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4860 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
<> 144:ef7eb2e8f9f7 4861 #define CEC_ISR_TXERR_Pos (11U)
<> 144:ef7eb2e8f9f7 4862 #define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4863 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
<> 144:ef7eb2e8f9f7 4864 #define CEC_ISR_TXACKE_Pos (12U)
<> 144:ef7eb2e8f9f7 4865 #define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4866 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 4867
<> 144:ef7eb2e8f9f7 4868 /******************* Bit definition for CEC_IER register ********************/
<> 144:ef7eb2e8f9f7 4869 #define CEC_IER_RXBRIE_Pos (0U)
<> 144:ef7eb2e8f9f7 4870 #define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4871 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
<> 144:ef7eb2e8f9f7 4872 #define CEC_IER_RXENDIE_Pos (1U)
<> 144:ef7eb2e8f9f7 4873 #define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4874 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
<> 144:ef7eb2e8f9f7 4875 #define CEC_IER_RXOVRIE_Pos (2U)
<> 144:ef7eb2e8f9f7 4876 #define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4877 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
<> 144:ef7eb2e8f9f7 4878 #define CEC_IER_BREIE_Pos (3U)
<> 144:ef7eb2e8f9f7 4879 #define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4880 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
<> 144:ef7eb2e8f9f7 4881 #define CEC_IER_SBPEIE_Pos (4U)
<> 144:ef7eb2e8f9f7 4882 #define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4883 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
<> 144:ef7eb2e8f9f7 4884 #define CEC_IER_LBPEIE_Pos (5U)
<> 144:ef7eb2e8f9f7 4885 #define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4886 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
<> 144:ef7eb2e8f9f7 4887 #define CEC_IER_RXACKEIE_Pos (6U)
<> 144:ef7eb2e8f9f7 4888 #define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4889 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
<> 144:ef7eb2e8f9f7 4890 #define CEC_IER_ARBLSTIE_Pos (7U)
<> 144:ef7eb2e8f9f7 4891 #define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 4892 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
<> 144:ef7eb2e8f9f7 4893 #define CEC_IER_TXBRIE_Pos (8U)
<> 144:ef7eb2e8f9f7 4894 #define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4895 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
<> 144:ef7eb2e8f9f7 4896 #define CEC_IER_TXENDIE_Pos (9U)
<> 144:ef7eb2e8f9f7 4897 #define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4898 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
<> 144:ef7eb2e8f9f7 4899 #define CEC_IER_TXUDRIE_Pos (10U)
<> 144:ef7eb2e8f9f7 4900 #define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4901 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
<> 144:ef7eb2e8f9f7 4902 #define CEC_IER_TXERRIE_Pos (11U)
<> 144:ef7eb2e8f9f7 4903 #define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4904 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
<> 144:ef7eb2e8f9f7 4905 #define CEC_IER_TXACKEIE_Pos (12U)
<> 144:ef7eb2e8f9f7 4906 #define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4907 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
<> 144:ef7eb2e8f9f7 4908
<> 144:ef7eb2e8f9f7 4909 /******************************************************************************/
<> 144:ef7eb2e8f9f7 4910 /* */
<> 144:ef7eb2e8f9f7 4911 /* Analog Comparators (COMP) */
<> 144:ef7eb2e8f9f7 4912 /* */
<> 144:ef7eb2e8f9f7 4913 /******************************************************************************/
<> 144:ef7eb2e8f9f7 4914 /*********************** Bit definition for COMP_CSR register ***************/
<> 144:ef7eb2e8f9f7 4915 /* COMP1 bits definition */
<> 144:ef7eb2e8f9f7 4916 #define COMP_CSR_COMP1EN_Pos (0U)
<> 144:ef7eb2e8f9f7 4917 #define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4918 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
<> 144:ef7eb2e8f9f7 4919 #define COMP_CSR_COMP1SW1_Pos (1U)
<> 144:ef7eb2e8f9f7 4920 #define COMP_CSR_COMP1SW1_Msk (0x1U << COMP_CSR_COMP1SW1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 4921 #define COMP_CSR_COMP1SW1 COMP_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */
<> 144:ef7eb2e8f9f7 4922 #define COMP_CSR_COMP1MODE_Pos (2U)
<> 144:ef7eb2e8f9f7 4923 #define COMP_CSR_COMP1MODE_Msk (0x3U << COMP_CSR_COMP1MODE_Pos) /*!< 0x0000000C */
<> 144:ef7eb2e8f9f7 4924 #define COMP_CSR_COMP1MODE COMP_CSR_COMP1MODE_Msk /*!< COMP1 power mode */
<> 144:ef7eb2e8f9f7 4925 #define COMP_CSR_COMP1MODE_0 (0x1U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4926 #define COMP_CSR_COMP1MODE_1 (0x2U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 4927 #define COMP_CSR_COMP1INSEL_Pos (4U)
<> 144:ef7eb2e8f9f7 4928 #define COMP_CSR_COMP1INSEL_Msk (0x7U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 4929 #define COMP_CSR_COMP1INSEL COMP_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */
<> 144:ef7eb2e8f9f7 4930 #define COMP_CSR_COMP1INSEL_0 (0x1U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 4931 #define COMP_CSR_COMP1INSEL_1 (0x2U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 4932 #define COMP_CSR_COMP1INSEL_2 (0x4U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 4933 #define COMP_CSR_COMP1OUTSEL_Pos (8U)
<> 144:ef7eb2e8f9f7 4934 #define COMP_CSR_COMP1OUTSEL_Msk (0x7U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000700 */
<> 144:ef7eb2e8f9f7 4935 #define COMP_CSR_COMP1OUTSEL COMP_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */
<> 144:ef7eb2e8f9f7 4936 #define COMP_CSR_COMP1OUTSEL_0 (0x1U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 4937 #define COMP_CSR_COMP1OUTSEL_1 (0x2U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 4938 #define COMP_CSR_COMP1OUTSEL_2 (0x4U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 4939 #define COMP_CSR_COMP1POL_Pos (11U)
<> 144:ef7eb2e8f9f7 4940 #define COMP_CSR_COMP1POL_Msk (0x1U << COMP_CSR_COMP1POL_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 4941 #define COMP_CSR_COMP1POL COMP_CSR_COMP1POL_Msk /*!< COMP1 output polarity */
<> 144:ef7eb2e8f9f7 4942 #define COMP_CSR_COMP1HYST_Pos (12U)
<> 144:ef7eb2e8f9f7 4943 #define COMP_CSR_COMP1HYST_Msk (0x3U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00003000 */
<> 144:ef7eb2e8f9f7 4944 #define COMP_CSR_COMP1HYST COMP_CSR_COMP1HYST_Msk /*!< COMP1 hysteresis */
<> 144:ef7eb2e8f9f7 4945 #define COMP_CSR_COMP1HYST_0 (0x1U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 4946 #define COMP_CSR_COMP1HYST_1 (0x2U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 4947 #define COMP_CSR_COMP1OUT_Pos (14U)
<> 144:ef7eb2e8f9f7 4948 #define COMP_CSR_COMP1OUT_Msk (0x1U << COMP_CSR_COMP1OUT_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 4949 #define COMP_CSR_COMP1OUT COMP_CSR_COMP1OUT_Msk /*!< COMP1 output level */
<> 144:ef7eb2e8f9f7 4950 #define COMP_CSR_COMP1LOCK_Pos (15U)
<> 144:ef7eb2e8f9f7 4951 #define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 4952 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
<> 144:ef7eb2e8f9f7 4953 /* COMP2 bits definition */
<> 144:ef7eb2e8f9f7 4954 #define COMP_CSR_COMP2EN_Pos (16U)
<> 144:ef7eb2e8f9f7 4955 #define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 4956 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
<> 144:ef7eb2e8f9f7 4957 #define COMP_CSR_COMP2MODE_Pos (18U)
<> 144:ef7eb2e8f9f7 4958 #define COMP_CSR_COMP2MODE_Msk (0x3U << COMP_CSR_COMP2MODE_Pos) /*!< 0x000C0000 */
<> 144:ef7eb2e8f9f7 4959 #define COMP_CSR_COMP2MODE COMP_CSR_COMP2MODE_Msk /*!< COMP2 power mode */
<> 144:ef7eb2e8f9f7 4960 #define COMP_CSR_COMP2MODE_0 (0x1U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 4961 #define COMP_CSR_COMP2MODE_1 (0x2U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 4962 #define COMP_CSR_COMP2INSEL_Pos (20U)
<> 144:ef7eb2e8f9f7 4963 #define COMP_CSR_COMP2INSEL_Msk (0x7U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
<> 144:ef7eb2e8f9f7 4964 #define COMP_CSR_COMP2INSEL COMP_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
<> 144:ef7eb2e8f9f7 4965 #define COMP_CSR_COMP2INSEL_0 (0x1U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 4966 #define COMP_CSR_COMP2INSEL_1 (0x2U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 4967 #define COMP_CSR_COMP2INSEL_2 (0x4U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 4968 #define COMP_CSR_WNDWEN_Pos (23U)
<> 144:ef7eb2e8f9f7 4969 #define COMP_CSR_WNDWEN_Msk (0x1U << COMP_CSR_WNDWEN_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 4970 #define COMP_CSR_WNDWEN COMP_CSR_WNDWEN_Msk /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
<> 144:ef7eb2e8f9f7 4971 #define COMP_CSR_COMP2OUTSEL_Pos (24U)
<> 144:ef7eb2e8f9f7 4972 #define COMP_CSR_COMP2OUTSEL_Msk (0x7U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x07000000 */
<> 144:ef7eb2e8f9f7 4973 #define COMP_CSR_COMP2OUTSEL COMP_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
<> 144:ef7eb2e8f9f7 4974 #define COMP_CSR_COMP2OUTSEL_0 (0x1U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 4975 #define COMP_CSR_COMP2OUTSEL_1 (0x2U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 4976 #define COMP_CSR_COMP2OUTSEL_2 (0x4U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 4977 #define COMP_CSR_COMP2POL_Pos (27U)
<> 144:ef7eb2e8f9f7 4978 #define COMP_CSR_COMP2POL_Msk (0x1U << COMP_CSR_COMP2POL_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 4979 #define COMP_CSR_COMP2POL COMP_CSR_COMP2POL_Msk /*!< COMP2 output polarity */
<> 144:ef7eb2e8f9f7 4980 #define COMP_CSR_COMP2HYST_Pos (28U)
<> 144:ef7eb2e8f9f7 4981 #define COMP_CSR_COMP2HYST_Msk (0x3U << COMP_CSR_COMP2HYST_Pos) /*!< 0x30000000 */
<> 144:ef7eb2e8f9f7 4982 #define COMP_CSR_COMP2HYST COMP_CSR_COMP2HYST_Msk /*!< COMP2 hysteresis */
<> 144:ef7eb2e8f9f7 4983 #define COMP_CSR_COMP2HYST_0 (0x1U << COMP_CSR_COMP2HYST_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 4984 #define COMP_CSR_COMP2HYST_1 (0x2U << COMP_CSR_COMP2HYST_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 4985 #define COMP_CSR_COMP2OUT_Pos (30U)
<> 144:ef7eb2e8f9f7 4986 #define COMP_CSR_COMP2OUT_Msk (0x1U << COMP_CSR_COMP2OUT_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 4987 #define COMP_CSR_COMP2OUT COMP_CSR_COMP2OUT_Msk /*!< COMP2 output level */
<> 144:ef7eb2e8f9f7 4988 #define COMP_CSR_COMP2LOCK_Pos (31U)
<> 144:ef7eb2e8f9f7 4989 #define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 4990 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
<> 144:ef7eb2e8f9f7 4991 /* COMPx bits definition */
<> 144:ef7eb2e8f9f7 4992 #define COMP_CSR_COMPxEN_Pos (0U)
<> 144:ef7eb2e8f9f7 4993 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 4994 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
<> 144:ef7eb2e8f9f7 4995 #define COMP_CSR_COMPxMODE_Pos (2U)
<> 144:ef7eb2e8f9f7 4996 #define COMP_CSR_COMPxMODE_Msk (0x3U << COMP_CSR_COMPxMODE_Pos) /*!< 0x0000000C */
<> 144:ef7eb2e8f9f7 4997 #define COMP_CSR_COMPxMODE COMP_CSR_COMPxMODE_Msk /*!< COMPx power mode */
<> 144:ef7eb2e8f9f7 4998 #define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 4999 #define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5000 #define COMP_CSR_COMPxINSEL_Pos (4U)
<> 144:ef7eb2e8f9f7 5001 #define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 5002 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
<> 144:ef7eb2e8f9f7 5003 #define COMP_CSR_COMPxINSEL_0 (0x1U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5004 #define COMP_CSR_COMPxINSEL_1 (0x2U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5005 #define COMP_CSR_COMPxINSEL_2 (0x4U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5006 #define COMP_CSR_COMPxOUTSEL_Pos (8U)
<> 144:ef7eb2e8f9f7 5007 #define COMP_CSR_COMPxOUTSEL_Msk (0x7U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000700 */
<> 144:ef7eb2e8f9f7 5008 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
<> 144:ef7eb2e8f9f7 5009 #define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5010 #define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5011 #define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5012 #define COMP_CSR_COMPxPOL_Pos (11U)
<> 144:ef7eb2e8f9f7 5013 #define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5014 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */
<> 144:ef7eb2e8f9f7 5015 #define COMP_CSR_COMPxHYST_Pos (12U)
<> 144:ef7eb2e8f9f7 5016 #define COMP_CSR_COMPxHYST_Msk (0x3U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00003000 */
<> 144:ef7eb2e8f9f7 5017 #define COMP_CSR_COMPxHYST COMP_CSR_COMPxHYST_Msk /*!< COMPx hysteresis */
<> 144:ef7eb2e8f9f7 5018 #define COMP_CSR_COMPxHYST_0 (0x1U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5019 #define COMP_CSR_COMPxHYST_1 (0x2U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5020 #define COMP_CSR_COMPxOUT_Pos (14U)
<> 144:ef7eb2e8f9f7 5021 #define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 5022 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */
<> 144:ef7eb2e8f9f7 5023 #define COMP_CSR_COMPxLOCK_Pos (15U)
<> 144:ef7eb2e8f9f7 5024 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 5025 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
<> 144:ef7eb2e8f9f7 5026
<> 144:ef7eb2e8f9f7 5027 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5028 /* */
<> 144:ef7eb2e8f9f7 5029 /* CRC calculation unit (CRC) */
<> 144:ef7eb2e8f9f7 5030 /* */
<> 144:ef7eb2e8f9f7 5031 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5032
<> 144:ef7eb2e8f9f7 5033 /*
<> 144:ef7eb2e8f9f7 5034 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 144:ef7eb2e8f9f7 5035 */
<> 144:ef7eb2e8f9f7 5036
<> 144:ef7eb2e8f9f7 5037 /* Support of Programmable Polynomial size and value feature */
<> 144:ef7eb2e8f9f7 5038 #define CRC_PROG_POLYNOMIAL_SUPPORT
<> 144:ef7eb2e8f9f7 5039
<> 144:ef7eb2e8f9f7 5040 /******************* Bit definition for CRC_DR register *********************/
<> 144:ef7eb2e8f9f7 5041 #define CRC_DR_DR_Pos (0U)
<> 144:ef7eb2e8f9f7 5042 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 5043 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
<> 144:ef7eb2e8f9f7 5044
<> 144:ef7eb2e8f9f7 5045 /******************* Bit definition for CRC_IDR register ********************/
<> 144:ef7eb2e8f9f7 5046 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
<> 144:ef7eb2e8f9f7 5047
<> 144:ef7eb2e8f9f7 5048 /******************** Bit definition for CRC_CR register ********************/
<> 144:ef7eb2e8f9f7 5049 #define CRC_CR_RESET_Pos (0U)
<> 144:ef7eb2e8f9f7 5050 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5051 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
<> 144:ef7eb2e8f9f7 5052 #define CRC_CR_POLYSIZE_Pos (3U)
<> 144:ef7eb2e8f9f7 5053 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
<> 144:ef7eb2e8f9f7 5054 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
<> 144:ef7eb2e8f9f7 5055 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5056 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5057 #define CRC_CR_REV_IN_Pos (5U)
<> 144:ef7eb2e8f9f7 5058 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
<> 144:ef7eb2e8f9f7 5059 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
<> 144:ef7eb2e8f9f7 5060 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5061 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5062 #define CRC_CR_REV_OUT_Pos (7U)
<> 144:ef7eb2e8f9f7 5063 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5064 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
<> 144:ef7eb2e8f9f7 5065
<> 144:ef7eb2e8f9f7 5066 /******************* Bit definition for CRC_INIT register *******************/
<> 144:ef7eb2e8f9f7 5067 #define CRC_INIT_INIT_Pos (0U)
<> 144:ef7eb2e8f9f7 5068 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 5069 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
<> 144:ef7eb2e8f9f7 5070
<> 144:ef7eb2e8f9f7 5071 /******************* Bit definition for CRC_POL register ********************/
<> 144:ef7eb2e8f9f7 5072 #define CRC_POL_POL_Pos (0U)
<> 144:ef7eb2e8f9f7 5073 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 5074 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
<> 144:ef7eb2e8f9f7 5075
<> 144:ef7eb2e8f9f7 5076 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5077 /* */
<> 144:ef7eb2e8f9f7 5078 /* CRS Clock Recovery System */
<> 144:ef7eb2e8f9f7 5079 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5080
<> 144:ef7eb2e8f9f7 5081 /******************* Bit definition for CRS_CR register *********************/
<> 144:ef7eb2e8f9f7 5082 #define CRS_CR_SYNCOKIE_Pos (0U)
<> 144:ef7eb2e8f9f7 5083 #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5084 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
<> 144:ef7eb2e8f9f7 5085 #define CRS_CR_SYNCWARNIE_Pos (1U)
<> 144:ef7eb2e8f9f7 5086 #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5087 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
<> 144:ef7eb2e8f9f7 5088 #define CRS_CR_ERRIE_Pos (2U)
<> 144:ef7eb2e8f9f7 5089 #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5090 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
<> 144:ef7eb2e8f9f7 5091 #define CRS_CR_ESYNCIE_Pos (3U)
<> 144:ef7eb2e8f9f7 5092 #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5093 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
<> 144:ef7eb2e8f9f7 5094 #define CRS_CR_CEN_Pos (5U)
<> 144:ef7eb2e8f9f7 5095 #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5096 #define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
<> 144:ef7eb2e8f9f7 5097 #define CRS_CR_AUTOTRIMEN_Pos (6U)
<> 144:ef7eb2e8f9f7 5098 #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5099 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
<> 144:ef7eb2e8f9f7 5100 #define CRS_CR_SWSYNC_Pos (7U)
<> 144:ef7eb2e8f9f7 5101 #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5102 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
<> 144:ef7eb2e8f9f7 5103 #define CRS_CR_TRIM_Pos (8U)
<> 144:ef7eb2e8f9f7 5104 #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
<> 144:ef7eb2e8f9f7 5105 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
<> 144:ef7eb2e8f9f7 5106
<> 144:ef7eb2e8f9f7 5107 /******************* Bit definition for CRS_CFGR register *********************/
<> 144:ef7eb2e8f9f7 5108 #define CRS_CFGR_RELOAD_Pos (0U)
<> 144:ef7eb2e8f9f7 5109 #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 5110 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
<> 144:ef7eb2e8f9f7 5111 #define CRS_CFGR_FELIM_Pos (16U)
<> 144:ef7eb2e8f9f7 5112 #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 5113 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
<> 144:ef7eb2e8f9f7 5114
<> 144:ef7eb2e8f9f7 5115 #define CRS_CFGR_SYNCDIV_Pos (24U)
<> 144:ef7eb2e8f9f7 5116 #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
<> 144:ef7eb2e8f9f7 5117 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
<> 144:ef7eb2e8f9f7 5118 #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 5119 #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 5120 #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 5121
<> 144:ef7eb2e8f9f7 5122 #define CRS_CFGR_SYNCSRC_Pos (28U)
<> 144:ef7eb2e8f9f7 5123 #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
<> 144:ef7eb2e8f9f7 5124 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
<> 144:ef7eb2e8f9f7 5125 #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 5126 #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 5127
<> 144:ef7eb2e8f9f7 5128 #define CRS_CFGR_SYNCPOL_Pos (31U)
<> 144:ef7eb2e8f9f7 5129 #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 5130 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
<> 144:ef7eb2e8f9f7 5131
<> 144:ef7eb2e8f9f7 5132 /******************* Bit definition for CRS_ISR register *********************/
<> 144:ef7eb2e8f9f7 5133 #define CRS_ISR_SYNCOKF_Pos (0U)
<> 144:ef7eb2e8f9f7 5134 #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5135 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
<> 144:ef7eb2e8f9f7 5136 #define CRS_ISR_SYNCWARNF_Pos (1U)
<> 144:ef7eb2e8f9f7 5137 #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5138 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
<> 144:ef7eb2e8f9f7 5139 #define CRS_ISR_ERRF_Pos (2U)
<> 144:ef7eb2e8f9f7 5140 #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5141 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
<> 144:ef7eb2e8f9f7 5142 #define CRS_ISR_ESYNCF_Pos (3U)
<> 144:ef7eb2e8f9f7 5143 #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5144 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
<> 144:ef7eb2e8f9f7 5145 #define CRS_ISR_SYNCERR_Pos (8U)
<> 144:ef7eb2e8f9f7 5146 #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5147 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
<> 144:ef7eb2e8f9f7 5148 #define CRS_ISR_SYNCMISS_Pos (9U)
<> 144:ef7eb2e8f9f7 5149 #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5150 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
<> 144:ef7eb2e8f9f7 5151 #define CRS_ISR_TRIMOVF_Pos (10U)
<> 144:ef7eb2e8f9f7 5152 #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5153 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
<> 144:ef7eb2e8f9f7 5154 #define CRS_ISR_FEDIR_Pos (15U)
<> 144:ef7eb2e8f9f7 5155 #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 5156 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
<> 144:ef7eb2e8f9f7 5157 #define CRS_ISR_FECAP_Pos (16U)
<> 144:ef7eb2e8f9f7 5158 #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
<> 144:ef7eb2e8f9f7 5159 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
<> 144:ef7eb2e8f9f7 5160
<> 144:ef7eb2e8f9f7 5161 /******************* Bit definition for CRS_ICR register *********************/
<> 144:ef7eb2e8f9f7 5162 #define CRS_ICR_SYNCOKC_Pos (0U)
<> 144:ef7eb2e8f9f7 5163 #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5164 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
<> 144:ef7eb2e8f9f7 5165 #define CRS_ICR_SYNCWARNC_Pos (1U)
<> 144:ef7eb2e8f9f7 5166 #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5167 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
<> 144:ef7eb2e8f9f7 5168 #define CRS_ICR_ERRC_Pos (2U)
<> 144:ef7eb2e8f9f7 5169 #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5170 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
<> 144:ef7eb2e8f9f7 5171 #define CRS_ICR_ESYNCC_Pos (3U)
<> 144:ef7eb2e8f9f7 5172 #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5173 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
<> 144:ef7eb2e8f9f7 5174
<> 144:ef7eb2e8f9f7 5175 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5176 /* */
<> 144:ef7eb2e8f9f7 5177 /* Digital to Analog Converter (DAC) */
<> 144:ef7eb2e8f9f7 5178 /* */
<> 144:ef7eb2e8f9f7 5179 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5180
<> 144:ef7eb2e8f9f7 5181 /*
<> 144:ef7eb2e8f9f7 5182 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 144:ef7eb2e8f9f7 5183 */
<> 144:ef7eb2e8f9f7 5184 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
<> 144:ef7eb2e8f9f7 5185
<> 144:ef7eb2e8f9f7 5186 /******************** Bit definition for DAC_CR register ********************/
<> 144:ef7eb2e8f9f7 5187 #define DAC_CR_EN1_Pos (0U)
<> 144:ef7eb2e8f9f7 5188 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5189 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
<> 144:ef7eb2e8f9f7 5190 #define DAC_CR_BOFF1_Pos (1U)
<> 144:ef7eb2e8f9f7 5191 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5192 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
<> 144:ef7eb2e8f9f7 5193 #define DAC_CR_TEN1_Pos (2U)
<> 144:ef7eb2e8f9f7 5194 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5195 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
<> 144:ef7eb2e8f9f7 5196
<> 144:ef7eb2e8f9f7 5197 #define DAC_CR_TSEL1_Pos (3U)
<> 144:ef7eb2e8f9f7 5198 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
<> 144:ef7eb2e8f9f7 5199 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 144:ef7eb2e8f9f7 5200 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5201 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5202 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5203
<> 144:ef7eb2e8f9f7 5204 #define DAC_CR_WAVE1_Pos (6U)
<> 144:ef7eb2e8f9f7 5205 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
<> 144:ef7eb2e8f9f7 5206 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 5207 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5208 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5209
<> 144:ef7eb2e8f9f7 5210 #define DAC_CR_MAMP1_Pos (8U)
<> 144:ef7eb2e8f9f7 5211 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 5212 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 5213 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5214 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5215 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5216 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5217
<> 144:ef7eb2e8f9f7 5218 #define DAC_CR_DMAEN1_Pos (12U)
<> 144:ef7eb2e8f9f7 5219 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5220 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
<> 144:ef7eb2e8f9f7 5221 #define DAC_CR_DMAUDRIE1_Pos (13U)
<> 144:ef7eb2e8f9f7 5222 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5223 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun Interrupt enable */
<> 144:ef7eb2e8f9f7 5224
<> 144:ef7eb2e8f9f7 5225 #define DAC_CR_EN2_Pos (16U)
<> 144:ef7eb2e8f9f7 5226 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 5227 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
<> 144:ef7eb2e8f9f7 5228 #define DAC_CR_BOFF2_Pos (17U)
<> 144:ef7eb2e8f9f7 5229 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 5230 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
<> 144:ef7eb2e8f9f7 5231 #define DAC_CR_TEN2_Pos (18U)
<> 144:ef7eb2e8f9f7 5232 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 5233 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
<> 144:ef7eb2e8f9f7 5234
<> 144:ef7eb2e8f9f7 5235 #define DAC_CR_TSEL2_Pos (19U)
<> 144:ef7eb2e8f9f7 5236 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
<> 144:ef7eb2e8f9f7 5237 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 144:ef7eb2e8f9f7 5238 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 5239 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 5240 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 5241
<> 144:ef7eb2e8f9f7 5242 #define DAC_CR_WAVE2_Pos (22U)
<> 144:ef7eb2e8f9f7 5243 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
<> 144:ef7eb2e8f9f7 5244 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 5245 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 5246 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 5247
<> 144:ef7eb2e8f9f7 5248 #define DAC_CR_MAMP2_Pos (24U)
<> 144:ef7eb2e8f9f7 5249 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
<> 144:ef7eb2e8f9f7 5250 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 5251 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 5252 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 5253 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 5254 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 5255
<> 144:ef7eb2e8f9f7 5256 #define DAC_CR_DMAEN2_Pos (28U)
<> 144:ef7eb2e8f9f7 5257 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 5258 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
<> 144:ef7eb2e8f9f7 5259 #define DAC_CR_DMAUDRIE2_Pos (29U)
<> 144:ef7eb2e8f9f7 5260 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 5261 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA Underrun Interrupt enable */
<> 144:ef7eb2e8f9f7 5262
<> 144:ef7eb2e8f9f7 5263 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 144:ef7eb2e8f9f7 5264 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
<> 144:ef7eb2e8f9f7 5265 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5266 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
<> 144:ef7eb2e8f9f7 5267 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
<> 144:ef7eb2e8f9f7 5268 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5269 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
<> 144:ef7eb2e8f9f7 5270
<> 144:ef7eb2e8f9f7 5271 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 144:ef7eb2e8f9f7 5272 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
<> 144:ef7eb2e8f9f7 5273 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 5274 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5275
<> 144:ef7eb2e8f9f7 5276 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 144:ef7eb2e8f9f7 5277 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
<> 144:ef7eb2e8f9f7 5278 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 144:ef7eb2e8f9f7 5279 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5280
<> 144:ef7eb2e8f9f7 5281 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 144:ef7eb2e8f9f7 5282 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
<> 144:ef7eb2e8f9f7 5283 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 5284 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5285
<> 144:ef7eb2e8f9f7 5286 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 144:ef7eb2e8f9f7 5287 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
<> 144:ef7eb2e8f9f7 5288 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 5289 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5290
<> 144:ef7eb2e8f9f7 5291 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 144:ef7eb2e8f9f7 5292 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
<> 144:ef7eb2e8f9f7 5293 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
<> 144:ef7eb2e8f9f7 5294 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5295
<> 144:ef7eb2e8f9f7 5296 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 144:ef7eb2e8f9f7 5297 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
<> 144:ef7eb2e8f9f7 5298 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 5299 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5300
<> 144:ef7eb2e8f9f7 5301 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 144:ef7eb2e8f9f7 5302 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
<> 144:ef7eb2e8f9f7 5303 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 5304 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5305 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
<> 144:ef7eb2e8f9f7 5306 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
<> 144:ef7eb2e8f9f7 5307 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5308
<> 144:ef7eb2e8f9f7 5309 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 144:ef7eb2e8f9f7 5310 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
<> 144:ef7eb2e8f9f7 5311 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 144:ef7eb2e8f9f7 5312 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5313 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
<> 144:ef7eb2e8f9f7 5314 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
<> 144:ef7eb2e8f9f7 5315 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5316
<> 144:ef7eb2e8f9f7 5317 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 144:ef7eb2e8f9f7 5318 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
<> 144:ef7eb2e8f9f7 5319 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 5320 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5321 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
<> 144:ef7eb2e8f9f7 5322 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 5323 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5324
<> 144:ef7eb2e8f9f7 5325 /******************* Bit definition for DAC_DOR1 register *******************/
<> 144:ef7eb2e8f9f7 5326 #define DAC_DOR1_DACC1DOR_Pos (0U)
<> 144:ef7eb2e8f9f7 5327 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 5328 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
<> 144:ef7eb2e8f9f7 5329
<> 144:ef7eb2e8f9f7 5330 /******************* Bit definition for DAC_DOR2 register *******************/
<> 144:ef7eb2e8f9f7 5331 #define DAC_DOR2_DACC2DOR_Pos (0U)
<> 144:ef7eb2e8f9f7 5332 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 5333 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
<> 144:ef7eb2e8f9f7 5334
<> 144:ef7eb2e8f9f7 5335 /******************** Bit definition for DAC_SR register ********************/
<> 144:ef7eb2e8f9f7 5336 #define DAC_SR_DMAUDR1_Pos (13U)
<> 144:ef7eb2e8f9f7 5337 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5338 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
<> 144:ef7eb2e8f9f7 5339 #define DAC_SR_DMAUDR2_Pos (29U)
<> 144:ef7eb2e8f9f7 5340 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 5341 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
<> 144:ef7eb2e8f9f7 5342
<> 144:ef7eb2e8f9f7 5343 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5344 /* */
<> 144:ef7eb2e8f9f7 5345 /* Debug MCU (DBGMCU) */
<> 144:ef7eb2e8f9f7 5346 /* */
<> 144:ef7eb2e8f9f7 5347 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5348
<> 144:ef7eb2e8f9f7 5349 /**************** Bit definition for DBGMCU_IDCODE register *****************/
<> 144:ef7eb2e8f9f7 5350 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
<> 144:ef7eb2e8f9f7 5351 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 5352 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
<> 144:ef7eb2e8f9f7 5353
<> 144:ef7eb2e8f9f7 5354 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
<> 144:ef7eb2e8f9f7 5355 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
<> 144:ef7eb2e8f9f7 5356 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
<> 144:ef7eb2e8f9f7 5357 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 5358 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 5359 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 5360 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 5361 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 5362 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 5363 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 5364 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 5365 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 5366 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 5367 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 5368 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 5369 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 5370 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 5371 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 5372 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 5373
<> 144:ef7eb2e8f9f7 5374 /****************** Bit definition for DBGMCU_CR register *******************/
<> 144:ef7eb2e8f9f7 5375 #define DBGMCU_CR_DBG_STOP_Pos (1U)
<> 144:ef7eb2e8f9f7 5376 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5377 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
<> 144:ef7eb2e8f9f7 5378 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
<> 144:ef7eb2e8f9f7 5379 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5380 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
<> 144:ef7eb2e8f9f7 5381
<> 144:ef7eb2e8f9f7 5382 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
<> 144:ef7eb2e8f9f7 5383 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
<> 144:ef7eb2e8f9f7 5384 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5385 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5386 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
<> 144:ef7eb2e8f9f7 5387 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5388 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5389 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
<> 144:ef7eb2e8f9f7 5390 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5391 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5392 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
<> 144:ef7eb2e8f9f7 5393 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5394 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5395 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
<> 144:ef7eb2e8f9f7 5396 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5397 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5398 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
<> 144:ef7eb2e8f9f7 5399 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5400 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
<> 144:ef7eb2e8f9f7 5401 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
<> 144:ef7eb2e8f9f7 5402 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5403 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
<> 144:ef7eb2e8f9f7 5404 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
<> 144:ef7eb2e8f9f7 5405 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5406 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
<> 144:ef7eb2e8f9f7 5407 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
<> 144:ef7eb2e8f9f7 5408 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 5409 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
<> 144:ef7eb2e8f9f7 5410 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)
<> 144:ef7eb2e8f9f7 5411 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 5412 #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk /*!< CAN debug stopped when Core is halted */
<> 144:ef7eb2e8f9f7 5413
<> 144:ef7eb2e8f9f7 5414 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
<> 144:ef7eb2e8f9f7 5415 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
<> 144:ef7eb2e8f9f7 5416 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5417 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5418 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U)
<> 144:ef7eb2e8f9f7 5419 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 5420 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5421 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
<> 144:ef7eb2e8f9f7 5422 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 5423 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5424 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
<> 144:ef7eb2e8f9f7 5425 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 5426 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 5427
<> 144:ef7eb2e8f9f7 5428 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5429 /* */
<> 144:ef7eb2e8f9f7 5430 /* DMA Controller (DMA) */
<> 144:ef7eb2e8f9f7 5431 /* */
<> 144:ef7eb2e8f9f7 5432 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5433 /******************* Bit definition for DMA_ISR register ********************/
<> 144:ef7eb2e8f9f7 5434 #define DMA_ISR_GIF1_Pos (0U)
<> 144:ef7eb2e8f9f7 5435 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5436 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
<> 144:ef7eb2e8f9f7 5437 #define DMA_ISR_TCIF1_Pos (1U)
<> 144:ef7eb2e8f9f7 5438 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5439 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 5440 #define DMA_ISR_HTIF1_Pos (2U)
<> 144:ef7eb2e8f9f7 5441 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5442 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
<> 144:ef7eb2e8f9f7 5443 #define DMA_ISR_TEIF1_Pos (3U)
<> 144:ef7eb2e8f9f7 5444 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5445 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
<> 144:ef7eb2e8f9f7 5446 #define DMA_ISR_GIF2_Pos (4U)
<> 144:ef7eb2e8f9f7 5447 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5448 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
<> 144:ef7eb2e8f9f7 5449 #define DMA_ISR_TCIF2_Pos (5U)
<> 144:ef7eb2e8f9f7 5450 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5451 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 5452 #define DMA_ISR_HTIF2_Pos (6U)
<> 144:ef7eb2e8f9f7 5453 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5454 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
<> 144:ef7eb2e8f9f7 5455 #define DMA_ISR_TEIF2_Pos (7U)
<> 144:ef7eb2e8f9f7 5456 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5457 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
<> 144:ef7eb2e8f9f7 5458 #define DMA_ISR_GIF3_Pos (8U)
<> 144:ef7eb2e8f9f7 5459 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5460 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
<> 144:ef7eb2e8f9f7 5461 #define DMA_ISR_TCIF3_Pos (9U)
<> 144:ef7eb2e8f9f7 5462 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5463 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 5464 #define DMA_ISR_HTIF3_Pos (10U)
<> 144:ef7eb2e8f9f7 5465 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5466 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
<> 144:ef7eb2e8f9f7 5467 #define DMA_ISR_TEIF3_Pos (11U)
<> 144:ef7eb2e8f9f7 5468 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5469 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
<> 144:ef7eb2e8f9f7 5470 #define DMA_ISR_GIF4_Pos (12U)
<> 144:ef7eb2e8f9f7 5471 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5472 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
<> 144:ef7eb2e8f9f7 5473 #define DMA_ISR_TCIF4_Pos (13U)
<> 144:ef7eb2e8f9f7 5474 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5475 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 5476 #define DMA_ISR_HTIF4_Pos (14U)
<> 144:ef7eb2e8f9f7 5477 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 5478 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
<> 144:ef7eb2e8f9f7 5479 #define DMA_ISR_TEIF4_Pos (15U)
<> 144:ef7eb2e8f9f7 5480 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 5481 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
<> 144:ef7eb2e8f9f7 5482 #define DMA_ISR_GIF5_Pos (16U)
<> 144:ef7eb2e8f9f7 5483 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 5484 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
<> 144:ef7eb2e8f9f7 5485 #define DMA_ISR_TCIF5_Pos (17U)
<> 144:ef7eb2e8f9f7 5486 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 5487 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 5488 #define DMA_ISR_HTIF5_Pos (18U)
<> 144:ef7eb2e8f9f7 5489 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 5490 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
<> 144:ef7eb2e8f9f7 5491 #define DMA_ISR_TEIF5_Pos (19U)
<> 144:ef7eb2e8f9f7 5492 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 5493 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
<> 144:ef7eb2e8f9f7 5494 #define DMA_ISR_GIF6_Pos (20U)
<> 144:ef7eb2e8f9f7 5495 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 5496 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
<> 144:ef7eb2e8f9f7 5497 #define DMA_ISR_TCIF6_Pos (21U)
<> 144:ef7eb2e8f9f7 5498 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 5499 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 5500 #define DMA_ISR_HTIF6_Pos (22U)
<> 144:ef7eb2e8f9f7 5501 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 5502 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
<> 144:ef7eb2e8f9f7 5503 #define DMA_ISR_TEIF6_Pos (23U)
<> 144:ef7eb2e8f9f7 5504 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 5505 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
<> 144:ef7eb2e8f9f7 5506 #define DMA_ISR_GIF7_Pos (24U)
<> 144:ef7eb2e8f9f7 5507 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 5508 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
<> 144:ef7eb2e8f9f7 5509 #define DMA_ISR_TCIF7_Pos (25U)
<> 144:ef7eb2e8f9f7 5510 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 5511 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 5512 #define DMA_ISR_HTIF7_Pos (26U)
<> 144:ef7eb2e8f9f7 5513 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 5514 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
<> 144:ef7eb2e8f9f7 5515 #define DMA_ISR_TEIF7_Pos (27U)
<> 144:ef7eb2e8f9f7 5516 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 5517 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
<> 144:ef7eb2e8f9f7 5518
<> 144:ef7eb2e8f9f7 5519 /******************* Bit definition for DMA_IFCR register *******************/
<> 144:ef7eb2e8f9f7 5520 #define DMA_IFCR_CGIF1_Pos (0U)
<> 144:ef7eb2e8f9f7 5521 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5522 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
<> 144:ef7eb2e8f9f7 5523 #define DMA_IFCR_CTCIF1_Pos (1U)
<> 144:ef7eb2e8f9f7 5524 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5525 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 5526 #define DMA_IFCR_CHTIF1_Pos (2U)
<> 144:ef7eb2e8f9f7 5527 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5528 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
<> 144:ef7eb2e8f9f7 5529 #define DMA_IFCR_CTEIF1_Pos (3U)
<> 144:ef7eb2e8f9f7 5530 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5531 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
<> 144:ef7eb2e8f9f7 5532 #define DMA_IFCR_CGIF2_Pos (4U)
<> 144:ef7eb2e8f9f7 5533 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5534 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
<> 144:ef7eb2e8f9f7 5535 #define DMA_IFCR_CTCIF2_Pos (5U)
<> 144:ef7eb2e8f9f7 5536 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5537 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 5538 #define DMA_IFCR_CHTIF2_Pos (6U)
<> 144:ef7eb2e8f9f7 5539 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5540 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
<> 144:ef7eb2e8f9f7 5541 #define DMA_IFCR_CTEIF2_Pos (7U)
<> 144:ef7eb2e8f9f7 5542 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5543 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
<> 144:ef7eb2e8f9f7 5544 #define DMA_IFCR_CGIF3_Pos (8U)
<> 144:ef7eb2e8f9f7 5545 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5546 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
<> 144:ef7eb2e8f9f7 5547 #define DMA_IFCR_CTCIF3_Pos (9U)
<> 144:ef7eb2e8f9f7 5548 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5549 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 5550 #define DMA_IFCR_CHTIF3_Pos (10U)
<> 144:ef7eb2e8f9f7 5551 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5552 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
<> 144:ef7eb2e8f9f7 5553 #define DMA_IFCR_CTEIF3_Pos (11U)
<> 144:ef7eb2e8f9f7 5554 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5555 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
<> 144:ef7eb2e8f9f7 5556 #define DMA_IFCR_CGIF4_Pos (12U)
<> 144:ef7eb2e8f9f7 5557 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5558 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
<> 144:ef7eb2e8f9f7 5559 #define DMA_IFCR_CTCIF4_Pos (13U)
<> 144:ef7eb2e8f9f7 5560 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5561 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 5562 #define DMA_IFCR_CHTIF4_Pos (14U)
<> 144:ef7eb2e8f9f7 5563 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 5564 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
<> 144:ef7eb2e8f9f7 5565 #define DMA_IFCR_CTEIF4_Pos (15U)
<> 144:ef7eb2e8f9f7 5566 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 5567 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
<> 144:ef7eb2e8f9f7 5568 #define DMA_IFCR_CGIF5_Pos (16U)
<> 144:ef7eb2e8f9f7 5569 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 5570 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
<> 144:ef7eb2e8f9f7 5571 #define DMA_IFCR_CTCIF5_Pos (17U)
<> 144:ef7eb2e8f9f7 5572 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 5573 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 5574 #define DMA_IFCR_CHTIF5_Pos (18U)
<> 144:ef7eb2e8f9f7 5575 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 5576 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
<> 144:ef7eb2e8f9f7 5577 #define DMA_IFCR_CTEIF5_Pos (19U)
<> 144:ef7eb2e8f9f7 5578 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 5579 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
<> 144:ef7eb2e8f9f7 5580 #define DMA_IFCR_CGIF6_Pos (20U)
<> 144:ef7eb2e8f9f7 5581 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 5582 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
<> 144:ef7eb2e8f9f7 5583 #define DMA_IFCR_CTCIF6_Pos (21U)
<> 144:ef7eb2e8f9f7 5584 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 5585 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 5586 #define DMA_IFCR_CHTIF6_Pos (22U)
<> 144:ef7eb2e8f9f7 5587 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 5588 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
<> 144:ef7eb2e8f9f7 5589 #define DMA_IFCR_CTEIF6_Pos (23U)
<> 144:ef7eb2e8f9f7 5590 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 5591 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
<> 144:ef7eb2e8f9f7 5592 #define DMA_IFCR_CGIF7_Pos (24U)
<> 144:ef7eb2e8f9f7 5593 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 5594 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
<> 144:ef7eb2e8f9f7 5595 #define DMA_IFCR_CTCIF7_Pos (25U)
<> 144:ef7eb2e8f9f7 5596 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 5597 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 5598 #define DMA_IFCR_CHTIF7_Pos (26U)
<> 144:ef7eb2e8f9f7 5599 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 5600 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
<> 144:ef7eb2e8f9f7 5601 #define DMA_IFCR_CTEIF7_Pos (27U)
<> 144:ef7eb2e8f9f7 5602 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 5603 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
<> 144:ef7eb2e8f9f7 5604
<> 144:ef7eb2e8f9f7 5605 /******************* Bit definition for DMA_CCR register ********************/
<> 144:ef7eb2e8f9f7 5606 #define DMA_CCR_EN_Pos (0U)
<> 144:ef7eb2e8f9f7 5607 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5608 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
<> 144:ef7eb2e8f9f7 5609 #define DMA_CCR_TCIE_Pos (1U)
<> 144:ef7eb2e8f9f7 5610 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5611 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 144:ef7eb2e8f9f7 5612 #define DMA_CCR_HTIE_Pos (2U)
<> 144:ef7eb2e8f9f7 5613 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5614 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
<> 144:ef7eb2e8f9f7 5615 #define DMA_CCR_TEIE_Pos (3U)
<> 144:ef7eb2e8f9f7 5616 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5617 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
<> 144:ef7eb2e8f9f7 5618 #define DMA_CCR_DIR_Pos (4U)
<> 144:ef7eb2e8f9f7 5619 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5620 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
<> 144:ef7eb2e8f9f7 5621 #define DMA_CCR_CIRC_Pos (5U)
<> 144:ef7eb2e8f9f7 5622 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5623 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
<> 144:ef7eb2e8f9f7 5624 #define DMA_CCR_PINC_Pos (6U)
<> 144:ef7eb2e8f9f7 5625 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5626 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
<> 144:ef7eb2e8f9f7 5627 #define DMA_CCR_MINC_Pos (7U)
<> 144:ef7eb2e8f9f7 5628 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5629 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
<> 144:ef7eb2e8f9f7 5630
<> 144:ef7eb2e8f9f7 5631 #define DMA_CCR_PSIZE_Pos (8U)
<> 144:ef7eb2e8f9f7 5632 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 5633 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
<> 144:ef7eb2e8f9f7 5634 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5635 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5636
<> 144:ef7eb2e8f9f7 5637 #define DMA_CCR_MSIZE_Pos (10U)
<> 144:ef7eb2e8f9f7 5638 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
<> 144:ef7eb2e8f9f7 5639 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
<> 144:ef7eb2e8f9f7 5640 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5641 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5642
<> 144:ef7eb2e8f9f7 5643 #define DMA_CCR_PL_Pos (12U)
<> 144:ef7eb2e8f9f7 5644 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
<> 144:ef7eb2e8f9f7 5645 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
<> 144:ef7eb2e8f9f7 5646 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5647 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5648
<> 144:ef7eb2e8f9f7 5649 #define DMA_CCR_MEM2MEM_Pos (14U)
<> 144:ef7eb2e8f9f7 5650 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 5651 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
<> 144:ef7eb2e8f9f7 5652
<> 144:ef7eb2e8f9f7 5653 /****************** Bit definition for DMA_CNDTR register *******************/
<> 144:ef7eb2e8f9f7 5654 #define DMA_CNDTR_NDT_Pos (0U)
<> 144:ef7eb2e8f9f7 5655 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 5656 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
<> 144:ef7eb2e8f9f7 5657
<> 144:ef7eb2e8f9f7 5658 /****************** Bit definition for DMA_CPAR register ********************/
<> 144:ef7eb2e8f9f7 5659 #define DMA_CPAR_PA_Pos (0U)
<> 144:ef7eb2e8f9f7 5660 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 5661 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
<> 144:ef7eb2e8f9f7 5662
<> 144:ef7eb2e8f9f7 5663 /****************** Bit definition for DMA_CMAR register ********************/
<> 144:ef7eb2e8f9f7 5664 #define DMA_CMAR_MA_Pos (0U)
<> 144:ef7eb2e8f9f7 5665 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 5666 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 5667
<> 144:ef7eb2e8f9f7 5668 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5669 /* */
<> 144:ef7eb2e8f9f7 5670 /* External Interrupt/Event Controller (EXTI) */
<> 144:ef7eb2e8f9f7 5671 /* */
<> 144:ef7eb2e8f9f7 5672 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5673 /******************* Bit definition for EXTI_IMR register *******************/
<> 144:ef7eb2e8f9f7 5674 #define EXTI_IMR_MR0_Pos (0U)
<> 144:ef7eb2e8f9f7 5675 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5676 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
<> 144:ef7eb2e8f9f7 5677 #define EXTI_IMR_MR1_Pos (1U)
<> 144:ef7eb2e8f9f7 5678 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5679 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
<> 144:ef7eb2e8f9f7 5680 #define EXTI_IMR_MR2_Pos (2U)
<> 144:ef7eb2e8f9f7 5681 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5682 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
<> 144:ef7eb2e8f9f7 5683 #define EXTI_IMR_MR3_Pos (3U)
<> 144:ef7eb2e8f9f7 5684 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5685 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
<> 144:ef7eb2e8f9f7 5686 #define EXTI_IMR_MR4_Pos (4U)
<> 144:ef7eb2e8f9f7 5687 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5688 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
<> 144:ef7eb2e8f9f7 5689 #define EXTI_IMR_MR5_Pos (5U)
<> 144:ef7eb2e8f9f7 5690 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5691 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
<> 144:ef7eb2e8f9f7 5692 #define EXTI_IMR_MR6_Pos (6U)
<> 144:ef7eb2e8f9f7 5693 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5694 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
<> 144:ef7eb2e8f9f7 5695 #define EXTI_IMR_MR7_Pos (7U)
<> 144:ef7eb2e8f9f7 5696 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5697 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
<> 144:ef7eb2e8f9f7 5698 #define EXTI_IMR_MR8_Pos (8U)
<> 144:ef7eb2e8f9f7 5699 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5700 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
<> 144:ef7eb2e8f9f7 5701 #define EXTI_IMR_MR9_Pos (9U)
<> 144:ef7eb2e8f9f7 5702 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5703 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
<> 144:ef7eb2e8f9f7 5704 #define EXTI_IMR_MR10_Pos (10U)
<> 144:ef7eb2e8f9f7 5705 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5706 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
<> 144:ef7eb2e8f9f7 5707 #define EXTI_IMR_MR11_Pos (11U)
<> 144:ef7eb2e8f9f7 5708 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5709 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
<> 144:ef7eb2e8f9f7 5710 #define EXTI_IMR_MR12_Pos (12U)
<> 144:ef7eb2e8f9f7 5711 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5712 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
<> 144:ef7eb2e8f9f7 5713 #define EXTI_IMR_MR13_Pos (13U)
<> 144:ef7eb2e8f9f7 5714 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5715 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
<> 144:ef7eb2e8f9f7 5716 #define EXTI_IMR_MR14_Pos (14U)
<> 144:ef7eb2e8f9f7 5717 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 5718 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
<> 144:ef7eb2e8f9f7 5719 #define EXTI_IMR_MR15_Pos (15U)
<> 144:ef7eb2e8f9f7 5720 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 5721 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
<> 144:ef7eb2e8f9f7 5722 #define EXTI_IMR_MR16_Pos (16U)
<> 144:ef7eb2e8f9f7 5723 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 5724 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
<> 144:ef7eb2e8f9f7 5725 #define EXTI_IMR_MR17_Pos (17U)
<> 144:ef7eb2e8f9f7 5726 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 5727 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
<> 144:ef7eb2e8f9f7 5728 #define EXTI_IMR_MR18_Pos (18U)
<> 144:ef7eb2e8f9f7 5729 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 5730 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
<> 144:ef7eb2e8f9f7 5731 #define EXTI_IMR_MR19_Pos (19U)
<> 144:ef7eb2e8f9f7 5732 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 5733 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
<> 144:ef7eb2e8f9f7 5734 #define EXTI_IMR_MR20_Pos (20U)
<> 144:ef7eb2e8f9f7 5735 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 5736 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
<> 144:ef7eb2e8f9f7 5737 #define EXTI_IMR_MR21_Pos (21U)
<> 144:ef7eb2e8f9f7 5738 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 5739 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
<> 144:ef7eb2e8f9f7 5740 #define EXTI_IMR_MR22_Pos (22U)
<> 144:ef7eb2e8f9f7 5741 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 5742 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
<> 144:ef7eb2e8f9f7 5743 #define EXTI_IMR_MR23_Pos (23U)
<> 144:ef7eb2e8f9f7 5744 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 5745 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
<> 144:ef7eb2e8f9f7 5746 #define EXTI_IMR_MR25_Pos (25U)
<> 144:ef7eb2e8f9f7 5747 #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 5748 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
<> 144:ef7eb2e8f9f7 5749 #define EXTI_IMR_MR26_Pos (26U)
<> 144:ef7eb2e8f9f7 5750 #define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 5751 #define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
<> 144:ef7eb2e8f9f7 5752 #define EXTI_IMR_MR27_Pos (27U)
<> 144:ef7eb2e8f9f7 5753 #define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 5754 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
<> 144:ef7eb2e8f9f7 5755 #define EXTI_IMR_MR31_Pos (31U)
<> 144:ef7eb2e8f9f7 5756 #define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 5757 #define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
<> 144:ef7eb2e8f9f7 5758
<> 144:ef7eb2e8f9f7 5759 /* References Defines */
<> 144:ef7eb2e8f9f7 5760 #define EXTI_IMR_IM0 EXTI_IMR_MR0
<> 144:ef7eb2e8f9f7 5761 #define EXTI_IMR_IM1 EXTI_IMR_MR1
<> 144:ef7eb2e8f9f7 5762 #define EXTI_IMR_IM2 EXTI_IMR_MR2
<> 144:ef7eb2e8f9f7 5763 #define EXTI_IMR_IM3 EXTI_IMR_MR3
<> 144:ef7eb2e8f9f7 5764 #define EXTI_IMR_IM4 EXTI_IMR_MR4
<> 144:ef7eb2e8f9f7 5765 #define EXTI_IMR_IM5 EXTI_IMR_MR5
<> 144:ef7eb2e8f9f7 5766 #define EXTI_IMR_IM6 EXTI_IMR_MR6
<> 144:ef7eb2e8f9f7 5767 #define EXTI_IMR_IM7 EXTI_IMR_MR7
<> 144:ef7eb2e8f9f7 5768 #define EXTI_IMR_IM8 EXTI_IMR_MR8
<> 144:ef7eb2e8f9f7 5769 #define EXTI_IMR_IM9 EXTI_IMR_MR9
<> 144:ef7eb2e8f9f7 5770 #define EXTI_IMR_IM10 EXTI_IMR_MR10
<> 144:ef7eb2e8f9f7 5771 #define EXTI_IMR_IM11 EXTI_IMR_MR11
<> 144:ef7eb2e8f9f7 5772 #define EXTI_IMR_IM12 EXTI_IMR_MR12
<> 144:ef7eb2e8f9f7 5773 #define EXTI_IMR_IM13 EXTI_IMR_MR13
<> 144:ef7eb2e8f9f7 5774 #define EXTI_IMR_IM14 EXTI_IMR_MR14
<> 144:ef7eb2e8f9f7 5775 #define EXTI_IMR_IM15 EXTI_IMR_MR15
<> 144:ef7eb2e8f9f7 5776 #define EXTI_IMR_IM16 EXTI_IMR_MR16
<> 144:ef7eb2e8f9f7 5777 #define EXTI_IMR_IM17 EXTI_IMR_MR17
<> 144:ef7eb2e8f9f7 5778 #define EXTI_IMR_IM18 EXTI_IMR_MR18
<> 144:ef7eb2e8f9f7 5779 #define EXTI_IMR_IM19 EXTI_IMR_MR19
<> 144:ef7eb2e8f9f7 5780 #define EXTI_IMR_IM20 EXTI_IMR_MR20
<> 144:ef7eb2e8f9f7 5781 #define EXTI_IMR_IM21 EXTI_IMR_MR21
<> 144:ef7eb2e8f9f7 5782 #define EXTI_IMR_IM22 EXTI_IMR_MR22
<> 144:ef7eb2e8f9f7 5783 #define EXTI_IMR_IM23 EXTI_IMR_MR23
<> 144:ef7eb2e8f9f7 5784 #define EXTI_IMR_IM25 EXTI_IMR_MR25
<> 144:ef7eb2e8f9f7 5785 #define EXTI_IMR_IM26 EXTI_IMR_MR26
<> 144:ef7eb2e8f9f7 5786 #define EXTI_IMR_IM27 EXTI_IMR_MR27
<> 144:ef7eb2e8f9f7 5787 #define EXTI_IMR_IM31 EXTI_IMR_MR31
<> 144:ef7eb2e8f9f7 5788
<> 144:ef7eb2e8f9f7 5789 #define EXTI_IMR_IM_Pos (0U)
<> 144:ef7eb2e8f9f7 5790 #define EXTI_IMR_IM_Msk (0x8EFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x8EFFFFFF */
<> 144:ef7eb2e8f9f7 5791 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
<> 144:ef7eb2e8f9f7 5792
<> 144:ef7eb2e8f9f7 5793
<> 144:ef7eb2e8f9f7 5794 /****************** Bit definition for EXTI_EMR register ********************/
<> 144:ef7eb2e8f9f7 5795 #define EXTI_EMR_MR0_Pos (0U)
<> 144:ef7eb2e8f9f7 5796 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5797 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
<> 144:ef7eb2e8f9f7 5798 #define EXTI_EMR_MR1_Pos (1U)
<> 144:ef7eb2e8f9f7 5799 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5800 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
<> 144:ef7eb2e8f9f7 5801 #define EXTI_EMR_MR2_Pos (2U)
<> 144:ef7eb2e8f9f7 5802 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5803 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
<> 144:ef7eb2e8f9f7 5804 #define EXTI_EMR_MR3_Pos (3U)
<> 144:ef7eb2e8f9f7 5805 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5806 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
<> 144:ef7eb2e8f9f7 5807 #define EXTI_EMR_MR4_Pos (4U)
<> 144:ef7eb2e8f9f7 5808 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5809 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
<> 144:ef7eb2e8f9f7 5810 #define EXTI_EMR_MR5_Pos (5U)
<> 144:ef7eb2e8f9f7 5811 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5812 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
<> 144:ef7eb2e8f9f7 5813 #define EXTI_EMR_MR6_Pos (6U)
<> 144:ef7eb2e8f9f7 5814 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5815 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
<> 144:ef7eb2e8f9f7 5816 #define EXTI_EMR_MR7_Pos (7U)
<> 144:ef7eb2e8f9f7 5817 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5818 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
<> 144:ef7eb2e8f9f7 5819 #define EXTI_EMR_MR8_Pos (8U)
<> 144:ef7eb2e8f9f7 5820 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5821 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
<> 144:ef7eb2e8f9f7 5822 #define EXTI_EMR_MR9_Pos (9U)
<> 144:ef7eb2e8f9f7 5823 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5824 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
<> 144:ef7eb2e8f9f7 5825 #define EXTI_EMR_MR10_Pos (10U)
<> 144:ef7eb2e8f9f7 5826 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5827 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
<> 144:ef7eb2e8f9f7 5828 #define EXTI_EMR_MR11_Pos (11U)
<> 144:ef7eb2e8f9f7 5829 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5830 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
<> 144:ef7eb2e8f9f7 5831 #define EXTI_EMR_MR12_Pos (12U)
<> 144:ef7eb2e8f9f7 5832 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5833 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
<> 144:ef7eb2e8f9f7 5834 #define EXTI_EMR_MR13_Pos (13U)
<> 144:ef7eb2e8f9f7 5835 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5836 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
<> 144:ef7eb2e8f9f7 5837 #define EXTI_EMR_MR14_Pos (14U)
<> 144:ef7eb2e8f9f7 5838 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 5839 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
<> 144:ef7eb2e8f9f7 5840 #define EXTI_EMR_MR15_Pos (15U)
<> 144:ef7eb2e8f9f7 5841 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 5842 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
<> 144:ef7eb2e8f9f7 5843 #define EXTI_EMR_MR16_Pos (16U)
<> 144:ef7eb2e8f9f7 5844 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 5845 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
<> 144:ef7eb2e8f9f7 5846 #define EXTI_EMR_MR17_Pos (17U)
<> 144:ef7eb2e8f9f7 5847 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 5848 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
<> 144:ef7eb2e8f9f7 5849 #define EXTI_EMR_MR18_Pos (18U)
<> 144:ef7eb2e8f9f7 5850 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 5851 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
<> 144:ef7eb2e8f9f7 5852 #define EXTI_EMR_MR19_Pos (19U)
<> 144:ef7eb2e8f9f7 5853 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 5854 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
<> 144:ef7eb2e8f9f7 5855 #define EXTI_EMR_MR20_Pos (20U)
<> 144:ef7eb2e8f9f7 5856 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 5857 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
<> 144:ef7eb2e8f9f7 5858 #define EXTI_EMR_MR21_Pos (21U)
<> 144:ef7eb2e8f9f7 5859 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 5860 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
<> 144:ef7eb2e8f9f7 5861 #define EXTI_EMR_MR22_Pos (22U)
<> 144:ef7eb2e8f9f7 5862 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 5863 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
<> 144:ef7eb2e8f9f7 5864 #define EXTI_EMR_MR23_Pos (23U)
<> 144:ef7eb2e8f9f7 5865 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 5866 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
<> 144:ef7eb2e8f9f7 5867 #define EXTI_EMR_MR25_Pos (25U)
<> 144:ef7eb2e8f9f7 5868 #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 5869 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
<> 144:ef7eb2e8f9f7 5870 #define EXTI_EMR_MR26_Pos (26U)
<> 144:ef7eb2e8f9f7 5871 #define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 5872 #define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
<> 144:ef7eb2e8f9f7 5873 #define EXTI_EMR_MR27_Pos (27U)
<> 144:ef7eb2e8f9f7 5874 #define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 5875 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
<> 144:ef7eb2e8f9f7 5876 #define EXTI_EMR_MR31_Pos (31U)
<> 144:ef7eb2e8f9f7 5877 #define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 5878 #define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
<> 144:ef7eb2e8f9f7 5879
<> 144:ef7eb2e8f9f7 5880 /* References Defines */
<> 144:ef7eb2e8f9f7 5881 #define EXTI_EMR_EM0 EXTI_EMR_MR0
<> 144:ef7eb2e8f9f7 5882 #define EXTI_EMR_EM1 EXTI_EMR_MR1
<> 144:ef7eb2e8f9f7 5883 #define EXTI_EMR_EM2 EXTI_EMR_MR2
<> 144:ef7eb2e8f9f7 5884 #define EXTI_EMR_EM3 EXTI_EMR_MR3
<> 144:ef7eb2e8f9f7 5885 #define EXTI_EMR_EM4 EXTI_EMR_MR4
<> 144:ef7eb2e8f9f7 5886 #define EXTI_EMR_EM5 EXTI_EMR_MR5
<> 144:ef7eb2e8f9f7 5887 #define EXTI_EMR_EM6 EXTI_EMR_MR6
<> 144:ef7eb2e8f9f7 5888 #define EXTI_EMR_EM7 EXTI_EMR_MR7
<> 144:ef7eb2e8f9f7 5889 #define EXTI_EMR_EM8 EXTI_EMR_MR8
<> 144:ef7eb2e8f9f7 5890 #define EXTI_EMR_EM9 EXTI_EMR_MR9
<> 144:ef7eb2e8f9f7 5891 #define EXTI_EMR_EM10 EXTI_EMR_MR10
<> 144:ef7eb2e8f9f7 5892 #define EXTI_EMR_EM11 EXTI_EMR_MR11
<> 144:ef7eb2e8f9f7 5893 #define EXTI_EMR_EM12 EXTI_EMR_MR12
<> 144:ef7eb2e8f9f7 5894 #define EXTI_EMR_EM13 EXTI_EMR_MR13
<> 144:ef7eb2e8f9f7 5895 #define EXTI_EMR_EM14 EXTI_EMR_MR14
<> 144:ef7eb2e8f9f7 5896 #define EXTI_EMR_EM15 EXTI_EMR_MR15
<> 144:ef7eb2e8f9f7 5897 #define EXTI_EMR_EM16 EXTI_EMR_MR16
<> 144:ef7eb2e8f9f7 5898 #define EXTI_EMR_EM17 EXTI_EMR_MR17
<> 144:ef7eb2e8f9f7 5899 #define EXTI_EMR_EM18 EXTI_EMR_MR18
<> 144:ef7eb2e8f9f7 5900 #define EXTI_EMR_EM19 EXTI_EMR_MR19
<> 144:ef7eb2e8f9f7 5901 #define EXTI_EMR_EM20 EXTI_EMR_MR20
<> 144:ef7eb2e8f9f7 5902 #define EXTI_EMR_EM21 EXTI_EMR_MR21
<> 144:ef7eb2e8f9f7 5903 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 144:ef7eb2e8f9f7 5904 #define EXTI_EMR_EM23 EXTI_EMR_MR23
<> 144:ef7eb2e8f9f7 5905 #define EXTI_EMR_EM25 EXTI_EMR_MR25
<> 144:ef7eb2e8f9f7 5906 #define EXTI_EMR_EM26 EXTI_EMR_MR26
<> 144:ef7eb2e8f9f7 5907 #define EXTI_EMR_EM27 EXTI_EMR_MR27
<> 144:ef7eb2e8f9f7 5908 #define EXTI_EMR_EM31 EXTI_EMR_MR31
<> 144:ef7eb2e8f9f7 5909
<> 144:ef7eb2e8f9f7 5910 /******************* Bit definition for EXTI_RTSR register ******************/
<> 144:ef7eb2e8f9f7 5911 #define EXTI_RTSR_TR0_Pos (0U)
<> 144:ef7eb2e8f9f7 5912 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 5913 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 5914 #define EXTI_RTSR_TR1_Pos (1U)
<> 144:ef7eb2e8f9f7 5915 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 5916 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 5917 #define EXTI_RTSR_TR2_Pos (2U)
<> 144:ef7eb2e8f9f7 5918 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 5919 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 5920 #define EXTI_RTSR_TR3_Pos (3U)
<> 144:ef7eb2e8f9f7 5921 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 5922 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 5923 #define EXTI_RTSR_TR4_Pos (4U)
<> 144:ef7eb2e8f9f7 5924 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 5925 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 5926 #define EXTI_RTSR_TR5_Pos (5U)
<> 144:ef7eb2e8f9f7 5927 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 5928 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 5929 #define EXTI_RTSR_TR6_Pos (6U)
<> 144:ef7eb2e8f9f7 5930 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 5931 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 5932 #define EXTI_RTSR_TR7_Pos (7U)
<> 144:ef7eb2e8f9f7 5933 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 5934 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 5935 #define EXTI_RTSR_TR8_Pos (8U)
<> 144:ef7eb2e8f9f7 5936 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 5937 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 5938 #define EXTI_RTSR_TR9_Pos (9U)
<> 144:ef7eb2e8f9f7 5939 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 5940 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 5941 #define EXTI_RTSR_TR10_Pos (10U)
<> 144:ef7eb2e8f9f7 5942 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 5943 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 5944 #define EXTI_RTSR_TR11_Pos (11U)
<> 144:ef7eb2e8f9f7 5945 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 5946 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 5947 #define EXTI_RTSR_TR12_Pos (12U)
<> 144:ef7eb2e8f9f7 5948 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 5949 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 5950 #define EXTI_RTSR_TR13_Pos (13U)
<> 144:ef7eb2e8f9f7 5951 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 5952 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 5953 #define EXTI_RTSR_TR14_Pos (14U)
<> 144:ef7eb2e8f9f7 5954 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 5955 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 5956 #define EXTI_RTSR_TR15_Pos (15U)
<> 144:ef7eb2e8f9f7 5957 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 5958 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 5959 #define EXTI_RTSR_TR16_Pos (16U)
<> 144:ef7eb2e8f9f7 5960 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 5961 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 5962 #define EXTI_RTSR_TR17_Pos (17U)
<> 144:ef7eb2e8f9f7 5963 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 5964 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 5965 #define EXTI_RTSR_TR19_Pos (19U)
<> 144:ef7eb2e8f9f7 5966 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 5967 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 5968 #define EXTI_RTSR_TR20_Pos (20U)
<> 144:ef7eb2e8f9f7 5969 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 5970 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 5971 #define EXTI_RTSR_TR21_Pos (21U)
<> 144:ef7eb2e8f9f7 5972 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 5973 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 5974 #define EXTI_RTSR_TR22_Pos (22U)
<> 144:ef7eb2e8f9f7 5975 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 5976 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 5977 #define EXTI_RTSR_TR31_Pos (31U)
<> 144:ef7eb2e8f9f7 5978 #define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 5979 #define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
<> 144:ef7eb2e8f9f7 5980
<> 144:ef7eb2e8f9f7 5981 /* References Defines */
<> 144:ef7eb2e8f9f7 5982 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
<> 144:ef7eb2e8f9f7 5983 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
<> 144:ef7eb2e8f9f7 5984 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
<> 144:ef7eb2e8f9f7 5985 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
<> 144:ef7eb2e8f9f7 5986 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
<> 144:ef7eb2e8f9f7 5987 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
<> 144:ef7eb2e8f9f7 5988 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
<> 144:ef7eb2e8f9f7 5989 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
<> 144:ef7eb2e8f9f7 5990 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
<> 144:ef7eb2e8f9f7 5991 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
<> 144:ef7eb2e8f9f7 5992 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
<> 144:ef7eb2e8f9f7 5993 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
<> 144:ef7eb2e8f9f7 5994 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
<> 144:ef7eb2e8f9f7 5995 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
<> 144:ef7eb2e8f9f7 5996 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
<> 144:ef7eb2e8f9f7 5997 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
<> 144:ef7eb2e8f9f7 5998 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
<> 144:ef7eb2e8f9f7 5999 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
<> 144:ef7eb2e8f9f7 6000 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
<> 144:ef7eb2e8f9f7 6001 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
<> 144:ef7eb2e8f9f7 6002 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
<> 144:ef7eb2e8f9f7 6003 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
<> 144:ef7eb2e8f9f7 6004 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31
<> 144:ef7eb2e8f9f7 6005
<> 144:ef7eb2e8f9f7 6006 /******************* Bit definition for EXTI_FTSR register *******************/
<> 144:ef7eb2e8f9f7 6007 #define EXTI_FTSR_TR0_Pos (0U)
<> 144:ef7eb2e8f9f7 6008 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6009 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 6010 #define EXTI_FTSR_TR1_Pos (1U)
<> 144:ef7eb2e8f9f7 6011 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6012 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 6013 #define EXTI_FTSR_TR2_Pos (2U)
<> 144:ef7eb2e8f9f7 6014 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6015 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 6016 #define EXTI_FTSR_TR3_Pos (3U)
<> 144:ef7eb2e8f9f7 6017 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 6018 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 6019 #define EXTI_FTSR_TR4_Pos (4U)
<> 144:ef7eb2e8f9f7 6020 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6021 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 6022 #define EXTI_FTSR_TR5_Pos (5U)
<> 144:ef7eb2e8f9f7 6023 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6024 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 6025 #define EXTI_FTSR_TR6_Pos (6U)
<> 144:ef7eb2e8f9f7 6026 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 6027 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 6028 #define EXTI_FTSR_TR7_Pos (7U)
<> 144:ef7eb2e8f9f7 6029 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 6030 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 6031 #define EXTI_FTSR_TR8_Pos (8U)
<> 144:ef7eb2e8f9f7 6032 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 6033 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 6034 #define EXTI_FTSR_TR9_Pos (9U)
<> 144:ef7eb2e8f9f7 6035 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6036 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 6037 #define EXTI_FTSR_TR10_Pos (10U)
<> 144:ef7eb2e8f9f7 6038 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6039 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 6040 #define EXTI_FTSR_TR11_Pos (11U)
<> 144:ef7eb2e8f9f7 6041 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 6042 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 6043 #define EXTI_FTSR_TR12_Pos (12U)
<> 144:ef7eb2e8f9f7 6044 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6045 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 6046 #define EXTI_FTSR_TR13_Pos (13U)
<> 144:ef7eb2e8f9f7 6047 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6048 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 6049 #define EXTI_FTSR_TR14_Pos (14U)
<> 144:ef7eb2e8f9f7 6050 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 6051 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 6052 #define EXTI_FTSR_TR15_Pos (15U)
<> 144:ef7eb2e8f9f7 6053 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 6054 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 6055 #define EXTI_FTSR_TR16_Pos (16U)
<> 144:ef7eb2e8f9f7 6056 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 6057 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 6058 #define EXTI_FTSR_TR17_Pos (17U)
<> 144:ef7eb2e8f9f7 6059 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 6060 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 6061 #define EXTI_FTSR_TR19_Pos (19U)
<> 144:ef7eb2e8f9f7 6062 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 6063 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 6064 #define EXTI_FTSR_TR20_Pos (20U)
<> 144:ef7eb2e8f9f7 6065 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 6066 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 6067 #define EXTI_FTSR_TR21_Pos (21U)
<> 144:ef7eb2e8f9f7 6068 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 6069 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 6070 #define EXTI_FTSR_TR22_Pos (22U)
<> 144:ef7eb2e8f9f7 6071 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 6072 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 6073 #define EXTI_FTSR_TR31_Pos (31U)
<> 144:ef7eb2e8f9f7 6074 #define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 6075 #define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
<> 144:ef7eb2e8f9f7 6076
<> 144:ef7eb2e8f9f7 6077 /* References Defines */
<> 144:ef7eb2e8f9f7 6078 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
<> 144:ef7eb2e8f9f7 6079 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
<> 144:ef7eb2e8f9f7 6080 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
<> 144:ef7eb2e8f9f7 6081 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
<> 144:ef7eb2e8f9f7 6082 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
<> 144:ef7eb2e8f9f7 6083 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
<> 144:ef7eb2e8f9f7 6084 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
<> 144:ef7eb2e8f9f7 6085 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
<> 144:ef7eb2e8f9f7 6086 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
<> 144:ef7eb2e8f9f7 6087 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
<> 144:ef7eb2e8f9f7 6088 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
<> 144:ef7eb2e8f9f7 6089 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
<> 144:ef7eb2e8f9f7 6090 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
<> 144:ef7eb2e8f9f7 6091 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
<> 144:ef7eb2e8f9f7 6092 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
<> 144:ef7eb2e8f9f7 6093 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
<> 144:ef7eb2e8f9f7 6094 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
<> 144:ef7eb2e8f9f7 6095 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
<> 144:ef7eb2e8f9f7 6096 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
<> 144:ef7eb2e8f9f7 6097 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
<> 144:ef7eb2e8f9f7 6098 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
<> 144:ef7eb2e8f9f7 6099 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
<> 144:ef7eb2e8f9f7 6100 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
<> 144:ef7eb2e8f9f7 6101
<> 144:ef7eb2e8f9f7 6102 /******************* Bit definition for EXTI_SWIER register *******************/
<> 144:ef7eb2e8f9f7 6103 #define EXTI_SWIER_SWIER0_Pos (0U)
<> 144:ef7eb2e8f9f7 6104 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6105 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
<> 144:ef7eb2e8f9f7 6106 #define EXTI_SWIER_SWIER1_Pos (1U)
<> 144:ef7eb2e8f9f7 6107 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6108 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
<> 144:ef7eb2e8f9f7 6109 #define EXTI_SWIER_SWIER2_Pos (2U)
<> 144:ef7eb2e8f9f7 6110 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6111 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
<> 144:ef7eb2e8f9f7 6112 #define EXTI_SWIER_SWIER3_Pos (3U)
<> 144:ef7eb2e8f9f7 6113 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 6114 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
<> 144:ef7eb2e8f9f7 6115 #define EXTI_SWIER_SWIER4_Pos (4U)
<> 144:ef7eb2e8f9f7 6116 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6117 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
<> 144:ef7eb2e8f9f7 6118 #define EXTI_SWIER_SWIER5_Pos (5U)
<> 144:ef7eb2e8f9f7 6119 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6120 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
<> 144:ef7eb2e8f9f7 6121 #define EXTI_SWIER_SWIER6_Pos (6U)
<> 144:ef7eb2e8f9f7 6122 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 6123 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
<> 144:ef7eb2e8f9f7 6124 #define EXTI_SWIER_SWIER7_Pos (7U)
<> 144:ef7eb2e8f9f7 6125 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 6126 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
<> 144:ef7eb2e8f9f7 6127 #define EXTI_SWIER_SWIER8_Pos (8U)
<> 144:ef7eb2e8f9f7 6128 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 6129 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
<> 144:ef7eb2e8f9f7 6130 #define EXTI_SWIER_SWIER9_Pos (9U)
<> 144:ef7eb2e8f9f7 6131 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6132 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
<> 144:ef7eb2e8f9f7 6133 #define EXTI_SWIER_SWIER10_Pos (10U)
<> 144:ef7eb2e8f9f7 6134 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6135 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
<> 144:ef7eb2e8f9f7 6136 #define EXTI_SWIER_SWIER11_Pos (11U)
<> 144:ef7eb2e8f9f7 6137 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 6138 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
<> 144:ef7eb2e8f9f7 6139 #define EXTI_SWIER_SWIER12_Pos (12U)
<> 144:ef7eb2e8f9f7 6140 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6141 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
<> 144:ef7eb2e8f9f7 6142 #define EXTI_SWIER_SWIER13_Pos (13U)
<> 144:ef7eb2e8f9f7 6143 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6144 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
<> 144:ef7eb2e8f9f7 6145 #define EXTI_SWIER_SWIER14_Pos (14U)
<> 144:ef7eb2e8f9f7 6146 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 6147 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
<> 144:ef7eb2e8f9f7 6148 #define EXTI_SWIER_SWIER15_Pos (15U)
<> 144:ef7eb2e8f9f7 6149 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 6150 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
<> 144:ef7eb2e8f9f7 6151 #define EXTI_SWIER_SWIER16_Pos (16U)
<> 144:ef7eb2e8f9f7 6152 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 6153 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
<> 144:ef7eb2e8f9f7 6154 #define EXTI_SWIER_SWIER17_Pos (17U)
<> 144:ef7eb2e8f9f7 6155 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 6156 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
<> 144:ef7eb2e8f9f7 6157 #define EXTI_SWIER_SWIER19_Pos (19U)
<> 144:ef7eb2e8f9f7 6158 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 6159 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
<> 144:ef7eb2e8f9f7 6160 #define EXTI_SWIER_SWIER20_Pos (20U)
<> 144:ef7eb2e8f9f7 6161 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 6162 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
<> 144:ef7eb2e8f9f7 6163 #define EXTI_SWIER_SWIER21_Pos (21U)
<> 144:ef7eb2e8f9f7 6164 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 6165 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
<> 144:ef7eb2e8f9f7 6166 #define EXTI_SWIER_SWIER22_Pos (22U)
<> 144:ef7eb2e8f9f7 6167 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 6168 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
<> 144:ef7eb2e8f9f7 6169 #define EXTI_SWIER_SWIER31_Pos (31U)
<> 144:ef7eb2e8f9f7 6170 #define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 6171 #define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
<> 144:ef7eb2e8f9f7 6172
<> 144:ef7eb2e8f9f7 6173 /* References Defines */
<> 144:ef7eb2e8f9f7 6174 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
<> 144:ef7eb2e8f9f7 6175 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
<> 144:ef7eb2e8f9f7 6176 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
<> 144:ef7eb2e8f9f7 6177 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
<> 144:ef7eb2e8f9f7 6178 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
<> 144:ef7eb2e8f9f7 6179 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
<> 144:ef7eb2e8f9f7 6180 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
<> 144:ef7eb2e8f9f7 6181 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
<> 144:ef7eb2e8f9f7 6182 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
<> 144:ef7eb2e8f9f7 6183 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
<> 144:ef7eb2e8f9f7 6184 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
<> 144:ef7eb2e8f9f7 6185 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
<> 144:ef7eb2e8f9f7 6186 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
<> 144:ef7eb2e8f9f7 6187 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
<> 144:ef7eb2e8f9f7 6188 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
<> 144:ef7eb2e8f9f7 6189 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
<> 144:ef7eb2e8f9f7 6190 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
<> 144:ef7eb2e8f9f7 6191 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
<> 144:ef7eb2e8f9f7 6192 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
<> 144:ef7eb2e8f9f7 6193 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
<> 144:ef7eb2e8f9f7 6194 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
<> 144:ef7eb2e8f9f7 6195 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
<> 144:ef7eb2e8f9f7 6196 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
<> 144:ef7eb2e8f9f7 6197
<> 144:ef7eb2e8f9f7 6198 /****************** Bit definition for EXTI_PR register *********************/
<> 144:ef7eb2e8f9f7 6199 #define EXTI_PR_PR0_Pos (0U)
<> 144:ef7eb2e8f9f7 6200 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6201 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */
<> 144:ef7eb2e8f9f7 6202 #define EXTI_PR_PR1_Pos (1U)
<> 144:ef7eb2e8f9f7 6203 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6204 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */
<> 144:ef7eb2e8f9f7 6205 #define EXTI_PR_PR2_Pos (2U)
<> 144:ef7eb2e8f9f7 6206 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6207 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */
<> 144:ef7eb2e8f9f7 6208 #define EXTI_PR_PR3_Pos (3U)
<> 144:ef7eb2e8f9f7 6209 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 6210 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */
<> 144:ef7eb2e8f9f7 6211 #define EXTI_PR_PR4_Pos (4U)
<> 144:ef7eb2e8f9f7 6212 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6213 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */
<> 144:ef7eb2e8f9f7 6214 #define EXTI_PR_PR5_Pos (5U)
<> 144:ef7eb2e8f9f7 6215 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6216 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */
<> 144:ef7eb2e8f9f7 6217 #define EXTI_PR_PR6_Pos (6U)
<> 144:ef7eb2e8f9f7 6218 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 6219 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */
<> 144:ef7eb2e8f9f7 6220 #define EXTI_PR_PR7_Pos (7U)
<> 144:ef7eb2e8f9f7 6221 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 6222 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */
<> 144:ef7eb2e8f9f7 6223 #define EXTI_PR_PR8_Pos (8U)
<> 144:ef7eb2e8f9f7 6224 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 6225 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */
<> 144:ef7eb2e8f9f7 6226 #define EXTI_PR_PR9_Pos (9U)
<> 144:ef7eb2e8f9f7 6227 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6228 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */
<> 144:ef7eb2e8f9f7 6229 #define EXTI_PR_PR10_Pos (10U)
<> 144:ef7eb2e8f9f7 6230 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6231 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */
<> 144:ef7eb2e8f9f7 6232 #define EXTI_PR_PR11_Pos (11U)
<> 144:ef7eb2e8f9f7 6233 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 6234 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */
<> 144:ef7eb2e8f9f7 6235 #define EXTI_PR_PR12_Pos (12U)
<> 144:ef7eb2e8f9f7 6236 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6237 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */
<> 144:ef7eb2e8f9f7 6238 #define EXTI_PR_PR13_Pos (13U)
<> 144:ef7eb2e8f9f7 6239 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6240 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */
<> 144:ef7eb2e8f9f7 6241 #define EXTI_PR_PR14_Pos (14U)
<> 144:ef7eb2e8f9f7 6242 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 6243 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */
<> 144:ef7eb2e8f9f7 6244 #define EXTI_PR_PR15_Pos (15U)
<> 144:ef7eb2e8f9f7 6245 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 6246 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */
<> 144:ef7eb2e8f9f7 6247 #define EXTI_PR_PR16_Pos (16U)
<> 144:ef7eb2e8f9f7 6248 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 6249 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */
<> 144:ef7eb2e8f9f7 6250 #define EXTI_PR_PR17_Pos (17U)
<> 144:ef7eb2e8f9f7 6251 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 6252 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */
<> 144:ef7eb2e8f9f7 6253 #define EXTI_PR_PR19_Pos (19U)
<> 144:ef7eb2e8f9f7 6254 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 6255 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */
<> 144:ef7eb2e8f9f7 6256 #define EXTI_PR_PR20_Pos (20U)
<> 144:ef7eb2e8f9f7 6257 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 6258 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit 20 */
<> 144:ef7eb2e8f9f7 6259 #define EXTI_PR_PR21_Pos (21U)
<> 144:ef7eb2e8f9f7 6260 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 6261 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */
<> 144:ef7eb2e8f9f7 6262 #define EXTI_PR_PR22_Pos (22U)
<> 144:ef7eb2e8f9f7 6263 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 6264 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */
<> 144:ef7eb2e8f9f7 6265 #define EXTI_PR_PR31_Pos (31U)
<> 144:ef7eb2e8f9f7 6266 #define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 6267 #define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit 31 */
<> 144:ef7eb2e8f9f7 6268
<> 144:ef7eb2e8f9f7 6269 /* References Defines */
<> 144:ef7eb2e8f9f7 6270 #define EXTI_PR_PIF0 EXTI_PR_PR0
<> 144:ef7eb2e8f9f7 6271 #define EXTI_PR_PIF1 EXTI_PR_PR1
<> 144:ef7eb2e8f9f7 6272 #define EXTI_PR_PIF2 EXTI_PR_PR2
<> 144:ef7eb2e8f9f7 6273 #define EXTI_PR_PIF3 EXTI_PR_PR3
<> 144:ef7eb2e8f9f7 6274 #define EXTI_PR_PIF4 EXTI_PR_PR4
<> 144:ef7eb2e8f9f7 6275 #define EXTI_PR_PIF5 EXTI_PR_PR5
<> 144:ef7eb2e8f9f7 6276 #define EXTI_PR_PIF6 EXTI_PR_PR6
<> 144:ef7eb2e8f9f7 6277 #define EXTI_PR_PIF7 EXTI_PR_PR7
<> 144:ef7eb2e8f9f7 6278 #define EXTI_PR_PIF8 EXTI_PR_PR8
<> 144:ef7eb2e8f9f7 6279 #define EXTI_PR_PIF9 EXTI_PR_PR9
<> 144:ef7eb2e8f9f7 6280 #define EXTI_PR_PIF10 EXTI_PR_PR10
<> 144:ef7eb2e8f9f7 6281 #define EXTI_PR_PIF11 EXTI_PR_PR11
<> 144:ef7eb2e8f9f7 6282 #define EXTI_PR_PIF12 EXTI_PR_PR12
<> 144:ef7eb2e8f9f7 6283 #define EXTI_PR_PIF13 EXTI_PR_PR13
<> 144:ef7eb2e8f9f7 6284 #define EXTI_PR_PIF14 EXTI_PR_PR14
<> 144:ef7eb2e8f9f7 6285 #define EXTI_PR_PIF15 EXTI_PR_PR15
<> 144:ef7eb2e8f9f7 6286 #define EXTI_PR_PIF16 EXTI_PR_PR16
<> 144:ef7eb2e8f9f7 6287 #define EXTI_PR_PIF17 EXTI_PR_PR17
<> 144:ef7eb2e8f9f7 6288 #define EXTI_PR_PIF19 EXTI_PR_PR19
<> 144:ef7eb2e8f9f7 6289 #define EXTI_PR_PIF20 EXTI_PR_PR20
<> 144:ef7eb2e8f9f7 6290 #define EXTI_PR_PIF21 EXTI_PR_PR21
<> 144:ef7eb2e8f9f7 6291 #define EXTI_PR_PIF22 EXTI_PR_PR22
<> 144:ef7eb2e8f9f7 6292 #define EXTI_PR_PIF31 EXTI_PR_PR31
<> 144:ef7eb2e8f9f7 6293
<> 144:ef7eb2e8f9f7 6294 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6295 /* */
<> 144:ef7eb2e8f9f7 6296 /* FLASH and Option Bytes Registers */
<> 144:ef7eb2e8f9f7 6297 /* */
<> 144:ef7eb2e8f9f7 6298 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6299
<> 144:ef7eb2e8f9f7 6300 /******************* Bit definition for FLASH_ACR register ******************/
<> 144:ef7eb2e8f9f7 6301 #define FLASH_ACR_LATENCY_Pos (0U)
<> 144:ef7eb2e8f9f7 6302 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6303 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
<> 144:ef7eb2e8f9f7 6304
<> 144:ef7eb2e8f9f7 6305 #define FLASH_ACR_PRFTBE_Pos (4U)
<> 144:ef7eb2e8f9f7 6306 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6307 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
<> 144:ef7eb2e8f9f7 6308 #define FLASH_ACR_PRFTBS_Pos (5U)
<> 144:ef7eb2e8f9f7 6309 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6310 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
<> 144:ef7eb2e8f9f7 6311
<> 144:ef7eb2e8f9f7 6312 /****************** Bit definition for FLASH_KEYR register ******************/
<> 144:ef7eb2e8f9f7 6313 #define FLASH_KEYR_FKEYR_Pos (0U)
<> 144:ef7eb2e8f9f7 6314 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 6315 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
<> 144:ef7eb2e8f9f7 6316
<> 144:ef7eb2e8f9f7 6317 /***************** Bit definition for FLASH_OPTKEYR register ****************/
<> 144:ef7eb2e8f9f7 6318 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
<> 144:ef7eb2e8f9f7 6319 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 6320 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
<> 144:ef7eb2e8f9f7 6321
<> 144:ef7eb2e8f9f7 6322 /****************** FLASH Keys **********************************************/
<> 144:ef7eb2e8f9f7 6323 #define FLASH_KEY1_Pos (0U)
<> 144:ef7eb2e8f9f7 6324 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
<> 144:ef7eb2e8f9f7 6325 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */
<> 144:ef7eb2e8f9f7 6326 #define FLASH_KEY2_Pos (0U)
<> 144:ef7eb2e8f9f7 6327 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
<> 144:ef7eb2e8f9f7 6328 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1
<> 144:ef7eb2e8f9f7 6329 to unlock the write access to the FPEC. */
<> 144:ef7eb2e8f9f7 6330
<> 144:ef7eb2e8f9f7 6331 #define FLASH_OPTKEY1_Pos (0U)
<> 144:ef7eb2e8f9f7 6332 #define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */
<> 144:ef7eb2e8f9f7 6333 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */
<> 144:ef7eb2e8f9f7 6334 #define FLASH_OPTKEY2_Pos (0U)
<> 144:ef7eb2e8f9f7 6335 #define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */
<> 144:ef7eb2e8f9f7 6336 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to
<> 144:ef7eb2e8f9f7 6337 unlock the write access to the option byte block */
<> 144:ef7eb2e8f9f7 6338
<> 144:ef7eb2e8f9f7 6339 /****************** Bit definition for FLASH_SR register *******************/
<> 144:ef7eb2e8f9f7 6340 #define FLASH_SR_BSY_Pos (0U)
<> 144:ef7eb2e8f9f7 6341 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6342 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
<> 144:ef7eb2e8f9f7 6343 #define FLASH_SR_PGERR_Pos (2U)
<> 144:ef7eb2e8f9f7 6344 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6345 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
<> 144:ef7eb2e8f9f7 6346 #define FLASH_SR_WRPRTERR_Pos (4U)
<> 144:ef7eb2e8f9f7 6347 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6348 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
<> 144:ef7eb2e8f9f7 6349 #define FLASH_SR_EOP_Pos (5U)
<> 144:ef7eb2e8f9f7 6350 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6351 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
<> 144:ef7eb2e8f9f7 6352 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
<> 144:ef7eb2e8f9f7 6353
<> 144:ef7eb2e8f9f7 6354 /******************* Bit definition for FLASH_CR register *******************/
<> 144:ef7eb2e8f9f7 6355 #define FLASH_CR_PG_Pos (0U)
<> 144:ef7eb2e8f9f7 6356 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6357 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
<> 144:ef7eb2e8f9f7 6358 #define FLASH_CR_PER_Pos (1U)
<> 144:ef7eb2e8f9f7 6359 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6360 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
<> 144:ef7eb2e8f9f7 6361 #define FLASH_CR_MER_Pos (2U)
<> 144:ef7eb2e8f9f7 6362 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6363 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
<> 144:ef7eb2e8f9f7 6364 #define FLASH_CR_OPTPG_Pos (4U)
<> 144:ef7eb2e8f9f7 6365 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6366 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
<> 144:ef7eb2e8f9f7 6367 #define FLASH_CR_OPTER_Pos (5U)
<> 144:ef7eb2e8f9f7 6368 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6369 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
<> 144:ef7eb2e8f9f7 6370 #define FLASH_CR_STRT_Pos (6U)
<> 144:ef7eb2e8f9f7 6371 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 6372 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
<> 144:ef7eb2e8f9f7 6373 #define FLASH_CR_LOCK_Pos (7U)
<> 144:ef7eb2e8f9f7 6374 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 6375 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
<> 144:ef7eb2e8f9f7 6376 #define FLASH_CR_OPTWRE_Pos (9U)
<> 144:ef7eb2e8f9f7 6377 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6378 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
<> 144:ef7eb2e8f9f7 6379 #define FLASH_CR_ERRIE_Pos (10U)
<> 144:ef7eb2e8f9f7 6380 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6381 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 6382 #define FLASH_CR_EOPIE_Pos (12U)
<> 144:ef7eb2e8f9f7 6383 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6384 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
<> 144:ef7eb2e8f9f7 6385 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
<> 144:ef7eb2e8f9f7 6386 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6387 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */
<> 144:ef7eb2e8f9f7 6388
<> 144:ef7eb2e8f9f7 6389 /******************* Bit definition for FLASH_AR register *******************/
<> 144:ef7eb2e8f9f7 6390 #define FLASH_AR_FAR_Pos (0U)
<> 144:ef7eb2e8f9f7 6391 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 6392 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
<> 144:ef7eb2e8f9f7 6393
<> 144:ef7eb2e8f9f7 6394 /****************** Bit definition for FLASH_OBR register *******************/
<> 144:ef7eb2e8f9f7 6395 #define FLASH_OBR_OPTERR_Pos (0U)
<> 144:ef7eb2e8f9f7 6396 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6397 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
<> 144:ef7eb2e8f9f7 6398 #define FLASH_OBR_RDPRT1_Pos (1U)
<> 144:ef7eb2e8f9f7 6399 #define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6400 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */
<> 144:ef7eb2e8f9f7 6401 #define FLASH_OBR_RDPRT2_Pos (2U)
<> 144:ef7eb2e8f9f7 6402 #define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6403 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */
<> 144:ef7eb2e8f9f7 6404
<> 144:ef7eb2e8f9f7 6405 #define FLASH_OBR_USER_Pos (8U)
<> 144:ef7eb2e8f9f7 6406 #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
<> 144:ef7eb2e8f9f7 6407 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
<> 144:ef7eb2e8f9f7 6408 #define FLASH_OBR_IWDG_SW_Pos (8U)
<> 144:ef7eb2e8f9f7 6409 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 6410 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
<> 144:ef7eb2e8f9f7 6411 #define FLASH_OBR_nRST_STOP_Pos (9U)
<> 144:ef7eb2e8f9f7 6412 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6413 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
<> 144:ef7eb2e8f9f7 6414 #define FLASH_OBR_nRST_STDBY_Pos (10U)
<> 144:ef7eb2e8f9f7 6415 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6416 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
<> 144:ef7eb2e8f9f7 6417 #define FLASH_OBR_nBOOT1_Pos (12U)
<> 144:ef7eb2e8f9f7 6418 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6419 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
<> 144:ef7eb2e8f9f7 6420 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
<> 144:ef7eb2e8f9f7 6421 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6422 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */
<> 144:ef7eb2e8f9f7 6423 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
<> 144:ef7eb2e8f9f7 6424 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 6425 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */
<> 144:ef7eb2e8f9f7 6426 #define FLASH_OBR_DATA0_Pos (16U)
<> 144:ef7eb2e8f9f7 6427 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 6428 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
<> 144:ef7eb2e8f9f7 6429 #define FLASH_OBR_DATA1_Pos (24U)
<> 144:ef7eb2e8f9f7 6430 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 6431 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
<> 144:ef7eb2e8f9f7 6432
<> 144:ef7eb2e8f9f7 6433 /* Old BOOT1 bit definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 6434 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
<> 144:ef7eb2e8f9f7 6435
<> 144:ef7eb2e8f9f7 6436 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 6437 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
<> 144:ef7eb2e8f9f7 6438
<> 144:ef7eb2e8f9f7 6439 /****************** Bit definition for FLASH_WRPR register ******************/
<> 144:ef7eb2e8f9f7 6440 #define FLASH_WRPR_WRP_Pos (0U)
<> 144:ef7eb2e8f9f7 6441 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 6442 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
<> 144:ef7eb2e8f9f7 6443
<> 144:ef7eb2e8f9f7 6444 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 6445
<> 144:ef7eb2e8f9f7 6446 /****************** Bit definition for OB_RDP register **********************/
<> 144:ef7eb2e8f9f7 6447 #define OB_RDP_RDP_Pos (0U)
<> 144:ef7eb2e8f9f7 6448 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 6449 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
<> 144:ef7eb2e8f9f7 6450 #define OB_RDP_nRDP_Pos (8U)
<> 144:ef7eb2e8f9f7 6451 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 6452 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
<> 144:ef7eb2e8f9f7 6453
<> 144:ef7eb2e8f9f7 6454 /****************** Bit definition for OB_USER register *********************/
<> 144:ef7eb2e8f9f7 6455 #define OB_USER_USER_Pos (16U)
<> 144:ef7eb2e8f9f7 6456 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 6457 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
<> 144:ef7eb2e8f9f7 6458 #define OB_USER_nUSER_Pos (24U)
<> 144:ef7eb2e8f9f7 6459 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 6460 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
<> 144:ef7eb2e8f9f7 6461
<> 144:ef7eb2e8f9f7 6462 /****************** Bit definition for OB_WRP0 register *********************/
<> 144:ef7eb2e8f9f7 6463 #define OB_WRP0_WRP0_Pos (0U)
<> 144:ef7eb2e8f9f7 6464 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 6465 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
<> 144:ef7eb2e8f9f7 6466 #define OB_WRP0_nWRP0_Pos (8U)
<> 144:ef7eb2e8f9f7 6467 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 6468 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
<> 144:ef7eb2e8f9f7 6469
<> 144:ef7eb2e8f9f7 6470 /****************** Bit definition for OB_WRP1 register *********************/
<> 144:ef7eb2e8f9f7 6471 #define OB_WRP1_WRP1_Pos (16U)
<> 144:ef7eb2e8f9f7 6472 #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 6473 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
<> 144:ef7eb2e8f9f7 6474 #define OB_WRP1_nWRP1_Pos (24U)
<> 144:ef7eb2e8f9f7 6475 #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 6476 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
<> 144:ef7eb2e8f9f7 6477
<> 144:ef7eb2e8f9f7 6478 /****************** Bit definition for OB_WRP2 register *********************/
<> 144:ef7eb2e8f9f7 6479 #define OB_WRP2_WRP2_Pos (0U)
<> 144:ef7eb2e8f9f7 6480 #define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 6481 #define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
<> 144:ef7eb2e8f9f7 6482 #define OB_WRP2_nWRP2_Pos (8U)
<> 144:ef7eb2e8f9f7 6483 #define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 6484 #define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
<> 144:ef7eb2e8f9f7 6485
<> 144:ef7eb2e8f9f7 6486 /****************** Bit definition for OB_WRP3 register *********************/
<> 144:ef7eb2e8f9f7 6487 #define OB_WRP3_WRP3_Pos (16U)
<> 144:ef7eb2e8f9f7 6488 #define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 6489 #define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
<> 144:ef7eb2e8f9f7 6490 #define OB_WRP3_nWRP3_Pos (24U)
<> 144:ef7eb2e8f9f7 6491 #define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 6492 #define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
<> 144:ef7eb2e8f9f7 6493
<> 144:ef7eb2e8f9f7 6494 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6495 /* */
<> 144:ef7eb2e8f9f7 6496 /* General Purpose IOs (GPIO) */
<> 144:ef7eb2e8f9f7 6497 /* */
<> 144:ef7eb2e8f9f7 6498 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6499 /******************* Bit definition for GPIO_MODER register *****************/
<> 144:ef7eb2e8f9f7 6500 #define GPIO_MODER_MODER0_Pos (0U)
<> 144:ef7eb2e8f9f7 6501 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 6502 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
<> 144:ef7eb2e8f9f7 6503 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6504 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6505 #define GPIO_MODER_MODER1_Pos (2U)
<> 144:ef7eb2e8f9f7 6506 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
<> 144:ef7eb2e8f9f7 6507 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
<> 144:ef7eb2e8f9f7 6508 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6509 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 6510 #define GPIO_MODER_MODER2_Pos (4U)
<> 144:ef7eb2e8f9f7 6511 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
<> 144:ef7eb2e8f9f7 6512 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
<> 144:ef7eb2e8f9f7 6513 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6514 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6515 #define GPIO_MODER_MODER3_Pos (6U)
<> 144:ef7eb2e8f9f7 6516 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
<> 144:ef7eb2e8f9f7 6517 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
<> 144:ef7eb2e8f9f7 6518 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 6519 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 6520 #define GPIO_MODER_MODER4_Pos (8U)
<> 144:ef7eb2e8f9f7 6521 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 6522 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
<> 144:ef7eb2e8f9f7 6523 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 6524 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6525 #define GPIO_MODER_MODER5_Pos (10U)
<> 144:ef7eb2e8f9f7 6526 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
<> 144:ef7eb2e8f9f7 6527 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
<> 144:ef7eb2e8f9f7 6528 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6529 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 6530 #define GPIO_MODER_MODER6_Pos (12U)
<> 144:ef7eb2e8f9f7 6531 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
<> 144:ef7eb2e8f9f7 6532 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
<> 144:ef7eb2e8f9f7 6533 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6534 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6535 #define GPIO_MODER_MODER7_Pos (14U)
<> 144:ef7eb2e8f9f7 6536 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
<> 144:ef7eb2e8f9f7 6537 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
<> 144:ef7eb2e8f9f7 6538 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 6539 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 6540 #define GPIO_MODER_MODER8_Pos (16U)
<> 144:ef7eb2e8f9f7 6541 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
<> 144:ef7eb2e8f9f7 6542 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
<> 144:ef7eb2e8f9f7 6543 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 6544 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 6545 #define GPIO_MODER_MODER9_Pos (18U)
<> 144:ef7eb2e8f9f7 6546 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
<> 144:ef7eb2e8f9f7 6547 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
<> 144:ef7eb2e8f9f7 6548 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 6549 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 6550 #define GPIO_MODER_MODER10_Pos (20U)
<> 144:ef7eb2e8f9f7 6551 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
<> 144:ef7eb2e8f9f7 6552 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
<> 144:ef7eb2e8f9f7 6553 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 6554 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 6555 #define GPIO_MODER_MODER11_Pos (22U)
<> 144:ef7eb2e8f9f7 6556 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
<> 144:ef7eb2e8f9f7 6557 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
<> 144:ef7eb2e8f9f7 6558 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 6559 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 6560 #define GPIO_MODER_MODER12_Pos (24U)
<> 144:ef7eb2e8f9f7 6561 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
<> 144:ef7eb2e8f9f7 6562 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
<> 144:ef7eb2e8f9f7 6563 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 6564 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 6565 #define GPIO_MODER_MODER13_Pos (26U)
<> 144:ef7eb2e8f9f7 6566 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
<> 144:ef7eb2e8f9f7 6567 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
<> 144:ef7eb2e8f9f7 6568 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 6569 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 6570 #define GPIO_MODER_MODER14_Pos (28U)
<> 144:ef7eb2e8f9f7 6571 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
<> 144:ef7eb2e8f9f7 6572 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
<> 144:ef7eb2e8f9f7 6573 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 6574 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 6575 #define GPIO_MODER_MODER15_Pos (30U)
<> 144:ef7eb2e8f9f7 6576 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
<> 144:ef7eb2e8f9f7 6577 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
<> 144:ef7eb2e8f9f7 6578 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 6579 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 6580
<> 144:ef7eb2e8f9f7 6581 /****************** Bit definition for GPIO_OTYPER register *****************/
<> 144:ef7eb2e8f9f7 6582 #define GPIO_OTYPER_OT_0 (0x00000001U)
<> 144:ef7eb2e8f9f7 6583 #define GPIO_OTYPER_OT_1 (0x00000002U)
<> 144:ef7eb2e8f9f7 6584 #define GPIO_OTYPER_OT_2 (0x00000004U)
<> 144:ef7eb2e8f9f7 6585 #define GPIO_OTYPER_OT_3 (0x00000008U)
<> 144:ef7eb2e8f9f7 6586 #define GPIO_OTYPER_OT_4 (0x00000010U)
<> 144:ef7eb2e8f9f7 6587 #define GPIO_OTYPER_OT_5 (0x00000020U)
<> 144:ef7eb2e8f9f7 6588 #define GPIO_OTYPER_OT_6 (0x00000040U)
<> 144:ef7eb2e8f9f7 6589 #define GPIO_OTYPER_OT_7 (0x00000080U)
<> 144:ef7eb2e8f9f7 6590 #define GPIO_OTYPER_OT_8 (0x00000100U)
<> 144:ef7eb2e8f9f7 6591 #define GPIO_OTYPER_OT_9 (0x00000200U)
<> 144:ef7eb2e8f9f7 6592 #define GPIO_OTYPER_OT_10 (0x00000400U)
<> 144:ef7eb2e8f9f7 6593 #define GPIO_OTYPER_OT_11 (0x00000800U)
<> 144:ef7eb2e8f9f7 6594 #define GPIO_OTYPER_OT_12 (0x00001000U)
<> 144:ef7eb2e8f9f7 6595 #define GPIO_OTYPER_OT_13 (0x00002000U)
<> 144:ef7eb2e8f9f7 6596 #define GPIO_OTYPER_OT_14 (0x00004000U)
<> 144:ef7eb2e8f9f7 6597 #define GPIO_OTYPER_OT_15 (0x00008000U)
<> 144:ef7eb2e8f9f7 6598
<> 144:ef7eb2e8f9f7 6599 /**************** Bit definition for GPIO_OSPEEDR register ******************/
<> 144:ef7eb2e8f9f7 6600 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
<> 144:ef7eb2e8f9f7 6601 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 6602 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
<> 144:ef7eb2e8f9f7 6603 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6604 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6605 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
<> 144:ef7eb2e8f9f7 6606 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
<> 144:ef7eb2e8f9f7 6607 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
<> 144:ef7eb2e8f9f7 6608 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6609 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 6610 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
<> 144:ef7eb2e8f9f7 6611 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
<> 144:ef7eb2e8f9f7 6612 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
<> 144:ef7eb2e8f9f7 6613 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6614 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6615 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
<> 144:ef7eb2e8f9f7 6616 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
<> 144:ef7eb2e8f9f7 6617 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
<> 144:ef7eb2e8f9f7 6618 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 6619 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 6620 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
<> 144:ef7eb2e8f9f7 6621 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 6622 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
<> 144:ef7eb2e8f9f7 6623 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 6624 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6625 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
<> 144:ef7eb2e8f9f7 6626 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
<> 144:ef7eb2e8f9f7 6627 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
<> 144:ef7eb2e8f9f7 6628 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6629 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 6630 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
<> 144:ef7eb2e8f9f7 6631 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
<> 144:ef7eb2e8f9f7 6632 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
<> 144:ef7eb2e8f9f7 6633 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6634 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6635 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
<> 144:ef7eb2e8f9f7 6636 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
<> 144:ef7eb2e8f9f7 6637 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
<> 144:ef7eb2e8f9f7 6638 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 6639 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 6640 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
<> 144:ef7eb2e8f9f7 6641 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
<> 144:ef7eb2e8f9f7 6642 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
<> 144:ef7eb2e8f9f7 6643 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 6644 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 6645 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
<> 144:ef7eb2e8f9f7 6646 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
<> 144:ef7eb2e8f9f7 6647 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
<> 144:ef7eb2e8f9f7 6648 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 6649 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 6650 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
<> 144:ef7eb2e8f9f7 6651 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
<> 144:ef7eb2e8f9f7 6652 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
<> 144:ef7eb2e8f9f7 6653 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 6654 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 6655 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
<> 144:ef7eb2e8f9f7 6656 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
<> 144:ef7eb2e8f9f7 6657 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
<> 144:ef7eb2e8f9f7 6658 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 6659 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 6660 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
<> 144:ef7eb2e8f9f7 6661 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
<> 144:ef7eb2e8f9f7 6662 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
<> 144:ef7eb2e8f9f7 6663 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 6664 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 6665 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
<> 144:ef7eb2e8f9f7 6666 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
<> 144:ef7eb2e8f9f7 6667 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
<> 144:ef7eb2e8f9f7 6668 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 6669 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 6670 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
<> 144:ef7eb2e8f9f7 6671 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
<> 144:ef7eb2e8f9f7 6672 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
<> 144:ef7eb2e8f9f7 6673 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 6674 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 6675 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
<> 144:ef7eb2e8f9f7 6676 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
<> 144:ef7eb2e8f9f7 6677 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
<> 144:ef7eb2e8f9f7 6678 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 6679 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 6680
<> 144:ef7eb2e8f9f7 6681 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 6682 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
<> 144:ef7eb2e8f9f7 6683 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
<> 144:ef7eb2e8f9f7 6684 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
<> 144:ef7eb2e8f9f7 6685 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
<> 144:ef7eb2e8f9f7 6686 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
<> 144:ef7eb2e8f9f7 6687 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
<> 144:ef7eb2e8f9f7 6688 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
<> 144:ef7eb2e8f9f7 6689 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
<> 144:ef7eb2e8f9f7 6690 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
<> 144:ef7eb2e8f9f7 6691 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
<> 144:ef7eb2e8f9f7 6692 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
<> 144:ef7eb2e8f9f7 6693 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
<> 144:ef7eb2e8f9f7 6694 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
<> 144:ef7eb2e8f9f7 6695 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
<> 144:ef7eb2e8f9f7 6696 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
<> 144:ef7eb2e8f9f7 6697 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
<> 144:ef7eb2e8f9f7 6698 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
<> 144:ef7eb2e8f9f7 6699 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
<> 144:ef7eb2e8f9f7 6700 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
<> 144:ef7eb2e8f9f7 6701 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
<> 144:ef7eb2e8f9f7 6702 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
<> 144:ef7eb2e8f9f7 6703 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
<> 144:ef7eb2e8f9f7 6704 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
<> 144:ef7eb2e8f9f7 6705 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
<> 144:ef7eb2e8f9f7 6706 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
<> 144:ef7eb2e8f9f7 6707 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
<> 144:ef7eb2e8f9f7 6708 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
<> 144:ef7eb2e8f9f7 6709 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
<> 144:ef7eb2e8f9f7 6710 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
<> 144:ef7eb2e8f9f7 6711 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
<> 144:ef7eb2e8f9f7 6712 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
<> 144:ef7eb2e8f9f7 6713 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
<> 144:ef7eb2e8f9f7 6714 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
<> 144:ef7eb2e8f9f7 6715 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
<> 144:ef7eb2e8f9f7 6716 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
<> 144:ef7eb2e8f9f7 6717 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
<> 144:ef7eb2e8f9f7 6718 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
<> 144:ef7eb2e8f9f7 6719 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
<> 144:ef7eb2e8f9f7 6720 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
<> 144:ef7eb2e8f9f7 6721 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
<> 144:ef7eb2e8f9f7 6722 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
<> 144:ef7eb2e8f9f7 6723 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
<> 144:ef7eb2e8f9f7 6724 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
<> 144:ef7eb2e8f9f7 6725 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
<> 144:ef7eb2e8f9f7 6726 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
<> 144:ef7eb2e8f9f7 6727 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
<> 144:ef7eb2e8f9f7 6728 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
<> 144:ef7eb2e8f9f7 6729 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
<> 144:ef7eb2e8f9f7 6730
<> 144:ef7eb2e8f9f7 6731 /******************* Bit definition for GPIO_PUPDR register ******************/
<> 144:ef7eb2e8f9f7 6732 #define GPIO_PUPDR_PUPDR0_Pos (0U)
<> 144:ef7eb2e8f9f7 6733 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 6734 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
<> 144:ef7eb2e8f9f7 6735 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6736 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6737 #define GPIO_PUPDR_PUPDR1_Pos (2U)
<> 144:ef7eb2e8f9f7 6738 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
<> 144:ef7eb2e8f9f7 6739 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
<> 144:ef7eb2e8f9f7 6740 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6741 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 6742 #define GPIO_PUPDR_PUPDR2_Pos (4U)
<> 144:ef7eb2e8f9f7 6743 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
<> 144:ef7eb2e8f9f7 6744 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
<> 144:ef7eb2e8f9f7 6745 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6746 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6747 #define GPIO_PUPDR_PUPDR3_Pos (6U)
<> 144:ef7eb2e8f9f7 6748 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
<> 144:ef7eb2e8f9f7 6749 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
<> 144:ef7eb2e8f9f7 6750 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 6751 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 6752 #define GPIO_PUPDR_PUPDR4_Pos (8U)
<> 144:ef7eb2e8f9f7 6753 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 6754 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
<> 144:ef7eb2e8f9f7 6755 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 6756 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6757 #define GPIO_PUPDR_PUPDR5_Pos (10U)
<> 144:ef7eb2e8f9f7 6758 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
<> 144:ef7eb2e8f9f7 6759 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
<> 144:ef7eb2e8f9f7 6760 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6761 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 6762 #define GPIO_PUPDR_PUPDR6_Pos (12U)
<> 144:ef7eb2e8f9f7 6763 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
<> 144:ef7eb2e8f9f7 6764 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
<> 144:ef7eb2e8f9f7 6765 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6766 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6767 #define GPIO_PUPDR_PUPDR7_Pos (14U)
<> 144:ef7eb2e8f9f7 6768 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
<> 144:ef7eb2e8f9f7 6769 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
<> 144:ef7eb2e8f9f7 6770 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 6771 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 6772 #define GPIO_PUPDR_PUPDR8_Pos (16U)
<> 144:ef7eb2e8f9f7 6773 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
<> 144:ef7eb2e8f9f7 6774 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
<> 144:ef7eb2e8f9f7 6775 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 6776 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 6777 #define GPIO_PUPDR_PUPDR9_Pos (18U)
<> 144:ef7eb2e8f9f7 6778 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
<> 144:ef7eb2e8f9f7 6779 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
<> 144:ef7eb2e8f9f7 6780 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 6781 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 6782 #define GPIO_PUPDR_PUPDR10_Pos (20U)
<> 144:ef7eb2e8f9f7 6783 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
<> 144:ef7eb2e8f9f7 6784 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
<> 144:ef7eb2e8f9f7 6785 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 6786 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 6787 #define GPIO_PUPDR_PUPDR11_Pos (22U)
<> 144:ef7eb2e8f9f7 6788 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
<> 144:ef7eb2e8f9f7 6789 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
<> 144:ef7eb2e8f9f7 6790 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 6791 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 6792 #define GPIO_PUPDR_PUPDR12_Pos (24U)
<> 144:ef7eb2e8f9f7 6793 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
<> 144:ef7eb2e8f9f7 6794 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
<> 144:ef7eb2e8f9f7 6795 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 6796 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 6797 #define GPIO_PUPDR_PUPDR13_Pos (26U)
<> 144:ef7eb2e8f9f7 6798 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
<> 144:ef7eb2e8f9f7 6799 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
<> 144:ef7eb2e8f9f7 6800 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 6801 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 6802 #define GPIO_PUPDR_PUPDR14_Pos (28U)
<> 144:ef7eb2e8f9f7 6803 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
<> 144:ef7eb2e8f9f7 6804 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
<> 144:ef7eb2e8f9f7 6805 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 6806 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 6807 #define GPIO_PUPDR_PUPDR15_Pos (30U)
<> 144:ef7eb2e8f9f7 6808 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
<> 144:ef7eb2e8f9f7 6809 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
<> 144:ef7eb2e8f9f7 6810 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 6811 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 6812
<> 144:ef7eb2e8f9f7 6813 /******************* Bit definition for GPIO_IDR register *******************/
<> 144:ef7eb2e8f9f7 6814 #define GPIO_IDR_0 (0x00000001U)
<> 144:ef7eb2e8f9f7 6815 #define GPIO_IDR_1 (0x00000002U)
<> 144:ef7eb2e8f9f7 6816 #define GPIO_IDR_2 (0x00000004U)
<> 144:ef7eb2e8f9f7 6817 #define GPIO_IDR_3 (0x00000008U)
<> 144:ef7eb2e8f9f7 6818 #define GPIO_IDR_4 (0x00000010U)
<> 144:ef7eb2e8f9f7 6819 #define GPIO_IDR_5 (0x00000020U)
<> 144:ef7eb2e8f9f7 6820 #define GPIO_IDR_6 (0x00000040U)
<> 144:ef7eb2e8f9f7 6821 #define GPIO_IDR_7 (0x00000080U)
<> 144:ef7eb2e8f9f7 6822 #define GPIO_IDR_8 (0x00000100U)
<> 144:ef7eb2e8f9f7 6823 #define GPIO_IDR_9 (0x00000200U)
<> 144:ef7eb2e8f9f7 6824 #define GPIO_IDR_10 (0x00000400U)
<> 144:ef7eb2e8f9f7 6825 #define GPIO_IDR_11 (0x00000800U)
<> 144:ef7eb2e8f9f7 6826 #define GPIO_IDR_12 (0x00001000U)
<> 144:ef7eb2e8f9f7 6827 #define GPIO_IDR_13 (0x00002000U)
<> 144:ef7eb2e8f9f7 6828 #define GPIO_IDR_14 (0x00004000U)
<> 144:ef7eb2e8f9f7 6829 #define GPIO_IDR_15 (0x00008000U)
<> 144:ef7eb2e8f9f7 6830
<> 144:ef7eb2e8f9f7 6831 /****************** Bit definition for GPIO_ODR register ********************/
<> 144:ef7eb2e8f9f7 6832 #define GPIO_ODR_0 (0x00000001U)
<> 144:ef7eb2e8f9f7 6833 #define GPIO_ODR_1 (0x00000002U)
<> 144:ef7eb2e8f9f7 6834 #define GPIO_ODR_2 (0x00000004U)
<> 144:ef7eb2e8f9f7 6835 #define GPIO_ODR_3 (0x00000008U)
<> 144:ef7eb2e8f9f7 6836 #define GPIO_ODR_4 (0x00000010U)
<> 144:ef7eb2e8f9f7 6837 #define GPIO_ODR_5 (0x00000020U)
<> 144:ef7eb2e8f9f7 6838 #define GPIO_ODR_6 (0x00000040U)
<> 144:ef7eb2e8f9f7 6839 #define GPIO_ODR_7 (0x00000080U)
<> 144:ef7eb2e8f9f7 6840 #define GPIO_ODR_8 (0x00000100U)
<> 144:ef7eb2e8f9f7 6841 #define GPIO_ODR_9 (0x00000200U)
<> 144:ef7eb2e8f9f7 6842 #define GPIO_ODR_10 (0x00000400U)
<> 144:ef7eb2e8f9f7 6843 #define GPIO_ODR_11 (0x00000800U)
<> 144:ef7eb2e8f9f7 6844 #define GPIO_ODR_12 (0x00001000U)
<> 144:ef7eb2e8f9f7 6845 #define GPIO_ODR_13 (0x00002000U)
<> 144:ef7eb2e8f9f7 6846 #define GPIO_ODR_14 (0x00004000U)
<> 144:ef7eb2e8f9f7 6847 #define GPIO_ODR_15 (0x00008000U)
<> 144:ef7eb2e8f9f7 6848
<> 144:ef7eb2e8f9f7 6849 /****************** Bit definition for GPIO_BSRR register ********************/
<> 144:ef7eb2e8f9f7 6850 #define GPIO_BSRR_BS_0 (0x00000001U)
<> 144:ef7eb2e8f9f7 6851 #define GPIO_BSRR_BS_1 (0x00000002U)
<> 144:ef7eb2e8f9f7 6852 #define GPIO_BSRR_BS_2 (0x00000004U)
<> 144:ef7eb2e8f9f7 6853 #define GPIO_BSRR_BS_3 (0x00000008U)
<> 144:ef7eb2e8f9f7 6854 #define GPIO_BSRR_BS_4 (0x00000010U)
<> 144:ef7eb2e8f9f7 6855 #define GPIO_BSRR_BS_5 (0x00000020U)
<> 144:ef7eb2e8f9f7 6856 #define GPIO_BSRR_BS_6 (0x00000040U)
<> 144:ef7eb2e8f9f7 6857 #define GPIO_BSRR_BS_7 (0x00000080U)
<> 144:ef7eb2e8f9f7 6858 #define GPIO_BSRR_BS_8 (0x00000100U)
<> 144:ef7eb2e8f9f7 6859 #define GPIO_BSRR_BS_9 (0x00000200U)
<> 144:ef7eb2e8f9f7 6860 #define GPIO_BSRR_BS_10 (0x00000400U)
<> 144:ef7eb2e8f9f7 6861 #define GPIO_BSRR_BS_11 (0x00000800U)
<> 144:ef7eb2e8f9f7 6862 #define GPIO_BSRR_BS_12 (0x00001000U)
<> 144:ef7eb2e8f9f7 6863 #define GPIO_BSRR_BS_13 (0x00002000U)
<> 144:ef7eb2e8f9f7 6864 #define GPIO_BSRR_BS_14 (0x00004000U)
<> 144:ef7eb2e8f9f7 6865 #define GPIO_BSRR_BS_15 (0x00008000U)
<> 144:ef7eb2e8f9f7 6866 #define GPIO_BSRR_BR_0 (0x00010000U)
<> 144:ef7eb2e8f9f7 6867 #define GPIO_BSRR_BR_1 (0x00020000U)
<> 144:ef7eb2e8f9f7 6868 #define GPIO_BSRR_BR_2 (0x00040000U)
<> 144:ef7eb2e8f9f7 6869 #define GPIO_BSRR_BR_3 (0x00080000U)
<> 144:ef7eb2e8f9f7 6870 #define GPIO_BSRR_BR_4 (0x00100000U)
<> 144:ef7eb2e8f9f7 6871 #define GPIO_BSRR_BR_5 (0x00200000U)
<> 144:ef7eb2e8f9f7 6872 #define GPIO_BSRR_BR_6 (0x00400000U)
<> 144:ef7eb2e8f9f7 6873 #define GPIO_BSRR_BR_7 (0x00800000U)
<> 144:ef7eb2e8f9f7 6874 #define GPIO_BSRR_BR_8 (0x01000000U)
<> 144:ef7eb2e8f9f7 6875 #define GPIO_BSRR_BR_9 (0x02000000U)
<> 144:ef7eb2e8f9f7 6876 #define GPIO_BSRR_BR_10 (0x04000000U)
<> 144:ef7eb2e8f9f7 6877 #define GPIO_BSRR_BR_11 (0x08000000U)
<> 144:ef7eb2e8f9f7 6878 #define GPIO_BSRR_BR_12 (0x10000000U)
<> 144:ef7eb2e8f9f7 6879 #define GPIO_BSRR_BR_13 (0x20000000U)
<> 144:ef7eb2e8f9f7 6880 #define GPIO_BSRR_BR_14 (0x40000000U)
<> 144:ef7eb2e8f9f7 6881 #define GPIO_BSRR_BR_15 (0x80000000U)
<> 144:ef7eb2e8f9f7 6882
<> 144:ef7eb2e8f9f7 6883 /****************** Bit definition for GPIO_LCKR register ********************/
<> 144:ef7eb2e8f9f7 6884 #define GPIO_LCKR_LCK0_Pos (0U)
<> 144:ef7eb2e8f9f7 6885 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6886 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
<> 144:ef7eb2e8f9f7 6887 #define GPIO_LCKR_LCK1_Pos (1U)
<> 144:ef7eb2e8f9f7 6888 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6889 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
<> 144:ef7eb2e8f9f7 6890 #define GPIO_LCKR_LCK2_Pos (2U)
<> 144:ef7eb2e8f9f7 6891 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6892 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
<> 144:ef7eb2e8f9f7 6893 #define GPIO_LCKR_LCK3_Pos (3U)
<> 144:ef7eb2e8f9f7 6894 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 6895 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
<> 144:ef7eb2e8f9f7 6896 #define GPIO_LCKR_LCK4_Pos (4U)
<> 144:ef7eb2e8f9f7 6897 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 6898 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
<> 144:ef7eb2e8f9f7 6899 #define GPIO_LCKR_LCK5_Pos (5U)
<> 144:ef7eb2e8f9f7 6900 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 6901 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
<> 144:ef7eb2e8f9f7 6902 #define GPIO_LCKR_LCK6_Pos (6U)
<> 144:ef7eb2e8f9f7 6903 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 6904 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
<> 144:ef7eb2e8f9f7 6905 #define GPIO_LCKR_LCK7_Pos (7U)
<> 144:ef7eb2e8f9f7 6906 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 6907 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
<> 144:ef7eb2e8f9f7 6908 #define GPIO_LCKR_LCK8_Pos (8U)
<> 144:ef7eb2e8f9f7 6909 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 6910 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
<> 144:ef7eb2e8f9f7 6911 #define GPIO_LCKR_LCK9_Pos (9U)
<> 144:ef7eb2e8f9f7 6912 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 6913 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
<> 144:ef7eb2e8f9f7 6914 #define GPIO_LCKR_LCK10_Pos (10U)
<> 144:ef7eb2e8f9f7 6915 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 6916 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
<> 144:ef7eb2e8f9f7 6917 #define GPIO_LCKR_LCK11_Pos (11U)
<> 144:ef7eb2e8f9f7 6918 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 6919 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
<> 144:ef7eb2e8f9f7 6920 #define GPIO_LCKR_LCK12_Pos (12U)
<> 144:ef7eb2e8f9f7 6921 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 6922 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
<> 144:ef7eb2e8f9f7 6923 #define GPIO_LCKR_LCK13_Pos (13U)
<> 144:ef7eb2e8f9f7 6924 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 6925 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
<> 144:ef7eb2e8f9f7 6926 #define GPIO_LCKR_LCK14_Pos (14U)
<> 144:ef7eb2e8f9f7 6927 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 6928 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
<> 144:ef7eb2e8f9f7 6929 #define GPIO_LCKR_LCK15_Pos (15U)
<> 144:ef7eb2e8f9f7 6930 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 6931 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
<> 144:ef7eb2e8f9f7 6932 #define GPIO_LCKR_LCKK_Pos (16U)
<> 144:ef7eb2e8f9f7 6933 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 6934 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
<> 144:ef7eb2e8f9f7 6935
<> 144:ef7eb2e8f9f7 6936 /****************** Bit definition for GPIO_AFRL register ********************/
<> 144:ef7eb2e8f9f7 6937 #define GPIO_AFRL_AFRL0_Pos (0U)
<> 144:ef7eb2e8f9f7 6938 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 6939 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
<> 144:ef7eb2e8f9f7 6940 #define GPIO_AFRL_AFRL1_Pos (4U)
<> 144:ef7eb2e8f9f7 6941 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 6942 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
<> 144:ef7eb2e8f9f7 6943 #define GPIO_AFRL_AFRL2_Pos (8U)
<> 144:ef7eb2e8f9f7 6944 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 6945 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
<> 144:ef7eb2e8f9f7 6946 #define GPIO_AFRL_AFRL3_Pos (12U)
<> 144:ef7eb2e8f9f7 6947 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
<> 144:ef7eb2e8f9f7 6948 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
<> 144:ef7eb2e8f9f7 6949 #define GPIO_AFRL_AFRL4_Pos (16U)
<> 144:ef7eb2e8f9f7 6950 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
<> 144:ef7eb2e8f9f7 6951 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
<> 144:ef7eb2e8f9f7 6952 #define GPIO_AFRL_AFRL5_Pos (20U)
<> 144:ef7eb2e8f9f7 6953 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
<> 144:ef7eb2e8f9f7 6954 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
<> 144:ef7eb2e8f9f7 6955 #define GPIO_AFRL_AFRL6_Pos (24U)
<> 144:ef7eb2e8f9f7 6956 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
<> 144:ef7eb2e8f9f7 6957 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
<> 144:ef7eb2e8f9f7 6958 #define GPIO_AFRL_AFRL7_Pos (28U)
<> 144:ef7eb2e8f9f7 6959 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
<> 144:ef7eb2e8f9f7 6960 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
<> 144:ef7eb2e8f9f7 6961
<> 144:ef7eb2e8f9f7 6962 /****************** Bit definition for GPIO_AFRH register ********************/
<> 144:ef7eb2e8f9f7 6963 #define GPIO_AFRH_AFRH0_Pos (0U)
<> 144:ef7eb2e8f9f7 6964 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 6965 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
<> 144:ef7eb2e8f9f7 6966 #define GPIO_AFRH_AFRH1_Pos (4U)
<> 144:ef7eb2e8f9f7 6967 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 6968 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
<> 144:ef7eb2e8f9f7 6969 #define GPIO_AFRH_AFRH2_Pos (8U)
<> 144:ef7eb2e8f9f7 6970 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 6971 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
<> 144:ef7eb2e8f9f7 6972 #define GPIO_AFRH_AFRH3_Pos (12U)
<> 144:ef7eb2e8f9f7 6973 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
<> 144:ef7eb2e8f9f7 6974 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
<> 144:ef7eb2e8f9f7 6975 #define GPIO_AFRH_AFRH4_Pos (16U)
<> 144:ef7eb2e8f9f7 6976 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
<> 144:ef7eb2e8f9f7 6977 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
<> 144:ef7eb2e8f9f7 6978 #define GPIO_AFRH_AFRH5_Pos (20U)
<> 144:ef7eb2e8f9f7 6979 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
<> 144:ef7eb2e8f9f7 6980 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
<> 144:ef7eb2e8f9f7 6981 #define GPIO_AFRH_AFRH6_Pos (24U)
<> 144:ef7eb2e8f9f7 6982 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
<> 144:ef7eb2e8f9f7 6983 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
<> 144:ef7eb2e8f9f7 6984 #define GPIO_AFRH_AFRH7_Pos (28U)
<> 144:ef7eb2e8f9f7 6985 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
<> 144:ef7eb2e8f9f7 6986 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
<> 144:ef7eb2e8f9f7 6987
<> 144:ef7eb2e8f9f7 6988 /****************** Bit definition for GPIO_BRR register *********************/
<> 144:ef7eb2e8f9f7 6989 #define GPIO_BRR_BR_0 (0x00000001U)
<> 144:ef7eb2e8f9f7 6990 #define GPIO_BRR_BR_1 (0x00000002U)
<> 144:ef7eb2e8f9f7 6991 #define GPIO_BRR_BR_2 (0x00000004U)
<> 144:ef7eb2e8f9f7 6992 #define GPIO_BRR_BR_3 (0x00000008U)
<> 144:ef7eb2e8f9f7 6993 #define GPIO_BRR_BR_4 (0x00000010U)
<> 144:ef7eb2e8f9f7 6994 #define GPIO_BRR_BR_5 (0x00000020U)
<> 144:ef7eb2e8f9f7 6995 #define GPIO_BRR_BR_6 (0x00000040U)
<> 144:ef7eb2e8f9f7 6996 #define GPIO_BRR_BR_7 (0x00000080U)
<> 144:ef7eb2e8f9f7 6997 #define GPIO_BRR_BR_8 (0x00000100U)
<> 144:ef7eb2e8f9f7 6998 #define GPIO_BRR_BR_9 (0x00000200U)
<> 144:ef7eb2e8f9f7 6999 #define GPIO_BRR_BR_10 (0x00000400U)
<> 144:ef7eb2e8f9f7 7000 #define GPIO_BRR_BR_11 (0x00000800U)
<> 144:ef7eb2e8f9f7 7001 #define GPIO_BRR_BR_12 (0x00001000U)
<> 144:ef7eb2e8f9f7 7002 #define GPIO_BRR_BR_13 (0x00002000U)
<> 144:ef7eb2e8f9f7 7003 #define GPIO_BRR_BR_14 (0x00004000U)
<> 144:ef7eb2e8f9f7 7004 #define GPIO_BRR_BR_15 (0x00008000U)
<> 144:ef7eb2e8f9f7 7005
<> 144:ef7eb2e8f9f7 7006 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7007 /* */
<> 144:ef7eb2e8f9f7 7008 /* Inter-integrated Circuit Interface (I2C) */
<> 144:ef7eb2e8f9f7 7009 /* */
<> 144:ef7eb2e8f9f7 7010 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7011
<> 144:ef7eb2e8f9f7 7012 /******************* Bit definition for I2C_CR1 register *******************/
<> 144:ef7eb2e8f9f7 7013 #define I2C_CR1_PE_Pos (0U)
<> 144:ef7eb2e8f9f7 7014 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7015 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
<> 144:ef7eb2e8f9f7 7016 #define I2C_CR1_TXIE_Pos (1U)
<> 144:ef7eb2e8f9f7 7017 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7018 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
<> 144:ef7eb2e8f9f7 7019 #define I2C_CR1_RXIE_Pos (2U)
<> 144:ef7eb2e8f9f7 7020 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7021 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
<> 144:ef7eb2e8f9f7 7022 #define I2C_CR1_ADDRIE_Pos (3U)
<> 144:ef7eb2e8f9f7 7023 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7024 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
<> 144:ef7eb2e8f9f7 7025 #define I2C_CR1_NACKIE_Pos (4U)
<> 144:ef7eb2e8f9f7 7026 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7027 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
<> 144:ef7eb2e8f9f7 7028 #define I2C_CR1_STOPIE_Pos (5U)
<> 144:ef7eb2e8f9f7 7029 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7030 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
<> 144:ef7eb2e8f9f7 7031 #define I2C_CR1_TCIE_Pos (6U)
<> 144:ef7eb2e8f9f7 7032 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 7033 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 144:ef7eb2e8f9f7 7034 #define I2C_CR1_ERRIE_Pos (7U)
<> 144:ef7eb2e8f9f7 7035 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 7036 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
<> 144:ef7eb2e8f9f7 7037 #define I2C_CR1_DNF_Pos (8U)
<> 144:ef7eb2e8f9f7 7038 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 7039 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
<> 144:ef7eb2e8f9f7 7040 #define I2C_CR1_ANFOFF_Pos (12U)
<> 144:ef7eb2e8f9f7 7041 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7042 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
<> 144:ef7eb2e8f9f7 7043 #define I2C_CR1_SWRST_Pos (13U)
<> 144:ef7eb2e8f9f7 7044 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 7045 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
<> 144:ef7eb2e8f9f7 7046 #define I2C_CR1_TXDMAEN_Pos (14U)
<> 144:ef7eb2e8f9f7 7047 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7048 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
<> 144:ef7eb2e8f9f7 7049 #define I2C_CR1_RXDMAEN_Pos (15U)
<> 144:ef7eb2e8f9f7 7050 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7051 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
<> 144:ef7eb2e8f9f7 7052 #define I2C_CR1_SBC_Pos (16U)
<> 144:ef7eb2e8f9f7 7053 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 7054 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
<> 144:ef7eb2e8f9f7 7055 #define I2C_CR1_NOSTRETCH_Pos (17U)
<> 144:ef7eb2e8f9f7 7056 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7057 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
<> 144:ef7eb2e8f9f7 7058 #define I2C_CR1_WUPEN_Pos (18U)
<> 144:ef7eb2e8f9f7 7059 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7060 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
<> 144:ef7eb2e8f9f7 7061 #define I2C_CR1_GCEN_Pos (19U)
<> 144:ef7eb2e8f9f7 7062 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 7063 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
<> 144:ef7eb2e8f9f7 7064 #define I2C_CR1_SMBHEN_Pos (20U)
<> 144:ef7eb2e8f9f7 7065 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 7066 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
<> 144:ef7eb2e8f9f7 7067 #define I2C_CR1_SMBDEN_Pos (21U)
<> 144:ef7eb2e8f9f7 7068 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 7069 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
<> 144:ef7eb2e8f9f7 7070 #define I2C_CR1_ALERTEN_Pos (22U)
<> 144:ef7eb2e8f9f7 7071 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 7072 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
<> 144:ef7eb2e8f9f7 7073 #define I2C_CR1_PECEN_Pos (23U)
<> 144:ef7eb2e8f9f7 7074 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 7075 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
<> 144:ef7eb2e8f9f7 7076
<> 144:ef7eb2e8f9f7 7077 /****************** Bit definition for I2C_CR2 register ********************/
<> 144:ef7eb2e8f9f7 7078 #define I2C_CR2_SADD_Pos (0U)
<> 144:ef7eb2e8f9f7 7079 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
<> 144:ef7eb2e8f9f7 7080 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
<> 144:ef7eb2e8f9f7 7081 #define I2C_CR2_RD_WRN_Pos (10U)
<> 144:ef7eb2e8f9f7 7082 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7083 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
<> 144:ef7eb2e8f9f7 7084 #define I2C_CR2_ADD10_Pos (11U)
<> 144:ef7eb2e8f9f7 7085 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7086 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
<> 144:ef7eb2e8f9f7 7087 #define I2C_CR2_HEAD10R_Pos (12U)
<> 144:ef7eb2e8f9f7 7088 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7089 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
<> 144:ef7eb2e8f9f7 7090 #define I2C_CR2_START_Pos (13U)
<> 144:ef7eb2e8f9f7 7091 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 7092 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
<> 144:ef7eb2e8f9f7 7093 #define I2C_CR2_STOP_Pos (14U)
<> 144:ef7eb2e8f9f7 7094 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7095 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
<> 144:ef7eb2e8f9f7 7096 #define I2C_CR2_NACK_Pos (15U)
<> 144:ef7eb2e8f9f7 7097 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7098 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
<> 144:ef7eb2e8f9f7 7099 #define I2C_CR2_NBYTES_Pos (16U)
<> 144:ef7eb2e8f9f7 7100 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
<> 144:ef7eb2e8f9f7 7101 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
<> 144:ef7eb2e8f9f7 7102 #define I2C_CR2_RELOAD_Pos (24U)
<> 144:ef7eb2e8f9f7 7103 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 7104 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
<> 144:ef7eb2e8f9f7 7105 #define I2C_CR2_AUTOEND_Pos (25U)
<> 144:ef7eb2e8f9f7 7106 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 7107 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
<> 144:ef7eb2e8f9f7 7108 #define I2C_CR2_PECBYTE_Pos (26U)
<> 144:ef7eb2e8f9f7 7109 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 7110 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
<> 144:ef7eb2e8f9f7 7111
<> 144:ef7eb2e8f9f7 7112 /******************* Bit definition for I2C_OAR1 register ******************/
<> 144:ef7eb2e8f9f7 7113 #define I2C_OAR1_OA1_Pos (0U)
<> 144:ef7eb2e8f9f7 7114 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
<> 144:ef7eb2e8f9f7 7115 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
<> 144:ef7eb2e8f9f7 7116 #define I2C_OAR1_OA1MODE_Pos (10U)
<> 144:ef7eb2e8f9f7 7117 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7118 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
<> 144:ef7eb2e8f9f7 7119 #define I2C_OAR1_OA1EN_Pos (15U)
<> 144:ef7eb2e8f9f7 7120 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7121 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
<> 144:ef7eb2e8f9f7 7122
<> 144:ef7eb2e8f9f7 7123 /******************* Bit definition for I2C_OAR2 register ******************/
<> 144:ef7eb2e8f9f7 7124 #define I2C_OAR2_OA2_Pos (1U)
<> 144:ef7eb2e8f9f7 7125 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
<> 144:ef7eb2e8f9f7 7126 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
<> 144:ef7eb2e8f9f7 7127 #define I2C_OAR2_OA2MSK_Pos (8U)
<> 144:ef7eb2e8f9f7 7128 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
<> 144:ef7eb2e8f9f7 7129 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
<> 144:ef7eb2e8f9f7 7130 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
<> 144:ef7eb2e8f9f7 7131 #define I2C_OAR2_OA2MASK01_Pos (8U)
<> 144:ef7eb2e8f9f7 7132 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7133 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
<> 144:ef7eb2e8f9f7 7134 #define I2C_OAR2_OA2MASK02_Pos (9U)
<> 144:ef7eb2e8f9f7 7135 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7136 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
<> 144:ef7eb2e8f9f7 7137 #define I2C_OAR2_OA2MASK03_Pos (8U)
<> 144:ef7eb2e8f9f7 7138 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 7139 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
<> 144:ef7eb2e8f9f7 7140 #define I2C_OAR2_OA2MASK04_Pos (10U)
<> 144:ef7eb2e8f9f7 7141 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7142 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
<> 144:ef7eb2e8f9f7 7143 #define I2C_OAR2_OA2MASK05_Pos (8U)
<> 144:ef7eb2e8f9f7 7144 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
<> 144:ef7eb2e8f9f7 7145 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
<> 144:ef7eb2e8f9f7 7146 #define I2C_OAR2_OA2MASK06_Pos (9U)
<> 144:ef7eb2e8f9f7 7147 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
<> 144:ef7eb2e8f9f7 7148 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
<> 144:ef7eb2e8f9f7 7149 #define I2C_OAR2_OA2MASK07_Pos (8U)
<> 144:ef7eb2e8f9f7 7150 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
<> 144:ef7eb2e8f9f7 7151 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
<> 144:ef7eb2e8f9f7 7152 #define I2C_OAR2_OA2EN_Pos (15U)
<> 144:ef7eb2e8f9f7 7153 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7154 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
<> 144:ef7eb2e8f9f7 7155
<> 144:ef7eb2e8f9f7 7156 /******************* Bit definition for I2C_TIMINGR register ****************/
<> 144:ef7eb2e8f9f7 7157 #define I2C_TIMINGR_SCLL_Pos (0U)
<> 144:ef7eb2e8f9f7 7158 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 7159 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
<> 144:ef7eb2e8f9f7 7160 #define I2C_TIMINGR_SCLH_Pos (8U)
<> 144:ef7eb2e8f9f7 7161 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 7162 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
<> 144:ef7eb2e8f9f7 7163 #define I2C_TIMINGR_SDADEL_Pos (16U)
<> 144:ef7eb2e8f9f7 7164 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
<> 144:ef7eb2e8f9f7 7165 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
<> 144:ef7eb2e8f9f7 7166 #define I2C_TIMINGR_SCLDEL_Pos (20U)
<> 144:ef7eb2e8f9f7 7167 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
<> 144:ef7eb2e8f9f7 7168 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
<> 144:ef7eb2e8f9f7 7169 #define I2C_TIMINGR_PRESC_Pos (28U)
<> 144:ef7eb2e8f9f7 7170 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
<> 144:ef7eb2e8f9f7 7171 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
<> 144:ef7eb2e8f9f7 7172
<> 144:ef7eb2e8f9f7 7173 /******************* Bit definition for I2C_TIMEOUTR register ****************/
<> 144:ef7eb2e8f9f7 7174 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
<> 144:ef7eb2e8f9f7 7175 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 7176 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
<> 144:ef7eb2e8f9f7 7177 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
<> 144:ef7eb2e8f9f7 7178 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7179 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
<> 144:ef7eb2e8f9f7 7180 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
<> 144:ef7eb2e8f9f7 7181 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7182 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
<> 144:ef7eb2e8f9f7 7183 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
<> 144:ef7eb2e8f9f7 7184 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
<> 144:ef7eb2e8f9f7 7185 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
<> 144:ef7eb2e8f9f7 7186 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
<> 144:ef7eb2e8f9f7 7187 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 7188 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
<> 144:ef7eb2e8f9f7 7189
<> 144:ef7eb2e8f9f7 7190 /****************** Bit definition for I2C_ISR register ********************/
<> 144:ef7eb2e8f9f7 7191 #define I2C_ISR_TXE_Pos (0U)
<> 144:ef7eb2e8f9f7 7192 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7193 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
<> 144:ef7eb2e8f9f7 7194 #define I2C_ISR_TXIS_Pos (1U)
<> 144:ef7eb2e8f9f7 7195 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7196 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
<> 144:ef7eb2e8f9f7 7197 #define I2C_ISR_RXNE_Pos (2U)
<> 144:ef7eb2e8f9f7 7198 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7199 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
<> 144:ef7eb2e8f9f7 7200 #define I2C_ISR_ADDR_Pos (3U)
<> 144:ef7eb2e8f9f7 7201 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7202 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
<> 144:ef7eb2e8f9f7 7203 #define I2C_ISR_NACKF_Pos (4U)
<> 144:ef7eb2e8f9f7 7204 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7205 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
<> 144:ef7eb2e8f9f7 7206 #define I2C_ISR_STOPF_Pos (5U)
<> 144:ef7eb2e8f9f7 7207 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7208 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
<> 144:ef7eb2e8f9f7 7209 #define I2C_ISR_TC_Pos (6U)
<> 144:ef7eb2e8f9f7 7210 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 7211 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
<> 144:ef7eb2e8f9f7 7212 #define I2C_ISR_TCR_Pos (7U)
<> 144:ef7eb2e8f9f7 7213 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 7214 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
<> 144:ef7eb2e8f9f7 7215 #define I2C_ISR_BERR_Pos (8U)
<> 144:ef7eb2e8f9f7 7216 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7217 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
<> 144:ef7eb2e8f9f7 7218 #define I2C_ISR_ARLO_Pos (9U)
<> 144:ef7eb2e8f9f7 7219 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7220 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
<> 144:ef7eb2e8f9f7 7221 #define I2C_ISR_OVR_Pos (10U)
<> 144:ef7eb2e8f9f7 7222 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7223 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
<> 144:ef7eb2e8f9f7 7224 #define I2C_ISR_PECERR_Pos (11U)
<> 144:ef7eb2e8f9f7 7225 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7226 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
<> 144:ef7eb2e8f9f7 7227 #define I2C_ISR_TIMEOUT_Pos (12U)
<> 144:ef7eb2e8f9f7 7228 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7229 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
<> 144:ef7eb2e8f9f7 7230 #define I2C_ISR_ALERT_Pos (13U)
<> 144:ef7eb2e8f9f7 7231 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 7232 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
<> 144:ef7eb2e8f9f7 7233 #define I2C_ISR_BUSY_Pos (15U)
<> 144:ef7eb2e8f9f7 7234 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7235 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
<> 144:ef7eb2e8f9f7 7236 #define I2C_ISR_DIR_Pos (16U)
<> 144:ef7eb2e8f9f7 7237 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 7238 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
<> 144:ef7eb2e8f9f7 7239 #define I2C_ISR_ADDCODE_Pos (17U)
<> 144:ef7eb2e8f9f7 7240 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
<> 144:ef7eb2e8f9f7 7241 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
<> 144:ef7eb2e8f9f7 7242
<> 144:ef7eb2e8f9f7 7243 /****************** Bit definition for I2C_ICR register ********************/
<> 144:ef7eb2e8f9f7 7244 #define I2C_ICR_ADDRCF_Pos (3U)
<> 144:ef7eb2e8f9f7 7245 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7246 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
<> 144:ef7eb2e8f9f7 7247 #define I2C_ICR_NACKCF_Pos (4U)
<> 144:ef7eb2e8f9f7 7248 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7249 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
<> 144:ef7eb2e8f9f7 7250 #define I2C_ICR_STOPCF_Pos (5U)
<> 144:ef7eb2e8f9f7 7251 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7252 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
<> 144:ef7eb2e8f9f7 7253 #define I2C_ICR_BERRCF_Pos (8U)
<> 144:ef7eb2e8f9f7 7254 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7255 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
<> 144:ef7eb2e8f9f7 7256 #define I2C_ICR_ARLOCF_Pos (9U)
<> 144:ef7eb2e8f9f7 7257 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7258 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
<> 144:ef7eb2e8f9f7 7259 #define I2C_ICR_OVRCF_Pos (10U)
<> 144:ef7eb2e8f9f7 7260 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7261 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
<> 144:ef7eb2e8f9f7 7262 #define I2C_ICR_PECCF_Pos (11U)
<> 144:ef7eb2e8f9f7 7263 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7264 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
<> 144:ef7eb2e8f9f7 7265 #define I2C_ICR_TIMOUTCF_Pos (12U)
<> 144:ef7eb2e8f9f7 7266 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7267 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
<> 144:ef7eb2e8f9f7 7268 #define I2C_ICR_ALERTCF_Pos (13U)
<> 144:ef7eb2e8f9f7 7269 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 7270 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
<> 144:ef7eb2e8f9f7 7271
<> 144:ef7eb2e8f9f7 7272 /****************** Bit definition for I2C_PECR register *******************/
<> 144:ef7eb2e8f9f7 7273 #define I2C_PECR_PEC_Pos (0U)
<> 144:ef7eb2e8f9f7 7274 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 7275 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
<> 144:ef7eb2e8f9f7 7276
<> 144:ef7eb2e8f9f7 7277 /****************** Bit definition for I2C_RXDR register *********************/
<> 144:ef7eb2e8f9f7 7278 #define I2C_RXDR_RXDATA_Pos (0U)
<> 144:ef7eb2e8f9f7 7279 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 7280 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
<> 144:ef7eb2e8f9f7 7281
<> 144:ef7eb2e8f9f7 7282 /****************** Bit definition for I2C_TXDR register *******************/
<> 144:ef7eb2e8f9f7 7283 #define I2C_TXDR_TXDATA_Pos (0U)
<> 144:ef7eb2e8f9f7 7284 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 7285 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
<> 144:ef7eb2e8f9f7 7286
<> 144:ef7eb2e8f9f7 7287 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 7288 /* */
<> 144:ef7eb2e8f9f7 7289 /* Independent WATCHDOG (IWDG) */
<> 144:ef7eb2e8f9f7 7290 /* */
<> 144:ef7eb2e8f9f7 7291 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 7292 /******************* Bit definition for IWDG_KR register *******************/
<> 144:ef7eb2e8f9f7 7293 #define IWDG_KR_KEY_Pos (0U)
<> 144:ef7eb2e8f9f7 7294 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 7295 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
<> 144:ef7eb2e8f9f7 7296
<> 144:ef7eb2e8f9f7 7297 /******************* Bit definition for IWDG_PR register *******************/
<> 144:ef7eb2e8f9f7 7298 #define IWDG_PR_PR_Pos (0U)
<> 144:ef7eb2e8f9f7 7299 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
<> 144:ef7eb2e8f9f7 7300 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
<> 144:ef7eb2e8f9f7 7301 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
<> 144:ef7eb2e8f9f7 7302 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
<> 144:ef7eb2e8f9f7 7303 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
<> 144:ef7eb2e8f9f7 7304
<> 144:ef7eb2e8f9f7 7305 /******************* Bit definition for IWDG_RLR register ******************/
<> 144:ef7eb2e8f9f7 7306 #define IWDG_RLR_RL_Pos (0U)
<> 144:ef7eb2e8f9f7 7307 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 7308 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
<> 144:ef7eb2e8f9f7 7309
<> 144:ef7eb2e8f9f7 7310 /******************* Bit definition for IWDG_SR register *******************/
<> 144:ef7eb2e8f9f7 7311 #define IWDG_SR_PVU_Pos (0U)
<> 144:ef7eb2e8f9f7 7312 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7313 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
<> 144:ef7eb2e8f9f7 7314 #define IWDG_SR_RVU_Pos (1U)
<> 144:ef7eb2e8f9f7 7315 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7316 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
<> 144:ef7eb2e8f9f7 7317 #define IWDG_SR_WVU_Pos (2U)
<> 144:ef7eb2e8f9f7 7318 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7319 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
<> 144:ef7eb2e8f9f7 7320
<> 144:ef7eb2e8f9f7 7321 /******************* Bit definition for IWDG_KR register *******************/
<> 144:ef7eb2e8f9f7 7322 #define IWDG_WINR_WIN_Pos (0U)
<> 144:ef7eb2e8f9f7 7323 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
<> 144:ef7eb2e8f9f7 7324 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
<> 144:ef7eb2e8f9f7 7325
<> 144:ef7eb2e8f9f7 7326 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 7327 /* */
<> 144:ef7eb2e8f9f7 7328 /* Power Control (PWR) */
<> 144:ef7eb2e8f9f7 7329 /* */
<> 144:ef7eb2e8f9f7 7330 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 7331
<> 144:ef7eb2e8f9f7 7332 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
<> 144:ef7eb2e8f9f7 7333
<> 144:ef7eb2e8f9f7 7334
<> 144:ef7eb2e8f9f7 7335 /******************** Bit definition for PWR_CR register *******************/
<> 144:ef7eb2e8f9f7 7336 #define PWR_CR_LPDS_Pos (0U)
<> 144:ef7eb2e8f9f7 7337 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7338 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
<> 144:ef7eb2e8f9f7 7339 #define PWR_CR_PDDS_Pos (1U)
<> 144:ef7eb2e8f9f7 7340 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7341 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
<> 144:ef7eb2e8f9f7 7342 #define PWR_CR_CWUF_Pos (2U)
<> 144:ef7eb2e8f9f7 7343 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7344 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
<> 144:ef7eb2e8f9f7 7345 #define PWR_CR_CSBF_Pos (3U)
<> 144:ef7eb2e8f9f7 7346 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7347 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
<> 144:ef7eb2e8f9f7 7348 #define PWR_CR_PVDE_Pos (4U)
<> 144:ef7eb2e8f9f7 7349 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7350 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
<> 144:ef7eb2e8f9f7 7351
<> 144:ef7eb2e8f9f7 7352 #define PWR_CR_PLS_Pos (5U)
<> 144:ef7eb2e8f9f7 7353 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
<> 144:ef7eb2e8f9f7 7354 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
<> 144:ef7eb2e8f9f7 7355 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7356 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 7357 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 7358
<> 144:ef7eb2e8f9f7 7359 /*!< PVD level configuration */
<> 144:ef7eb2e8f9f7 7360 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
<> 144:ef7eb2e8f9f7 7361 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
<> 144:ef7eb2e8f9f7 7362 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
<> 144:ef7eb2e8f9f7 7363 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
<> 144:ef7eb2e8f9f7 7364 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
<> 144:ef7eb2e8f9f7 7365 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
<> 144:ef7eb2e8f9f7 7366 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
<> 144:ef7eb2e8f9f7 7367 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
<> 144:ef7eb2e8f9f7 7368
<> 144:ef7eb2e8f9f7 7369 #define PWR_CR_DBP_Pos (8U)
<> 144:ef7eb2e8f9f7 7370 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7371 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
<> 144:ef7eb2e8f9f7 7372
<> 144:ef7eb2e8f9f7 7373 /******************* Bit definition for PWR_CSR register *******************/
<> 144:ef7eb2e8f9f7 7374 #define PWR_CSR_WUF_Pos (0U)
<> 144:ef7eb2e8f9f7 7375 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7376 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
<> 144:ef7eb2e8f9f7 7377 #define PWR_CSR_SBF_Pos (1U)
<> 144:ef7eb2e8f9f7 7378 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7379 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
<> 144:ef7eb2e8f9f7 7380 #define PWR_CSR_PVDO_Pos (2U)
<> 144:ef7eb2e8f9f7 7381 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7382 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
<> 144:ef7eb2e8f9f7 7383 #define PWR_CSR_VREFINTRDYF_Pos (3U)
<> 144:ef7eb2e8f9f7 7384 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7385 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
<> 144:ef7eb2e8f9f7 7386
<> 144:ef7eb2e8f9f7 7387 #define PWR_CSR_EWUP1_Pos (8U)
<> 144:ef7eb2e8f9f7 7388 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7389 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
<> 144:ef7eb2e8f9f7 7390 #define PWR_CSR_EWUP2_Pos (9U)
<> 144:ef7eb2e8f9f7 7391 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7392 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
<> 144:ef7eb2e8f9f7 7393 #define PWR_CSR_EWUP3_Pos (10U)
<> 144:ef7eb2e8f9f7 7394 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7395 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
<> 144:ef7eb2e8f9f7 7396 #define PWR_CSR_EWUP4_Pos (11U)
<> 144:ef7eb2e8f9f7 7397 #define PWR_CSR_EWUP4_Msk (0x1U << PWR_CSR_EWUP4_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7398 #define PWR_CSR_EWUP4 PWR_CSR_EWUP4_Msk /*!< Enable WKUP pin 4 */
<> 144:ef7eb2e8f9f7 7399 #define PWR_CSR_EWUP5_Pos (12U)
<> 144:ef7eb2e8f9f7 7400 #define PWR_CSR_EWUP5_Msk (0x1U << PWR_CSR_EWUP5_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7401 #define PWR_CSR_EWUP5 PWR_CSR_EWUP5_Msk /*!< Enable WKUP pin 5 */
<> 144:ef7eb2e8f9f7 7402 #define PWR_CSR_EWUP6_Pos (13U)
<> 144:ef7eb2e8f9f7 7403 #define PWR_CSR_EWUP6_Msk (0x1U << PWR_CSR_EWUP6_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 7404 #define PWR_CSR_EWUP6 PWR_CSR_EWUP6_Msk /*!< Enable WKUP pin 6 */
<> 144:ef7eb2e8f9f7 7405 #define PWR_CSR_EWUP7_Pos (14U)
<> 144:ef7eb2e8f9f7 7406 #define PWR_CSR_EWUP7_Msk (0x1U << PWR_CSR_EWUP7_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7407 #define PWR_CSR_EWUP7 PWR_CSR_EWUP7_Msk /*!< Enable WKUP pin 7 */
<> 144:ef7eb2e8f9f7 7408 #define PWR_CSR_EWUP8_Pos (15U)
<> 144:ef7eb2e8f9f7 7409 #define PWR_CSR_EWUP8_Msk (0x1U << PWR_CSR_EWUP8_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7410 #define PWR_CSR_EWUP8 PWR_CSR_EWUP8_Msk /*!< Enable WKUP pin 8 */
<> 144:ef7eb2e8f9f7 7411
<> 144:ef7eb2e8f9f7 7412 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 7413 /* */
<> 144:ef7eb2e8f9f7 7414 /* Reset and Clock Control */
<> 144:ef7eb2e8f9f7 7415 /* */
<> 144:ef7eb2e8f9f7 7416 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 7417 /*
<> 144:ef7eb2e8f9f7 7418 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 144:ef7eb2e8f9f7 7419 */
<> 144:ef7eb2e8f9f7 7420 #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
<> 144:ef7eb2e8f9f7 7421 #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */
<> 144:ef7eb2e8f9f7 7422
<> 144:ef7eb2e8f9f7 7423 /******************** Bit definition for RCC_CR register *******************/
<> 144:ef7eb2e8f9f7 7424 #define RCC_CR_HSION_Pos (0U)
<> 144:ef7eb2e8f9f7 7425 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7426 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
<> 144:ef7eb2e8f9f7 7427 #define RCC_CR_HSIRDY_Pos (1U)
<> 144:ef7eb2e8f9f7 7428 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7429 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
<> 144:ef7eb2e8f9f7 7430
<> 144:ef7eb2e8f9f7 7431 #define RCC_CR_HSITRIM_Pos (3U)
<> 144:ef7eb2e8f9f7 7432 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
<> 144:ef7eb2e8f9f7 7433 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
<> 144:ef7eb2e8f9f7 7434 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7435 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7436 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7437 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 7438 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 7439
<> 144:ef7eb2e8f9f7 7440 #define RCC_CR_HSICAL_Pos (8U)
<> 144:ef7eb2e8f9f7 7441 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 7442 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
<> 144:ef7eb2e8f9f7 7443 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7444 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7445 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7446 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7447 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7448 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 7449 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7450 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7451
<> 144:ef7eb2e8f9f7 7452 #define RCC_CR_HSEON_Pos (16U)
<> 144:ef7eb2e8f9f7 7453 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 7454 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
<> 144:ef7eb2e8f9f7 7455 #define RCC_CR_HSERDY_Pos (17U)
<> 144:ef7eb2e8f9f7 7456 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7457 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
<> 144:ef7eb2e8f9f7 7458 #define RCC_CR_HSEBYP_Pos (18U)
<> 144:ef7eb2e8f9f7 7459 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7460 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
<> 144:ef7eb2e8f9f7 7461 #define RCC_CR_CSSON_Pos (19U)
<> 144:ef7eb2e8f9f7 7462 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 7463 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
<> 144:ef7eb2e8f9f7 7464 #define RCC_CR_PLLON_Pos (24U)
<> 144:ef7eb2e8f9f7 7465 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 7466 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
<> 144:ef7eb2e8f9f7 7467 #define RCC_CR_PLLRDY_Pos (25U)
<> 144:ef7eb2e8f9f7 7468 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 7469 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
<> 144:ef7eb2e8f9f7 7470
<> 144:ef7eb2e8f9f7 7471 /******************** Bit definition for RCC_CFGR register *****************/
<> 144:ef7eb2e8f9f7 7472 /*!< SW configuration */
<> 144:ef7eb2e8f9f7 7473 #define RCC_CFGR_SW_Pos (0U)
<> 144:ef7eb2e8f9f7 7474 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 7475 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
<> 144:ef7eb2e8f9f7 7476 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7477 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7478
<> 144:ef7eb2e8f9f7 7479 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
<> 144:ef7eb2e8f9f7 7480 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
<> 144:ef7eb2e8f9f7 7481 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
<> 144:ef7eb2e8f9f7 7482 #define RCC_CFGR_SW_HSI48 (0x00000003U) /*!< HSI48 selected as system clock */
<> 144:ef7eb2e8f9f7 7483
<> 144:ef7eb2e8f9f7 7484 /*!< SWS configuration */
<> 144:ef7eb2e8f9f7 7485 #define RCC_CFGR_SWS_Pos (2U)
<> 144:ef7eb2e8f9f7 7486 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
<> 144:ef7eb2e8f9f7 7487 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 144:ef7eb2e8f9f7 7488 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7489 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7490
<> 144:ef7eb2e8f9f7 7491 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
<> 144:ef7eb2e8f9f7 7492 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
<> 144:ef7eb2e8f9f7 7493 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
<> 144:ef7eb2e8f9f7 7494 #define RCC_CFGR_SWS_HSI48 (0x0000000CU) /*!< HSI48 oscillator used as system clock */
<> 144:ef7eb2e8f9f7 7495
<> 144:ef7eb2e8f9f7 7496 /*!< HPRE configuration */
<> 144:ef7eb2e8f9f7 7497 #define RCC_CFGR_HPRE_Pos (4U)
<> 144:ef7eb2e8f9f7 7498 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 7499 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
<> 144:ef7eb2e8f9f7 7500 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7501 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7502 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 7503 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 7504
<> 144:ef7eb2e8f9f7 7505 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
<> 144:ef7eb2e8f9f7 7506 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
<> 144:ef7eb2e8f9f7 7507 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
<> 144:ef7eb2e8f9f7 7508 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
<> 144:ef7eb2e8f9f7 7509 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
<> 144:ef7eb2e8f9f7 7510 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
<> 144:ef7eb2e8f9f7 7511 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
<> 144:ef7eb2e8f9f7 7512 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
<> 144:ef7eb2e8f9f7 7513 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
<> 144:ef7eb2e8f9f7 7514
<> 144:ef7eb2e8f9f7 7515 /*!< PPRE configuration */
<> 144:ef7eb2e8f9f7 7516 #define RCC_CFGR_PPRE_Pos (8U)
<> 144:ef7eb2e8f9f7 7517 #define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */
<> 144:ef7eb2e8f9f7 7518 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */
<> 144:ef7eb2e8f9f7 7519 #define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7520 #define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7521 #define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7522
<> 144:ef7eb2e8f9f7 7523 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 7524 #define RCC_CFGR_PPRE_DIV2_Pos (10U)
<> 144:ef7eb2e8f9f7 7525 #define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7526 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 7527 #define RCC_CFGR_PPRE_DIV4_Pos (8U)
<> 144:ef7eb2e8f9f7 7528 #define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
<> 144:ef7eb2e8f9f7 7529 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 7530 #define RCC_CFGR_PPRE_DIV8_Pos (9U)
<> 144:ef7eb2e8f9f7 7531 #define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
<> 144:ef7eb2e8f9f7 7532 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 7533 #define RCC_CFGR_PPRE_DIV16_Pos (8U)
<> 144:ef7eb2e8f9f7 7534 #define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
<> 144:ef7eb2e8f9f7 7535 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 7536
<> 144:ef7eb2e8f9f7 7537 /*!< ADCPPRE configuration */
<> 144:ef7eb2e8f9f7 7538 #define RCC_CFGR_ADCPRE_Pos (14U)
<> 144:ef7eb2e8f9f7 7539 #define RCC_CFGR_ADCPRE_Msk (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7540 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */
<> 144:ef7eb2e8f9f7 7541
<> 144:ef7eb2e8f9f7 7542 #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */
<> 144:ef7eb2e8f9f7 7543 #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */
<> 144:ef7eb2e8f9f7 7544
<> 144:ef7eb2e8f9f7 7545 #define RCC_CFGR_PLLSRC_Pos (15U)
<> 144:ef7eb2e8f9f7 7546 #define RCC_CFGR_PLLSRC_Msk (0x3U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
<> 144:ef7eb2e8f9f7 7547 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
<> 144:ef7eb2e8f9f7 7548 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
<> 144:ef7eb2e8f9f7 7549 #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */
<> 144:ef7eb2e8f9f7 7550 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
<> 144:ef7eb2e8f9f7 7551 #define RCC_CFGR_PLLSRC_HSI48_PREDIV (0x00018000U) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
<> 144:ef7eb2e8f9f7 7552
<> 144:ef7eb2e8f9f7 7553 #define RCC_CFGR_PLLXTPRE_Pos (17U)
<> 144:ef7eb2e8f9f7 7554 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7555 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
<> 144:ef7eb2e8f9f7 7556 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
<> 144:ef7eb2e8f9f7 7557 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
<> 144:ef7eb2e8f9f7 7558
<> 144:ef7eb2e8f9f7 7559 /*!< PLLMUL configuration */
<> 144:ef7eb2e8f9f7 7560 #define RCC_CFGR_PLLMUL_Pos (18U)
<> 144:ef7eb2e8f9f7 7561 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
<> 144:ef7eb2e8f9f7 7562 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
<> 144:ef7eb2e8f9f7 7563 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7564 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 7565 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 7566 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 7567
<> 144:ef7eb2e8f9f7 7568 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
<> 144:ef7eb2e8f9f7 7569 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
<> 144:ef7eb2e8f9f7 7570 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
<> 144:ef7eb2e8f9f7 7571 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
<> 144:ef7eb2e8f9f7 7572 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
<> 144:ef7eb2e8f9f7 7573 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
<> 144:ef7eb2e8f9f7 7574 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
<> 144:ef7eb2e8f9f7 7575 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
<> 144:ef7eb2e8f9f7 7576 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
<> 144:ef7eb2e8f9f7 7577 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
<> 144:ef7eb2e8f9f7 7578 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
<> 144:ef7eb2e8f9f7 7579 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
<> 144:ef7eb2e8f9f7 7580 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
<> 144:ef7eb2e8f9f7 7581 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
<> 144:ef7eb2e8f9f7 7582 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
<> 144:ef7eb2e8f9f7 7583
<> 144:ef7eb2e8f9f7 7584 /*!< USB configuration */
<> 144:ef7eb2e8f9f7 7585 #define RCC_CFGR_USBPRE_Pos (22U)
<> 144:ef7eb2e8f9f7 7586 #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 7587 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB prescaler */
<> 144:ef7eb2e8f9f7 7588
<> 144:ef7eb2e8f9f7 7589 /*!< MCO configuration */
<> 144:ef7eb2e8f9f7 7590 #define RCC_CFGR_MCO_Pos (24U)
<> 144:ef7eb2e8f9f7 7591 #define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
<> 144:ef7eb2e8f9f7 7592 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
<> 144:ef7eb2e8f9f7 7593 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 7594 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 7595 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 7596 #define RCC_CFGR_MCO_3 (0x08000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 7597
<> 144:ef7eb2e8f9f7 7598 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
<> 144:ef7eb2e8f9f7 7599 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */
<> 144:ef7eb2e8f9f7 7600 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
<> 144:ef7eb2e8f9f7 7601 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
<> 144:ef7eb2e8f9f7 7602 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
<> 144:ef7eb2e8f9f7 7603 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
<> 144:ef7eb2e8f9f7 7604 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
<> 144:ef7eb2e8f9f7 7605 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
<> 144:ef7eb2e8f9f7 7606 #define RCC_CFGR_MCO_HSI48 (0x08000000U) /*!< HSI48 clock selected as MCO source */
<> 144:ef7eb2e8f9f7 7607
<> 144:ef7eb2e8f9f7 7608 #define RCC_CFGR_MCOPRE_Pos (28U)
<> 144:ef7eb2e8f9f7 7609 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
<> 144:ef7eb2e8f9f7 7610 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
<> 144:ef7eb2e8f9f7 7611 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
<> 144:ef7eb2e8f9f7 7612 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
<> 144:ef7eb2e8f9f7 7613 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
<> 144:ef7eb2e8f9f7 7614 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
<> 144:ef7eb2e8f9f7 7615 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
<> 144:ef7eb2e8f9f7 7616 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */
<> 144:ef7eb2e8f9f7 7617 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */
<> 144:ef7eb2e8f9f7 7618 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */
<> 144:ef7eb2e8f9f7 7619
<> 144:ef7eb2e8f9f7 7620 #define RCC_CFGR_PLLNODIV_Pos (31U)
<> 144:ef7eb2e8f9f7 7621 #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 7622 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< PLL is not divided to MCO */
<> 144:ef7eb2e8f9f7 7623
<> 144:ef7eb2e8f9f7 7624 /* Reference defines */
<> 144:ef7eb2e8f9f7 7625 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
<> 144:ef7eb2e8f9f7 7626 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
<> 144:ef7eb2e8f9f7 7627 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
<> 144:ef7eb2e8f9f7 7628 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
<> 144:ef7eb2e8f9f7 7629 #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3
<> 144:ef7eb2e8f9f7 7630 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
<> 144:ef7eb2e8f9f7 7631 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
<> 144:ef7eb2e8f9f7 7632 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
<> 144:ef7eb2e8f9f7 7633 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
<> 144:ef7eb2e8f9f7 7634 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
<> 144:ef7eb2e8f9f7 7635 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
<> 144:ef7eb2e8f9f7 7636 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
<> 144:ef7eb2e8f9f7 7637 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
<> 144:ef7eb2e8f9f7 7638 #define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCO_HSI48
<> 144:ef7eb2e8f9f7 7639
<> 144:ef7eb2e8f9f7 7640 /*!<****************** Bit definition for RCC_CIR register *****************/
<> 144:ef7eb2e8f9f7 7641 #define RCC_CIR_LSIRDYF_Pos (0U)
<> 144:ef7eb2e8f9f7 7642 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7643 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 7644 #define RCC_CIR_LSERDYF_Pos (1U)
<> 144:ef7eb2e8f9f7 7645 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7646 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 7647 #define RCC_CIR_HSIRDYF_Pos (2U)
<> 144:ef7eb2e8f9f7 7648 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7649 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 7650 #define RCC_CIR_HSERDYF_Pos (3U)
<> 144:ef7eb2e8f9f7 7651 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7652 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 7653 #define RCC_CIR_PLLRDYF_Pos (4U)
<> 144:ef7eb2e8f9f7 7654 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7655 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 7656 #define RCC_CIR_HSI14RDYF_Pos (5U)
<> 144:ef7eb2e8f9f7 7657 #define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7658 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 7659 #define RCC_CIR_HSI48RDYF_Pos (6U)
<> 144:ef7eb2e8f9f7 7660 #define RCC_CIR_HSI48RDYF_Msk (0x1U << RCC_CIR_HSI48RDYF_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 7661 #define RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 7662 #define RCC_CIR_CSSF_Pos (7U)
<> 144:ef7eb2e8f9f7 7663 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 7664 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
<> 144:ef7eb2e8f9f7 7665 #define RCC_CIR_LSIRDYIE_Pos (8U)
<> 144:ef7eb2e8f9f7 7666 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7667 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 7668 #define RCC_CIR_LSERDYIE_Pos (9U)
<> 144:ef7eb2e8f9f7 7669 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7670 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 7671 #define RCC_CIR_HSIRDYIE_Pos (10U)
<> 144:ef7eb2e8f9f7 7672 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 7673 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 7674 #define RCC_CIR_HSERDYIE_Pos (11U)
<> 144:ef7eb2e8f9f7 7675 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7676 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 7677 #define RCC_CIR_PLLRDYIE_Pos (12U)
<> 144:ef7eb2e8f9f7 7678 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7679 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 7680 #define RCC_CIR_HSI14RDYIE_Pos (13U)
<> 144:ef7eb2e8f9f7 7681 #define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 7682 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 7683 #define RCC_CIR_HSI48RDYIE_Pos (14U)
<> 144:ef7eb2e8f9f7 7684 #define RCC_CIR_HSI48RDYIE_Msk (0x1U << RCC_CIR_HSI48RDYIE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7685 #define RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 7686 #define RCC_CIR_LSIRDYC_Pos (16U)
<> 144:ef7eb2e8f9f7 7687 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 7688 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 7689 #define RCC_CIR_LSERDYC_Pos (17U)
<> 144:ef7eb2e8f9f7 7690 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7691 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 7692 #define RCC_CIR_HSIRDYC_Pos (18U)
<> 144:ef7eb2e8f9f7 7693 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7694 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 7695 #define RCC_CIR_HSERDYC_Pos (19U)
<> 144:ef7eb2e8f9f7 7696 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 7697 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 7698 #define RCC_CIR_PLLRDYC_Pos (20U)
<> 144:ef7eb2e8f9f7 7699 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 7700 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 7701 #define RCC_CIR_HSI14RDYC_Pos (21U)
<> 144:ef7eb2e8f9f7 7702 #define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 7703 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 7704 #define RCC_CIR_HSI48RDYC_Pos (22U)
<> 144:ef7eb2e8f9f7 7705 #define RCC_CIR_HSI48RDYC_Msk (0x1U << RCC_CIR_HSI48RDYC_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 7706 #define RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 7707 #define RCC_CIR_CSSC_Pos (23U)
<> 144:ef7eb2e8f9f7 7708 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 7709 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
<> 144:ef7eb2e8f9f7 7710
<> 144:ef7eb2e8f9f7 7711 /***************** Bit definition for RCC_APB2RSTR register ****************/
<> 144:ef7eb2e8f9f7 7712 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
<> 144:ef7eb2e8f9f7 7713 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7714 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
<> 144:ef7eb2e8f9f7 7715 #define RCC_APB2RSTR_ADCRST_Pos (9U)
<> 144:ef7eb2e8f9f7 7716 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7717 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */
<> 144:ef7eb2e8f9f7 7718 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
<> 144:ef7eb2e8f9f7 7719 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7720 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */
<> 144:ef7eb2e8f9f7 7721 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
<> 144:ef7eb2e8f9f7 7722 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7723 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
<> 144:ef7eb2e8f9f7 7724 #define RCC_APB2RSTR_USART1RST_Pos (14U)
<> 144:ef7eb2e8f9f7 7725 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7726 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */
<> 144:ef7eb2e8f9f7 7727 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
<> 144:ef7eb2e8f9f7 7728 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 7729 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */
<> 144:ef7eb2e8f9f7 7730 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
<> 144:ef7eb2e8f9f7 7731 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7732 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */
<> 144:ef7eb2e8f9f7 7733 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
<> 144:ef7eb2e8f9f7 7734 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7735 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */
<> 144:ef7eb2e8f9f7 7736 #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
<> 144:ef7eb2e8f9f7 7737 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 7738 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */
<> 144:ef7eb2e8f9f7 7739
<> 144:ef7eb2e8f9f7 7740 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 7741 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
<> 144:ef7eb2e8f9f7 7742
<> 144:ef7eb2e8f9f7 7743 /***************** Bit definition for RCC_APB1RSTR register ****************/
<> 144:ef7eb2e8f9f7 7744 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
<> 144:ef7eb2e8f9f7 7745 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7746 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */
<> 144:ef7eb2e8f9f7 7747 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
<> 144:ef7eb2e8f9f7 7748 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7749 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */
<> 144:ef7eb2e8f9f7 7750 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
<> 144:ef7eb2e8f9f7 7751 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7752 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */
<> 144:ef7eb2e8f9f7 7753 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
<> 144:ef7eb2e8f9f7 7754 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7755 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */
<> 144:ef7eb2e8f9f7 7756 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
<> 144:ef7eb2e8f9f7 7757 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7758 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */
<> 144:ef7eb2e8f9f7 7759 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
<> 144:ef7eb2e8f9f7 7760 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7761 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
<> 144:ef7eb2e8f9f7 7762 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
<> 144:ef7eb2e8f9f7 7763 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7764 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */
<> 144:ef7eb2e8f9f7 7765 #define RCC_APB1RSTR_USART2RST_Pos (17U)
<> 144:ef7eb2e8f9f7 7766 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7767 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */
<> 144:ef7eb2e8f9f7 7768 #define RCC_APB1RSTR_USART3RST_Pos (18U)
<> 144:ef7eb2e8f9f7 7769 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7770 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */
<> 144:ef7eb2e8f9f7 7771 #define RCC_APB1RSTR_USART4RST_Pos (19U)
<> 144:ef7eb2e8f9f7 7772 #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 7773 #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */
<> 144:ef7eb2e8f9f7 7774 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
<> 144:ef7eb2e8f9f7 7775 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 7776 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
<> 144:ef7eb2e8f9f7 7777 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
<> 144:ef7eb2e8f9f7 7778 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 7779 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */
<> 144:ef7eb2e8f9f7 7780 #define RCC_APB1RSTR_USBRST_Pos (23U)
<> 144:ef7eb2e8f9f7 7781 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 7782 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */
<> 144:ef7eb2e8f9f7 7783 #define RCC_APB1RSTR_CANRST_Pos (25U)
<> 144:ef7eb2e8f9f7 7784 #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 7785 #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */
<> 144:ef7eb2e8f9f7 7786 #define RCC_APB1RSTR_CRSRST_Pos (27U)
<> 144:ef7eb2e8f9f7 7787 #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 7788 #define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */
<> 144:ef7eb2e8f9f7 7789 #define RCC_APB1RSTR_PWRRST_Pos (28U)
<> 144:ef7eb2e8f9f7 7790 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 7791 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
<> 144:ef7eb2e8f9f7 7792 #define RCC_APB1RSTR_DACRST_Pos (29U)
<> 144:ef7eb2e8f9f7 7793 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7794 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */
<> 144:ef7eb2e8f9f7 7795 #define RCC_APB1RSTR_CECRST_Pos (30U)
<> 144:ef7eb2e8f9f7 7796 #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 7797 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */
<> 144:ef7eb2e8f9f7 7798
<> 144:ef7eb2e8f9f7 7799 /****************** Bit definition for RCC_AHBENR register *****************/
<> 144:ef7eb2e8f9f7 7800 #define RCC_AHBENR_DMAEN_Pos (0U)
<> 144:ef7eb2e8f9f7 7801 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7802 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
<> 144:ef7eb2e8f9f7 7803 #define RCC_AHBENR_SRAMEN_Pos (2U)
<> 144:ef7eb2e8f9f7 7804 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7805 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
<> 144:ef7eb2e8f9f7 7806 #define RCC_AHBENR_FLITFEN_Pos (4U)
<> 144:ef7eb2e8f9f7 7807 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7808 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
<> 144:ef7eb2e8f9f7 7809 #define RCC_AHBENR_CRCEN_Pos (6U)
<> 144:ef7eb2e8f9f7 7810 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 7811 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
<> 144:ef7eb2e8f9f7 7812 #define RCC_AHBENR_GPIOAEN_Pos (17U)
<> 144:ef7eb2e8f9f7 7813 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7814 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
<> 144:ef7eb2e8f9f7 7815 #define RCC_AHBENR_GPIOBEN_Pos (18U)
<> 144:ef7eb2e8f9f7 7816 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7817 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
<> 144:ef7eb2e8f9f7 7818 #define RCC_AHBENR_GPIOCEN_Pos (19U)
<> 144:ef7eb2e8f9f7 7819 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 7820 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
<> 144:ef7eb2e8f9f7 7821 #define RCC_AHBENR_GPIODEN_Pos (20U)
<> 144:ef7eb2e8f9f7 7822 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 7823 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
<> 144:ef7eb2e8f9f7 7824 #define RCC_AHBENR_GPIOEEN_Pos (21U)
<> 144:ef7eb2e8f9f7 7825 #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 7826 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIOE clock enable */
<> 144:ef7eb2e8f9f7 7827 #define RCC_AHBENR_GPIOFEN_Pos (22U)
<> 144:ef7eb2e8f9f7 7828 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 7829 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
<> 144:ef7eb2e8f9f7 7830 #define RCC_AHBENR_TSCEN_Pos (24U)
<> 144:ef7eb2e8f9f7 7831 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 7832 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller clock enable */
<> 144:ef7eb2e8f9f7 7833
<> 144:ef7eb2e8f9f7 7834 /* Old Bit definition maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 7835 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
<> 144:ef7eb2e8f9f7 7836 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
<> 144:ef7eb2e8f9f7 7837
<> 144:ef7eb2e8f9f7 7838 /***************** Bit definition for RCC_APB2ENR register *****************/
<> 144:ef7eb2e8f9f7 7839 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
<> 144:ef7eb2e8f9f7 7840 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7841 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */
<> 144:ef7eb2e8f9f7 7842 #define RCC_APB2ENR_ADCEN_Pos (9U)
<> 144:ef7eb2e8f9f7 7843 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7844 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
<> 144:ef7eb2e8f9f7 7845 #define RCC_APB2ENR_TIM1EN_Pos (11U)
<> 144:ef7eb2e8f9f7 7846 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7847 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
<> 144:ef7eb2e8f9f7 7848 #define RCC_APB2ENR_SPI1EN_Pos (12U)
<> 144:ef7eb2e8f9f7 7849 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 7850 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
<> 144:ef7eb2e8f9f7 7851 #define RCC_APB2ENR_USART1EN_Pos (14U)
<> 144:ef7eb2e8f9f7 7852 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7853 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
<> 144:ef7eb2e8f9f7 7854 #define RCC_APB2ENR_TIM15EN_Pos (16U)
<> 144:ef7eb2e8f9f7 7855 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 7856 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
<> 144:ef7eb2e8f9f7 7857 #define RCC_APB2ENR_TIM16EN_Pos (17U)
<> 144:ef7eb2e8f9f7 7858 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7859 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
<> 144:ef7eb2e8f9f7 7860 #define RCC_APB2ENR_TIM17EN_Pos (18U)
<> 144:ef7eb2e8f9f7 7861 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7862 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
<> 144:ef7eb2e8f9f7 7863 #define RCC_APB2ENR_DBGMCUEN_Pos (22U)
<> 144:ef7eb2e8f9f7 7864 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 7865 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */
<> 144:ef7eb2e8f9f7 7866
<> 144:ef7eb2e8f9f7 7867 /* Old Bit definition maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 7868 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
<> 144:ef7eb2e8f9f7 7869 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
<> 144:ef7eb2e8f9f7 7870
<> 144:ef7eb2e8f9f7 7871 /***************** Bit definition for RCC_APB1ENR register *****************/
<> 144:ef7eb2e8f9f7 7872 #define RCC_APB1ENR_TIM2EN_Pos (0U)
<> 144:ef7eb2e8f9f7 7873 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7874 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
<> 144:ef7eb2e8f9f7 7875 #define RCC_APB1ENR_TIM3EN_Pos (1U)
<> 144:ef7eb2e8f9f7 7876 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7877 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
<> 144:ef7eb2e8f9f7 7878 #define RCC_APB1ENR_TIM6EN_Pos (4U)
<> 144:ef7eb2e8f9f7 7879 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7880 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
<> 144:ef7eb2e8f9f7 7881 #define RCC_APB1ENR_TIM7EN_Pos (5U)
<> 144:ef7eb2e8f9f7 7882 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 7883 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
<> 144:ef7eb2e8f9f7 7884 #define RCC_APB1ENR_TIM14EN_Pos (8U)
<> 144:ef7eb2e8f9f7 7885 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7886 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */
<> 144:ef7eb2e8f9f7 7887 #define RCC_APB1ENR_WWDGEN_Pos (11U)
<> 144:ef7eb2e8f9f7 7888 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 7889 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
<> 144:ef7eb2e8f9f7 7890 #define RCC_APB1ENR_SPI2EN_Pos (14U)
<> 144:ef7eb2e8f9f7 7891 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 7892 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
<> 144:ef7eb2e8f9f7 7893 #define RCC_APB1ENR_USART2EN_Pos (17U)
<> 144:ef7eb2e8f9f7 7894 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 7895 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
<> 144:ef7eb2e8f9f7 7896 #define RCC_APB1ENR_USART3EN_Pos (18U)
<> 144:ef7eb2e8f9f7 7897 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 7898 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART3 clock enable */
<> 144:ef7eb2e8f9f7 7899 #define RCC_APB1ENR_USART4EN_Pos (19U)
<> 144:ef7eb2e8f9f7 7900 #define RCC_APB1ENR_USART4EN_Msk (0x1U << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 7901 #define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */
<> 144:ef7eb2e8f9f7 7902 #define RCC_APB1ENR_I2C1EN_Pos (21U)
<> 144:ef7eb2e8f9f7 7903 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 7904 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
<> 144:ef7eb2e8f9f7 7905 #define RCC_APB1ENR_I2C2EN_Pos (22U)
<> 144:ef7eb2e8f9f7 7906 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 7907 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
<> 144:ef7eb2e8f9f7 7908 #define RCC_APB1ENR_USBEN_Pos (23U)
<> 144:ef7eb2e8f9f7 7909 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 7910 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
<> 144:ef7eb2e8f9f7 7911 #define RCC_APB1ENR_CANEN_Pos (25U)
<> 144:ef7eb2e8f9f7 7912 #define RCC_APB1ENR_CANEN_Msk (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 7913 #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */
<> 144:ef7eb2e8f9f7 7914 #define RCC_APB1ENR_CRSEN_Pos (27U)
<> 144:ef7eb2e8f9f7 7915 #define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 7916 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
<> 144:ef7eb2e8f9f7 7917 #define RCC_APB1ENR_PWREN_Pos (28U)
<> 144:ef7eb2e8f9f7 7918 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 7919 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
<> 144:ef7eb2e8f9f7 7920 #define RCC_APB1ENR_DACEN_Pos (29U)
<> 144:ef7eb2e8f9f7 7921 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7922 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
<> 144:ef7eb2e8f9f7 7923 #define RCC_APB1ENR_CECEN_Pos (30U)
<> 144:ef7eb2e8f9f7 7924 #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 7925 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enable */
<> 144:ef7eb2e8f9f7 7926
<> 144:ef7eb2e8f9f7 7927 /******************* Bit definition for RCC_BDCR register ******************/
<> 144:ef7eb2e8f9f7 7928 #define RCC_BDCR_LSEON_Pos (0U)
<> 144:ef7eb2e8f9f7 7929 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7930 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
<> 144:ef7eb2e8f9f7 7931 #define RCC_BDCR_LSERDY_Pos (1U)
<> 144:ef7eb2e8f9f7 7932 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7933 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
<> 144:ef7eb2e8f9f7 7934 #define RCC_BDCR_LSEBYP_Pos (2U)
<> 144:ef7eb2e8f9f7 7935 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 7936 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
<> 144:ef7eb2e8f9f7 7937
<> 144:ef7eb2e8f9f7 7938 #define RCC_BDCR_LSEDRV_Pos (3U)
<> 144:ef7eb2e8f9f7 7939 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
<> 144:ef7eb2e8f9f7 7940 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
<> 144:ef7eb2e8f9f7 7941 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 7942 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 7943
<> 144:ef7eb2e8f9f7 7944 #define RCC_BDCR_RTCSEL_Pos (8U)
<> 144:ef7eb2e8f9f7 7945 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 7946 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
<> 144:ef7eb2e8f9f7 7947 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 7948 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 7949
<> 144:ef7eb2e8f9f7 7950 /*!< RTC configuration */
<> 144:ef7eb2e8f9f7 7951 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
<> 144:ef7eb2e8f9f7 7952 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
<> 144:ef7eb2e8f9f7 7953 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
<> 144:ef7eb2e8f9f7 7954 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */
<> 144:ef7eb2e8f9f7 7955
<> 144:ef7eb2e8f9f7 7956 #define RCC_BDCR_RTCEN_Pos (15U)
<> 144:ef7eb2e8f9f7 7957 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 7958 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
<> 144:ef7eb2e8f9f7 7959 #define RCC_BDCR_BDRST_Pos (16U)
<> 144:ef7eb2e8f9f7 7960 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 7961 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
<> 144:ef7eb2e8f9f7 7962
<> 144:ef7eb2e8f9f7 7963 /******************* Bit definition for RCC_CSR register *******************/
<> 144:ef7eb2e8f9f7 7964 #define RCC_CSR_LSION_Pos (0U)
<> 144:ef7eb2e8f9f7 7965 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 7966 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
<> 144:ef7eb2e8f9f7 7967 #define RCC_CSR_LSIRDY_Pos (1U)
<> 144:ef7eb2e8f9f7 7968 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 7969 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
<> 144:ef7eb2e8f9f7 7970 #define RCC_CSR_V18PWRRSTF_Pos (23U)
<> 144:ef7eb2e8f9f7 7971 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 7972 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
<> 144:ef7eb2e8f9f7 7973 #define RCC_CSR_RMVF_Pos (24U)
<> 144:ef7eb2e8f9f7 7974 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 7975 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
<> 144:ef7eb2e8f9f7 7976 #define RCC_CSR_OBLRSTF_Pos (25U)
<> 144:ef7eb2e8f9f7 7977 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 7978 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
<> 144:ef7eb2e8f9f7 7979 #define RCC_CSR_PINRSTF_Pos (26U)
<> 144:ef7eb2e8f9f7 7980 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 7981 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
<> 144:ef7eb2e8f9f7 7982 #define RCC_CSR_PORRSTF_Pos (27U)
<> 144:ef7eb2e8f9f7 7983 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 7984 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
<> 144:ef7eb2e8f9f7 7985 #define RCC_CSR_SFTRSTF_Pos (28U)
<> 144:ef7eb2e8f9f7 7986 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 7987 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
<> 144:ef7eb2e8f9f7 7988 #define RCC_CSR_IWDGRSTF_Pos (29U)
<> 144:ef7eb2e8f9f7 7989 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7990 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
<> 144:ef7eb2e8f9f7 7991 #define RCC_CSR_WWDGRSTF_Pos (30U)
<> 144:ef7eb2e8f9f7 7992 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 7993 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
<> 144:ef7eb2e8f9f7 7994 #define RCC_CSR_LPWRRSTF_Pos (31U)
<> 144:ef7eb2e8f9f7 7995 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 7996 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
<> 144:ef7eb2e8f9f7 7997
<> 144:ef7eb2e8f9f7 7998 /* Old Bit definition maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 7999 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
<> 144:ef7eb2e8f9f7 8000
<> 144:ef7eb2e8f9f7 8001 /******************* Bit definition for RCC_AHBRSTR register ***************/
<> 144:ef7eb2e8f9f7 8002 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
<> 144:ef7eb2e8f9f7 8003 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8004 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */
<> 144:ef7eb2e8f9f7 8005 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
<> 144:ef7eb2e8f9f7 8006 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 8007 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */
<> 144:ef7eb2e8f9f7 8008 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
<> 144:ef7eb2e8f9f7 8009 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8010 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */
<> 144:ef7eb2e8f9f7 8011 #define RCC_AHBRSTR_GPIODRST_Pos (20U)
<> 144:ef7eb2e8f9f7 8012 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 8013 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */
<> 144:ef7eb2e8f9f7 8014 #define RCC_AHBRSTR_GPIOERST_Pos (21U)
<> 144:ef7eb2e8f9f7 8015 #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 8016 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE clock reset */
<> 144:ef7eb2e8f9f7 8017 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
<> 144:ef7eb2e8f9f7 8018 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 8019 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */
<> 144:ef7eb2e8f9f7 8020 #define RCC_AHBRSTR_TSCRST_Pos (24U)
<> 144:ef7eb2e8f9f7 8021 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 8022 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */
<> 144:ef7eb2e8f9f7 8023
<> 144:ef7eb2e8f9f7 8024 /* Old Bit definition maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 8025 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
<> 144:ef7eb2e8f9f7 8026
<> 144:ef7eb2e8f9f7 8027 /******************* Bit definition for RCC_CFGR2 register *****************/
<> 144:ef7eb2e8f9f7 8028 /*!< PREDIV configuration */
<> 144:ef7eb2e8f9f7 8029 #define RCC_CFGR2_PREDIV_Pos (0U)
<> 144:ef7eb2e8f9f7 8030 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 8031 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
<> 144:ef7eb2e8f9f7 8032 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8033 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8034 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8035 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8036
<> 144:ef7eb2e8f9f7 8037 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
<> 144:ef7eb2e8f9f7 8038 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
<> 144:ef7eb2e8f9f7 8039 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
<> 144:ef7eb2e8f9f7 8040 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
<> 144:ef7eb2e8f9f7 8041 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
<> 144:ef7eb2e8f9f7 8042 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
<> 144:ef7eb2e8f9f7 8043 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
<> 144:ef7eb2e8f9f7 8044 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
<> 144:ef7eb2e8f9f7 8045 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
<> 144:ef7eb2e8f9f7 8046 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
<> 144:ef7eb2e8f9f7 8047 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
<> 144:ef7eb2e8f9f7 8048 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
<> 144:ef7eb2e8f9f7 8049 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
<> 144:ef7eb2e8f9f7 8050 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
<> 144:ef7eb2e8f9f7 8051 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
<> 144:ef7eb2e8f9f7 8052 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
<> 144:ef7eb2e8f9f7 8053
<> 144:ef7eb2e8f9f7 8054 /******************* Bit definition for RCC_CFGR3 register *****************/
<> 144:ef7eb2e8f9f7 8055 /*!< USART1 Clock source selection */
<> 144:ef7eb2e8f9f7 8056 #define RCC_CFGR3_USART1SW_Pos (0U)
<> 144:ef7eb2e8f9f7 8057 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 8058 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
<> 144:ef7eb2e8f9f7 8059 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8060 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8061
<> 144:ef7eb2e8f9f7 8062 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */
<> 144:ef7eb2e8f9f7 8063 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
<> 144:ef7eb2e8f9f7 8064 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
<> 144:ef7eb2e8f9f7 8065 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
<> 144:ef7eb2e8f9f7 8066
<> 144:ef7eb2e8f9f7 8067 /*!< I2C1 Clock source selection */
<> 144:ef7eb2e8f9f7 8068 #define RCC_CFGR3_I2C1SW_Pos (4U)
<> 144:ef7eb2e8f9f7 8069 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8070 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
<> 144:ef7eb2e8f9f7 8071
<> 144:ef7eb2e8f9f7 8072 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
<> 144:ef7eb2e8f9f7 8073 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
<> 144:ef7eb2e8f9f7 8074 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8075 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
<> 144:ef7eb2e8f9f7 8076
<> 144:ef7eb2e8f9f7 8077 /*!< CEC Clock source selection */
<> 144:ef7eb2e8f9f7 8078 #define RCC_CFGR3_CECSW_Pos (6U)
<> 144:ef7eb2e8f9f7 8079 #define RCC_CFGR3_CECSW_Msk (0x1U << RCC_CFGR3_CECSW_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8080 #define RCC_CFGR3_CECSW RCC_CFGR3_CECSW_Msk /*!< CECSW bits */
<> 144:ef7eb2e8f9f7 8081
<> 144:ef7eb2e8f9f7 8082 #define RCC_CFGR3_CECSW_HSI_DIV244 (0x00000000U) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
<> 144:ef7eb2e8f9f7 8083 #define RCC_CFGR3_CECSW_LSE_Pos (6U)
<> 144:ef7eb2e8f9f7 8084 #define RCC_CFGR3_CECSW_LSE_Msk (0x1U << RCC_CFGR3_CECSW_LSE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8085 #define RCC_CFGR3_CECSW_LSE RCC_CFGR3_CECSW_LSE_Msk /*!< LSE clock selected as HDMI CEC entry clock source */
<> 144:ef7eb2e8f9f7 8086
<> 144:ef7eb2e8f9f7 8087 /*!< USB Clock source selection */
<> 144:ef7eb2e8f9f7 8088 #define RCC_CFGR3_USBSW_Pos (7U)
<> 144:ef7eb2e8f9f7 8089 #define RCC_CFGR3_USBSW_Msk (0x1U << RCC_CFGR3_USBSW_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8090 #define RCC_CFGR3_USBSW RCC_CFGR3_USBSW_Msk /*!< USBSW bits */
<> 144:ef7eb2e8f9f7 8091
<> 144:ef7eb2e8f9f7 8092 #define RCC_CFGR3_USBSW_HSI48 (0x00000000U) /*!< HSI48 oscillator clock used as USB clock source */
<> 144:ef7eb2e8f9f7 8093 #define RCC_CFGR3_USBSW_PLLCLK_Pos (7U)
<> 144:ef7eb2e8f9f7 8094 #define RCC_CFGR3_USBSW_PLLCLK_Msk (0x1U << RCC_CFGR3_USBSW_PLLCLK_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8095 #define RCC_CFGR3_USBSW_PLLCLK RCC_CFGR3_USBSW_PLLCLK_Msk /*!< PLLCLK selected as USB clock source */
<> 144:ef7eb2e8f9f7 8096
<> 144:ef7eb2e8f9f7 8097 /*!< USART2 Clock source selection */
<> 144:ef7eb2e8f9f7 8098 #define RCC_CFGR3_USART2SW_Pos (16U)
<> 144:ef7eb2e8f9f7 8099 #define RCC_CFGR3_USART2SW_Msk (0x3U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */
<> 144:ef7eb2e8f9f7 8100 #define RCC_CFGR3_USART2SW RCC_CFGR3_USART2SW_Msk /*!< USART2SW[1:0] bits */
<> 144:ef7eb2e8f9f7 8101 #define RCC_CFGR3_USART2SW_0 (0x1U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8102 #define RCC_CFGR3_USART2SW_1 (0x2U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8103
<> 144:ef7eb2e8f9f7 8104 #define RCC_CFGR3_USART2SW_PCLK (0x00000000U) /*!< PCLK clock used as USART2 clock source */
<> 144:ef7eb2e8f9f7 8105 #define RCC_CFGR3_USART2SW_SYSCLK (0x00010000U) /*!< System clock selected as USART2 clock source */
<> 144:ef7eb2e8f9f7 8106 #define RCC_CFGR3_USART2SW_LSE (0x00020000U) /*!< LSE oscillator clock used as USART2 clock source */
<> 144:ef7eb2e8f9f7 8107 #define RCC_CFGR3_USART2SW_HSI (0x00030000U) /*!< HSI oscillator clock used as USART2 clock source */
<> 144:ef7eb2e8f9f7 8108
<> 144:ef7eb2e8f9f7 8109 /******************* Bit definition for RCC_CR2 register *******************/
<> 144:ef7eb2e8f9f7 8110 #define RCC_CR2_HSI14ON_Pos (0U)
<> 144:ef7eb2e8f9f7 8111 #define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8112 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */
<> 144:ef7eb2e8f9f7 8113 #define RCC_CR2_HSI14RDY_Pos (1U)
<> 144:ef7eb2e8f9f7 8114 #define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8115 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */
<> 144:ef7eb2e8f9f7 8116 #define RCC_CR2_HSI14DIS_Pos (2U)
<> 144:ef7eb2e8f9f7 8117 #define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8118 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */
<> 144:ef7eb2e8f9f7 8119 #define RCC_CR2_HSI14TRIM_Pos (3U)
<> 144:ef7eb2e8f9f7 8120 #define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
<> 144:ef7eb2e8f9f7 8121 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */
<> 144:ef7eb2e8f9f7 8122 #define RCC_CR2_HSI14CAL_Pos (8U)
<> 144:ef7eb2e8f9f7 8123 #define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 8124 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */
<> 144:ef7eb2e8f9f7 8125 #define RCC_CR2_HSI48ON_Pos (16U)
<> 144:ef7eb2e8f9f7 8126 #define RCC_CR2_HSI48ON_Msk (0x1U << RCC_CR2_HSI48ON_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8127 #define RCC_CR2_HSI48ON RCC_CR2_HSI48ON_Msk /*!< Internal High Speed 48MHz clock enable */
<> 144:ef7eb2e8f9f7 8128 #define RCC_CR2_HSI48RDY_Pos (17U)
<> 144:ef7eb2e8f9f7 8129 #define RCC_CR2_HSI48RDY_Msk (0x1U << RCC_CR2_HSI48RDY_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8130 #define RCC_CR2_HSI48RDY RCC_CR2_HSI48RDY_Msk /*!< Internal High Speed 48MHz clock ready flag */
<> 144:ef7eb2e8f9f7 8131 #define RCC_CR2_HSI48CAL_Pos (24U)
<> 144:ef7eb2e8f9f7 8132 #define RCC_CR2_HSI48CAL_Msk (0xFFU << RCC_CR2_HSI48CAL_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 8133 #define RCC_CR2_HSI48CAL RCC_CR2_HSI48CAL_Msk /*!< Internal High Speed 48MHz clock Calibration */
<> 144:ef7eb2e8f9f7 8134
<> 144:ef7eb2e8f9f7 8135 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 8136 /* */
<> 144:ef7eb2e8f9f7 8137 /* Real-Time Clock (RTC) */
<> 144:ef7eb2e8f9f7 8138 /* */
<> 144:ef7eb2e8f9f7 8139 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 8140 /*
<> 144:ef7eb2e8f9f7 8141 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 144:ef7eb2e8f9f7 8142 */
<> 144:ef7eb2e8f9f7 8143 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
<> 144:ef7eb2e8f9f7 8144 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
<> 144:ef7eb2e8f9f7 8145 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
<> 144:ef7eb2e8f9f7 8146 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
<> 144:ef7eb2e8f9f7 8147 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
<> 144:ef7eb2e8f9f7 8148
<> 144:ef7eb2e8f9f7 8149 /******************** Bits definition for RTC_TR register ******************/
<> 144:ef7eb2e8f9f7 8150 #define RTC_TR_PM_Pos (22U)
<> 144:ef7eb2e8f9f7 8151 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 8152 #define RTC_TR_PM RTC_TR_PM_Msk
<> 144:ef7eb2e8f9f7 8153 #define RTC_TR_HT_Pos (20U)
<> 144:ef7eb2e8f9f7 8154 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
<> 144:ef7eb2e8f9f7 8155 #define RTC_TR_HT RTC_TR_HT_Msk
<> 144:ef7eb2e8f9f7 8156 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 8157 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 8158 #define RTC_TR_HU_Pos (16U)
<> 144:ef7eb2e8f9f7 8159 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
<> 144:ef7eb2e8f9f7 8160 #define RTC_TR_HU RTC_TR_HU_Msk
<> 144:ef7eb2e8f9f7 8161 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8162 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8163 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 8164 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8165 #define RTC_TR_MNT_Pos (12U)
<> 144:ef7eb2e8f9f7 8166 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
<> 144:ef7eb2e8f9f7 8167 #define RTC_TR_MNT RTC_TR_MNT_Msk
<> 144:ef7eb2e8f9f7 8168 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8169 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8170 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8171 #define RTC_TR_MNU_Pos (8U)
<> 144:ef7eb2e8f9f7 8172 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 8173 #define RTC_TR_MNU RTC_TR_MNU_Msk
<> 144:ef7eb2e8f9f7 8174 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8175 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8176 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8177 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8178 #define RTC_TR_ST_Pos (4U)
<> 144:ef7eb2e8f9f7 8179 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 8180 #define RTC_TR_ST RTC_TR_ST_Msk
<> 144:ef7eb2e8f9f7 8181 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8182 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8183 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8184 #define RTC_TR_SU_Pos (0U)
<> 144:ef7eb2e8f9f7 8185 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 8186 #define RTC_TR_SU RTC_TR_SU_Msk
<> 144:ef7eb2e8f9f7 8187 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8188 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8189 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8190 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8191
<> 144:ef7eb2e8f9f7 8192 /******************** Bits definition for RTC_DR register ******************/
<> 144:ef7eb2e8f9f7 8193 #define RTC_DR_YT_Pos (20U)
<> 144:ef7eb2e8f9f7 8194 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
<> 144:ef7eb2e8f9f7 8195 #define RTC_DR_YT RTC_DR_YT_Msk
<> 144:ef7eb2e8f9f7 8196 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 8197 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 8198 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 8199 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 8200 #define RTC_DR_YU_Pos (16U)
<> 144:ef7eb2e8f9f7 8201 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
<> 144:ef7eb2e8f9f7 8202 #define RTC_DR_YU RTC_DR_YU_Msk
<> 144:ef7eb2e8f9f7 8203 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8204 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8205 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 8206 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8207 #define RTC_DR_WDU_Pos (13U)
<> 144:ef7eb2e8f9f7 8208 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
<> 144:ef7eb2e8f9f7 8209 #define RTC_DR_WDU RTC_DR_WDU_Msk
<> 144:ef7eb2e8f9f7 8210 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8211 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8212 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 8213 #define RTC_DR_MT_Pos (12U)
<> 144:ef7eb2e8f9f7 8214 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8215 #define RTC_DR_MT RTC_DR_MT_Msk
<> 144:ef7eb2e8f9f7 8216 #define RTC_DR_MU_Pos (8U)
<> 144:ef7eb2e8f9f7 8217 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 8218 #define RTC_DR_MU RTC_DR_MU_Msk
<> 144:ef7eb2e8f9f7 8219 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8220 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8221 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8222 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8223 #define RTC_DR_DT_Pos (4U)
<> 144:ef7eb2e8f9f7 8224 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
<> 144:ef7eb2e8f9f7 8225 #define RTC_DR_DT RTC_DR_DT_Msk
<> 144:ef7eb2e8f9f7 8226 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8227 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8228 #define RTC_DR_DU_Pos (0U)
<> 144:ef7eb2e8f9f7 8229 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 8230 #define RTC_DR_DU RTC_DR_DU_Msk
<> 144:ef7eb2e8f9f7 8231 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8232 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8233 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8234 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8235
<> 144:ef7eb2e8f9f7 8236 /******************** Bits definition for RTC_CR register ******************/
<> 144:ef7eb2e8f9f7 8237 #define RTC_CR_COE_Pos (23U)
<> 144:ef7eb2e8f9f7 8238 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 8239 #define RTC_CR_COE RTC_CR_COE_Msk
<> 144:ef7eb2e8f9f7 8240 #define RTC_CR_OSEL_Pos (21U)
<> 144:ef7eb2e8f9f7 8241 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
<> 144:ef7eb2e8f9f7 8242 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
<> 144:ef7eb2e8f9f7 8243 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 8244 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 8245 #define RTC_CR_POL_Pos (20U)
<> 144:ef7eb2e8f9f7 8246 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 8247 #define RTC_CR_POL RTC_CR_POL_Msk
<> 144:ef7eb2e8f9f7 8248 #define RTC_CR_COSEL_Pos (19U)
<> 144:ef7eb2e8f9f7 8249 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8250 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
<> 144:ef7eb2e8f9f7 8251 #define RTC_CR_BCK_Pos (18U)
<> 144:ef7eb2e8f9f7 8252 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 8253 #define RTC_CR_BCK RTC_CR_BCK_Msk
<> 144:ef7eb2e8f9f7 8254 #define RTC_CR_SUB1H_Pos (17U)
<> 144:ef7eb2e8f9f7 8255 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8256 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
<> 144:ef7eb2e8f9f7 8257 #define RTC_CR_ADD1H_Pos (16U)
<> 144:ef7eb2e8f9f7 8258 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8259 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
<> 144:ef7eb2e8f9f7 8260 #define RTC_CR_TSIE_Pos (15U)
<> 144:ef7eb2e8f9f7 8261 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 8262 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
<> 144:ef7eb2e8f9f7 8263 #define RTC_CR_WUTIE_Pos (14U)
<> 144:ef7eb2e8f9f7 8264 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8265 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
<> 144:ef7eb2e8f9f7 8266 #define RTC_CR_ALRAIE_Pos (12U)
<> 144:ef7eb2e8f9f7 8267 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8268 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
<> 144:ef7eb2e8f9f7 8269 #define RTC_CR_TSE_Pos (11U)
<> 144:ef7eb2e8f9f7 8270 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8271 #define RTC_CR_TSE RTC_CR_TSE_Msk
<> 144:ef7eb2e8f9f7 8272 #define RTC_CR_WUTE_Pos (10U)
<> 144:ef7eb2e8f9f7 8273 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8274 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
<> 144:ef7eb2e8f9f7 8275 #define RTC_CR_ALRAE_Pos (8U)
<> 144:ef7eb2e8f9f7 8276 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8277 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
<> 144:ef7eb2e8f9f7 8278 #define RTC_CR_FMT_Pos (6U)
<> 144:ef7eb2e8f9f7 8279 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8280 #define RTC_CR_FMT RTC_CR_FMT_Msk
<> 144:ef7eb2e8f9f7 8281 #define RTC_CR_BYPSHAD_Pos (5U)
<> 144:ef7eb2e8f9f7 8282 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8283 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
<> 144:ef7eb2e8f9f7 8284 #define RTC_CR_REFCKON_Pos (4U)
<> 144:ef7eb2e8f9f7 8285 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8286 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
<> 144:ef7eb2e8f9f7 8287 #define RTC_CR_TSEDGE_Pos (3U)
<> 144:ef7eb2e8f9f7 8288 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8289 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
<> 144:ef7eb2e8f9f7 8290 #define RTC_CR_WUCKSEL_Pos (0U)
<> 144:ef7eb2e8f9f7 8291 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
<> 144:ef7eb2e8f9f7 8292 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
<> 144:ef7eb2e8f9f7 8293 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8294 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8295 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8296
<> 144:ef7eb2e8f9f7 8297 /******************** Bits definition for RTC_ISR register *****************/
<> 144:ef7eb2e8f9f7 8298 #define RTC_ISR_RECALPF_Pos (16U)
<> 144:ef7eb2e8f9f7 8299 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8300 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
<> 144:ef7eb2e8f9f7 8301 #define RTC_ISR_TAMP3F_Pos (15U)
<> 144:ef7eb2e8f9f7 8302 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 8303 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
<> 144:ef7eb2e8f9f7 8304 #define RTC_ISR_TAMP2F_Pos (14U)
<> 144:ef7eb2e8f9f7 8305 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8306 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
<> 144:ef7eb2e8f9f7 8307 #define RTC_ISR_TAMP1F_Pos (13U)
<> 144:ef7eb2e8f9f7 8308 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8309 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
<> 144:ef7eb2e8f9f7 8310 #define RTC_ISR_TSOVF_Pos (12U)
<> 144:ef7eb2e8f9f7 8311 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8312 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
<> 144:ef7eb2e8f9f7 8313 #define RTC_ISR_TSF_Pos (11U)
<> 144:ef7eb2e8f9f7 8314 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8315 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
<> 144:ef7eb2e8f9f7 8316 #define RTC_ISR_WUTF_Pos (10U)
<> 144:ef7eb2e8f9f7 8317 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8318 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
<> 144:ef7eb2e8f9f7 8319 #define RTC_ISR_ALRAF_Pos (8U)
<> 144:ef7eb2e8f9f7 8320 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8321 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
<> 144:ef7eb2e8f9f7 8322 #define RTC_ISR_INIT_Pos (7U)
<> 144:ef7eb2e8f9f7 8323 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8324 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
<> 144:ef7eb2e8f9f7 8325 #define RTC_ISR_INITF_Pos (6U)
<> 144:ef7eb2e8f9f7 8326 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8327 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
<> 144:ef7eb2e8f9f7 8328 #define RTC_ISR_RSF_Pos (5U)
<> 144:ef7eb2e8f9f7 8329 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8330 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
<> 144:ef7eb2e8f9f7 8331 #define RTC_ISR_INITS_Pos (4U)
<> 144:ef7eb2e8f9f7 8332 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8333 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
<> 144:ef7eb2e8f9f7 8334 #define RTC_ISR_SHPF_Pos (3U)
<> 144:ef7eb2e8f9f7 8335 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8336 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
<> 144:ef7eb2e8f9f7 8337 #define RTC_ISR_WUTWF_Pos (2U)
<> 144:ef7eb2e8f9f7 8338 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8339 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
<> 144:ef7eb2e8f9f7 8340 #define RTC_ISR_ALRAWF_Pos (0U)
<> 144:ef7eb2e8f9f7 8341 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8342 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
<> 144:ef7eb2e8f9f7 8343
<> 144:ef7eb2e8f9f7 8344 /******************** Bits definition for RTC_PRER register ****************/
<> 144:ef7eb2e8f9f7 8345 #define RTC_PRER_PREDIV_A_Pos (16U)
<> 144:ef7eb2e8f9f7 8346 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
<> 144:ef7eb2e8f9f7 8347 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
<> 144:ef7eb2e8f9f7 8348 #define RTC_PRER_PREDIV_S_Pos (0U)
<> 144:ef7eb2e8f9f7 8349 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
<> 144:ef7eb2e8f9f7 8350 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
<> 144:ef7eb2e8f9f7 8351
<> 144:ef7eb2e8f9f7 8352 /******************** Bits definition for RTC_WUTR register ****************/
<> 144:ef7eb2e8f9f7 8353 #define RTC_WUTR_WUT_Pos (0U)
<> 144:ef7eb2e8f9f7 8354 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 8355 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
<> 144:ef7eb2e8f9f7 8356
<> 144:ef7eb2e8f9f7 8357 /******************** Bits definition for RTC_ALRMAR register **************/
<> 144:ef7eb2e8f9f7 8358 #define RTC_ALRMAR_MSK4_Pos (31U)
<> 144:ef7eb2e8f9f7 8359 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8360 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
<> 144:ef7eb2e8f9f7 8361 #define RTC_ALRMAR_WDSEL_Pos (30U)
<> 144:ef7eb2e8f9f7 8362 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 8363 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
<> 144:ef7eb2e8f9f7 8364 #define RTC_ALRMAR_DT_Pos (28U)
<> 144:ef7eb2e8f9f7 8365 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
<> 144:ef7eb2e8f9f7 8366 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
<> 144:ef7eb2e8f9f7 8367 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 8368 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8369 #define RTC_ALRMAR_DU_Pos (24U)
<> 144:ef7eb2e8f9f7 8370 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
<> 144:ef7eb2e8f9f7 8371 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
<> 144:ef7eb2e8f9f7 8372 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 8373 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 8374 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 8375 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 8376 #define RTC_ALRMAR_MSK3_Pos (23U)
<> 144:ef7eb2e8f9f7 8377 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 8378 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
<> 144:ef7eb2e8f9f7 8379 #define RTC_ALRMAR_PM_Pos (22U)
<> 144:ef7eb2e8f9f7 8380 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 8381 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
<> 144:ef7eb2e8f9f7 8382 #define RTC_ALRMAR_HT_Pos (20U)
<> 144:ef7eb2e8f9f7 8383 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
<> 144:ef7eb2e8f9f7 8384 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
<> 144:ef7eb2e8f9f7 8385 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 8386 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 8387 #define RTC_ALRMAR_HU_Pos (16U)
<> 144:ef7eb2e8f9f7 8388 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
<> 144:ef7eb2e8f9f7 8389 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
<> 144:ef7eb2e8f9f7 8390 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8391 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8392 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 8393 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8394 #define RTC_ALRMAR_MSK2_Pos (15U)
<> 144:ef7eb2e8f9f7 8395 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 8396 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
<> 144:ef7eb2e8f9f7 8397 #define RTC_ALRMAR_MNT_Pos (12U)
<> 144:ef7eb2e8f9f7 8398 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
<> 144:ef7eb2e8f9f7 8399 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
<> 144:ef7eb2e8f9f7 8400 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8401 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8402 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8403 #define RTC_ALRMAR_MNU_Pos (8U)
<> 144:ef7eb2e8f9f7 8404 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 8405 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
<> 144:ef7eb2e8f9f7 8406 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8407 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8408 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8409 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8410 #define RTC_ALRMAR_MSK1_Pos (7U)
<> 144:ef7eb2e8f9f7 8411 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8412 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
<> 144:ef7eb2e8f9f7 8413 #define RTC_ALRMAR_ST_Pos (4U)
<> 144:ef7eb2e8f9f7 8414 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 8415 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
<> 144:ef7eb2e8f9f7 8416 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8417 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8418 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8419 #define RTC_ALRMAR_SU_Pos (0U)
<> 144:ef7eb2e8f9f7 8420 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 8421 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
<> 144:ef7eb2e8f9f7 8422 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8423 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8424 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8425 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8426
<> 144:ef7eb2e8f9f7 8427 /******************** Bits definition for RTC_WPR register *****************/
<> 144:ef7eb2e8f9f7 8428 #define RTC_WPR_KEY_Pos (0U)
<> 144:ef7eb2e8f9f7 8429 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 8430 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
<> 144:ef7eb2e8f9f7 8431
<> 144:ef7eb2e8f9f7 8432 /******************** Bits definition for RTC_SSR register *****************/
<> 144:ef7eb2e8f9f7 8433 #define RTC_SSR_SS_Pos (0U)
<> 144:ef7eb2e8f9f7 8434 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 8435 #define RTC_SSR_SS RTC_SSR_SS_Msk
<> 144:ef7eb2e8f9f7 8436
<> 144:ef7eb2e8f9f7 8437 /******************** Bits definition for RTC_SHIFTR register **************/
<> 144:ef7eb2e8f9f7 8438 #define RTC_SHIFTR_SUBFS_Pos (0U)
<> 144:ef7eb2e8f9f7 8439 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
<> 144:ef7eb2e8f9f7 8440 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
<> 144:ef7eb2e8f9f7 8441 #define RTC_SHIFTR_ADD1S_Pos (31U)
<> 144:ef7eb2e8f9f7 8442 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8443 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
<> 144:ef7eb2e8f9f7 8444
<> 144:ef7eb2e8f9f7 8445 /******************** Bits definition for RTC_TSTR register ****************/
<> 144:ef7eb2e8f9f7 8446 #define RTC_TSTR_PM_Pos (22U)
<> 144:ef7eb2e8f9f7 8447 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 8448 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
<> 144:ef7eb2e8f9f7 8449 #define RTC_TSTR_HT_Pos (20U)
<> 144:ef7eb2e8f9f7 8450 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
<> 144:ef7eb2e8f9f7 8451 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
<> 144:ef7eb2e8f9f7 8452 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 8453 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 8454 #define RTC_TSTR_HU_Pos (16U)
<> 144:ef7eb2e8f9f7 8455 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
<> 144:ef7eb2e8f9f7 8456 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
<> 144:ef7eb2e8f9f7 8457 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8458 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8459 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 8460 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8461 #define RTC_TSTR_MNT_Pos (12U)
<> 144:ef7eb2e8f9f7 8462 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
<> 144:ef7eb2e8f9f7 8463 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
<> 144:ef7eb2e8f9f7 8464 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8465 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8466 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8467 #define RTC_TSTR_MNU_Pos (8U)
<> 144:ef7eb2e8f9f7 8468 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 8469 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
<> 144:ef7eb2e8f9f7 8470 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8471 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8472 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8473 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8474 #define RTC_TSTR_ST_Pos (4U)
<> 144:ef7eb2e8f9f7 8475 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 8476 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
<> 144:ef7eb2e8f9f7 8477 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8478 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8479 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8480 #define RTC_TSTR_SU_Pos (0U)
<> 144:ef7eb2e8f9f7 8481 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 8482 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
<> 144:ef7eb2e8f9f7 8483 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8484 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8485 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8486 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8487
<> 144:ef7eb2e8f9f7 8488 /******************** Bits definition for RTC_TSDR register ****************/
<> 144:ef7eb2e8f9f7 8489 #define RTC_TSDR_WDU_Pos (13U)
<> 144:ef7eb2e8f9f7 8490 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
<> 144:ef7eb2e8f9f7 8491 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
<> 144:ef7eb2e8f9f7 8492 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8493 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8494 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 8495 #define RTC_TSDR_MT_Pos (12U)
<> 144:ef7eb2e8f9f7 8496 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8497 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
<> 144:ef7eb2e8f9f7 8498 #define RTC_TSDR_MU_Pos (8U)
<> 144:ef7eb2e8f9f7 8499 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 8500 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
<> 144:ef7eb2e8f9f7 8501 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8502 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8503 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8504 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8505 #define RTC_TSDR_DT_Pos (4U)
<> 144:ef7eb2e8f9f7 8506 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
<> 144:ef7eb2e8f9f7 8507 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
<> 144:ef7eb2e8f9f7 8508 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8509 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8510 #define RTC_TSDR_DU_Pos (0U)
<> 144:ef7eb2e8f9f7 8511 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 8512 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
<> 144:ef7eb2e8f9f7 8513 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8514 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8515 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8516 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8517
<> 144:ef7eb2e8f9f7 8518 /******************** Bits definition for RTC_TSSSR register ***************/
<> 144:ef7eb2e8f9f7 8519 #define RTC_TSSSR_SS_Pos (0U)
<> 144:ef7eb2e8f9f7 8520 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 8521 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
<> 144:ef7eb2e8f9f7 8522
<> 144:ef7eb2e8f9f7 8523 /******************** Bits definition for RTC_CALR register ****************/
<> 144:ef7eb2e8f9f7 8524 #define RTC_CALR_CALP_Pos (15U)
<> 144:ef7eb2e8f9f7 8525 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 8526 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
<> 144:ef7eb2e8f9f7 8527 #define RTC_CALR_CALW8_Pos (14U)
<> 144:ef7eb2e8f9f7 8528 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8529 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
<> 144:ef7eb2e8f9f7 8530 #define RTC_CALR_CALW16_Pos (13U)
<> 144:ef7eb2e8f9f7 8531 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8532 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
<> 144:ef7eb2e8f9f7 8533 #define RTC_CALR_CALM_Pos (0U)
<> 144:ef7eb2e8f9f7 8534 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
<> 144:ef7eb2e8f9f7 8535 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
<> 144:ef7eb2e8f9f7 8536 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8537 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8538 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8539 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8540 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8541 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8542 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8543 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8544 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8545
<> 144:ef7eb2e8f9f7 8546 /******************** Bits definition for RTC_TAFCR register ***************/
<> 144:ef7eb2e8f9f7 8547 #define RTC_TAFCR_PC15MODE_Pos (23U)
<> 144:ef7eb2e8f9f7 8548 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 8549 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
<> 144:ef7eb2e8f9f7 8550 #define RTC_TAFCR_PC15VALUE_Pos (22U)
<> 144:ef7eb2e8f9f7 8551 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 8552 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
<> 144:ef7eb2e8f9f7 8553 #define RTC_TAFCR_PC14MODE_Pos (21U)
<> 144:ef7eb2e8f9f7 8554 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 8555 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
<> 144:ef7eb2e8f9f7 8556 #define RTC_TAFCR_PC14VALUE_Pos (20U)
<> 144:ef7eb2e8f9f7 8557 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 8558 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
<> 144:ef7eb2e8f9f7 8559 #define RTC_TAFCR_PC13MODE_Pos (19U)
<> 144:ef7eb2e8f9f7 8560 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8561 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
<> 144:ef7eb2e8f9f7 8562 #define RTC_TAFCR_PC13VALUE_Pos (18U)
<> 144:ef7eb2e8f9f7 8563 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 8564 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
<> 144:ef7eb2e8f9f7 8565 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
<> 144:ef7eb2e8f9f7 8566 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 8567 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
<> 144:ef7eb2e8f9f7 8568 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
<> 144:ef7eb2e8f9f7 8569 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
<> 144:ef7eb2e8f9f7 8570 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
<> 144:ef7eb2e8f9f7 8571 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8572 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8573 #define RTC_TAFCR_TAMPFLT_Pos (11U)
<> 144:ef7eb2e8f9f7 8574 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
<> 144:ef7eb2e8f9f7 8575 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
<> 144:ef7eb2e8f9f7 8576 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8577 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8578 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
<> 144:ef7eb2e8f9f7 8579 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
<> 144:ef7eb2e8f9f7 8580 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
<> 144:ef7eb2e8f9f7 8581 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8582 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8583 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8584 #define RTC_TAFCR_TAMPTS_Pos (7U)
<> 144:ef7eb2e8f9f7 8585 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8586 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
<> 144:ef7eb2e8f9f7 8587 #define RTC_TAFCR_TAMP3TRG_Pos (6U)
<> 144:ef7eb2e8f9f7 8588 #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8589 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
<> 144:ef7eb2e8f9f7 8590 #define RTC_TAFCR_TAMP3E_Pos (5U)
<> 144:ef7eb2e8f9f7 8591 #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8592 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
<> 144:ef7eb2e8f9f7 8593 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
<> 144:ef7eb2e8f9f7 8594 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8595 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
<> 144:ef7eb2e8f9f7 8596 #define RTC_TAFCR_TAMP2E_Pos (3U)
<> 144:ef7eb2e8f9f7 8597 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8598 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
<> 144:ef7eb2e8f9f7 8599 #define RTC_TAFCR_TAMPIE_Pos (2U)
<> 144:ef7eb2e8f9f7 8600 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8601 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
<> 144:ef7eb2e8f9f7 8602 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
<> 144:ef7eb2e8f9f7 8603 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8604 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
<> 144:ef7eb2e8f9f7 8605 #define RTC_TAFCR_TAMP1E_Pos (0U)
<> 144:ef7eb2e8f9f7 8606 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8607 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
<> 144:ef7eb2e8f9f7 8608
<> 144:ef7eb2e8f9f7 8609 /* Reference defines */
<> 144:ef7eb2e8f9f7 8610 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
<> 144:ef7eb2e8f9f7 8611
<> 144:ef7eb2e8f9f7 8612 /******************** Bits definition for RTC_ALRMASSR register ************/
<> 144:ef7eb2e8f9f7 8613 #define RTC_ALRMASSR_MASKSS_Pos (24U)
<> 144:ef7eb2e8f9f7 8614 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 144:ef7eb2e8f9f7 8615 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
<> 144:ef7eb2e8f9f7 8616 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 8617 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 8618 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 8619 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 8620 #define RTC_ALRMASSR_SS_Pos (0U)
<> 144:ef7eb2e8f9f7 8621 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
<> 144:ef7eb2e8f9f7 8622 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
<> 144:ef7eb2e8f9f7 8623
<> 144:ef7eb2e8f9f7 8624 /******************** Bits definition for RTC_BKP0R register ***************/
<> 144:ef7eb2e8f9f7 8625 #define RTC_BKP0R_Pos (0U)
<> 144:ef7eb2e8f9f7 8626 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8627 #define RTC_BKP0R RTC_BKP0R_Msk
<> 144:ef7eb2e8f9f7 8628
<> 144:ef7eb2e8f9f7 8629 /******************** Bits definition for RTC_BKP1R register ***************/
<> 144:ef7eb2e8f9f7 8630 #define RTC_BKP1R_Pos (0U)
<> 144:ef7eb2e8f9f7 8631 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8632 #define RTC_BKP1R RTC_BKP1R_Msk
<> 144:ef7eb2e8f9f7 8633
<> 144:ef7eb2e8f9f7 8634 /******************** Bits definition for RTC_BKP2R register ***************/
<> 144:ef7eb2e8f9f7 8635 #define RTC_BKP2R_Pos (0U)
<> 144:ef7eb2e8f9f7 8636 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8637 #define RTC_BKP2R RTC_BKP2R_Msk
<> 144:ef7eb2e8f9f7 8638
<> 144:ef7eb2e8f9f7 8639 /******************** Bits definition for RTC_BKP3R register ***************/
<> 144:ef7eb2e8f9f7 8640 #define RTC_BKP3R_Pos (0U)
<> 144:ef7eb2e8f9f7 8641 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8642 #define RTC_BKP3R RTC_BKP3R_Msk
<> 144:ef7eb2e8f9f7 8643
<> 144:ef7eb2e8f9f7 8644 /******************** Bits definition for RTC_BKP4R register ***************/
<> 144:ef7eb2e8f9f7 8645 #define RTC_BKP4R_Pos (0U)
<> 144:ef7eb2e8f9f7 8646 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8647 #define RTC_BKP4R RTC_BKP4R_Msk
<> 144:ef7eb2e8f9f7 8648
<> 144:ef7eb2e8f9f7 8649 /******************** Number of backup registers ******************************/
<> 144:ef7eb2e8f9f7 8650 #define RTC_BKP_NUMBER 0x00000005U
<> 144:ef7eb2e8f9f7 8651
<> 144:ef7eb2e8f9f7 8652 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 8653 /* */
<> 144:ef7eb2e8f9f7 8654 /* Serial Peripheral Interface (SPI) */
<> 144:ef7eb2e8f9f7 8655 /* */
<> 144:ef7eb2e8f9f7 8656 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 8657
<> 144:ef7eb2e8f9f7 8658 /*
<> 144:ef7eb2e8f9f7 8659 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 144:ef7eb2e8f9f7 8660 */
<> 144:ef7eb2e8f9f7 8661 #define SPI_I2S_SUPPORT /*!< I2S support */
<> 144:ef7eb2e8f9f7 8662
<> 144:ef7eb2e8f9f7 8663 /******************* Bit definition for SPI_CR1 register *******************/
<> 144:ef7eb2e8f9f7 8664 #define SPI_CR1_CPHA_Pos (0U)
<> 144:ef7eb2e8f9f7 8665 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8666 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
<> 144:ef7eb2e8f9f7 8667 #define SPI_CR1_CPOL_Pos (1U)
<> 144:ef7eb2e8f9f7 8668 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8669 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
<> 144:ef7eb2e8f9f7 8670 #define SPI_CR1_MSTR_Pos (2U)
<> 144:ef7eb2e8f9f7 8671 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8672 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
<> 144:ef7eb2e8f9f7 8673 #define SPI_CR1_BR_Pos (3U)
<> 144:ef7eb2e8f9f7 8674 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
<> 144:ef7eb2e8f9f7 8675 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
<> 144:ef7eb2e8f9f7 8676 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8677 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8678 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8679 #define SPI_CR1_SPE_Pos (6U)
<> 144:ef7eb2e8f9f7 8680 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8681 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
<> 144:ef7eb2e8f9f7 8682 #define SPI_CR1_LSBFIRST_Pos (7U)
<> 144:ef7eb2e8f9f7 8683 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8684 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
<> 144:ef7eb2e8f9f7 8685 #define SPI_CR1_SSI_Pos (8U)
<> 144:ef7eb2e8f9f7 8686 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8687 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
<> 144:ef7eb2e8f9f7 8688 #define SPI_CR1_SSM_Pos (9U)
<> 144:ef7eb2e8f9f7 8689 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8690 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
<> 144:ef7eb2e8f9f7 8691 #define SPI_CR1_RXONLY_Pos (10U)
<> 144:ef7eb2e8f9f7 8692 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8693 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
<> 144:ef7eb2e8f9f7 8694 #define SPI_CR1_CRCL_Pos (11U)
<> 144:ef7eb2e8f9f7 8695 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8696 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
<> 144:ef7eb2e8f9f7 8697 #define SPI_CR1_CRCNEXT_Pos (12U)
<> 144:ef7eb2e8f9f7 8698 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8699 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
<> 144:ef7eb2e8f9f7 8700 #define SPI_CR1_CRCEN_Pos (13U)
<> 144:ef7eb2e8f9f7 8701 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8702 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
<> 144:ef7eb2e8f9f7 8703 #define SPI_CR1_BIDIOE_Pos (14U)
<> 144:ef7eb2e8f9f7 8704 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8705 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
<> 144:ef7eb2e8f9f7 8706 #define SPI_CR1_BIDIMODE_Pos (15U)
<> 144:ef7eb2e8f9f7 8707 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 8708 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
<> 144:ef7eb2e8f9f7 8709
<> 144:ef7eb2e8f9f7 8710 /******************* Bit definition for SPI_CR2 register *******************/
<> 144:ef7eb2e8f9f7 8711 #define SPI_CR2_RXDMAEN_Pos (0U)
<> 144:ef7eb2e8f9f7 8712 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8713 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 8714 #define SPI_CR2_TXDMAEN_Pos (1U)
<> 144:ef7eb2e8f9f7 8715 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8716 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 8717 #define SPI_CR2_SSOE_Pos (2U)
<> 144:ef7eb2e8f9f7 8718 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8719 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
<> 144:ef7eb2e8f9f7 8720 #define SPI_CR2_NSSP_Pos (3U)
<> 144:ef7eb2e8f9f7 8721 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8722 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
<> 144:ef7eb2e8f9f7 8723 #define SPI_CR2_FRF_Pos (4U)
<> 144:ef7eb2e8f9f7 8724 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8725 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
<> 144:ef7eb2e8f9f7 8726 #define SPI_CR2_ERRIE_Pos (5U)
<> 144:ef7eb2e8f9f7 8727 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8728 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 8729 #define SPI_CR2_RXNEIE_Pos (6U)
<> 144:ef7eb2e8f9f7 8730 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8731 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 8732 #define SPI_CR2_TXEIE_Pos (7U)
<> 144:ef7eb2e8f9f7 8733 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8734 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 8735 #define SPI_CR2_DS_Pos (8U)
<> 144:ef7eb2e8f9f7 8736 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 8737 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
<> 144:ef7eb2e8f9f7 8738 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8739 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8740 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8741 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8742 #define SPI_CR2_FRXTH_Pos (12U)
<> 144:ef7eb2e8f9f7 8743 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8744 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
<> 144:ef7eb2e8f9f7 8745 #define SPI_CR2_LDMARX_Pos (13U)
<> 144:ef7eb2e8f9f7 8746 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8747 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
<> 144:ef7eb2e8f9f7 8748 #define SPI_CR2_LDMATX_Pos (14U)
<> 144:ef7eb2e8f9f7 8749 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8750 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
<> 144:ef7eb2e8f9f7 8751
<> 144:ef7eb2e8f9f7 8752 /******************** Bit definition for SPI_SR register *******************/
<> 144:ef7eb2e8f9f7 8753 #define SPI_SR_RXNE_Pos (0U)
<> 144:ef7eb2e8f9f7 8754 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8755 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
<> 144:ef7eb2e8f9f7 8756 #define SPI_SR_TXE_Pos (1U)
<> 144:ef7eb2e8f9f7 8757 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8758 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
<> 144:ef7eb2e8f9f7 8759 #define SPI_SR_CHSIDE_Pos (2U)
<> 144:ef7eb2e8f9f7 8760 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8761 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
<> 144:ef7eb2e8f9f7 8762 #define SPI_SR_UDR_Pos (3U)
<> 144:ef7eb2e8f9f7 8763 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8764 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
<> 144:ef7eb2e8f9f7 8765 #define SPI_SR_CRCERR_Pos (4U)
<> 144:ef7eb2e8f9f7 8766 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8767 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
<> 144:ef7eb2e8f9f7 8768 #define SPI_SR_MODF_Pos (5U)
<> 144:ef7eb2e8f9f7 8769 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8770 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
<> 144:ef7eb2e8f9f7 8771 #define SPI_SR_OVR_Pos (6U)
<> 144:ef7eb2e8f9f7 8772 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 8773 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
<> 144:ef7eb2e8f9f7 8774 #define SPI_SR_BSY_Pos (7U)
<> 144:ef7eb2e8f9f7 8775 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8776 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
<> 144:ef7eb2e8f9f7 8777 #define SPI_SR_FRE_Pos (8U)
<> 144:ef7eb2e8f9f7 8778 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8779 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
<> 144:ef7eb2e8f9f7 8780 #define SPI_SR_FRLVL_Pos (9U)
<> 144:ef7eb2e8f9f7 8781 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
<> 144:ef7eb2e8f9f7 8782 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
<> 144:ef7eb2e8f9f7 8783 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8784 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8785 #define SPI_SR_FTLVL_Pos (11U)
<> 144:ef7eb2e8f9f7 8786 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
<> 144:ef7eb2e8f9f7 8787 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
<> 144:ef7eb2e8f9f7 8788 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8789 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8790
<> 144:ef7eb2e8f9f7 8791 /******************** Bit definition for SPI_DR register *******************/
<> 144:ef7eb2e8f9f7 8792 #define SPI_DR_DR_Pos (0U)
<> 144:ef7eb2e8f9f7 8793 #define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8794 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
<> 144:ef7eb2e8f9f7 8795
<> 144:ef7eb2e8f9f7 8796 /******************* Bit definition for SPI_CRCPR register *****************/
<> 144:ef7eb2e8f9f7 8797 #define SPI_CRCPR_CRCPOLY_Pos (0U)
<> 144:ef7eb2e8f9f7 8798 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8799 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
<> 144:ef7eb2e8f9f7 8800
<> 144:ef7eb2e8f9f7 8801 /****************** Bit definition for SPI_RXCRCR register *****************/
<> 144:ef7eb2e8f9f7 8802 #define SPI_RXCRCR_RXCRC_Pos (0U)
<> 144:ef7eb2e8f9f7 8803 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8804 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
<> 144:ef7eb2e8f9f7 8805
<> 144:ef7eb2e8f9f7 8806 /****************** Bit definition for SPI_TXCRCR register *****************/
<> 144:ef7eb2e8f9f7 8807 #define SPI_TXCRCR_TXCRC_Pos (0U)
<> 144:ef7eb2e8f9f7 8808 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 8809 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
<> 144:ef7eb2e8f9f7 8810
<> 144:ef7eb2e8f9f7 8811 /****************** Bit definition for SPI_I2SCFGR register ****************/
<> 144:ef7eb2e8f9f7 8812 #define SPI_I2SCFGR_CHLEN_Pos (0U)
<> 144:ef7eb2e8f9f7 8813 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8814 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
<> 144:ef7eb2e8f9f7 8815 #define SPI_I2SCFGR_DATLEN_Pos (1U)
<> 144:ef7eb2e8f9f7 8816 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
<> 144:ef7eb2e8f9f7 8817 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 144:ef7eb2e8f9f7 8818 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8819 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8820 #define SPI_I2SCFGR_CKPOL_Pos (3U)
<> 144:ef7eb2e8f9f7 8821 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8822 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
<> 144:ef7eb2e8f9f7 8823 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
<> 144:ef7eb2e8f9f7 8824 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
<> 144:ef7eb2e8f9f7 8825 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 144:ef7eb2e8f9f7 8826 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 8827 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 8828 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
<> 144:ef7eb2e8f9f7 8829 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 8830 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
<> 144:ef7eb2e8f9f7 8831 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
<> 144:ef7eb2e8f9f7 8832 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 8833 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 144:ef7eb2e8f9f7 8834 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8835 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8836 #define SPI_I2SCFGR_I2SE_Pos (10U)
<> 144:ef7eb2e8f9f7 8837 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8838 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
<> 144:ef7eb2e8f9f7 8839 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
<> 144:ef7eb2e8f9f7 8840 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8841 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
<> 144:ef7eb2e8f9f7 8842
<> 144:ef7eb2e8f9f7 8843 /****************** Bit definition for SPI_I2SPR register ******************/
<> 144:ef7eb2e8f9f7 8844 #define SPI_I2SPR_I2SDIV_Pos (0U)
<> 144:ef7eb2e8f9f7 8845 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 8846 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
<> 144:ef7eb2e8f9f7 8847 #define SPI_I2SPR_ODD_Pos (8U)
<> 144:ef7eb2e8f9f7 8848 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8849 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
<> 144:ef7eb2e8f9f7 8850 #define SPI_I2SPR_MCKOE_Pos (9U)
<> 144:ef7eb2e8f9f7 8851 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8852 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
<> 144:ef7eb2e8f9f7 8853
<> 144:ef7eb2e8f9f7 8854 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 8855 /* */
<> 144:ef7eb2e8f9f7 8856 /* System Configuration (SYSCFG) */
<> 144:ef7eb2e8f9f7 8857 /* */
<> 144:ef7eb2e8f9f7 8858 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 8859 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
<> 144:ef7eb2e8f9f7 8860 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
<> 144:ef7eb2e8f9f7 8861 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 8862 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
<> 144:ef7eb2e8f9f7 8863 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 8864 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 8865
<> 144:ef7eb2e8f9f7 8866 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
<> 144:ef7eb2e8f9f7 8867 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x7F007FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x7F007F00 */
<> 144:ef7eb2e8f9f7 8868 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
<> 144:ef7eb2e8f9f7 8869 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U)
<> 144:ef7eb2e8f9f7 8870 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 8871 #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */
<> 144:ef7eb2e8f9f7 8872 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U)
<> 144:ef7eb2e8f9f7 8873 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 8874 #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */
<> 144:ef7eb2e8f9f7 8875 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U)
<> 144:ef7eb2e8f9f7 8876 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 8877 #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */
<> 144:ef7eb2e8f9f7 8878 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
<> 144:ef7eb2e8f9f7 8879 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 8880 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
<> 144:ef7eb2e8f9f7 8881 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
<> 144:ef7eb2e8f9f7 8882 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 8883 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
<> 144:ef7eb2e8f9f7 8884 #define SYSCFG_CFGR1_TIM16_DMA_RMP2_Pos (13U)
<> 144:ef7eb2e8f9f7 8885 #define SYSCFG_CFGR1_TIM16_DMA_RMP2_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP2_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 8886 #define SYSCFG_CFGR1_TIM16_DMA_RMP2 SYSCFG_CFGR1_TIM16_DMA_RMP2_Msk /*!< Timer 16 DMA remap 2 */
<> 144:ef7eb2e8f9f7 8887 #define SYSCFG_CFGR1_TIM17_DMA_RMP2_Pos (14U)
<> 144:ef7eb2e8f9f7 8888 #define SYSCFG_CFGR1_TIM17_DMA_RMP2_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP2_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8889 #define SYSCFG_CFGR1_TIM17_DMA_RMP2 SYSCFG_CFGR1_TIM17_DMA_RMP2_Msk /*!< Timer 17 DMA remap 2 */
<> 144:ef7eb2e8f9f7 8890 #define SYSCFG_CFGR1_SPI2_DMA_RMP_Pos (24U)
<> 144:ef7eb2e8f9f7 8891 #define SYSCFG_CFGR1_SPI2_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_SPI2_DMA_RMP_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 8892 #define SYSCFG_CFGR1_SPI2_DMA_RMP SYSCFG_CFGR1_SPI2_DMA_RMP_Msk /*!< SPI2 DMA remap */
<> 144:ef7eb2e8f9f7 8893 #define SYSCFG_CFGR1_USART2_DMA_RMP_Pos (25U)
<> 144:ef7eb2e8f9f7 8894 #define SYSCFG_CFGR1_USART2_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART2_DMA_RMP_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 8895 #define SYSCFG_CFGR1_USART2_DMA_RMP SYSCFG_CFGR1_USART2_DMA_RMP_Msk /*!< USART2 DMA remap */
<> 144:ef7eb2e8f9f7 8896 #define SYSCFG_CFGR1_USART3_DMA_RMP_Pos (26U)
<> 144:ef7eb2e8f9f7 8897 #define SYSCFG_CFGR1_USART3_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART3_DMA_RMP_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 8898 #define SYSCFG_CFGR1_USART3_DMA_RMP SYSCFG_CFGR1_USART3_DMA_RMP_Msk /*!< USART3 DMA remap */
<> 144:ef7eb2e8f9f7 8899 #define SYSCFG_CFGR1_I2C1_DMA_RMP_Pos (27U)
<> 144:ef7eb2e8f9f7 8900 #define SYSCFG_CFGR1_I2C1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_DMA_RMP_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 8901 #define SYSCFG_CFGR1_I2C1_DMA_RMP SYSCFG_CFGR1_I2C1_DMA_RMP_Msk /*!< I2C1 DMA remap */
<> 144:ef7eb2e8f9f7 8902 #define SYSCFG_CFGR1_TIM1_DMA_RMP_Pos (28U)
<> 144:ef7eb2e8f9f7 8903 #define SYSCFG_CFGR1_TIM1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM1_DMA_RMP_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 8904 #define SYSCFG_CFGR1_TIM1_DMA_RMP SYSCFG_CFGR1_TIM1_DMA_RMP_Msk /*!< TIM1 DMA remap */
<> 144:ef7eb2e8f9f7 8905 #define SYSCFG_CFGR1_TIM2_DMA_RMP_Pos (29U)
<> 144:ef7eb2e8f9f7 8906 #define SYSCFG_CFGR1_TIM2_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM2_DMA_RMP_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8907 #define SYSCFG_CFGR1_TIM2_DMA_RMP SYSCFG_CFGR1_TIM2_DMA_RMP_Msk /*!< TIM2 DMA remap */
<> 144:ef7eb2e8f9f7 8908 #define SYSCFG_CFGR1_TIM3_DMA_RMP_Pos (30U)
<> 144:ef7eb2e8f9f7 8909 #define SYSCFG_CFGR1_TIM3_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM3_DMA_RMP_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 8910 #define SYSCFG_CFGR1_TIM3_DMA_RMP SYSCFG_CFGR1_TIM3_DMA_RMP_Msk /*!< TIM3 DMA remap */
<> 144:ef7eb2e8f9f7 8911
<> 144:ef7eb2e8f9f7 8912 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
<> 144:ef7eb2e8f9f7 8913 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 8914 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */
<> 144:ef7eb2e8f9f7 8915 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
<> 144:ef7eb2e8f9f7 8916 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 8917 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */
<> 144:ef7eb2e8f9f7 8918 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
<> 144:ef7eb2e8f9f7 8919 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 8920 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */
<> 144:ef7eb2e8f9f7 8921 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
<> 144:ef7eb2e8f9f7 8922 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8923 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */
<> 144:ef7eb2e8f9f7 8924 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U)
<> 144:ef7eb2e8f9f7 8925 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 8926 #define SYSCFG_CFGR1_I2C_FMP_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
<> 144:ef7eb2e8f9f7 8927 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Pos (21U)
<> 144:ef7eb2e8f9f7 8928 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C2_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 8929 #define SYSCFG_CFGR1_I2C_FMP_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2_Msk /*!< Enable I2C2 Fast mode plus */
<> 144:ef7eb2e8f9f7 8930
<> 144:ef7eb2e8f9f7 8931 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
<> 144:ef7eb2e8f9f7 8932 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
<> 144:ef7eb2e8f9f7 8933 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 8934 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
<> 144:ef7eb2e8f9f7 8935 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
<> 144:ef7eb2e8f9f7 8936 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 8937 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
<> 144:ef7eb2e8f9f7 8938 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
<> 144:ef7eb2e8f9f7 8939 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 8940 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
<> 144:ef7eb2e8f9f7 8941 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
<> 144:ef7eb2e8f9f7 8942 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
<> 144:ef7eb2e8f9f7 8943 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
<> 144:ef7eb2e8f9f7 8944
<> 144:ef7eb2e8f9f7 8945 /**
<> 144:ef7eb2e8f9f7 8946 * @brief EXTI0 configuration
<> 144:ef7eb2e8f9f7 8947 */
<> 144:ef7eb2e8f9f7 8948 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
<> 144:ef7eb2e8f9f7 8949 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
<> 144:ef7eb2e8f9f7 8950 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
<> 144:ef7eb2e8f9f7 8951 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
<> 144:ef7eb2e8f9f7 8952 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
<> 144:ef7eb2e8f9f7 8953 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
<> 144:ef7eb2e8f9f7 8954
<> 144:ef7eb2e8f9f7 8955 /**
<> 144:ef7eb2e8f9f7 8956 * @brief EXTI1 configuration
<> 144:ef7eb2e8f9f7 8957 */
<> 144:ef7eb2e8f9f7 8958 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
<> 144:ef7eb2e8f9f7 8959 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
<> 144:ef7eb2e8f9f7 8960 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
<> 144:ef7eb2e8f9f7 8961 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
<> 144:ef7eb2e8f9f7 8962 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
<> 144:ef7eb2e8f9f7 8963 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
<> 144:ef7eb2e8f9f7 8964
<> 144:ef7eb2e8f9f7 8965 /**
<> 144:ef7eb2e8f9f7 8966 * @brief EXTI2 configuration
<> 144:ef7eb2e8f9f7 8967 */
<> 144:ef7eb2e8f9f7 8968 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
<> 144:ef7eb2e8f9f7 8969 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
<> 144:ef7eb2e8f9f7 8970 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
<> 144:ef7eb2e8f9f7 8971 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
<> 144:ef7eb2e8f9f7 8972 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
<> 144:ef7eb2e8f9f7 8973 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
<> 144:ef7eb2e8f9f7 8974
<> 144:ef7eb2e8f9f7 8975 /**
<> 144:ef7eb2e8f9f7 8976 * @brief EXTI3 configuration
<> 144:ef7eb2e8f9f7 8977 */
<> 144:ef7eb2e8f9f7 8978 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
<> 144:ef7eb2e8f9f7 8979 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
<> 144:ef7eb2e8f9f7 8980 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
<> 144:ef7eb2e8f9f7 8981 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
<> 144:ef7eb2e8f9f7 8982 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
<> 144:ef7eb2e8f9f7 8983 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */
<> 144:ef7eb2e8f9f7 8984
<> 144:ef7eb2e8f9f7 8985 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
<> 144:ef7eb2e8f9f7 8986 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
<> 144:ef7eb2e8f9f7 8987 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 8988 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
<> 144:ef7eb2e8f9f7 8989 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
<> 144:ef7eb2e8f9f7 8990 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 8991 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
<> 144:ef7eb2e8f9f7 8992 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
<> 144:ef7eb2e8f9f7 8993 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 8994 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
<> 144:ef7eb2e8f9f7 8995 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
<> 144:ef7eb2e8f9f7 8996 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
<> 144:ef7eb2e8f9f7 8997 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
<> 144:ef7eb2e8f9f7 8998
<> 144:ef7eb2e8f9f7 8999 /**
<> 144:ef7eb2e8f9f7 9000 * @brief EXTI4 configuration
<> 144:ef7eb2e8f9f7 9001 */
<> 144:ef7eb2e8f9f7 9002 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
<> 144:ef7eb2e8f9f7 9003 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
<> 144:ef7eb2e8f9f7 9004 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
<> 144:ef7eb2e8f9f7 9005 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
<> 144:ef7eb2e8f9f7 9006 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
<> 144:ef7eb2e8f9f7 9007 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
<> 144:ef7eb2e8f9f7 9008
<> 144:ef7eb2e8f9f7 9009 /**
<> 144:ef7eb2e8f9f7 9010 * @brief EXTI5 configuration
<> 144:ef7eb2e8f9f7 9011 */
<> 144:ef7eb2e8f9f7 9012 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
<> 144:ef7eb2e8f9f7 9013 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
<> 144:ef7eb2e8f9f7 9014 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
<> 144:ef7eb2e8f9f7 9015 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
<> 144:ef7eb2e8f9f7 9016 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
<> 144:ef7eb2e8f9f7 9017 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
<> 144:ef7eb2e8f9f7 9018
<> 144:ef7eb2e8f9f7 9019 /**
<> 144:ef7eb2e8f9f7 9020 * @brief EXTI6 configuration
<> 144:ef7eb2e8f9f7 9021 */
<> 144:ef7eb2e8f9f7 9022 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
<> 144:ef7eb2e8f9f7 9023 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
<> 144:ef7eb2e8f9f7 9024 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
<> 144:ef7eb2e8f9f7 9025 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
<> 144:ef7eb2e8f9f7 9026 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
<> 144:ef7eb2e8f9f7 9027 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
<> 144:ef7eb2e8f9f7 9028
<> 144:ef7eb2e8f9f7 9029 /**
<> 144:ef7eb2e8f9f7 9030 * @brief EXTI7 configuration
<> 144:ef7eb2e8f9f7 9031 */
<> 144:ef7eb2e8f9f7 9032 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
<> 144:ef7eb2e8f9f7 9033 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
<> 144:ef7eb2e8f9f7 9034 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
<> 144:ef7eb2e8f9f7 9035 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
<> 144:ef7eb2e8f9f7 9036 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
<> 144:ef7eb2e8f9f7 9037 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
<> 144:ef7eb2e8f9f7 9038
<> 144:ef7eb2e8f9f7 9039 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
<> 144:ef7eb2e8f9f7 9040 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
<> 144:ef7eb2e8f9f7 9041 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 9042 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
<> 144:ef7eb2e8f9f7 9043 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
<> 144:ef7eb2e8f9f7 9044 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 9045 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
<> 144:ef7eb2e8f9f7 9046 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
<> 144:ef7eb2e8f9f7 9047 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 9048 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
<> 144:ef7eb2e8f9f7 9049 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
<> 144:ef7eb2e8f9f7 9050 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
<> 144:ef7eb2e8f9f7 9051 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
<> 144:ef7eb2e8f9f7 9052
<> 144:ef7eb2e8f9f7 9053 /**
<> 144:ef7eb2e8f9f7 9054 * @brief EXTI8 configuration
<> 144:ef7eb2e8f9f7 9055 */
<> 144:ef7eb2e8f9f7 9056 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
<> 144:ef7eb2e8f9f7 9057 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
<> 144:ef7eb2e8f9f7 9058 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
<> 144:ef7eb2e8f9f7 9059 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
<> 144:ef7eb2e8f9f7 9060 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
<> 144:ef7eb2e8f9f7 9061
<> 144:ef7eb2e8f9f7 9062
<> 144:ef7eb2e8f9f7 9063 /**
<> 144:ef7eb2e8f9f7 9064 * @brief EXTI9 configuration
<> 144:ef7eb2e8f9f7 9065 */
<> 144:ef7eb2e8f9f7 9066 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
<> 144:ef7eb2e8f9f7 9067 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
<> 144:ef7eb2e8f9f7 9068 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
<> 144:ef7eb2e8f9f7 9069 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
<> 144:ef7eb2e8f9f7 9070 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
<> 144:ef7eb2e8f9f7 9071 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
<> 144:ef7eb2e8f9f7 9072
<> 144:ef7eb2e8f9f7 9073 /**
<> 144:ef7eb2e8f9f7 9074 * @brief EXTI10 configuration
<> 144:ef7eb2e8f9f7 9075 */
<> 144:ef7eb2e8f9f7 9076 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
<> 144:ef7eb2e8f9f7 9077 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
<> 144:ef7eb2e8f9f7 9078 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
<> 144:ef7eb2e8f9f7 9079 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
<> 144:ef7eb2e8f9f7 9080 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
<> 144:ef7eb2e8f9f7 9081 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
<> 144:ef7eb2e8f9f7 9082
<> 144:ef7eb2e8f9f7 9083 /**
<> 144:ef7eb2e8f9f7 9084 * @brief EXTI11 configuration
<> 144:ef7eb2e8f9f7 9085 */
<> 144:ef7eb2e8f9f7 9086 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
<> 144:ef7eb2e8f9f7 9087 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
<> 144:ef7eb2e8f9f7 9088 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
<> 144:ef7eb2e8f9f7 9089 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
<> 144:ef7eb2e8f9f7 9090 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
<> 144:ef7eb2e8f9f7 9091
<> 144:ef7eb2e8f9f7 9092 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
<> 144:ef7eb2e8f9f7 9093 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
<> 144:ef7eb2e8f9f7 9094 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 9095 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
<> 144:ef7eb2e8f9f7 9096 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
<> 144:ef7eb2e8f9f7 9097 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 9098 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
<> 144:ef7eb2e8f9f7 9099 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
<> 144:ef7eb2e8f9f7 9100 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 9101 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
<> 144:ef7eb2e8f9f7 9102 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
<> 144:ef7eb2e8f9f7 9103 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
<> 144:ef7eb2e8f9f7 9104 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
<> 144:ef7eb2e8f9f7 9105
<> 144:ef7eb2e8f9f7 9106 /**
<> 144:ef7eb2e8f9f7 9107 * @brief EXTI12 configuration
<> 144:ef7eb2e8f9f7 9108 */
<> 144:ef7eb2e8f9f7 9109 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
<> 144:ef7eb2e8f9f7 9110 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
<> 144:ef7eb2e8f9f7 9111 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
<> 144:ef7eb2e8f9f7 9112 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
<> 144:ef7eb2e8f9f7 9113 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
<> 144:ef7eb2e8f9f7 9114
<> 144:ef7eb2e8f9f7 9115 /**
<> 144:ef7eb2e8f9f7 9116 * @brief EXTI13 configuration
<> 144:ef7eb2e8f9f7 9117 */
<> 144:ef7eb2e8f9f7 9118 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
<> 144:ef7eb2e8f9f7 9119 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
<> 144:ef7eb2e8f9f7 9120 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
<> 144:ef7eb2e8f9f7 9121 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
<> 144:ef7eb2e8f9f7 9122 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
<> 144:ef7eb2e8f9f7 9123
<> 144:ef7eb2e8f9f7 9124 /**
<> 144:ef7eb2e8f9f7 9125 * @brief EXTI14 configuration
<> 144:ef7eb2e8f9f7 9126 */
<> 144:ef7eb2e8f9f7 9127 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
<> 144:ef7eb2e8f9f7 9128 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
<> 144:ef7eb2e8f9f7 9129 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
<> 144:ef7eb2e8f9f7 9130 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
<> 144:ef7eb2e8f9f7 9131 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
<> 144:ef7eb2e8f9f7 9132
<> 144:ef7eb2e8f9f7 9133 /**
<> 144:ef7eb2e8f9f7 9134 * @brief EXTI15 configuration
<> 144:ef7eb2e8f9f7 9135 */
<> 144:ef7eb2e8f9f7 9136 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
<> 144:ef7eb2e8f9f7 9137 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
<> 144:ef7eb2e8f9f7 9138 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
<> 144:ef7eb2e8f9f7 9139 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
<> 144:ef7eb2e8f9f7 9140 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
<> 144:ef7eb2e8f9f7 9141
<> 144:ef7eb2e8f9f7 9142 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
<> 144:ef7eb2e8f9f7 9143 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
<> 144:ef7eb2e8f9f7 9144 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9145 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
<> 144:ef7eb2e8f9f7 9146 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
<> 144:ef7eb2e8f9f7 9147 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9148 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
<> 144:ef7eb2e8f9f7 9149 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
<> 144:ef7eb2e8f9f7 9150 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9151 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
<> 144:ef7eb2e8f9f7 9152 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
<> 144:ef7eb2e8f9f7 9153 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9154 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */
<> 144:ef7eb2e8f9f7 9155 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
<> 144:ef7eb2e8f9f7 9156
<> 144:ef7eb2e8f9f7 9157 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 9158 /* */
<> 144:ef7eb2e8f9f7 9159 /* Timers (TIM) */
<> 144:ef7eb2e8f9f7 9160 /* */
<> 144:ef7eb2e8f9f7 9161 /*****************************************************************************/
<> 144:ef7eb2e8f9f7 9162 /******************* Bit definition for TIM_CR1 register *******************/
<> 144:ef7eb2e8f9f7 9163 #define TIM_CR1_CEN_Pos (0U)
<> 144:ef7eb2e8f9f7 9164 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9165 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
<> 144:ef7eb2e8f9f7 9166 #define TIM_CR1_UDIS_Pos (1U)
<> 144:ef7eb2e8f9f7 9167 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9168 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
<> 144:ef7eb2e8f9f7 9169 #define TIM_CR1_URS_Pos (2U)
<> 144:ef7eb2e8f9f7 9170 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9171 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
<> 144:ef7eb2e8f9f7 9172 #define TIM_CR1_OPM_Pos (3U)
<> 144:ef7eb2e8f9f7 9173 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9174 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
<> 144:ef7eb2e8f9f7 9175 #define TIM_CR1_DIR_Pos (4U)
<> 144:ef7eb2e8f9f7 9176 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9177 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
<> 144:ef7eb2e8f9f7 9178
<> 144:ef7eb2e8f9f7 9179 #define TIM_CR1_CMS_Pos (5U)
<> 144:ef7eb2e8f9f7 9180 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
<> 144:ef7eb2e8f9f7 9181 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 144:ef7eb2e8f9f7 9182 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9183 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9184
<> 144:ef7eb2e8f9f7 9185 #define TIM_CR1_ARPE_Pos (7U)
<> 144:ef7eb2e8f9f7 9186 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9187 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
<> 144:ef7eb2e8f9f7 9188
<> 144:ef7eb2e8f9f7 9189 #define TIM_CR1_CKD_Pos (8U)
<> 144:ef7eb2e8f9f7 9190 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 9191 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
<> 144:ef7eb2e8f9f7 9192 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9193 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9194
<> 144:ef7eb2e8f9f7 9195 /******************* Bit definition for TIM_CR2 register *******************/
<> 144:ef7eb2e8f9f7 9196 #define TIM_CR2_CCPC_Pos (0U)
<> 144:ef7eb2e8f9f7 9197 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9198 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
<> 144:ef7eb2e8f9f7 9199 #define TIM_CR2_CCUS_Pos (2U)
<> 144:ef7eb2e8f9f7 9200 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9201 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
<> 144:ef7eb2e8f9f7 9202 #define TIM_CR2_CCDS_Pos (3U)
<> 144:ef7eb2e8f9f7 9203 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9204 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
<> 144:ef7eb2e8f9f7 9205
<> 144:ef7eb2e8f9f7 9206 #define TIM_CR2_MMS_Pos (4U)
<> 144:ef7eb2e8f9f7 9207 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 9208 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 144:ef7eb2e8f9f7 9209 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9210 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9211 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9212
<> 144:ef7eb2e8f9f7 9213 #define TIM_CR2_TI1S_Pos (7U)
<> 144:ef7eb2e8f9f7 9214 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9215 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
<> 144:ef7eb2e8f9f7 9216 #define TIM_CR2_OIS1_Pos (8U)
<> 144:ef7eb2e8f9f7 9217 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9218 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
<> 144:ef7eb2e8f9f7 9219 #define TIM_CR2_OIS1N_Pos (9U)
<> 144:ef7eb2e8f9f7 9220 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9221 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
<> 144:ef7eb2e8f9f7 9222 #define TIM_CR2_OIS2_Pos (10U)
<> 144:ef7eb2e8f9f7 9223 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9224 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
<> 144:ef7eb2e8f9f7 9225 #define TIM_CR2_OIS2N_Pos (11U)
<> 144:ef7eb2e8f9f7 9226 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9227 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
<> 144:ef7eb2e8f9f7 9228 #define TIM_CR2_OIS3_Pos (12U)
<> 144:ef7eb2e8f9f7 9229 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9230 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
<> 144:ef7eb2e8f9f7 9231 #define TIM_CR2_OIS3N_Pos (13U)
<> 144:ef7eb2e8f9f7 9232 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9233 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
<> 144:ef7eb2e8f9f7 9234 #define TIM_CR2_OIS4_Pos (14U)
<> 144:ef7eb2e8f9f7 9235 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9236 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
<> 144:ef7eb2e8f9f7 9237
<> 144:ef7eb2e8f9f7 9238 /******************* Bit definition for TIM_SMCR register ******************/
<> 144:ef7eb2e8f9f7 9239 #define TIM_SMCR_SMS_Pos (0U)
<> 144:ef7eb2e8f9f7 9240 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
<> 144:ef7eb2e8f9f7 9241 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
<> 144:ef7eb2e8f9f7 9242 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9243 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9244 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9245
<> 144:ef7eb2e8f9f7 9246 #define TIM_SMCR_OCCS_Pos (3U)
<> 144:ef7eb2e8f9f7 9247 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9248 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
<> 144:ef7eb2e8f9f7 9249
<> 144:ef7eb2e8f9f7 9250 #define TIM_SMCR_TS_Pos (4U)
<> 144:ef7eb2e8f9f7 9251 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 9252 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
<> 144:ef7eb2e8f9f7 9253 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9254 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9255 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9256
<> 144:ef7eb2e8f9f7 9257 #define TIM_SMCR_MSM_Pos (7U)
<> 144:ef7eb2e8f9f7 9258 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9259 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
<> 144:ef7eb2e8f9f7 9260
<> 144:ef7eb2e8f9f7 9261 #define TIM_SMCR_ETF_Pos (8U)
<> 144:ef7eb2e8f9f7 9262 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
<> 144:ef7eb2e8f9f7 9263 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
<> 144:ef7eb2e8f9f7 9264 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9265 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9266 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9267 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9268
<> 144:ef7eb2e8f9f7 9269 #define TIM_SMCR_ETPS_Pos (12U)
<> 144:ef7eb2e8f9f7 9270 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
<> 144:ef7eb2e8f9f7 9271 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 144:ef7eb2e8f9f7 9272 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9273 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9274
<> 144:ef7eb2e8f9f7 9275 #define TIM_SMCR_ECE_Pos (14U)
<> 144:ef7eb2e8f9f7 9276 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9277 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
<> 144:ef7eb2e8f9f7 9278 #define TIM_SMCR_ETP_Pos (15U)
<> 144:ef7eb2e8f9f7 9279 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9280 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
<> 144:ef7eb2e8f9f7 9281
<> 144:ef7eb2e8f9f7 9282 /******************* Bit definition for TIM_DIER register ******************/
<> 144:ef7eb2e8f9f7 9283 #define TIM_DIER_UIE_Pos (0U)
<> 144:ef7eb2e8f9f7 9284 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9285 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
<> 144:ef7eb2e8f9f7 9286 #define TIM_DIER_CC1IE_Pos (1U)
<> 144:ef7eb2e8f9f7 9287 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9288 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
<> 144:ef7eb2e8f9f7 9289 #define TIM_DIER_CC2IE_Pos (2U)
<> 144:ef7eb2e8f9f7 9290 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9291 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
<> 144:ef7eb2e8f9f7 9292 #define TIM_DIER_CC3IE_Pos (3U)
<> 144:ef7eb2e8f9f7 9293 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9294 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
<> 144:ef7eb2e8f9f7 9295 #define TIM_DIER_CC4IE_Pos (4U)
<> 144:ef7eb2e8f9f7 9296 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9297 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
<> 144:ef7eb2e8f9f7 9298 #define TIM_DIER_COMIE_Pos (5U)
<> 144:ef7eb2e8f9f7 9299 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9300 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
<> 144:ef7eb2e8f9f7 9301 #define TIM_DIER_TIE_Pos (6U)
<> 144:ef7eb2e8f9f7 9302 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9303 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
<> 144:ef7eb2e8f9f7 9304 #define TIM_DIER_BIE_Pos (7U)
<> 144:ef7eb2e8f9f7 9305 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9306 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
<> 144:ef7eb2e8f9f7 9307 #define TIM_DIER_UDE_Pos (8U)
<> 144:ef7eb2e8f9f7 9308 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9309 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
<> 144:ef7eb2e8f9f7 9310 #define TIM_DIER_CC1DE_Pos (9U)
<> 144:ef7eb2e8f9f7 9311 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9312 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
<> 144:ef7eb2e8f9f7 9313 #define TIM_DIER_CC2DE_Pos (10U)
<> 144:ef7eb2e8f9f7 9314 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9315 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
<> 144:ef7eb2e8f9f7 9316 #define TIM_DIER_CC3DE_Pos (11U)
<> 144:ef7eb2e8f9f7 9317 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9318 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
<> 144:ef7eb2e8f9f7 9319 #define TIM_DIER_CC4DE_Pos (12U)
<> 144:ef7eb2e8f9f7 9320 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9321 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
<> 144:ef7eb2e8f9f7 9322 #define TIM_DIER_COMDE_Pos (13U)
<> 144:ef7eb2e8f9f7 9323 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9324 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
<> 144:ef7eb2e8f9f7 9325 #define TIM_DIER_TDE_Pos (14U)
<> 144:ef7eb2e8f9f7 9326 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9327 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
<> 144:ef7eb2e8f9f7 9328
<> 144:ef7eb2e8f9f7 9329 /******************** Bit definition for TIM_SR register *******************/
<> 144:ef7eb2e8f9f7 9330 #define TIM_SR_UIF_Pos (0U)
<> 144:ef7eb2e8f9f7 9331 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9332 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
<> 144:ef7eb2e8f9f7 9333 #define TIM_SR_CC1IF_Pos (1U)
<> 144:ef7eb2e8f9f7 9334 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9335 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
<> 144:ef7eb2e8f9f7 9336 #define TIM_SR_CC2IF_Pos (2U)
<> 144:ef7eb2e8f9f7 9337 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9338 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
<> 144:ef7eb2e8f9f7 9339 #define TIM_SR_CC3IF_Pos (3U)
<> 144:ef7eb2e8f9f7 9340 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9341 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
<> 144:ef7eb2e8f9f7 9342 #define TIM_SR_CC4IF_Pos (4U)
<> 144:ef7eb2e8f9f7 9343 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9344 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
<> 144:ef7eb2e8f9f7 9345 #define TIM_SR_COMIF_Pos (5U)
<> 144:ef7eb2e8f9f7 9346 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9347 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
<> 144:ef7eb2e8f9f7 9348 #define TIM_SR_TIF_Pos (6U)
<> 144:ef7eb2e8f9f7 9349 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9350 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
<> 144:ef7eb2e8f9f7 9351 #define TIM_SR_BIF_Pos (7U)
<> 144:ef7eb2e8f9f7 9352 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9353 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
<> 144:ef7eb2e8f9f7 9354 #define TIM_SR_CC1OF_Pos (9U)
<> 144:ef7eb2e8f9f7 9355 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9356 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
<> 144:ef7eb2e8f9f7 9357 #define TIM_SR_CC2OF_Pos (10U)
<> 144:ef7eb2e8f9f7 9358 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9359 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
<> 144:ef7eb2e8f9f7 9360 #define TIM_SR_CC3OF_Pos (11U)
<> 144:ef7eb2e8f9f7 9361 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9362 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
<> 144:ef7eb2e8f9f7 9363 #define TIM_SR_CC4OF_Pos (12U)
<> 144:ef7eb2e8f9f7 9364 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9365 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
<> 144:ef7eb2e8f9f7 9366
<> 144:ef7eb2e8f9f7 9367 /******************* Bit definition for TIM_EGR register *******************/
<> 144:ef7eb2e8f9f7 9368 #define TIM_EGR_UG_Pos (0U)
<> 144:ef7eb2e8f9f7 9369 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9370 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
<> 144:ef7eb2e8f9f7 9371 #define TIM_EGR_CC1G_Pos (1U)
<> 144:ef7eb2e8f9f7 9372 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9373 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
<> 144:ef7eb2e8f9f7 9374 #define TIM_EGR_CC2G_Pos (2U)
<> 144:ef7eb2e8f9f7 9375 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9376 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
<> 144:ef7eb2e8f9f7 9377 #define TIM_EGR_CC3G_Pos (3U)
<> 144:ef7eb2e8f9f7 9378 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9379 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
<> 144:ef7eb2e8f9f7 9380 #define TIM_EGR_CC4G_Pos (4U)
<> 144:ef7eb2e8f9f7 9381 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9382 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
<> 144:ef7eb2e8f9f7 9383 #define TIM_EGR_COMG_Pos (5U)
<> 144:ef7eb2e8f9f7 9384 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9385 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
<> 144:ef7eb2e8f9f7 9386 #define TIM_EGR_TG_Pos (6U)
<> 144:ef7eb2e8f9f7 9387 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9388 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
<> 144:ef7eb2e8f9f7 9389 #define TIM_EGR_BG_Pos (7U)
<> 144:ef7eb2e8f9f7 9390 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9391 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
<> 144:ef7eb2e8f9f7 9392
<> 144:ef7eb2e8f9f7 9393 /****************** Bit definition for TIM_CCMR1 register ******************/
<> 144:ef7eb2e8f9f7 9394 #define TIM_CCMR1_CC1S_Pos (0U)
<> 144:ef7eb2e8f9f7 9395 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 9396 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 144:ef7eb2e8f9f7 9397 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9398 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9399
<> 144:ef7eb2e8f9f7 9400 #define TIM_CCMR1_OC1FE_Pos (2U)
<> 144:ef7eb2e8f9f7 9401 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9402 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
<> 144:ef7eb2e8f9f7 9403 #define TIM_CCMR1_OC1PE_Pos (3U)
<> 144:ef7eb2e8f9f7 9404 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9405 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
<> 144:ef7eb2e8f9f7 9406
<> 144:ef7eb2e8f9f7 9407 #define TIM_CCMR1_OC1M_Pos (4U)
<> 144:ef7eb2e8f9f7 9408 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 9409 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 144:ef7eb2e8f9f7 9410 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9411 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9412 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9413
<> 144:ef7eb2e8f9f7 9414 #define TIM_CCMR1_OC1CE_Pos (7U)
<> 144:ef7eb2e8f9f7 9415 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9416 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
<> 144:ef7eb2e8f9f7 9417
<> 144:ef7eb2e8f9f7 9418 #define TIM_CCMR1_CC2S_Pos (8U)
<> 144:ef7eb2e8f9f7 9419 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 9420 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 144:ef7eb2e8f9f7 9421 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9422 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9423
<> 144:ef7eb2e8f9f7 9424 #define TIM_CCMR1_OC2FE_Pos (10U)
<> 144:ef7eb2e8f9f7 9425 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9426 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
<> 144:ef7eb2e8f9f7 9427 #define TIM_CCMR1_OC2PE_Pos (11U)
<> 144:ef7eb2e8f9f7 9428 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9429 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
<> 144:ef7eb2e8f9f7 9430
<> 144:ef7eb2e8f9f7 9431 #define TIM_CCMR1_OC2M_Pos (12U)
<> 144:ef7eb2e8f9f7 9432 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
<> 144:ef7eb2e8f9f7 9433 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 144:ef7eb2e8f9f7 9434 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9435 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9436 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9437
<> 144:ef7eb2e8f9f7 9438 #define TIM_CCMR1_OC2CE_Pos (15U)
<> 144:ef7eb2e8f9f7 9439 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9440 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
<> 144:ef7eb2e8f9f7 9441
<> 144:ef7eb2e8f9f7 9442 /*---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 9443
<> 144:ef7eb2e8f9f7 9444 #define TIM_CCMR1_IC1PSC_Pos (2U)
<> 144:ef7eb2e8f9f7 9445 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
<> 144:ef7eb2e8f9f7 9446 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 144:ef7eb2e8f9f7 9447 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9448 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9449
<> 144:ef7eb2e8f9f7 9450 #define TIM_CCMR1_IC1F_Pos (4U)
<> 144:ef7eb2e8f9f7 9451 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 9452 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 144:ef7eb2e8f9f7 9453 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9454 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9455 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9456 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9457
<> 144:ef7eb2e8f9f7 9458 #define TIM_CCMR1_IC2PSC_Pos (10U)
<> 144:ef7eb2e8f9f7 9459 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
<> 144:ef7eb2e8f9f7 9460 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 144:ef7eb2e8f9f7 9461 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9462 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9463
<> 144:ef7eb2e8f9f7 9464 #define TIM_CCMR1_IC2F_Pos (12U)
<> 144:ef7eb2e8f9f7 9465 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
<> 144:ef7eb2e8f9f7 9466 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 144:ef7eb2e8f9f7 9467 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9468 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9469 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9470 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9471
<> 144:ef7eb2e8f9f7 9472 /****************** Bit definition for TIM_CCMR2 register ******************/
<> 144:ef7eb2e8f9f7 9473 #define TIM_CCMR2_CC3S_Pos (0U)
<> 144:ef7eb2e8f9f7 9474 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 9475 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 144:ef7eb2e8f9f7 9476 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9477 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9478
<> 144:ef7eb2e8f9f7 9479 #define TIM_CCMR2_OC3FE_Pos (2U)
<> 144:ef7eb2e8f9f7 9480 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9481 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
<> 144:ef7eb2e8f9f7 9482 #define TIM_CCMR2_OC3PE_Pos (3U)
<> 144:ef7eb2e8f9f7 9483 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9484 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
<> 144:ef7eb2e8f9f7 9485
<> 144:ef7eb2e8f9f7 9486 #define TIM_CCMR2_OC3M_Pos (4U)
<> 144:ef7eb2e8f9f7 9487 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
<> 144:ef7eb2e8f9f7 9488 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 144:ef7eb2e8f9f7 9489 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9490 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9491 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9492
<> 144:ef7eb2e8f9f7 9493 #define TIM_CCMR2_OC3CE_Pos (7U)
<> 144:ef7eb2e8f9f7 9494 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9495 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
<> 144:ef7eb2e8f9f7 9496
<> 144:ef7eb2e8f9f7 9497 #define TIM_CCMR2_CC4S_Pos (8U)
<> 144:ef7eb2e8f9f7 9498 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 9499 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 144:ef7eb2e8f9f7 9500 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9501 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9502
<> 144:ef7eb2e8f9f7 9503 #define TIM_CCMR2_OC4FE_Pos (10U)
<> 144:ef7eb2e8f9f7 9504 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9505 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
<> 144:ef7eb2e8f9f7 9506 #define TIM_CCMR2_OC4PE_Pos (11U)
<> 144:ef7eb2e8f9f7 9507 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9508 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
<> 144:ef7eb2e8f9f7 9509
<> 144:ef7eb2e8f9f7 9510 #define TIM_CCMR2_OC4M_Pos (12U)
<> 144:ef7eb2e8f9f7 9511 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
<> 144:ef7eb2e8f9f7 9512 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 144:ef7eb2e8f9f7 9513 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9514 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9515 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9516
<> 144:ef7eb2e8f9f7 9517 #define TIM_CCMR2_OC4CE_Pos (15U)
<> 144:ef7eb2e8f9f7 9518 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9519 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
<> 144:ef7eb2e8f9f7 9520
<> 144:ef7eb2e8f9f7 9521 /*---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 9522
<> 144:ef7eb2e8f9f7 9523 #define TIM_CCMR2_IC3PSC_Pos (2U)
<> 144:ef7eb2e8f9f7 9524 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
<> 144:ef7eb2e8f9f7 9525 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 144:ef7eb2e8f9f7 9526 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9527 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9528
<> 144:ef7eb2e8f9f7 9529 #define TIM_CCMR2_IC3F_Pos (4U)
<> 144:ef7eb2e8f9f7 9530 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
<> 144:ef7eb2e8f9f7 9531 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 144:ef7eb2e8f9f7 9532 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9533 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9534 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9535 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9536
<> 144:ef7eb2e8f9f7 9537 #define TIM_CCMR2_IC4PSC_Pos (10U)
<> 144:ef7eb2e8f9f7 9538 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
<> 144:ef7eb2e8f9f7 9539 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 144:ef7eb2e8f9f7 9540 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9541 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9542
<> 144:ef7eb2e8f9f7 9543 #define TIM_CCMR2_IC4F_Pos (12U)
<> 144:ef7eb2e8f9f7 9544 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
<> 144:ef7eb2e8f9f7 9545 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 144:ef7eb2e8f9f7 9546 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9547 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9548 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9549 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9550
<> 144:ef7eb2e8f9f7 9551 /******************* Bit definition for TIM_CCER register ******************/
<> 144:ef7eb2e8f9f7 9552 #define TIM_CCER_CC1E_Pos (0U)
<> 144:ef7eb2e8f9f7 9553 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9554 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
<> 144:ef7eb2e8f9f7 9555 #define TIM_CCER_CC1P_Pos (1U)
<> 144:ef7eb2e8f9f7 9556 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9557 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
<> 144:ef7eb2e8f9f7 9558 #define TIM_CCER_CC1NE_Pos (2U)
<> 144:ef7eb2e8f9f7 9559 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9560 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
<> 144:ef7eb2e8f9f7 9561 #define TIM_CCER_CC1NP_Pos (3U)
<> 144:ef7eb2e8f9f7 9562 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9563 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 9564 #define TIM_CCER_CC2E_Pos (4U)
<> 144:ef7eb2e8f9f7 9565 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9566 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
<> 144:ef7eb2e8f9f7 9567 #define TIM_CCER_CC2P_Pos (5U)
<> 144:ef7eb2e8f9f7 9568 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9569 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
<> 144:ef7eb2e8f9f7 9570 #define TIM_CCER_CC2NE_Pos (6U)
<> 144:ef7eb2e8f9f7 9571 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9572 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
<> 144:ef7eb2e8f9f7 9573 #define TIM_CCER_CC2NP_Pos (7U)
<> 144:ef7eb2e8f9f7 9574 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9575 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 9576 #define TIM_CCER_CC3E_Pos (8U)
<> 144:ef7eb2e8f9f7 9577 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9578 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
<> 144:ef7eb2e8f9f7 9579 #define TIM_CCER_CC3P_Pos (9U)
<> 144:ef7eb2e8f9f7 9580 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9581 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
<> 144:ef7eb2e8f9f7 9582 #define TIM_CCER_CC3NE_Pos (10U)
<> 144:ef7eb2e8f9f7 9583 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9584 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
<> 144:ef7eb2e8f9f7 9585 #define TIM_CCER_CC3NP_Pos (11U)
<> 144:ef7eb2e8f9f7 9586 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9587 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 9588 #define TIM_CCER_CC4E_Pos (12U)
<> 144:ef7eb2e8f9f7 9589 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9590 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
<> 144:ef7eb2e8f9f7 9591 #define TIM_CCER_CC4P_Pos (13U)
<> 144:ef7eb2e8f9f7 9592 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9593 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
<> 144:ef7eb2e8f9f7 9594 #define TIM_CCER_CC4NP_Pos (15U)
<> 144:ef7eb2e8f9f7 9595 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9596 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 9597
<> 144:ef7eb2e8f9f7 9598 /******************* Bit definition for TIM_CNT register *******************/
<> 144:ef7eb2e8f9f7 9599 #define TIM_CNT_CNT_Pos (0U)
<> 144:ef7eb2e8f9f7 9600 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 9601 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
<> 144:ef7eb2e8f9f7 9602
<> 144:ef7eb2e8f9f7 9603 /******************* Bit definition for TIM_PSC register *******************/
<> 144:ef7eb2e8f9f7 9604 #define TIM_PSC_PSC_Pos (0U)
<> 144:ef7eb2e8f9f7 9605 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 9606 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
<> 144:ef7eb2e8f9f7 9607
<> 144:ef7eb2e8f9f7 9608 /******************* Bit definition for TIM_ARR register *******************/
<> 144:ef7eb2e8f9f7 9609 #define TIM_ARR_ARR_Pos (0U)
<> 144:ef7eb2e8f9f7 9610 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 9611 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
<> 144:ef7eb2e8f9f7 9612
<> 144:ef7eb2e8f9f7 9613 /******************* Bit definition for TIM_RCR register *******************/
<> 144:ef7eb2e8f9f7 9614 #define TIM_RCR_REP_Pos (0U)
<> 144:ef7eb2e8f9f7 9615 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 9616 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
<> 144:ef7eb2e8f9f7 9617
<> 144:ef7eb2e8f9f7 9618 /******************* Bit definition for TIM_CCR1 register ******************/
<> 144:ef7eb2e8f9f7 9619 #define TIM_CCR1_CCR1_Pos (0U)
<> 144:ef7eb2e8f9f7 9620 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 9621 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
<> 144:ef7eb2e8f9f7 9622
<> 144:ef7eb2e8f9f7 9623 /******************* Bit definition for TIM_CCR2 register ******************/
<> 144:ef7eb2e8f9f7 9624 #define TIM_CCR2_CCR2_Pos (0U)
<> 144:ef7eb2e8f9f7 9625 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 9626 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
<> 144:ef7eb2e8f9f7 9627
<> 144:ef7eb2e8f9f7 9628 /******************* Bit definition for TIM_CCR3 register ******************/
<> 144:ef7eb2e8f9f7 9629 #define TIM_CCR3_CCR3_Pos (0U)
<> 144:ef7eb2e8f9f7 9630 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 9631 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
<> 144:ef7eb2e8f9f7 9632
<> 144:ef7eb2e8f9f7 9633 /******************* Bit definition for TIM_CCR4 register ******************/
<> 144:ef7eb2e8f9f7 9634 #define TIM_CCR4_CCR4_Pos (0U)
<> 144:ef7eb2e8f9f7 9635 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 9636 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
<> 144:ef7eb2e8f9f7 9637
<> 144:ef7eb2e8f9f7 9638 /******************* Bit definition for TIM_BDTR register ******************/
<> 144:ef7eb2e8f9f7 9639 #define TIM_BDTR_DTG_Pos (0U)
<> 144:ef7eb2e8f9f7 9640 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 9641 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 144:ef7eb2e8f9f7 9642 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9643 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9644 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9645 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9646 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9647 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9648 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9649 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9650
<> 144:ef7eb2e8f9f7 9651 #define TIM_BDTR_LOCK_Pos (8U)
<> 144:ef7eb2e8f9f7 9652 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
<> 144:ef7eb2e8f9f7 9653 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
<> 144:ef7eb2e8f9f7 9654 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9655 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9656
<> 144:ef7eb2e8f9f7 9657 #define TIM_BDTR_OSSI_Pos (10U)
<> 144:ef7eb2e8f9f7 9658 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9659 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
<> 144:ef7eb2e8f9f7 9660 #define TIM_BDTR_OSSR_Pos (11U)
<> 144:ef7eb2e8f9f7 9661 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9662 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
<> 144:ef7eb2e8f9f7 9663 #define TIM_BDTR_BKE_Pos (12U)
<> 144:ef7eb2e8f9f7 9664 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9665 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
<> 144:ef7eb2e8f9f7 9666 #define TIM_BDTR_BKP_Pos (13U)
<> 144:ef7eb2e8f9f7 9667 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9668 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
<> 144:ef7eb2e8f9f7 9669 #define TIM_BDTR_AOE_Pos (14U)
<> 144:ef7eb2e8f9f7 9670 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9671 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
<> 144:ef7eb2e8f9f7 9672 #define TIM_BDTR_MOE_Pos (15U)
<> 144:ef7eb2e8f9f7 9673 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9674 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
<> 144:ef7eb2e8f9f7 9675
<> 144:ef7eb2e8f9f7 9676 /******************* Bit definition for TIM_DCR register *******************/
<> 144:ef7eb2e8f9f7 9677 #define TIM_DCR_DBA_Pos (0U)
<> 144:ef7eb2e8f9f7 9678 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
<> 144:ef7eb2e8f9f7 9679 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
<> 144:ef7eb2e8f9f7 9680 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9681 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9682 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9683 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9684 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9685
<> 144:ef7eb2e8f9f7 9686 #define TIM_DCR_DBL_Pos (8U)
<> 144:ef7eb2e8f9f7 9687 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
<> 144:ef7eb2e8f9f7 9688 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
<> 144:ef7eb2e8f9f7 9689 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9690 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9691 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9692 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9693 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9694
<> 144:ef7eb2e8f9f7 9695 /******************* Bit definition for TIM_DMAR register ******************/
<> 144:ef7eb2e8f9f7 9696 #define TIM_DMAR_DMAB_Pos (0U)
<> 144:ef7eb2e8f9f7 9697 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
<> 144:ef7eb2e8f9f7 9698 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
<> 144:ef7eb2e8f9f7 9699
<> 144:ef7eb2e8f9f7 9700 /******************* Bit definition for TIM14_OR register ********************/
<> 144:ef7eb2e8f9f7 9701 #define TIM14_OR_TI1_RMP_Pos (0U)
<> 144:ef7eb2e8f9f7 9702 #define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */
<> 144:ef7eb2e8f9f7 9703 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
<> 144:ef7eb2e8f9f7 9704 #define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9705 #define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9706
<> 144:ef7eb2e8f9f7 9707 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9708 /* */
<> 144:ef7eb2e8f9f7 9709 /* Touch Sensing Controller (TSC) */
<> 144:ef7eb2e8f9f7 9710 /* */
<> 144:ef7eb2e8f9f7 9711 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9712 /******************* Bit definition for TSC_CR register *********************/
<> 144:ef7eb2e8f9f7 9713 #define TSC_CR_TSCE_Pos (0U)
<> 144:ef7eb2e8f9f7 9714 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9715 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
<> 144:ef7eb2e8f9f7 9716 #define TSC_CR_START_Pos (1U)
<> 144:ef7eb2e8f9f7 9717 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9718 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
<> 144:ef7eb2e8f9f7 9719 #define TSC_CR_AM_Pos (2U)
<> 144:ef7eb2e8f9f7 9720 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9721 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
<> 144:ef7eb2e8f9f7 9722 #define TSC_CR_SYNCPOL_Pos (3U)
<> 144:ef7eb2e8f9f7 9723 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9724 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
<> 144:ef7eb2e8f9f7 9725 #define TSC_CR_IODEF_Pos (4U)
<> 144:ef7eb2e8f9f7 9726 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9727 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
<> 144:ef7eb2e8f9f7 9728
<> 144:ef7eb2e8f9f7 9729 #define TSC_CR_MCV_Pos (5U)
<> 144:ef7eb2e8f9f7 9730 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
<> 144:ef7eb2e8f9f7 9731 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
<> 144:ef7eb2e8f9f7 9732 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9733 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9734 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9735
<> 144:ef7eb2e8f9f7 9736 #define TSC_CR_PGPSC_Pos (12U)
<> 144:ef7eb2e8f9f7 9737 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
<> 144:ef7eb2e8f9f7 9738 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
<> 144:ef7eb2e8f9f7 9739 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9740 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9741 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9742
<> 144:ef7eb2e8f9f7 9743 #define TSC_CR_SSPSC_Pos (15U)
<> 144:ef7eb2e8f9f7 9744 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9745 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
<> 144:ef7eb2e8f9f7 9746 #define TSC_CR_SSE_Pos (16U)
<> 144:ef7eb2e8f9f7 9747 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 9748 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
<> 144:ef7eb2e8f9f7 9749
<> 144:ef7eb2e8f9f7 9750 #define TSC_CR_SSD_Pos (17U)
<> 144:ef7eb2e8f9f7 9751 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
<> 144:ef7eb2e8f9f7 9752 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
<> 144:ef7eb2e8f9f7 9753 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 9754 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 9755 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 9756 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 9757 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 9758 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 9759 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 9760
<> 144:ef7eb2e8f9f7 9761 #define TSC_CR_CTPL_Pos (24U)
<> 144:ef7eb2e8f9f7 9762 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
<> 144:ef7eb2e8f9f7 9763 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
<> 144:ef7eb2e8f9f7 9764 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 9765 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 9766 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 9767 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 9768
<> 144:ef7eb2e8f9f7 9769 #define TSC_CR_CTPH_Pos (28U)
<> 144:ef7eb2e8f9f7 9770 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
<> 144:ef7eb2e8f9f7 9771 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
<> 144:ef7eb2e8f9f7 9772 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 9773 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 9774 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 9775 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 9776
<> 144:ef7eb2e8f9f7 9777 /******************* Bit definition for TSC_IER register ********************/
<> 144:ef7eb2e8f9f7 9778 #define TSC_IER_EOAIE_Pos (0U)
<> 144:ef7eb2e8f9f7 9779 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9780 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
<> 144:ef7eb2e8f9f7 9781 #define TSC_IER_MCEIE_Pos (1U)
<> 144:ef7eb2e8f9f7 9782 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9783 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
<> 144:ef7eb2e8f9f7 9784
<> 144:ef7eb2e8f9f7 9785 /******************* Bit definition for TSC_ICR register ********************/
<> 144:ef7eb2e8f9f7 9786 #define TSC_ICR_EOAIC_Pos (0U)
<> 144:ef7eb2e8f9f7 9787 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9788 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
<> 144:ef7eb2e8f9f7 9789 #define TSC_ICR_MCEIC_Pos (1U)
<> 144:ef7eb2e8f9f7 9790 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9791 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
<> 144:ef7eb2e8f9f7 9792
<> 144:ef7eb2e8f9f7 9793 /******************* Bit definition for TSC_ISR register ********************/
<> 144:ef7eb2e8f9f7 9794 #define TSC_ISR_EOAF_Pos (0U)
<> 144:ef7eb2e8f9f7 9795 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9796 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
<> 144:ef7eb2e8f9f7 9797 #define TSC_ISR_MCEF_Pos (1U)
<> 144:ef7eb2e8f9f7 9798 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9799 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
<> 144:ef7eb2e8f9f7 9800
<> 144:ef7eb2e8f9f7 9801 /******************* Bit definition for TSC_IOHCR register ******************/
<> 144:ef7eb2e8f9f7 9802 #define TSC_IOHCR_G1_IO1_Pos (0U)
<> 144:ef7eb2e8f9f7 9803 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9804 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9805 #define TSC_IOHCR_G1_IO2_Pos (1U)
<> 144:ef7eb2e8f9f7 9806 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9807 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9808 #define TSC_IOHCR_G1_IO3_Pos (2U)
<> 144:ef7eb2e8f9f7 9809 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9810 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9811 #define TSC_IOHCR_G1_IO4_Pos (3U)
<> 144:ef7eb2e8f9f7 9812 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9813 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9814 #define TSC_IOHCR_G2_IO1_Pos (4U)
<> 144:ef7eb2e8f9f7 9815 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9816 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9817 #define TSC_IOHCR_G2_IO2_Pos (5U)
<> 144:ef7eb2e8f9f7 9818 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9819 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9820 #define TSC_IOHCR_G2_IO3_Pos (6U)
<> 144:ef7eb2e8f9f7 9821 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9822 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9823 #define TSC_IOHCR_G2_IO4_Pos (7U)
<> 144:ef7eb2e8f9f7 9824 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9825 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9826 #define TSC_IOHCR_G3_IO1_Pos (8U)
<> 144:ef7eb2e8f9f7 9827 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9828 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9829 #define TSC_IOHCR_G3_IO2_Pos (9U)
<> 144:ef7eb2e8f9f7 9830 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9831 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9832 #define TSC_IOHCR_G3_IO3_Pos (10U)
<> 144:ef7eb2e8f9f7 9833 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9834 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9835 #define TSC_IOHCR_G3_IO4_Pos (11U)
<> 144:ef7eb2e8f9f7 9836 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9837 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9838 #define TSC_IOHCR_G4_IO1_Pos (12U)
<> 144:ef7eb2e8f9f7 9839 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9840 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9841 #define TSC_IOHCR_G4_IO2_Pos (13U)
<> 144:ef7eb2e8f9f7 9842 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9843 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9844 #define TSC_IOHCR_G4_IO3_Pos (14U)
<> 144:ef7eb2e8f9f7 9845 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9846 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9847 #define TSC_IOHCR_G4_IO4_Pos (15U)
<> 144:ef7eb2e8f9f7 9848 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9849 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9850 #define TSC_IOHCR_G5_IO1_Pos (16U)
<> 144:ef7eb2e8f9f7 9851 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 9852 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9853 #define TSC_IOHCR_G5_IO2_Pos (17U)
<> 144:ef7eb2e8f9f7 9854 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 9855 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9856 #define TSC_IOHCR_G5_IO3_Pos (18U)
<> 144:ef7eb2e8f9f7 9857 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 9858 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9859 #define TSC_IOHCR_G5_IO4_Pos (19U)
<> 144:ef7eb2e8f9f7 9860 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 9861 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9862 #define TSC_IOHCR_G6_IO1_Pos (20U)
<> 144:ef7eb2e8f9f7 9863 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 9864 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9865 #define TSC_IOHCR_G6_IO2_Pos (21U)
<> 144:ef7eb2e8f9f7 9866 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 9867 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9868 #define TSC_IOHCR_G6_IO3_Pos (22U)
<> 144:ef7eb2e8f9f7 9869 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 9870 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9871 #define TSC_IOHCR_G6_IO4_Pos (23U)
<> 144:ef7eb2e8f9f7 9872 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 9873 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9874 #define TSC_IOHCR_G7_IO1_Pos (24U)
<> 144:ef7eb2e8f9f7 9875 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 9876 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9877 #define TSC_IOHCR_G7_IO2_Pos (25U)
<> 144:ef7eb2e8f9f7 9878 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 9879 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9880 #define TSC_IOHCR_G7_IO3_Pos (26U)
<> 144:ef7eb2e8f9f7 9881 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 9882 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9883 #define TSC_IOHCR_G7_IO4_Pos (27U)
<> 144:ef7eb2e8f9f7 9884 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 9885 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9886 #define TSC_IOHCR_G8_IO1_Pos (28U)
<> 144:ef7eb2e8f9f7 9887 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 9888 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9889 #define TSC_IOHCR_G8_IO2_Pos (29U)
<> 144:ef7eb2e8f9f7 9890 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 9891 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9892 #define TSC_IOHCR_G8_IO3_Pos (30U)
<> 144:ef7eb2e8f9f7 9893 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 9894 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9895 #define TSC_IOHCR_G8_IO4_Pos (31U)
<> 144:ef7eb2e8f9f7 9896 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 9897 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
<> 144:ef7eb2e8f9f7 9898
<> 144:ef7eb2e8f9f7 9899 /******************* Bit definition for TSC_IOASCR register *****************/
<> 144:ef7eb2e8f9f7 9900 #define TSC_IOASCR_G1_IO1_Pos (0U)
<> 144:ef7eb2e8f9f7 9901 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 9902 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
<> 144:ef7eb2e8f9f7 9903 #define TSC_IOASCR_G1_IO2_Pos (1U)
<> 144:ef7eb2e8f9f7 9904 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 9905 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
<> 144:ef7eb2e8f9f7 9906 #define TSC_IOASCR_G1_IO3_Pos (2U)
<> 144:ef7eb2e8f9f7 9907 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 9908 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
<> 144:ef7eb2e8f9f7 9909 #define TSC_IOASCR_G1_IO4_Pos (3U)
<> 144:ef7eb2e8f9f7 9910 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 9911 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
<> 144:ef7eb2e8f9f7 9912 #define TSC_IOASCR_G2_IO1_Pos (4U)
<> 144:ef7eb2e8f9f7 9913 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 9914 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
<> 144:ef7eb2e8f9f7 9915 #define TSC_IOASCR_G2_IO2_Pos (5U)
<> 144:ef7eb2e8f9f7 9916 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 9917 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
<> 144:ef7eb2e8f9f7 9918 #define TSC_IOASCR_G2_IO3_Pos (6U)
<> 144:ef7eb2e8f9f7 9919 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 9920 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
<> 144:ef7eb2e8f9f7 9921 #define TSC_IOASCR_G2_IO4_Pos (7U)
<> 144:ef7eb2e8f9f7 9922 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 9923 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
<> 144:ef7eb2e8f9f7 9924 #define TSC_IOASCR_G3_IO1_Pos (8U)
<> 144:ef7eb2e8f9f7 9925 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 9926 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
<> 144:ef7eb2e8f9f7 9927 #define TSC_IOASCR_G3_IO2_Pos (9U)
<> 144:ef7eb2e8f9f7 9928 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 9929 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
<> 144:ef7eb2e8f9f7 9930 #define TSC_IOASCR_G3_IO3_Pos (10U)
<> 144:ef7eb2e8f9f7 9931 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 9932 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
<> 144:ef7eb2e8f9f7 9933 #define TSC_IOASCR_G3_IO4_Pos (11U)
<> 144:ef7eb2e8f9f7 9934 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 9935 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
<> 144:ef7eb2e8f9f7 9936 #define TSC_IOASCR_G4_IO1_Pos (12U)
<> 144:ef7eb2e8f9f7 9937 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 9938 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
<> 144:ef7eb2e8f9f7 9939 #define TSC_IOASCR_G4_IO2_Pos (13U)
<> 144:ef7eb2e8f9f7 9940 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 9941 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
<> 144:ef7eb2e8f9f7 9942 #define TSC_IOASCR_G4_IO3_Pos (14U)
<> 144:ef7eb2e8f9f7 9943 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 9944 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
<> 144:ef7eb2e8f9f7 9945 #define TSC_IOASCR_G4_IO4_Pos (15U)
<> 144:ef7eb2e8f9f7 9946 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 9947 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
<> 144:ef7eb2e8f9f7 9948 #define TSC_IOASCR_G5_IO1_Pos (16U)
<> 144:ef7eb2e8f9f7 9949 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 9950 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
<> 144:ef7eb2e8f9f7 9951 #define TSC_IOASCR_G5_IO2_Pos (17U)
<> 144:ef7eb2e8f9f7 9952 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 9953 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
<> 144:ef7eb2e8f9f7 9954 #define TSC_IOASCR_G5_IO3_Pos (18U)
<> 144:ef7eb2e8f9f7 9955 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 9956 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
<> 144:ef7eb2e8f9f7 9957 #define TSC_IOASCR_G5_IO4_Pos (19U)
<> 144:ef7eb2e8f9f7 9958 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 9959 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
<> 144:ef7eb2e8f9f7 9960 #define TSC_IOASCR_G6_IO1_Pos (20U)
<> 144:ef7eb2e8f9f7 9961 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 9962 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
<> 144:ef7eb2e8f9f7 9963 #define TSC_IOASCR_G6_IO2_Pos (21U)
<> 144:ef7eb2e8f9f7 9964 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 9965 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
<> 144:ef7eb2e8f9f7 9966 #define TSC_IOASCR_G6_IO3_Pos (22U)
<> 144:ef7eb2e8f9f7 9967 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 9968 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
<> 144:ef7eb2e8f9f7 9969 #define TSC_IOASCR_G6_IO4_Pos (23U)
<> 144:ef7eb2e8f9f7 9970 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 9971 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
<> 144:ef7eb2e8f9f7 9972 #define TSC_IOASCR_G7_IO1_Pos (24U)
<> 144:ef7eb2e8f9f7 9973 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 9974 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
<> 144:ef7eb2e8f9f7 9975 #define TSC_IOASCR_G7_IO2_Pos (25U)
<> 144:ef7eb2e8f9f7 9976 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 9977 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
<> 144:ef7eb2e8f9f7 9978 #define TSC_IOASCR_G7_IO3_Pos (26U)
<> 144:ef7eb2e8f9f7 9979 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 9980 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
<> 144:ef7eb2e8f9f7 9981 #define TSC_IOASCR_G7_IO4_Pos (27U)
<> 144:ef7eb2e8f9f7 9982 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 9983 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
<> 144:ef7eb2e8f9f7 9984 #define TSC_IOASCR_G8_IO1_Pos (28U)
<> 144:ef7eb2e8f9f7 9985 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 9986 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
<> 144:ef7eb2e8f9f7 9987 #define TSC_IOASCR_G8_IO2_Pos (29U)
<> 144:ef7eb2e8f9f7 9988 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 9989 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
<> 144:ef7eb2e8f9f7 9990 #define TSC_IOASCR_G8_IO3_Pos (30U)
<> 144:ef7eb2e8f9f7 9991 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 9992 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
<> 144:ef7eb2e8f9f7 9993 #define TSC_IOASCR_G8_IO4_Pos (31U)
<> 144:ef7eb2e8f9f7 9994 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 9995 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
<> 144:ef7eb2e8f9f7 9996
<> 144:ef7eb2e8f9f7 9997 /******************* Bit definition for TSC_IOSCR register ******************/
<> 144:ef7eb2e8f9f7 9998 #define TSC_IOSCR_G1_IO1_Pos (0U)
<> 144:ef7eb2e8f9f7 9999 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10000 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
<> 144:ef7eb2e8f9f7 10001 #define TSC_IOSCR_G1_IO2_Pos (1U)
<> 144:ef7eb2e8f9f7 10002 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10003 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
<> 144:ef7eb2e8f9f7 10004 #define TSC_IOSCR_G1_IO3_Pos (2U)
<> 144:ef7eb2e8f9f7 10005 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10006 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
<> 144:ef7eb2e8f9f7 10007 #define TSC_IOSCR_G1_IO4_Pos (3U)
<> 144:ef7eb2e8f9f7 10008 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10009 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
<> 144:ef7eb2e8f9f7 10010 #define TSC_IOSCR_G2_IO1_Pos (4U)
<> 144:ef7eb2e8f9f7 10011 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10012 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
<> 144:ef7eb2e8f9f7 10013 #define TSC_IOSCR_G2_IO2_Pos (5U)
<> 144:ef7eb2e8f9f7 10014 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10015 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
<> 144:ef7eb2e8f9f7 10016 #define TSC_IOSCR_G2_IO3_Pos (6U)
<> 144:ef7eb2e8f9f7 10017 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10018 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
<> 144:ef7eb2e8f9f7 10019 #define TSC_IOSCR_G2_IO4_Pos (7U)
<> 144:ef7eb2e8f9f7 10020 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10021 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
<> 144:ef7eb2e8f9f7 10022 #define TSC_IOSCR_G3_IO1_Pos (8U)
<> 144:ef7eb2e8f9f7 10023 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 10024 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
<> 144:ef7eb2e8f9f7 10025 #define TSC_IOSCR_G3_IO2_Pos (9U)
<> 144:ef7eb2e8f9f7 10026 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 10027 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
<> 144:ef7eb2e8f9f7 10028 #define TSC_IOSCR_G3_IO3_Pos (10U)
<> 144:ef7eb2e8f9f7 10029 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 10030 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
<> 144:ef7eb2e8f9f7 10031 #define TSC_IOSCR_G3_IO4_Pos (11U)
<> 144:ef7eb2e8f9f7 10032 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 10033 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
<> 144:ef7eb2e8f9f7 10034 #define TSC_IOSCR_G4_IO1_Pos (12U)
<> 144:ef7eb2e8f9f7 10035 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 10036 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
<> 144:ef7eb2e8f9f7 10037 #define TSC_IOSCR_G4_IO2_Pos (13U)
<> 144:ef7eb2e8f9f7 10038 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 10039 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
<> 144:ef7eb2e8f9f7 10040 #define TSC_IOSCR_G4_IO3_Pos (14U)
<> 144:ef7eb2e8f9f7 10041 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 10042 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
<> 144:ef7eb2e8f9f7 10043 #define TSC_IOSCR_G4_IO4_Pos (15U)
<> 144:ef7eb2e8f9f7 10044 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 10045 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
<> 144:ef7eb2e8f9f7 10046 #define TSC_IOSCR_G5_IO1_Pos (16U)
<> 144:ef7eb2e8f9f7 10047 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 10048 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
<> 144:ef7eb2e8f9f7 10049 #define TSC_IOSCR_G5_IO2_Pos (17U)
<> 144:ef7eb2e8f9f7 10050 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 10051 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
<> 144:ef7eb2e8f9f7 10052 #define TSC_IOSCR_G5_IO3_Pos (18U)
<> 144:ef7eb2e8f9f7 10053 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 10054 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
<> 144:ef7eb2e8f9f7 10055 #define TSC_IOSCR_G5_IO4_Pos (19U)
<> 144:ef7eb2e8f9f7 10056 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10057 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
<> 144:ef7eb2e8f9f7 10058 #define TSC_IOSCR_G6_IO1_Pos (20U)
<> 144:ef7eb2e8f9f7 10059 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10060 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
<> 144:ef7eb2e8f9f7 10061 #define TSC_IOSCR_G6_IO2_Pos (21U)
<> 144:ef7eb2e8f9f7 10062 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 10063 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
<> 144:ef7eb2e8f9f7 10064 #define TSC_IOSCR_G6_IO3_Pos (22U)
<> 144:ef7eb2e8f9f7 10065 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 10066 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
<> 144:ef7eb2e8f9f7 10067 #define TSC_IOSCR_G6_IO4_Pos (23U)
<> 144:ef7eb2e8f9f7 10068 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 10069 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
<> 144:ef7eb2e8f9f7 10070 #define TSC_IOSCR_G7_IO1_Pos (24U)
<> 144:ef7eb2e8f9f7 10071 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 10072 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
<> 144:ef7eb2e8f9f7 10073 #define TSC_IOSCR_G7_IO2_Pos (25U)
<> 144:ef7eb2e8f9f7 10074 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 10075 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
<> 144:ef7eb2e8f9f7 10076 #define TSC_IOSCR_G7_IO3_Pos (26U)
<> 144:ef7eb2e8f9f7 10077 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 10078 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
<> 144:ef7eb2e8f9f7 10079 #define TSC_IOSCR_G7_IO4_Pos (27U)
<> 144:ef7eb2e8f9f7 10080 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 10081 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
<> 144:ef7eb2e8f9f7 10082 #define TSC_IOSCR_G8_IO1_Pos (28U)
<> 144:ef7eb2e8f9f7 10083 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 10084 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
<> 144:ef7eb2e8f9f7 10085 #define TSC_IOSCR_G8_IO2_Pos (29U)
<> 144:ef7eb2e8f9f7 10086 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 10087 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
<> 144:ef7eb2e8f9f7 10088 #define TSC_IOSCR_G8_IO3_Pos (30U)
<> 144:ef7eb2e8f9f7 10089 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 10090 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
<> 144:ef7eb2e8f9f7 10091 #define TSC_IOSCR_G8_IO4_Pos (31U)
<> 144:ef7eb2e8f9f7 10092 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 10093 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
<> 144:ef7eb2e8f9f7 10094
<> 144:ef7eb2e8f9f7 10095 /******************* Bit definition for TSC_IOCCR register ******************/
<> 144:ef7eb2e8f9f7 10096 #define TSC_IOCCR_G1_IO1_Pos (0U)
<> 144:ef7eb2e8f9f7 10097 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10098 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
<> 144:ef7eb2e8f9f7 10099 #define TSC_IOCCR_G1_IO2_Pos (1U)
<> 144:ef7eb2e8f9f7 10100 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10101 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
<> 144:ef7eb2e8f9f7 10102 #define TSC_IOCCR_G1_IO3_Pos (2U)
<> 144:ef7eb2e8f9f7 10103 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10104 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
<> 144:ef7eb2e8f9f7 10105 #define TSC_IOCCR_G1_IO4_Pos (3U)
<> 144:ef7eb2e8f9f7 10106 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10107 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
<> 144:ef7eb2e8f9f7 10108 #define TSC_IOCCR_G2_IO1_Pos (4U)
<> 144:ef7eb2e8f9f7 10109 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10110 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
<> 144:ef7eb2e8f9f7 10111 #define TSC_IOCCR_G2_IO2_Pos (5U)
<> 144:ef7eb2e8f9f7 10112 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10113 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
<> 144:ef7eb2e8f9f7 10114 #define TSC_IOCCR_G2_IO3_Pos (6U)
<> 144:ef7eb2e8f9f7 10115 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10116 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
<> 144:ef7eb2e8f9f7 10117 #define TSC_IOCCR_G2_IO4_Pos (7U)
<> 144:ef7eb2e8f9f7 10118 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10119 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
<> 144:ef7eb2e8f9f7 10120 #define TSC_IOCCR_G3_IO1_Pos (8U)
<> 144:ef7eb2e8f9f7 10121 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 10122 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
<> 144:ef7eb2e8f9f7 10123 #define TSC_IOCCR_G3_IO2_Pos (9U)
<> 144:ef7eb2e8f9f7 10124 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 10125 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
<> 144:ef7eb2e8f9f7 10126 #define TSC_IOCCR_G3_IO3_Pos (10U)
<> 144:ef7eb2e8f9f7 10127 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 10128 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
<> 144:ef7eb2e8f9f7 10129 #define TSC_IOCCR_G3_IO4_Pos (11U)
<> 144:ef7eb2e8f9f7 10130 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 10131 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
<> 144:ef7eb2e8f9f7 10132 #define TSC_IOCCR_G4_IO1_Pos (12U)
<> 144:ef7eb2e8f9f7 10133 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 10134 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
<> 144:ef7eb2e8f9f7 10135 #define TSC_IOCCR_G4_IO2_Pos (13U)
<> 144:ef7eb2e8f9f7 10136 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 10137 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
<> 144:ef7eb2e8f9f7 10138 #define TSC_IOCCR_G4_IO3_Pos (14U)
<> 144:ef7eb2e8f9f7 10139 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 10140 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
<> 144:ef7eb2e8f9f7 10141 #define TSC_IOCCR_G4_IO4_Pos (15U)
<> 144:ef7eb2e8f9f7 10142 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 10143 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
<> 144:ef7eb2e8f9f7 10144 #define TSC_IOCCR_G5_IO1_Pos (16U)
<> 144:ef7eb2e8f9f7 10145 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 10146 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
<> 144:ef7eb2e8f9f7 10147 #define TSC_IOCCR_G5_IO2_Pos (17U)
<> 144:ef7eb2e8f9f7 10148 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 10149 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
<> 144:ef7eb2e8f9f7 10150 #define TSC_IOCCR_G5_IO3_Pos (18U)
<> 144:ef7eb2e8f9f7 10151 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 10152 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
<> 144:ef7eb2e8f9f7 10153 #define TSC_IOCCR_G5_IO4_Pos (19U)
<> 144:ef7eb2e8f9f7 10154 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10155 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
<> 144:ef7eb2e8f9f7 10156 #define TSC_IOCCR_G6_IO1_Pos (20U)
<> 144:ef7eb2e8f9f7 10157 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10158 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
<> 144:ef7eb2e8f9f7 10159 #define TSC_IOCCR_G6_IO2_Pos (21U)
<> 144:ef7eb2e8f9f7 10160 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 10161 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
<> 144:ef7eb2e8f9f7 10162 #define TSC_IOCCR_G6_IO3_Pos (22U)
<> 144:ef7eb2e8f9f7 10163 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 10164 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
<> 144:ef7eb2e8f9f7 10165 #define TSC_IOCCR_G6_IO4_Pos (23U)
<> 144:ef7eb2e8f9f7 10166 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 10167 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
<> 144:ef7eb2e8f9f7 10168 #define TSC_IOCCR_G7_IO1_Pos (24U)
<> 144:ef7eb2e8f9f7 10169 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 10170 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
<> 144:ef7eb2e8f9f7 10171 #define TSC_IOCCR_G7_IO2_Pos (25U)
<> 144:ef7eb2e8f9f7 10172 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 10173 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
<> 144:ef7eb2e8f9f7 10174 #define TSC_IOCCR_G7_IO3_Pos (26U)
<> 144:ef7eb2e8f9f7 10175 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 10176 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
<> 144:ef7eb2e8f9f7 10177 #define TSC_IOCCR_G7_IO4_Pos (27U)
<> 144:ef7eb2e8f9f7 10178 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 10179 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
<> 144:ef7eb2e8f9f7 10180 #define TSC_IOCCR_G8_IO1_Pos (28U)
<> 144:ef7eb2e8f9f7 10181 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 10182 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
<> 144:ef7eb2e8f9f7 10183 #define TSC_IOCCR_G8_IO2_Pos (29U)
<> 144:ef7eb2e8f9f7 10184 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 10185 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
<> 144:ef7eb2e8f9f7 10186 #define TSC_IOCCR_G8_IO3_Pos (30U)
<> 144:ef7eb2e8f9f7 10187 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 10188 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
<> 144:ef7eb2e8f9f7 10189 #define TSC_IOCCR_G8_IO4_Pos (31U)
<> 144:ef7eb2e8f9f7 10190 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 10191 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
<> 144:ef7eb2e8f9f7 10192
<> 144:ef7eb2e8f9f7 10193 /******************* Bit definition for TSC_IOGCSR register *****************/
<> 144:ef7eb2e8f9f7 10194 #define TSC_IOGCSR_G1E_Pos (0U)
<> 144:ef7eb2e8f9f7 10195 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10196 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
<> 144:ef7eb2e8f9f7 10197 #define TSC_IOGCSR_G2E_Pos (1U)
<> 144:ef7eb2e8f9f7 10198 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10199 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
<> 144:ef7eb2e8f9f7 10200 #define TSC_IOGCSR_G3E_Pos (2U)
<> 144:ef7eb2e8f9f7 10201 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10202 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
<> 144:ef7eb2e8f9f7 10203 #define TSC_IOGCSR_G4E_Pos (3U)
<> 144:ef7eb2e8f9f7 10204 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10205 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
<> 144:ef7eb2e8f9f7 10206 #define TSC_IOGCSR_G5E_Pos (4U)
<> 144:ef7eb2e8f9f7 10207 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10208 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
<> 144:ef7eb2e8f9f7 10209 #define TSC_IOGCSR_G6E_Pos (5U)
<> 144:ef7eb2e8f9f7 10210 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10211 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
<> 144:ef7eb2e8f9f7 10212 #define TSC_IOGCSR_G7E_Pos (6U)
<> 144:ef7eb2e8f9f7 10213 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10214 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
<> 144:ef7eb2e8f9f7 10215 #define TSC_IOGCSR_G8E_Pos (7U)
<> 144:ef7eb2e8f9f7 10216 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10217 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
<> 144:ef7eb2e8f9f7 10218 #define TSC_IOGCSR_G1S_Pos (16U)
<> 144:ef7eb2e8f9f7 10219 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 10220 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
<> 144:ef7eb2e8f9f7 10221 #define TSC_IOGCSR_G2S_Pos (17U)
<> 144:ef7eb2e8f9f7 10222 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 10223 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
<> 144:ef7eb2e8f9f7 10224 #define TSC_IOGCSR_G3S_Pos (18U)
<> 144:ef7eb2e8f9f7 10225 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 10226 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
<> 144:ef7eb2e8f9f7 10227 #define TSC_IOGCSR_G4S_Pos (19U)
<> 144:ef7eb2e8f9f7 10228 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10229 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
<> 144:ef7eb2e8f9f7 10230 #define TSC_IOGCSR_G5S_Pos (20U)
<> 144:ef7eb2e8f9f7 10231 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10232 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
<> 144:ef7eb2e8f9f7 10233 #define TSC_IOGCSR_G6S_Pos (21U)
<> 144:ef7eb2e8f9f7 10234 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 10235 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
<> 144:ef7eb2e8f9f7 10236 #define TSC_IOGCSR_G7S_Pos (22U)
<> 144:ef7eb2e8f9f7 10237 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 10238 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
<> 144:ef7eb2e8f9f7 10239 #define TSC_IOGCSR_G8S_Pos (23U)
<> 144:ef7eb2e8f9f7 10240 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 10241 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
<> 144:ef7eb2e8f9f7 10242
<> 144:ef7eb2e8f9f7 10243 /******************* Bit definition for TSC_IOGXCR register *****************/
<> 144:ef7eb2e8f9f7 10244 #define TSC_IOGXCR_CNT_Pos (0U)
<> 144:ef7eb2e8f9f7 10245 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
<> 144:ef7eb2e8f9f7 10246 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
<> 144:ef7eb2e8f9f7 10247
<> 144:ef7eb2e8f9f7 10248 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10249 /* */
<> 144:ef7eb2e8f9f7 10250 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
<> 144:ef7eb2e8f9f7 10251 /* */
<> 144:ef7eb2e8f9f7 10252 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10253
<> 144:ef7eb2e8f9f7 10254 /*
<> 144:ef7eb2e8f9f7 10255 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 144:ef7eb2e8f9f7 10256 */
<> 144:ef7eb2e8f9f7 10257
<> 144:ef7eb2e8f9f7 10258 /* Support of 7 bits data length feature */
<> 144:ef7eb2e8f9f7 10259 #define USART_7BITS_SUPPORT
<> 144:ef7eb2e8f9f7 10260
<> 144:ef7eb2e8f9f7 10261 /* Support of LIN feature */
<> 144:ef7eb2e8f9f7 10262 #define USART_LIN_SUPPORT
<> 144:ef7eb2e8f9f7 10263
<> 144:ef7eb2e8f9f7 10264 /* Support of Smartcard feature */
<> 144:ef7eb2e8f9f7 10265 #define USART_SMARTCARD_SUPPORT
<> 144:ef7eb2e8f9f7 10266
<> 144:ef7eb2e8f9f7 10267 /* Support of Irda feature */
<> 144:ef7eb2e8f9f7 10268 #define USART_IRDA_SUPPORT
<> 144:ef7eb2e8f9f7 10269
<> 144:ef7eb2e8f9f7 10270 /* Support of Wake Up from Stop Mode feature */
<> 144:ef7eb2e8f9f7 10271 #define USART_WUSM_SUPPORT
<> 144:ef7eb2e8f9f7 10272
<> 144:ef7eb2e8f9f7 10273 /* Support of Full Auto Baud rate feature (4 modes) activation */
<> 144:ef7eb2e8f9f7 10274 #define USART_FABR_SUPPORT
<> 144:ef7eb2e8f9f7 10275
<> 144:ef7eb2e8f9f7 10276 /****************** Bit definition for USART_CR1 register *******************/
<> 144:ef7eb2e8f9f7 10277 #define USART_CR1_UE_Pos (0U)
<> 144:ef7eb2e8f9f7 10278 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10279 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
<> 144:ef7eb2e8f9f7 10280 #define USART_CR1_UESM_Pos (1U)
<> 144:ef7eb2e8f9f7 10281 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10282 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
<> 144:ef7eb2e8f9f7 10283 #define USART_CR1_RE_Pos (2U)
<> 144:ef7eb2e8f9f7 10284 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10285 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
<> 144:ef7eb2e8f9f7 10286 #define USART_CR1_TE_Pos (3U)
<> 144:ef7eb2e8f9f7 10287 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10288 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
<> 144:ef7eb2e8f9f7 10289 #define USART_CR1_IDLEIE_Pos (4U)
<> 144:ef7eb2e8f9f7 10290 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10291 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
<> 144:ef7eb2e8f9f7 10292 #define USART_CR1_RXNEIE_Pos (5U)
<> 144:ef7eb2e8f9f7 10293 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10294 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
<> 144:ef7eb2e8f9f7 10295 #define USART_CR1_TCIE_Pos (6U)
<> 144:ef7eb2e8f9f7 10296 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10297 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 10298 #define USART_CR1_TXEIE_Pos (7U)
<> 144:ef7eb2e8f9f7 10299 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10300 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
<> 144:ef7eb2e8f9f7 10301 #define USART_CR1_PEIE_Pos (8U)
<> 144:ef7eb2e8f9f7 10302 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 10303 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 10304 #define USART_CR1_PS_Pos (9U)
<> 144:ef7eb2e8f9f7 10305 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 10306 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
<> 144:ef7eb2e8f9f7 10307 #define USART_CR1_PCE_Pos (10U)
<> 144:ef7eb2e8f9f7 10308 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 10309 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
<> 144:ef7eb2e8f9f7 10310 #define USART_CR1_WAKE_Pos (11U)
<> 144:ef7eb2e8f9f7 10311 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 10312 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
<> 144:ef7eb2e8f9f7 10313 #define USART_CR1_M0_Pos (12U)
<> 144:ef7eb2e8f9f7 10314 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 10315 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */
<> 144:ef7eb2e8f9f7 10316 #define USART_CR1_MME_Pos (13U)
<> 144:ef7eb2e8f9f7 10317 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 10318 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
<> 144:ef7eb2e8f9f7 10319 #define USART_CR1_CMIE_Pos (14U)
<> 144:ef7eb2e8f9f7 10320 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 10321 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
<> 144:ef7eb2e8f9f7 10322 #define USART_CR1_OVER8_Pos (15U)
<> 144:ef7eb2e8f9f7 10323 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 10324 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
<> 144:ef7eb2e8f9f7 10325 #define USART_CR1_DEDT_Pos (16U)
<> 144:ef7eb2e8f9f7 10326 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
<> 144:ef7eb2e8f9f7 10327 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
<> 144:ef7eb2e8f9f7 10328 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 10329 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 10330 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 10331 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10332 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10333 #define USART_CR1_DEAT_Pos (21U)
<> 144:ef7eb2e8f9f7 10334 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
<> 144:ef7eb2e8f9f7 10335 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
<> 144:ef7eb2e8f9f7 10336 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 10337 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 10338 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 10339 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 10340 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 10341 #define USART_CR1_RTOIE_Pos (26U)
<> 144:ef7eb2e8f9f7 10342 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 10343 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
<> 144:ef7eb2e8f9f7 10344 #define USART_CR1_EOBIE_Pos (27U)
<> 144:ef7eb2e8f9f7 10345 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 10346 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
<> 144:ef7eb2e8f9f7 10347 #define USART_CR1_M1_Pos (28U)
<> 144:ef7eb2e8f9f7 10348 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
<> 144:ef7eb2e8f9f7 10349 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */
<> 144:ef7eb2e8f9f7 10350 #define USART_CR1_M_Pos (12U)
<> 144:ef7eb2e8f9f7 10351 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
<> 144:ef7eb2e8f9f7 10352 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */
<> 144:ef7eb2e8f9f7 10353
<> 144:ef7eb2e8f9f7 10354 /****************** Bit definition for USART_CR2 register *******************/
<> 144:ef7eb2e8f9f7 10355 #define USART_CR2_ADDM7_Pos (4U)
<> 144:ef7eb2e8f9f7 10356 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10357 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
<> 144:ef7eb2e8f9f7 10358 #define USART_CR2_LBDL_Pos (5U)
<> 144:ef7eb2e8f9f7 10359 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10360 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
<> 144:ef7eb2e8f9f7 10361 #define USART_CR2_LBDIE_Pos (6U)
<> 144:ef7eb2e8f9f7 10362 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10363 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
<> 144:ef7eb2e8f9f7 10364 #define USART_CR2_LBCL_Pos (8U)
<> 144:ef7eb2e8f9f7 10365 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 10366 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
<> 144:ef7eb2e8f9f7 10367 #define USART_CR2_CPHA_Pos (9U)
<> 144:ef7eb2e8f9f7 10368 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 10369 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
<> 144:ef7eb2e8f9f7 10370 #define USART_CR2_CPOL_Pos (10U)
<> 144:ef7eb2e8f9f7 10371 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 10372 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
<> 144:ef7eb2e8f9f7 10373 #define USART_CR2_CLKEN_Pos (11U)
<> 144:ef7eb2e8f9f7 10374 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 10375 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
<> 144:ef7eb2e8f9f7 10376 #define USART_CR2_STOP_Pos (12U)
<> 144:ef7eb2e8f9f7 10377 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
<> 144:ef7eb2e8f9f7 10378 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
<> 144:ef7eb2e8f9f7 10379 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 10380 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 10381 #define USART_CR2_LINEN_Pos (14U)
<> 144:ef7eb2e8f9f7 10382 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 10383 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
<> 144:ef7eb2e8f9f7 10384 #define USART_CR2_SWAP_Pos (15U)
<> 144:ef7eb2e8f9f7 10385 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 10386 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
<> 144:ef7eb2e8f9f7 10387 #define USART_CR2_RXINV_Pos (16U)
<> 144:ef7eb2e8f9f7 10388 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 10389 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
<> 144:ef7eb2e8f9f7 10390 #define USART_CR2_TXINV_Pos (17U)
<> 144:ef7eb2e8f9f7 10391 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 10392 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
<> 144:ef7eb2e8f9f7 10393 #define USART_CR2_DATAINV_Pos (18U)
<> 144:ef7eb2e8f9f7 10394 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 10395 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
<> 144:ef7eb2e8f9f7 10396 #define USART_CR2_MSBFIRST_Pos (19U)
<> 144:ef7eb2e8f9f7 10397 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10398 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
<> 144:ef7eb2e8f9f7 10399 #define USART_CR2_ABREN_Pos (20U)
<> 144:ef7eb2e8f9f7 10400 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10401 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
<> 144:ef7eb2e8f9f7 10402 #define USART_CR2_ABRMODE_Pos (21U)
<> 144:ef7eb2e8f9f7 10403 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
<> 144:ef7eb2e8f9f7 10404 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
<> 144:ef7eb2e8f9f7 10405 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 10406 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 10407 #define USART_CR2_RTOEN_Pos (23U)
<> 144:ef7eb2e8f9f7 10408 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 10409 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
<> 144:ef7eb2e8f9f7 10410 #define USART_CR2_ADD_Pos (24U)
<> 144:ef7eb2e8f9f7 10411 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 10412 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
<> 144:ef7eb2e8f9f7 10413
<> 144:ef7eb2e8f9f7 10414 /****************** Bit definition for USART_CR3 register *******************/
<> 144:ef7eb2e8f9f7 10415 #define USART_CR3_EIE_Pos (0U)
<> 144:ef7eb2e8f9f7 10416 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10417 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 10418 #define USART_CR3_IREN_Pos (1U)
<> 144:ef7eb2e8f9f7 10419 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10420 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
<> 144:ef7eb2e8f9f7 10421 #define USART_CR3_IRLP_Pos (2U)
<> 144:ef7eb2e8f9f7 10422 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10423 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
<> 144:ef7eb2e8f9f7 10424 #define USART_CR3_HDSEL_Pos (3U)
<> 144:ef7eb2e8f9f7 10425 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10426 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
<> 144:ef7eb2e8f9f7 10427 #define USART_CR3_NACK_Pos (4U)
<> 144:ef7eb2e8f9f7 10428 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10429 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
<> 144:ef7eb2e8f9f7 10430 #define USART_CR3_SCEN_Pos (5U)
<> 144:ef7eb2e8f9f7 10431 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10432 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
<> 144:ef7eb2e8f9f7 10433 #define USART_CR3_DMAR_Pos (6U)
<> 144:ef7eb2e8f9f7 10434 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10435 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
<> 144:ef7eb2e8f9f7 10436 #define USART_CR3_DMAT_Pos (7U)
<> 144:ef7eb2e8f9f7 10437 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10438 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
<> 144:ef7eb2e8f9f7 10439 #define USART_CR3_RTSE_Pos (8U)
<> 144:ef7eb2e8f9f7 10440 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 10441 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
<> 144:ef7eb2e8f9f7 10442 #define USART_CR3_CTSE_Pos (9U)
<> 144:ef7eb2e8f9f7 10443 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 10444 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
<> 144:ef7eb2e8f9f7 10445 #define USART_CR3_CTSIE_Pos (10U)
<> 144:ef7eb2e8f9f7 10446 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 10447 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
<> 144:ef7eb2e8f9f7 10448 #define USART_CR3_ONEBIT_Pos (11U)
<> 144:ef7eb2e8f9f7 10449 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 10450 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
<> 144:ef7eb2e8f9f7 10451 #define USART_CR3_OVRDIS_Pos (12U)
<> 144:ef7eb2e8f9f7 10452 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 10453 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
<> 144:ef7eb2e8f9f7 10454 #define USART_CR3_DDRE_Pos (13U)
<> 144:ef7eb2e8f9f7 10455 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
<> 144:ef7eb2e8f9f7 10456 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
<> 144:ef7eb2e8f9f7 10457 #define USART_CR3_DEM_Pos (14U)
<> 144:ef7eb2e8f9f7 10458 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 10459 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
<> 144:ef7eb2e8f9f7 10460 #define USART_CR3_DEP_Pos (15U)
<> 144:ef7eb2e8f9f7 10461 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 10462 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
<> 144:ef7eb2e8f9f7 10463 #define USART_CR3_SCARCNT_Pos (17U)
<> 144:ef7eb2e8f9f7 10464 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
<> 144:ef7eb2e8f9f7 10465 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
<> 144:ef7eb2e8f9f7 10466 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 10467 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 10468 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10469 #define USART_CR3_WUS_Pos (20U)
<> 144:ef7eb2e8f9f7 10470 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
<> 144:ef7eb2e8f9f7 10471 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
<> 144:ef7eb2e8f9f7 10472 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10473 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 10474 #define USART_CR3_WUFIE_Pos (22U)
<> 144:ef7eb2e8f9f7 10475 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 10476 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
<> 144:ef7eb2e8f9f7 10477
<> 144:ef7eb2e8f9f7 10478 /****************** Bit definition for USART_BRR register *******************/
<> 144:ef7eb2e8f9f7 10479 #define USART_BRR_DIV_FRACTION_Pos (0U)
<> 144:ef7eb2e8f9f7 10480 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
<> 144:ef7eb2e8f9f7 10481 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
<> 144:ef7eb2e8f9f7 10482 #define USART_BRR_DIV_MANTISSA_Pos (4U)
<> 144:ef7eb2e8f9f7 10483 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
<> 144:ef7eb2e8f9f7 10484 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
<> 144:ef7eb2e8f9f7 10485
<> 144:ef7eb2e8f9f7 10486 /****************** Bit definition for USART_GTPR register ******************/
<> 144:ef7eb2e8f9f7 10487 #define USART_GTPR_PSC_Pos (0U)
<> 144:ef7eb2e8f9f7 10488 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
<> 144:ef7eb2e8f9f7 10489 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
<> 144:ef7eb2e8f9f7 10490 #define USART_GTPR_GT_Pos (8U)
<> 144:ef7eb2e8f9f7 10491 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
<> 144:ef7eb2e8f9f7 10492 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
<> 144:ef7eb2e8f9f7 10493
<> 144:ef7eb2e8f9f7 10494
<> 144:ef7eb2e8f9f7 10495 /******************* Bit definition for USART_RTOR register *****************/
<> 144:ef7eb2e8f9f7 10496 #define USART_RTOR_RTO_Pos (0U)
<> 144:ef7eb2e8f9f7 10497 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
<> 144:ef7eb2e8f9f7 10498 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
<> 144:ef7eb2e8f9f7 10499 #define USART_RTOR_BLEN_Pos (24U)
<> 144:ef7eb2e8f9f7 10500 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
<> 144:ef7eb2e8f9f7 10501 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
<> 144:ef7eb2e8f9f7 10502
<> 144:ef7eb2e8f9f7 10503 /******************* Bit definition for USART_RQR register ******************/
<> 144:ef7eb2e8f9f7 10504 #define USART_RQR_ABRRQ_Pos (0U)
<> 144:ef7eb2e8f9f7 10505 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10506 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
<> 144:ef7eb2e8f9f7 10507 #define USART_RQR_SBKRQ_Pos (1U)
<> 144:ef7eb2e8f9f7 10508 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10509 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
<> 144:ef7eb2e8f9f7 10510 #define USART_RQR_MMRQ_Pos (2U)
<> 144:ef7eb2e8f9f7 10511 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10512 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
<> 144:ef7eb2e8f9f7 10513 #define USART_RQR_RXFRQ_Pos (3U)
<> 144:ef7eb2e8f9f7 10514 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10515 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
<> 144:ef7eb2e8f9f7 10516 #define USART_RQR_TXFRQ_Pos (4U)
<> 144:ef7eb2e8f9f7 10517 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10518 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
<> 144:ef7eb2e8f9f7 10519
<> 144:ef7eb2e8f9f7 10520 /******************* Bit definition for USART_ISR register ******************/
<> 144:ef7eb2e8f9f7 10521 #define USART_ISR_PE_Pos (0U)
<> 144:ef7eb2e8f9f7 10522 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10523 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
<> 144:ef7eb2e8f9f7 10524 #define USART_ISR_FE_Pos (1U)
<> 144:ef7eb2e8f9f7 10525 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10526 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
<> 144:ef7eb2e8f9f7 10527 #define USART_ISR_NE_Pos (2U)
<> 144:ef7eb2e8f9f7 10528 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10529 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
<> 144:ef7eb2e8f9f7 10530 #define USART_ISR_ORE_Pos (3U)
<> 144:ef7eb2e8f9f7 10531 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10532 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
<> 144:ef7eb2e8f9f7 10533 #define USART_ISR_IDLE_Pos (4U)
<> 144:ef7eb2e8f9f7 10534 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10535 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
<> 144:ef7eb2e8f9f7 10536 #define USART_ISR_RXNE_Pos (5U)
<> 144:ef7eb2e8f9f7 10537 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10538 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
<> 144:ef7eb2e8f9f7 10539 #define USART_ISR_TC_Pos (6U)
<> 144:ef7eb2e8f9f7 10540 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10541 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
<> 144:ef7eb2e8f9f7 10542 #define USART_ISR_TXE_Pos (7U)
<> 144:ef7eb2e8f9f7 10543 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10544 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
<> 144:ef7eb2e8f9f7 10545 #define USART_ISR_LBDF_Pos (8U)
<> 144:ef7eb2e8f9f7 10546 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 10547 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
<> 144:ef7eb2e8f9f7 10548 #define USART_ISR_CTSIF_Pos (9U)
<> 144:ef7eb2e8f9f7 10549 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 10550 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
<> 144:ef7eb2e8f9f7 10551 #define USART_ISR_CTS_Pos (10U)
<> 144:ef7eb2e8f9f7 10552 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
<> 144:ef7eb2e8f9f7 10553 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
<> 144:ef7eb2e8f9f7 10554 #define USART_ISR_RTOF_Pos (11U)
<> 144:ef7eb2e8f9f7 10555 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 10556 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
<> 144:ef7eb2e8f9f7 10557 #define USART_ISR_EOBF_Pos (12U)
<> 144:ef7eb2e8f9f7 10558 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 10559 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
<> 144:ef7eb2e8f9f7 10560 #define USART_ISR_ABRE_Pos (14U)
<> 144:ef7eb2e8f9f7 10561 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 10562 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
<> 144:ef7eb2e8f9f7 10563 #define USART_ISR_ABRF_Pos (15U)
<> 144:ef7eb2e8f9f7 10564 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 10565 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
<> 144:ef7eb2e8f9f7 10566 #define USART_ISR_BUSY_Pos (16U)
<> 144:ef7eb2e8f9f7 10567 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
<> 144:ef7eb2e8f9f7 10568 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
<> 144:ef7eb2e8f9f7 10569 #define USART_ISR_CMF_Pos (17U)
<> 144:ef7eb2e8f9f7 10570 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 10571 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
<> 144:ef7eb2e8f9f7 10572 #define USART_ISR_SBKF_Pos (18U)
<> 144:ef7eb2e8f9f7 10573 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 10574 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
<> 144:ef7eb2e8f9f7 10575 #define USART_ISR_RWU_Pos (19U)
<> 144:ef7eb2e8f9f7 10576 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10577 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
<> 144:ef7eb2e8f9f7 10578 #define USART_ISR_WUF_Pos (20U)
<> 144:ef7eb2e8f9f7 10579 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10580 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
<> 144:ef7eb2e8f9f7 10581 #define USART_ISR_TEACK_Pos (21U)
<> 144:ef7eb2e8f9f7 10582 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 10583 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
<> 144:ef7eb2e8f9f7 10584 #define USART_ISR_REACK_Pos (22U)
<> 144:ef7eb2e8f9f7 10585 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
<> 144:ef7eb2e8f9f7 10586 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
<> 144:ef7eb2e8f9f7 10587
<> 144:ef7eb2e8f9f7 10588 /******************* Bit definition for USART_ICR register ******************/
<> 144:ef7eb2e8f9f7 10589 #define USART_ICR_PECF_Pos (0U)
<> 144:ef7eb2e8f9f7 10590 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10591 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
<> 144:ef7eb2e8f9f7 10592 #define USART_ICR_FECF_Pos (1U)
<> 144:ef7eb2e8f9f7 10593 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10594 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
<> 144:ef7eb2e8f9f7 10595 #define USART_ICR_NCF_Pos (2U)
<> 144:ef7eb2e8f9f7 10596 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10597 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
<> 144:ef7eb2e8f9f7 10598 #define USART_ICR_ORECF_Pos (3U)
<> 144:ef7eb2e8f9f7 10599 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10600 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
<> 144:ef7eb2e8f9f7 10601 #define USART_ICR_IDLECF_Pos (4U)
<> 144:ef7eb2e8f9f7 10602 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10603 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
<> 144:ef7eb2e8f9f7 10604 #define USART_ICR_TCCF_Pos (6U)
<> 144:ef7eb2e8f9f7 10605 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10606 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
<> 144:ef7eb2e8f9f7 10607 #define USART_ICR_LBDCF_Pos (8U)
<> 144:ef7eb2e8f9f7 10608 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 10609 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
<> 144:ef7eb2e8f9f7 10610 #define USART_ICR_CTSCF_Pos (9U)
<> 144:ef7eb2e8f9f7 10611 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 10612 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
<> 144:ef7eb2e8f9f7 10613 #define USART_ICR_RTOCF_Pos (11U)
<> 144:ef7eb2e8f9f7 10614 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 10615 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
<> 144:ef7eb2e8f9f7 10616 #define USART_ICR_EOBCF_Pos (12U)
<> 144:ef7eb2e8f9f7 10617 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 10618 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
<> 144:ef7eb2e8f9f7 10619 #define USART_ICR_CMCF_Pos (17U)
<> 144:ef7eb2e8f9f7 10620 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 10621 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
<> 144:ef7eb2e8f9f7 10622 #define USART_ICR_WUCF_Pos (20U)
<> 144:ef7eb2e8f9f7 10623 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10624 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
<> 144:ef7eb2e8f9f7 10625
<> 144:ef7eb2e8f9f7 10626 /******************* Bit definition for USART_RDR register ******************/
<> 144:ef7eb2e8f9f7 10627 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
<> 144:ef7eb2e8f9f7 10628
<> 144:ef7eb2e8f9f7 10629 /******************* Bit definition for USART_TDR register ******************/
<> 144:ef7eb2e8f9f7 10630 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
<> 144:ef7eb2e8f9f7 10631
<> 144:ef7eb2e8f9f7 10632 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10633 /* */
<> 144:ef7eb2e8f9f7 10634 /* USB Device General registers */
<> 144:ef7eb2e8f9f7 10635 /* */
<> 144:ef7eb2e8f9f7 10636 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10637 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
<> 144:ef7eb2e8f9f7 10638 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
<> 144:ef7eb2e8f9f7 10639 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
<> 144:ef7eb2e8f9f7 10640 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
<> 144:ef7eb2e8f9f7 10641 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
<> 144:ef7eb2e8f9f7 10642 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
<> 144:ef7eb2e8f9f7 10643 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
<> 144:ef7eb2e8f9f7 10644
<> 144:ef7eb2e8f9f7 10645 /**************************** ISTR interrupt events *************************/
<> 144:ef7eb2e8f9f7 10646 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
<> 144:ef7eb2e8f9f7 10647 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
<> 144:ef7eb2e8f9f7 10648 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
<> 144:ef7eb2e8f9f7 10649 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
<> 144:ef7eb2e8f9f7 10650 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
<> 144:ef7eb2e8f9f7 10651 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
<> 144:ef7eb2e8f9f7 10652 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
<> 144:ef7eb2e8f9f7 10653 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
<> 144:ef7eb2e8f9f7 10654 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
<> 144:ef7eb2e8f9f7 10655 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
<> 144:ef7eb2e8f9f7 10656 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
<> 144:ef7eb2e8f9f7 10657
<> 144:ef7eb2e8f9f7 10658 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
<> 144:ef7eb2e8f9f7 10659 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
<> 144:ef7eb2e8f9f7 10660 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
<> 144:ef7eb2e8f9f7 10661 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
<> 144:ef7eb2e8f9f7 10662 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
<> 144:ef7eb2e8f9f7 10663 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
<> 144:ef7eb2e8f9f7 10664 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
<> 144:ef7eb2e8f9f7 10665 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
<> 144:ef7eb2e8f9f7 10666 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
<> 144:ef7eb2e8f9f7 10667
<> 144:ef7eb2e8f9f7 10668 /************************* CNTR control register bits definitions ***********/
<> 144:ef7eb2e8f9f7 10669 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
<> 144:ef7eb2e8f9f7 10670 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
<> 144:ef7eb2e8f9f7 10671 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
<> 144:ef7eb2e8f9f7 10672 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
<> 144:ef7eb2e8f9f7 10673 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
<> 144:ef7eb2e8f9f7 10674 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
<> 144:ef7eb2e8f9f7 10675 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
<> 144:ef7eb2e8f9f7 10676 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
<> 144:ef7eb2e8f9f7 10677 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
<> 144:ef7eb2e8f9f7 10678 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
<> 144:ef7eb2e8f9f7 10679 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
<> 144:ef7eb2e8f9f7 10680 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
<> 144:ef7eb2e8f9f7 10681 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
<> 144:ef7eb2e8f9f7 10682 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
<> 144:ef7eb2e8f9f7 10683 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
<> 144:ef7eb2e8f9f7 10684
<> 144:ef7eb2e8f9f7 10685 /************************* BCDR control register bits definitions ***********/
<> 144:ef7eb2e8f9f7 10686 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
<> 144:ef7eb2e8f9f7 10687 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
<> 144:ef7eb2e8f9f7 10688 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
<> 144:ef7eb2e8f9f7 10689 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
<> 144:ef7eb2e8f9f7 10690 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
<> 144:ef7eb2e8f9f7 10691 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
<> 144:ef7eb2e8f9f7 10692 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
<> 144:ef7eb2e8f9f7 10693 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
<> 144:ef7eb2e8f9f7 10694 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
<> 144:ef7eb2e8f9f7 10695
<> 144:ef7eb2e8f9f7 10696 /*************************** LPM register bits definitions ******************/
<> 144:ef7eb2e8f9f7 10697 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
<> 144:ef7eb2e8f9f7 10698 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
<> 144:ef7eb2e8f9f7 10699 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
<> 144:ef7eb2e8f9f7 10700 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
<> 144:ef7eb2e8f9f7 10701
<> 144:ef7eb2e8f9f7 10702 /******************** FNR Frame Number Register bit definitions ************/
<> 144:ef7eb2e8f9f7 10703 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
<> 144:ef7eb2e8f9f7 10704 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
<> 144:ef7eb2e8f9f7 10705 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
<> 144:ef7eb2e8f9f7 10706 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
<> 144:ef7eb2e8f9f7 10707 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
<> 144:ef7eb2e8f9f7 10708
<> 144:ef7eb2e8f9f7 10709 /******************** DADDR Device ADDRess bit definitions ****************/
<> 144:ef7eb2e8f9f7 10710 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
<> 144:ef7eb2e8f9f7 10711 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
<> 144:ef7eb2e8f9f7 10712
<> 144:ef7eb2e8f9f7 10713 /****************************** Endpoint register *************************/
<> 144:ef7eb2e8f9f7 10714 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
<> 144:ef7eb2e8f9f7 10715 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
<> 144:ef7eb2e8f9f7 10716 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
<> 144:ef7eb2e8f9f7 10717 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
<> 144:ef7eb2e8f9f7 10718 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
<> 144:ef7eb2e8f9f7 10719 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
<> 144:ef7eb2e8f9f7 10720 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
<> 144:ef7eb2e8f9f7 10721 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
<> 144:ef7eb2e8f9f7 10722 /* bit positions */
<> 144:ef7eb2e8f9f7 10723 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
<> 144:ef7eb2e8f9f7 10724 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
<> 144:ef7eb2e8f9f7 10725 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
<> 144:ef7eb2e8f9f7 10726 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
<> 144:ef7eb2e8f9f7 10727 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
<> 144:ef7eb2e8f9f7 10728 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
<> 144:ef7eb2e8f9f7 10729 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
<> 144:ef7eb2e8f9f7 10730 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
<> 144:ef7eb2e8f9f7 10731 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
<> 144:ef7eb2e8f9f7 10732 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
<> 144:ef7eb2e8f9f7 10733
<> 144:ef7eb2e8f9f7 10734 /* EndPoint REGister MASK (no toggle fields) */
<> 144:ef7eb2e8f9f7 10735 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
<> 144:ef7eb2e8f9f7 10736 /*!< EP_TYPE[1:0] EndPoint TYPE */
<> 144:ef7eb2e8f9f7 10737 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
<> 144:ef7eb2e8f9f7 10738 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
<> 144:ef7eb2e8f9f7 10739 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
<> 144:ef7eb2e8f9f7 10740 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
<> 144:ef7eb2e8f9f7 10741 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
<> 144:ef7eb2e8f9f7 10742 #define USB_EP_T_MASK (((uint16_t)(~USB_EP_T_FIELD)) & USB_EPREG_MASK)
<> 144:ef7eb2e8f9f7 10743
<> 144:ef7eb2e8f9f7 10744 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
<> 144:ef7eb2e8f9f7 10745 /*!< STAT_TX[1:0] STATus for TX transfer */
<> 144:ef7eb2e8f9f7 10746 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
<> 144:ef7eb2e8f9f7 10747 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
<> 144:ef7eb2e8f9f7 10748 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
<> 144:ef7eb2e8f9f7 10749 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
<> 144:ef7eb2e8f9f7 10750 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
<> 144:ef7eb2e8f9f7 10751 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
<> 144:ef7eb2e8f9f7 10752 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
<> 144:ef7eb2e8f9f7 10753 /*!< STAT_RX[1:0] STATus for RX transfer */
<> 144:ef7eb2e8f9f7 10754 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
<> 144:ef7eb2e8f9f7 10755 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
<> 144:ef7eb2e8f9f7 10756 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
<> 144:ef7eb2e8f9f7 10757 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
<> 144:ef7eb2e8f9f7 10758 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 144:ef7eb2e8f9f7 10759 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 144:ef7eb2e8f9f7 10760 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
<> 144:ef7eb2e8f9f7 10761
<> 144:ef7eb2e8f9f7 10762 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10763 /* */
<> 144:ef7eb2e8f9f7 10764 /* Window WATCHDOG (WWDG) */
<> 144:ef7eb2e8f9f7 10765 /* */
<> 144:ef7eb2e8f9f7 10766 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10767
<> 144:ef7eb2e8f9f7 10768 /******************* Bit definition for WWDG_CR register ********************/
<> 144:ef7eb2e8f9f7 10769 #define WWDG_CR_T_Pos (0U)
<> 144:ef7eb2e8f9f7 10770 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
<> 144:ef7eb2e8f9f7 10771 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 144:ef7eb2e8f9f7 10772 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10773 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10774 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10775 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10776 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10777 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10778 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10779
<> 144:ef7eb2e8f9f7 10780 /* Legacy defines */
<> 144:ef7eb2e8f9f7 10781 #define WWDG_CR_T0 WWDG_CR_T_0
<> 144:ef7eb2e8f9f7 10782 #define WWDG_CR_T1 WWDG_CR_T_1
<> 144:ef7eb2e8f9f7 10783 #define WWDG_CR_T2 WWDG_CR_T_2
<> 144:ef7eb2e8f9f7 10784 #define WWDG_CR_T3 WWDG_CR_T_3
<> 144:ef7eb2e8f9f7 10785 #define WWDG_CR_T4 WWDG_CR_T_4
<> 144:ef7eb2e8f9f7 10786 #define WWDG_CR_T5 WWDG_CR_T_5
<> 144:ef7eb2e8f9f7 10787 #define WWDG_CR_T6 WWDG_CR_T_6
<> 144:ef7eb2e8f9f7 10788
<> 144:ef7eb2e8f9f7 10789 #define WWDG_CR_WDGA_Pos (7U)
<> 144:ef7eb2e8f9f7 10790 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10791 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
<> 144:ef7eb2e8f9f7 10792
<> 144:ef7eb2e8f9f7 10793 /******************* Bit definition for WWDG_CFR register *******************/
<> 144:ef7eb2e8f9f7 10794 #define WWDG_CFR_W_Pos (0U)
<> 144:ef7eb2e8f9f7 10795 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
<> 144:ef7eb2e8f9f7 10796 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
<> 144:ef7eb2e8f9f7 10797 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10798 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 10799 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 10800 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 10801 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
<> 144:ef7eb2e8f9f7 10802 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 10803 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
<> 144:ef7eb2e8f9f7 10804
<> 144:ef7eb2e8f9f7 10805 /* Legacy defines */
<> 144:ef7eb2e8f9f7 10806 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 144:ef7eb2e8f9f7 10807 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 144:ef7eb2e8f9f7 10808 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 144:ef7eb2e8f9f7 10809 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 144:ef7eb2e8f9f7 10810 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 144:ef7eb2e8f9f7 10811 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 144:ef7eb2e8f9f7 10812 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 144:ef7eb2e8f9f7 10813
<> 144:ef7eb2e8f9f7 10814 #define WWDG_CFR_WDGTB_Pos (7U)
<> 144:ef7eb2e8f9f7 10815 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
<> 144:ef7eb2e8f9f7 10816 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
<> 144:ef7eb2e8f9f7 10817 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10818 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 10819
<> 144:ef7eb2e8f9f7 10820 /* Legacy defines */
<> 144:ef7eb2e8f9f7 10821 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 144:ef7eb2e8f9f7 10822 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 144:ef7eb2e8f9f7 10823
<> 144:ef7eb2e8f9f7 10824 #define WWDG_CFR_EWI_Pos (9U)
<> 144:ef7eb2e8f9f7 10825 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
<> 144:ef7eb2e8f9f7 10826 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
<> 144:ef7eb2e8f9f7 10827
<> 144:ef7eb2e8f9f7 10828 /******************* Bit definition for WWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 10829 #define WWDG_SR_EWIF_Pos (0U)
<> 144:ef7eb2e8f9f7 10830 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 10831 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
<> 144:ef7eb2e8f9f7 10832
<> 144:ef7eb2e8f9f7 10833 /**
<> 144:ef7eb2e8f9f7 10834 * @}
<> 144:ef7eb2e8f9f7 10835 */
<> 144:ef7eb2e8f9f7 10836
<> 144:ef7eb2e8f9f7 10837 /**
<> 144:ef7eb2e8f9f7 10838 * @}
<> 144:ef7eb2e8f9f7 10839 */
<> 144:ef7eb2e8f9f7 10840
<> 144:ef7eb2e8f9f7 10841
<> 144:ef7eb2e8f9f7 10842 /** @addtogroup Exported_macro
<> 144:ef7eb2e8f9f7 10843 * @{
<> 144:ef7eb2e8f9f7 10844 */
<> 144:ef7eb2e8f9f7 10845
<> 144:ef7eb2e8f9f7 10846 /****************************** ADC Instances *********************************/
<> 144:ef7eb2e8f9f7 10847 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<> 144:ef7eb2e8f9f7 10848
<> 144:ef7eb2e8f9f7 10849 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
<> 144:ef7eb2e8f9f7 10850
<> 144:ef7eb2e8f9f7 10851 /******************************* CAN Instances ********************************/
<> 144:ef7eb2e8f9f7 10852 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
<> 144:ef7eb2e8f9f7 10853
<> 144:ef7eb2e8f9f7 10854 /****************************** COMP Instances *********************************/
<> 144:ef7eb2e8f9f7 10855 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
<> 144:ef7eb2e8f9f7 10856 ((INSTANCE) == COMP2))
<> 144:ef7eb2e8f9f7 10857
<> 144:ef7eb2e8f9f7 10858 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
<> 144:ef7eb2e8f9f7 10859
<> 144:ef7eb2e8f9f7 10860 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
<> 144:ef7eb2e8f9f7 10861
<> 144:ef7eb2e8f9f7 10862 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
<> 144:ef7eb2e8f9f7 10863
<> 144:ef7eb2e8f9f7 10864 /****************************** CEC Instances *********************************/
<> 144:ef7eb2e8f9f7 10865 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
<> 144:ef7eb2e8f9f7 10866
<> 144:ef7eb2e8f9f7 10867 /****************************** CRC Instances *********************************/
<> 144:ef7eb2e8f9f7 10868 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 144:ef7eb2e8f9f7 10869
<> 144:ef7eb2e8f9f7 10870 /******************************* DAC Instances ********************************/
<> 144:ef7eb2e8f9f7 10871 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
<> 144:ef7eb2e8f9f7 10872
<> 144:ef7eb2e8f9f7 10873 /******************************* DMA Instances ********************************/
<> 144:ef7eb2e8f9f7 10874 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
<> 144:ef7eb2e8f9f7 10875 ((INSTANCE) == DMA1_Channel2) || \
<> 144:ef7eb2e8f9f7 10876 ((INSTANCE) == DMA1_Channel3) || \
<> 144:ef7eb2e8f9f7 10877 ((INSTANCE) == DMA1_Channel4) || \
<> 144:ef7eb2e8f9f7 10878 ((INSTANCE) == DMA1_Channel5) || \
<> 144:ef7eb2e8f9f7 10879 ((INSTANCE) == DMA1_Channel6) || \
<> 144:ef7eb2e8f9f7 10880 ((INSTANCE) == DMA1_Channel7))
<> 144:ef7eb2e8f9f7 10881
<> 144:ef7eb2e8f9f7 10882 /****************************** GPIO Instances ********************************/
<> 144:ef7eb2e8f9f7 10883 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 144:ef7eb2e8f9f7 10884 ((INSTANCE) == GPIOB) || \
<> 144:ef7eb2e8f9f7 10885 ((INSTANCE) == GPIOC) || \
<> 144:ef7eb2e8f9f7 10886 ((INSTANCE) == GPIOD) || \
<> 144:ef7eb2e8f9f7 10887 ((INSTANCE) == GPIOE) || \
<> 144:ef7eb2e8f9f7 10888 ((INSTANCE) == GPIOF))
<> 144:ef7eb2e8f9f7 10889
<> 144:ef7eb2e8f9f7 10890 /**************************** GPIO Alternate Function Instances ***************/
<> 144:ef7eb2e8f9f7 10891 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 144:ef7eb2e8f9f7 10892 ((INSTANCE) == GPIOB) || \
<> 144:ef7eb2e8f9f7 10893 ((INSTANCE) == GPIOC) || \
<> 144:ef7eb2e8f9f7 10894 ((INSTANCE) == GPIOD) || \
<> 144:ef7eb2e8f9f7 10895 ((INSTANCE) == GPIOE))
<> 144:ef7eb2e8f9f7 10896
<> 144:ef7eb2e8f9f7 10897 /****************************** GPIO Lock Instances ***************************/
<> 144:ef7eb2e8f9f7 10898 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 144:ef7eb2e8f9f7 10899 ((INSTANCE) == GPIOB))
<> 144:ef7eb2e8f9f7 10900
<> 144:ef7eb2e8f9f7 10901 /****************************** I2C Instances *********************************/
<> 144:ef7eb2e8f9f7 10902 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 144:ef7eb2e8f9f7 10903 ((INSTANCE) == I2C2))
<> 144:ef7eb2e8f9f7 10904
<> 144:ef7eb2e8f9f7 10905 /****************** I2C Instances : wakeup capability from stop modes *********/
<> 144:ef7eb2e8f9f7 10906 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
<> 144:ef7eb2e8f9f7 10907
<> 144:ef7eb2e8f9f7 10908 /****************************** I2S Instances *********************************/
<> 144:ef7eb2e8f9f7 10909 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 144:ef7eb2e8f9f7 10910 ((INSTANCE) == SPI2))
<> 144:ef7eb2e8f9f7 10911
<> 144:ef7eb2e8f9f7 10912 /****************************** IWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 10913 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 144:ef7eb2e8f9f7 10914
<> 144:ef7eb2e8f9f7 10915 /****************************** RTC Instances *********************************/
<> 144:ef7eb2e8f9f7 10916 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 144:ef7eb2e8f9f7 10917
<> 144:ef7eb2e8f9f7 10918 /****************************** SMBUS Instances *********************************/
<> 144:ef7eb2e8f9f7 10919 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
<> 144:ef7eb2e8f9f7 10920
<> 144:ef7eb2e8f9f7 10921 /****************************** SPI Instances *********************************/
<> 144:ef7eb2e8f9f7 10922 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 144:ef7eb2e8f9f7 10923 ((INSTANCE) == SPI2))
<> 144:ef7eb2e8f9f7 10924
<> 144:ef7eb2e8f9f7 10925 /****************************** TIM Instances *********************************/
<> 144:ef7eb2e8f9f7 10926 #define IS_TIM_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10927 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10928 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10929 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 10930 ((INSTANCE) == TIM6) || \
<> 144:ef7eb2e8f9f7 10931 ((INSTANCE) == TIM7) || \
<> 144:ef7eb2e8f9f7 10932 ((INSTANCE) == TIM14) || \
<> 144:ef7eb2e8f9f7 10933 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 10934 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 10935 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 10936
<> 144:ef7eb2e8f9f7 10937 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10938 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10939 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10940 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 10941 ((INSTANCE) == TIM14) || \
<> 144:ef7eb2e8f9f7 10942 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 10943 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 10944 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 10945
<> 144:ef7eb2e8f9f7 10946 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10947 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10948 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10949 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 10950 ((INSTANCE) == TIM15))
<> 144:ef7eb2e8f9f7 10951
<> 144:ef7eb2e8f9f7 10952 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10953 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10954 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10955 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 10956
<> 144:ef7eb2e8f9f7 10957 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10958 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10959 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10960 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 10961
<> 144:ef7eb2e8f9f7 10962 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10963 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10964 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10965 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 10966
<> 144:ef7eb2e8f9f7 10967 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10968 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10969 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10970 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 10971
<> 144:ef7eb2e8f9f7 10972 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10973 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10974 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10975 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 10976 ((INSTANCE) == TIM15))
<> 144:ef7eb2e8f9f7 10977
<> 144:ef7eb2e8f9f7 10978 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10979 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10980 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10981 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 10982 ((INSTANCE) == TIM15))
<> 144:ef7eb2e8f9f7 10983
<> 144:ef7eb2e8f9f7 10984 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10985 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10986 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10987 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 10988
<> 144:ef7eb2e8f9f7 10989 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10990 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 10991 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 10992 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 10993
<> 144:ef7eb2e8f9f7 10994 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10995 (((INSTANCE) == TIM1))
<> 144:ef7eb2e8f9f7 10996
<> 144:ef7eb2e8f9f7 10997 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 10998 (((INSTANCE) == TIM1))
<> 144:ef7eb2e8f9f7 10999
<> 144:ef7eb2e8f9f7 11000 #define IS_TIM_ETR_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11001 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11002 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11003 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 11004
<> 144:ef7eb2e8f9f7 11005 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11006 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11007 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11008 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 11009
<> 144:ef7eb2e8f9f7 11010 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11011 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11012 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11013 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 11014 ((INSTANCE) == TIM6) || \
<> 144:ef7eb2e8f9f7 11015 ((INSTANCE) == TIM7) || \
<> 144:ef7eb2e8f9f7 11016 ((INSTANCE) == TIM15))
<> 144:ef7eb2e8f9f7 11017
<> 144:ef7eb2e8f9f7 11018 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11019 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11020 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11021 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 11022 ((INSTANCE) == TIM15))
<> 144:ef7eb2e8f9f7 11023
<> 144:ef7eb2e8f9f7 11024 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11025 ((INSTANCE) == TIM2)
<> 144:ef7eb2e8f9f7 11026
<> 144:ef7eb2e8f9f7 11027 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11028 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11029 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11030 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 11031 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 11032 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 11033 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 11034
<> 144:ef7eb2e8f9f7 11035 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11036 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11037 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 11038 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 11039 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 11040
<> 144:ef7eb2e8f9f7 11041 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 144:ef7eb2e8f9f7 11042 ((((INSTANCE) == TIM1) && \
<> 144:ef7eb2e8f9f7 11043 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 11044 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 11045 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 11046 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 11047 || \
<> 144:ef7eb2e8f9f7 11048 (((INSTANCE) == TIM2) && \
<> 144:ef7eb2e8f9f7 11049 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 11050 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 11051 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 11052 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 11053 || \
<> 144:ef7eb2e8f9f7 11054 (((INSTANCE) == TIM3) && \
<> 144:ef7eb2e8f9f7 11055 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 11056 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 11057 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 11058 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 11059 || \
<> 144:ef7eb2e8f9f7 11060 (((INSTANCE) == TIM14) && \
<> 144:ef7eb2e8f9f7 11061 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 11062 || \
<> 144:ef7eb2e8f9f7 11063 (((INSTANCE) == TIM15) && \
<> 144:ef7eb2e8f9f7 11064 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 11065 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 144:ef7eb2e8f9f7 11066 || \
<> 144:ef7eb2e8f9f7 11067 (((INSTANCE) == TIM16) && \
<> 144:ef7eb2e8f9f7 11068 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 11069 || \
<> 144:ef7eb2e8f9f7 11070 (((INSTANCE) == TIM17) && \
<> 144:ef7eb2e8f9f7 11071 (((CHANNEL) == TIM_CHANNEL_1))))
<> 144:ef7eb2e8f9f7 11072
<> 144:ef7eb2e8f9f7 11073 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
<> 144:ef7eb2e8f9f7 11074 ((((INSTANCE) == TIM1) && \
<> 144:ef7eb2e8f9f7 11075 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 11076 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 11077 ((CHANNEL) == TIM_CHANNEL_3))) \
<> 144:ef7eb2e8f9f7 11078 || \
<> 144:ef7eb2e8f9f7 11079 (((INSTANCE) == TIM15) && \
<> 144:ef7eb2e8f9f7 11080 ((CHANNEL) == TIM_CHANNEL_1)) \
<> 144:ef7eb2e8f9f7 11081 || \
<> 144:ef7eb2e8f9f7 11082 (((INSTANCE) == TIM16) && \
<> 144:ef7eb2e8f9f7 11083 ((CHANNEL) == TIM_CHANNEL_1)) \
<> 144:ef7eb2e8f9f7 11084 || \
<> 144:ef7eb2e8f9f7 11085 (((INSTANCE) == TIM17) && \
<> 144:ef7eb2e8f9f7 11086 ((CHANNEL) == TIM_CHANNEL_1)))
<> 144:ef7eb2e8f9f7 11087
<> 144:ef7eb2e8f9f7 11088 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11089 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11090 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11091 ((INSTANCE) == TIM3))
<> 144:ef7eb2e8f9f7 11092
<> 144:ef7eb2e8f9f7 11093 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11094 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11095 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 11096 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 11097 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 11098
<> 144:ef7eb2e8f9f7 11099 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11100 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11101 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11102 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 11103 ((INSTANCE) == TIM14) || \
<> 144:ef7eb2e8f9f7 11104 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 11105 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 11106 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 11107
<> 144:ef7eb2e8f9f7 11108 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11109 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11110 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11111 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 11112 ((INSTANCE) == TIM6) || \
<> 144:ef7eb2e8f9f7 11113 ((INSTANCE) == TIM7) || \
<> 144:ef7eb2e8f9f7 11114 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 11115 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 11116 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 11117
<> 144:ef7eb2e8f9f7 11118 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11119 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11120 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 11121 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 11122 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 11123 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 11124 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 11125
<> 144:ef7eb2e8f9f7 11126 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11127 (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 11128 ((INSTANCE) == TIM15) || \
<> 144:ef7eb2e8f9f7 11129 ((INSTANCE) == TIM16) || \
<> 144:ef7eb2e8f9f7 11130 ((INSTANCE) == TIM17))
<> 144:ef7eb2e8f9f7 11131
<> 144:ef7eb2e8f9f7 11132 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
<> 144:ef7eb2e8f9f7 11133 ((INSTANCE) == TIM14)
<> 144:ef7eb2e8f9f7 11134
<> 144:ef7eb2e8f9f7 11135 /****************************** TSC Instances *********************************/
<> 144:ef7eb2e8f9f7 11136 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
<> 144:ef7eb2e8f9f7 11137
<> 144:ef7eb2e8f9f7 11138 /*********************** UART Instances : IRDA mode ***************************/
<> 144:ef7eb2e8f9f7 11139 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11140 ((INSTANCE) == USART2))
<> 144:ef7eb2e8f9f7 11141
<> 144:ef7eb2e8f9f7 11142 /********************* UART Instances : Smard card mode ***********************/
<> 144:ef7eb2e8f9f7 11143 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11144 ((INSTANCE) == USART2))
<> 144:ef7eb2e8f9f7 11145
<> 144:ef7eb2e8f9f7 11146 /******************** USART Instances : Synchronous mode **********************/
<> 144:ef7eb2e8f9f7 11147 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11148 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 11149 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 11150 ((INSTANCE) == USART4))
<> 144:ef7eb2e8f9f7 11151
<> 144:ef7eb2e8f9f7 11152 /******************** USART Instances : auto Baud rate detection **************/
<> 144:ef7eb2e8f9f7 11153 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11154 ((INSTANCE) == USART2))
<> 144:ef7eb2e8f9f7 11155
<> 144:ef7eb2e8f9f7 11156 /******************** UART Instances : Asynchronous mode **********************/
<> 144:ef7eb2e8f9f7 11157 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11158 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 11159 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 11160 ((INSTANCE) == USART4))
<> 144:ef7eb2e8f9f7 11161
<> 144:ef7eb2e8f9f7 11162 /******************** UART Instances : Half-Duplex mode **********************/
<> 144:ef7eb2e8f9f7 11163 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11164 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 11165 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 11166 ((INSTANCE) == USART4))
<> 144:ef7eb2e8f9f7 11167
<> 144:ef7eb2e8f9f7 11168 /****************** UART Instances : Hardware Flow control ********************/
<> 144:ef7eb2e8f9f7 11169 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11170 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 11171 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 11172 ((INSTANCE) == USART4))
<> 144:ef7eb2e8f9f7 11173
<> 144:ef7eb2e8f9f7 11174 /****************** UART Instances : LIN mode ********************/
<> 144:ef7eb2e8f9f7 11175 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11176 ((INSTANCE) == USART2))
<> 144:ef7eb2e8f9f7 11177
<> 144:ef7eb2e8f9f7 11178 /****************** UART Instances : wakeup from stop mode ********************/
<> 144:ef7eb2e8f9f7 11179 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11180 ((INSTANCE) == USART2))
<> 144:ef7eb2e8f9f7 11181 /* Old macro definition maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 11182 #define IS_UART_WAKEUP_INSTANCE IS_UART_WAKEUP_FROMSTOP_INSTANCE
<> 144:ef7eb2e8f9f7 11183
<> 144:ef7eb2e8f9f7 11184 /****************** UART Instances : Driver enable detection ********************/
<> 144:ef7eb2e8f9f7 11185 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 11186 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 11187 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 11188 ((INSTANCE) == USART4))
<> 144:ef7eb2e8f9f7 11189
<> 144:ef7eb2e8f9f7 11190 /****************************** USB Instances ********************************/
<> 144:ef7eb2e8f9f7 11191 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
<> 144:ef7eb2e8f9f7 11192
<> 144:ef7eb2e8f9f7 11193 /****************************** WWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 11194 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 144:ef7eb2e8f9f7 11195
<> 144:ef7eb2e8f9f7 11196 /**
<> 144:ef7eb2e8f9f7 11197 * @}
<> 144:ef7eb2e8f9f7 11198 */
<> 144:ef7eb2e8f9f7 11199
<> 144:ef7eb2e8f9f7 11200
<> 144:ef7eb2e8f9f7 11201 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11202 /* For a painless codes migration between the STM32F0xx device product */
<> 144:ef7eb2e8f9f7 11203 /* lines, the aliases defined below are put in place to overcome the */
<> 144:ef7eb2e8f9f7 11204 /* differences in the interrupt handlers and IRQn definitions. */
<> 144:ef7eb2e8f9f7 11205 /* No need to update developed interrupt code when moving across */
<> 144:ef7eb2e8f9f7 11206 /* product lines within the same STM32F0 Family */
<> 144:ef7eb2e8f9f7 11207 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11208
<> 144:ef7eb2e8f9f7 11209 /* Aliases for __IRQn */
<> 144:ef7eb2e8f9f7 11210 #define ADC1_IRQn ADC1_COMP_IRQn
<> 144:ef7eb2e8f9f7 11211 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
<> 144:ef7eb2e8f9f7 11212 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
<> 144:ef7eb2e8f9f7 11213 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_6_7_IRQn
<> 144:ef7eb2e8f9f7 11214 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
<> 144:ef7eb2e8f9f7 11215 #define PVD_IRQn PVD_VDDIO2_IRQn
<> 144:ef7eb2e8f9f7 11216 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
<> 144:ef7eb2e8f9f7 11217 #define RCC_IRQn RCC_CRS_IRQn
<> 144:ef7eb2e8f9f7 11218 #define TIM6_IRQn TIM6_DAC_IRQn
<> 144:ef7eb2e8f9f7 11219 #define USART3_6_IRQn USART3_4_IRQn
<> 144:ef7eb2e8f9f7 11220 #define USART3_8_IRQn USART3_4_IRQn
<> 144:ef7eb2e8f9f7 11221
<> 144:ef7eb2e8f9f7 11222
<> 144:ef7eb2e8f9f7 11223 /* Aliases for __IRQHandler */
<> 144:ef7eb2e8f9f7 11224 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
<> 144:ef7eb2e8f9f7 11225 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 11226 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
<> 144:ef7eb2e8f9f7 11227 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
<> 144:ef7eb2e8f9f7 11228 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
<> 144:ef7eb2e8f9f7 11229 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
<> 144:ef7eb2e8f9f7 11230 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
<> 144:ef7eb2e8f9f7 11231 #define RCC_IRQHandler RCC_CRS_IRQHandler
<> 144:ef7eb2e8f9f7 11232 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 11233 #define USART3_6_IRQHandler USART3_4_IRQHandler
<> 144:ef7eb2e8f9f7 11234 #define USART3_8_IRQHandler USART3_4_IRQHandler
<> 144:ef7eb2e8f9f7 11235
<> 144:ef7eb2e8f9f7 11236
<> 144:ef7eb2e8f9f7 11237 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 11238 }
<> 144:ef7eb2e8f9f7 11239 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 11240
<> 144:ef7eb2e8f9f7 11241 #endif /* __STM32F072xB_H */
<> 144:ef7eb2e8f9f7 11242
<> 144:ef7eb2e8f9f7 11243 /**
<> 144:ef7eb2e8f9f7 11244 * @}
<> 144:ef7eb2e8f9f7 11245 */
<> 144:ef7eb2e8f9f7 11246
<> 144:ef7eb2e8f9f7 11247 /**
<> 144:ef7eb2e8f9f7 11248 * @}
<> 144:ef7eb2e8f9f7 11249 */
<> 144:ef7eb2e8f9f7 11250
<> 144:ef7eb2e8f9f7 11251 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/