mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999
Child:
181:57724642e740
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_pwr.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of PWR HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L4xx_HAL_PWR_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L4xx_HAL_PWR_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup PWR
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup PWR_Exported_Types PWR Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief PWR PVD configuration structure definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
<> 144:ef7eb2e8f9f7 69 This parameter can be a value of @ref PWR_PVD_detection_level. */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 144:ef7eb2e8f9f7 72 This parameter can be a value of @ref PWR_PVD_Mode. */
<> 144:ef7eb2e8f9f7 73 }PWR_PVDTypeDef;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @}
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @defgroup PWR_Exported_Constants PWR Exported Constants
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90 #define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
<> 144:ef7eb2e8f9f7 91 #define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
<> 144:ef7eb2e8f9f7 92 #define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
<> 144:ef7eb2e8f9f7 93 #define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
<> 144:ef7eb2e8f9f7 94 #define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
<> 144:ef7eb2e8f9f7 95 #define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
<> 144:ef7eb2e8f9f7 96 #define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
<> 144:ef7eb2e8f9f7 97 #define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */
<> 144:ef7eb2e8f9f7 98 /**
<> 144:ef7eb2e8f9f7 99 * @}
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
<> 144:ef7eb2e8f9f7 106 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 107 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 108 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 109 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 110 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 111 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 112 /**
<> 144:ef7eb2e8f9f7 113 * @}
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */
<> 144:ef7eb2e8f9f7 123 #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @}
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
<> 144:ef7eb2e8f9f7 129 * @{
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
<> 144:ef7eb2e8f9f7 132 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 #define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
<> 144:ef7eb2e8f9f7 141 #define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @}
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 #define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @}
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @}
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 168 /** @defgroup PWR_Exported_Macros PWR Exported Macros
<> 144:ef7eb2e8f9f7 169 * @{
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /** @brief Check whether or not a specific PWR flag is set.
<> 144:ef7eb2e8f9f7 173 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 174 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 175 * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 176 * was received from the WKUP pin 1.
<> 144:ef7eb2e8f9f7 177 * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 178 * was received from the WKUP pin 2.
<> 144:ef7eb2e8f9f7 179 * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 180 * was received from the WKUP pin 3.
<> 144:ef7eb2e8f9f7 181 * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 182 * was received from the WKUP pin 4.
<> 144:ef7eb2e8f9f7 183 * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 184 * was received from the WKUP pin 5.
<> 144:ef7eb2e8f9f7 185 * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
<> 144:ef7eb2e8f9f7 186 * entered StandBy mode.
<> 144:ef7eb2e8f9f7 187 * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
<> 144:ef7eb2e8f9f7 188 * the internal wakeup line.
<> 144:ef7eb2e8f9f7 189 * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
<> 144:ef7eb2e8f9f7 190 * low-power regulator is ready.
<> 144:ef7eb2e8f9f7 191 * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
<> 144:ef7eb2e8f9f7 192 * regulator is ready in main mode or is in low-power mode.
<> 144:ef7eb2e8f9f7 193 * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
<> 144:ef7eb2e8f9f7 194 * in the selected voltage range or is still changing to the required voltage level.
<> 144:ef7eb2e8f9f7 195 * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
<> 144:ef7eb2e8f9f7 196 * below or above the selected PVD threshold.
<> 144:ef7eb2e8f9f7 197 * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
<> 144:ef7eb2e8f9f7 198 * is below or above PVM1 threshold (applicable when USB feature is supported).
<> 144:ef7eb2e8f9f7 199 @if STM32L486xx
<> 144:ef7eb2e8f9f7 200 * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
<> 144:ef7eb2e8f9f7 201 * is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
<> 144:ef7eb2e8f9f7 202 @endif
<> 144:ef7eb2e8f9f7 203 * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
<> 144:ef7eb2e8f9f7 204 * is below or above PVM3 threshold.
<> 144:ef7eb2e8f9f7 205 * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
<> 144:ef7eb2e8f9f7 206 * is below or above PVM4 threshold.
<> 144:ef7eb2e8f9f7 207 *
<> 144:ef7eb2e8f9f7 208 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 #define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\
<> 144:ef7eb2e8f9f7 211 (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
<> 144:ef7eb2e8f9f7 212 (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @brief Clear a specific PWR flag.
<> 144:ef7eb2e8f9f7 215 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 216 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 217 * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 218 * was received from the WKUP pin 1.
<> 144:ef7eb2e8f9f7 219 * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 220 * was received from the WKUP pin 2.
<> 144:ef7eb2e8f9f7 221 * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 222 * was received from the WKUP pin 3.
<> 144:ef7eb2e8f9f7 223 * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 224 * was received from the WKUP pin 4.
<> 144:ef7eb2e8f9f7 225 * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
<> 144:ef7eb2e8f9f7 226 * was received from the WKUP pin 5.
<> 144:ef7eb2e8f9f7 227 * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
<> 144:ef7eb2e8f9f7 228 * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
<> 144:ef7eb2e8f9f7 229 * entered Standby mode.
<> 144:ef7eb2e8f9f7 230 * @retval None
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
<> 144:ef7eb2e8f9f7 233 (PWR->SCR = (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 234 (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @brief Enable the PVD Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 237 * @retval None
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @brief Disable the PVD Extended Interrupt Line.
<> 144:ef7eb2e8f9f7 243 * @retval None
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @brief Enable the PVD Event Line.
<> 144:ef7eb2e8f9f7 249 * @retval None
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @brief Disable the PVD Event Line.
<> 144:ef7eb2e8f9f7 255 * @retval None
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief Enable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 261 * @retval None
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 267 * @retval None
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @brief Enable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 273 * @retval None
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 280 * @retval None
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 287 * @retval None
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 290 do { \
<> 144:ef7eb2e8f9f7 291 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 292 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 293 } while(0)
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 297 * @retval None
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 300 do { \
<> 144:ef7eb2e8f9f7 301 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
<> 144:ef7eb2e8f9f7 302 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
<> 144:ef7eb2e8f9f7 303 } while(0)
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 307 * @retval None
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @brief Check whether or not the PVD EXTI interrupt flag is set.
<> 144:ef7eb2e8f9f7 313 * @retval EXTI PVD Line Status.
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief Clear the PVD EXTI interrupt flag.
<> 144:ef7eb2e8f9f7 319 * @retval None
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @}
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 329 /** @addtogroup PWR_Private_Macros PWR Private Macros
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 144:ef7eb2e8f9f7 334 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 144:ef7eb2e8f9f7 335 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 144:ef7eb2e8f9f7 336 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
<> 144:ef7eb2e8f9f7 339 ((MODE) == PWR_PVD_MODE_IT_RISING) ||\
<> 144:ef7eb2e8f9f7 340 ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
<> 144:ef7eb2e8f9f7 341 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
<> 144:ef7eb2e8f9f7 342 ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
<> 144:ef7eb2e8f9f7 343 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
<> 144:ef7eb2e8f9f7 344 ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
<> 144:ef7eb2e8f9f7 347 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Include PWR HAL Extended module */
<> 144:ef7eb2e8f9f7 358 #include "stm32l4xx_hal_pwr_ex.h"
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
<> 144:ef7eb2e8f9f7 363 * @{
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 367 * @{
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Initialization and de-initialization functions *******************************/
<> 144:ef7eb2e8f9f7 371 void HAL_PWR_DeInit(void);
<> 144:ef7eb2e8f9f7 372 void HAL_PWR_EnableBkUpAccess(void);
<> 144:ef7eb2e8f9f7 373 void HAL_PWR_DisableBkUpAccess(void);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /**
<> 144:ef7eb2e8f9f7 376 * @}
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 380 * @{
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 384 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 144:ef7eb2e8f9f7 385 void HAL_PWR_EnablePVD(void);
<> 144:ef7eb2e8f9f7 386 void HAL_PWR_DisablePVD(void);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* WakeUp pins configuration functions ****************************************/
<> 144:ef7eb2e8f9f7 390 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
<> 144:ef7eb2e8f9f7 391 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Low Power modes configuration functions ************************************/
<> 144:ef7eb2e8f9f7 394 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
<> 144:ef7eb2e8f9f7 395 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
<> 144:ef7eb2e8f9f7 396 void HAL_PWR_EnterSTANDBYMode(void);
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 void HAL_PWR_EnableSleepOnExit(void);
<> 144:ef7eb2e8f9f7 399 void HAL_PWR_DisableSleepOnExit(void);
<> 144:ef7eb2e8f9f7 400 void HAL_PWR_EnableSEVOnPend(void);
<> 144:ef7eb2e8f9f7 401 void HAL_PWR_DisableSEVOnPend(void);
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 void HAL_PWR_PVDCallback(void);
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @}
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @}
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 #endif
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 #endif /* __STM32L4xx_HAL_PWR_H */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/