mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999
Child:
181:57724642e740
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 144:ef7eb2e8f9f7 19 (except for internal SRAM / FLASH memories: no initialization is
<> 144:ef7eb2e8f9f7 20 necessary). Please refer to the Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 21 and DMA requests.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) For a given Channel, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 24 Channel request, Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 25 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
<> 144:ef7eb2e8f9f7 26 using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 27
AnnaBridge 167:e84263d55307 28 Prior to HAL_DMA_Init the CLK shall be enabled for both DMA thanks to:
AnnaBridge 167:e84263d55307 29 __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE()
AnnaBridge 167:e84263d55307 30
<> 144:ef7eb2e8f9f7 31 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 32 detection.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 37 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 38 =================================
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 41 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 42 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 43 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 46 ===================================
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 49 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 50 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 51 Source address and destination address and the Length of data to be transferred.
<> 144:ef7eb2e8f9f7 52 In this case the DMA interrupt is configured
<> 144:ef7eb2e8f9f7 53 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 54 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 55 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 56 XferErrorCallback (i.e. a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 59 =============================================
<> 144:ef7eb2e8f9f7 60 [..]
<> 144:ef7eb2e8f9f7 61 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 64 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 65 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 66 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 67 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 68 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 69 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 [..]
<> 144:ef7eb2e8f9f7 72 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 @endverbatim
<> 144:ef7eb2e8f9f7 75 ******************************************************************************
<> 144:ef7eb2e8f9f7 76 * @attention
<> 144:ef7eb2e8f9f7 77 *
AnnaBridge 167:e84263d55307 78 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 81 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 82 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 83 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 84 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 85 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 86 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 87 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 88 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 89 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 90 *
<> 144:ef7eb2e8f9f7 91 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 92 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 93 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 94 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 95 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 96 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 97 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 98 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 99 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 100 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 101 *
<> 144:ef7eb2e8f9f7 102 ******************************************************************************
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 106 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 113 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 122 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 124 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 128 /**
<> 144:ef7eb2e8f9f7 129 * @}
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 139 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 @verbatim
<> 144:ef7eb2e8f9f7 142 ===============================================================================
<> 144:ef7eb2e8f9f7 143 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 144 ===============================================================================
<> 144:ef7eb2e8f9f7 145 [..]
<> 144:ef7eb2e8f9f7 146 This section provides functions allowing to initialize the DMA Channel source
<> 144:ef7eb2e8f9f7 147 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 148 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 144:ef7eb2e8f9f7 149 [..]
<> 144:ef7eb2e8f9f7 150 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 151 reference manual.
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 @endverbatim
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @brief Initialize the DMA according to the specified
<> 144:ef7eb2e8f9f7 159 * parameters in the DMA_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 160 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 161 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 162 * @retval HAL status
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 uint32_t tmp = 0;
AnnaBridge 167:e84263d55307 167
<> 144:ef7eb2e8f9f7 168 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 169 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Check the parameters */
<> 144:ef7eb2e8f9f7 175 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 176 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 177 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 178 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 179 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 180 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
AnnaBridge 167:e84263d55307 183
<> 144:ef7eb2e8f9f7 184 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* calculation of the channel index */
<> 144:ef7eb2e8f9f7 190 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /* DMA1 */
<> 144:ef7eb2e8f9f7 193 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 194 hdma->DmaBaseAddress = DMA1;
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196 else
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 /* DMA2 */
<> 144:ef7eb2e8f9f7 199 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 200 hdma->DmaBaseAddress = DMA2;
<> 144:ef7eb2e8f9f7 201 }
AnnaBridge 167:e84263d55307 202
<> 144:ef7eb2e8f9f7 203 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 204 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 207 tmp = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 144:ef7eb2e8f9f7 210 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 144:ef7eb2e8f9f7 211 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 144:ef7eb2e8f9f7 212 DMA_CCR_DIR));
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 215 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 216 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 217 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 218 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Write to DMA Channel CR register */
<> 144:ef7eb2e8f9f7 221 hdma->Instance->CCR = tmp;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Set request selection */
<> 144:ef7eb2e8f9f7 224 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /* Write to DMA channel selection register */
<> 144:ef7eb2e8f9f7 227 if (DMA1 == hdma->DmaBaseAddress)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 /* Reset request selection for DMA1 Channelx */
<> 144:ef7eb2e8f9f7 230 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Configure request selection for DMA1 Channelx */
<> 144:ef7eb2e8f9f7 233 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 else /* DMA2 */
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 /* Reset request selection for DMA2 Channelx */
<> 144:ef7eb2e8f9f7 238 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Configure request selection for DMA2 Channelx */
<> 144:ef7eb2e8f9f7 241 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Clean callbacks */
<> 144:ef7eb2e8f9f7 246 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 247 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 248 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 249 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 252 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Initialize the DMA state*/
<> 144:ef7eb2e8f9f7 255 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 258 hdma->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 return HAL_OK;
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief DeInitialize the DMA peripheral.
<> 144:ef7eb2e8f9f7 265 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 266 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 267 * @retval HAL status
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 272 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Check the parameters */
<> 144:ef7eb2e8f9f7 278 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* Disable the selected DMA Channelx */
<> 144:ef7eb2e8f9f7 281 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Reset DMA Channel control register */
<> 144:ef7eb2e8f9f7 284 hdma->Instance->CCR = 0;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Calculation of the channel index */
<> 144:ef7eb2e8f9f7 287 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* DMA1 */
<> 144:ef7eb2e8f9f7 290 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 291 hdma->DmaBaseAddress = DMA1;
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293 else
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 /* DMA2 */
<> 144:ef7eb2e8f9f7 296 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 297 hdma->DmaBaseAddress = DMA2;
<> 144:ef7eb2e8f9f7 298 }
AnnaBridge 167:e84263d55307 299
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Clear all flags */
AnnaBridge 167:e84263d55307 302 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
AnnaBridge 167:e84263d55307 303
<> 144:ef7eb2e8f9f7 304 /* Reset DMA channel selection register */
<> 144:ef7eb2e8f9f7 305 if (DMA1 == hdma->DmaBaseAddress)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 /* DMA1 */
<> 144:ef7eb2e8f9f7 308 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310 else
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 /* DMA2 */
<> 144:ef7eb2e8f9f7 313 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 317 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 320 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Release Lock */
<> 144:ef7eb2e8f9f7 323 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 return HAL_OK;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @}
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 333 * @brief Input and Output operation functions
<> 144:ef7eb2e8f9f7 334 *
<> 144:ef7eb2e8f9f7 335 @verbatim
<> 144:ef7eb2e8f9f7 336 ===============================================================================
<> 144:ef7eb2e8f9f7 337 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 338 ===============================================================================
<> 144:ef7eb2e8f9f7 339 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 340 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 341 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 342 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 343 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 344 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 345 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 @endverbatim
<> 144:ef7eb2e8f9f7 348 * @{
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @brief Start the DMA Transfer.
<> 144:ef7eb2e8f9f7 353 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 354 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 355 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 356 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 357 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 358 * @retval HAL status
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Check the parameters */
<> 144:ef7eb2e8f9f7 365 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Process locked */
<> 144:ef7eb2e8f9f7 368 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 373 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 374 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 377 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Configure the source, destination address and the data length & clear flags*/
<> 144:ef7eb2e8f9f7 380 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 383 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385 else
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 388 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 389 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391 return status;
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /**
<> 144:ef7eb2e8f9f7 395 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 396 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 397 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 398 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 399 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 400 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 401 * @retval HAL status
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Check the parameters */
<> 144:ef7eb2e8f9f7 408 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Process locked */
<> 144:ef7eb2e8f9f7 411 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 414 {
<> 144:ef7eb2e8f9f7 415 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 416 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 417 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 420 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Configure the source, destination address and the data length & clear flags*/
<> 144:ef7eb2e8f9f7 423 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Enable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 426 /* Enable the transfer Error interrupt */
<> 144:ef7eb2e8f9f7 427 if(NULL != hdma->XferHalfCpltCallback )
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 /* Enable the Half transfer complete interrupt as well */
<> 144:ef7eb2e8f9f7 430 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432 else
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 435 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 438 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440 else
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 443 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* Remain BUSY */
<> 144:ef7eb2e8f9f7 446 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 return status;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /**
<> 144:ef7eb2e8f9f7 452 * @brief Abort the DMA Transfer.
<> 144:ef7eb2e8f9f7 453 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 454 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 455 * @retval HAL status
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 167:e84263d55307 460
<> 144:ef7eb2e8f9f7 461 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 464 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468 else
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 /* Disable DMA IT */
<> 144:ef7eb2e8f9f7 471 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* Disable the channel */
<> 144:ef7eb2e8f9f7 474 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Clear all flags */
AnnaBridge 167:e84263d55307 477 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 480 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 483 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485 return status;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 144:ef7eb2e8f9f7 490 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 491 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 492 * @retval HAL status
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 501 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505 else
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 /* Disable DMA IT */
<> 144:ef7eb2e8f9f7 508 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Disable the channel */
<> 144:ef7eb2e8f9f7 511 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* Clear all flags */
AnnaBridge 167:e84263d55307 514 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 517 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 520 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Call User Abort callback */
<> 144:ef7eb2e8f9f7 523 if(hdma->XferAbortCallback != NULL)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 hdma->XferAbortCallback(hdma);
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528 return status;
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 533 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 534 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 535 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 536 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 537 * @retval HAL status
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 uint32_t temp;
<> 144:ef7eb2e8f9f7 542 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 547 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Polling mode not supported in circular mode */
<> 144:ef7eb2e8f9f7 553 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 144:ef7eb2e8f9f7 556 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 560 if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 563 temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565 else
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 568 temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Get tick */
<> 144:ef7eb2e8f9f7 572 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 while(RESET == (hdma->DmaBaseAddress->ISR & temp))
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))))
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 /* When a DMA transfer error occurs */
<> 144:ef7eb2e8f9f7 579 /* A hardware clear of its EN bits is performed */
<> 144:ef7eb2e8f9f7 580 /* Clear all flags */
AnnaBridge 167:e84263d55307 581 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Update error code */
<> 144:ef7eb2e8f9f7 584 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 587 hdma->State= HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 590 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 595 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 596 {
<> 144:ef7eb2e8f9f7 597 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 /* Update error code */
<> 144:ef7eb2e8f9f7 600 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 603 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 606 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611 }
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 /* Clear the transfer complete flag */
AnnaBridge 167:e84263d55307 616 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 619 all transfers are complete) */
<> 144:ef7eb2e8f9f7 620 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622 else
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 /* Clear the half transfer complete flag */
AnnaBridge 167:e84263d55307 625 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Process unlocked */
<> 144:ef7eb2e8f9f7 629 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 return HAL_OK;
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /**
<> 144:ef7eb2e8f9f7 635 * @brief Handle DMA interrupt request.
<> 144:ef7eb2e8f9f7 636 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 637 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 638 * @retval None
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
<> 144:ef7eb2e8f9f7 643 uint32_t source_it = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Half Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 646 if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 649 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 /* Disable the half transfer interrupt */
<> 144:ef7eb2e8f9f7 652 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 /* Clear the half transfer complete flag */
AnnaBridge 167:e84263d55307 655 hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* DMA peripheral state is not updated in Half Transfer */
<> 144:ef7eb2e8f9f7 658 /* but in Transfer Complete case */
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 663 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Transfer Complete Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 668 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 /* Disable the transfer complete and error interrupt */
<> 144:ef7eb2e8f9f7 673 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 676 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678 /* Clear the transfer complete flag */
AnnaBridge 167:e84263d55307 679 hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 682 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 687 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 688 }
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /* Transfer Error Interrupt management **************************************/
<> 144:ef7eb2e8f9f7 692 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 /* When a DMA transfer error occurs */
<> 144:ef7eb2e8f9f7 695 /* A hardware clear of its EN bits is performed */
<> 144:ef7eb2e8f9f7 696 /* Disable ALL DMA IT */
<> 144:ef7eb2e8f9f7 697 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Clear all flags */
AnnaBridge 167:e84263d55307 700 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Update error code */
<> 144:ef7eb2e8f9f7 703 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 706 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 709 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 if (hdma->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 /* Transfer error callback */
<> 144:ef7eb2e8f9f7 714 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717 return;
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /**
<> 144:ef7eb2e8f9f7 721 * @brief Register callbacks
<> 144:ef7eb2e8f9f7 722 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 723 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 724 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 725 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 144:ef7eb2e8f9f7 726 * @param pCallback: pointer to private callbacsk function which has pointer to
<> 144:ef7eb2e8f9f7 727 * a DMA_HandleTypeDef structure as parameter.
<> 144:ef7eb2e8f9f7 728 * @retval HAL status
<> 144:ef7eb2e8f9f7 729 */
<> 144:ef7eb2e8f9f7 730 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Process locked */
<> 144:ef7eb2e8f9f7 735 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 switch (CallbackID)
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 742 hdma->XferCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 743 break;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 746 hdma->XferHalfCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 747 break;
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 750 hdma->XferErrorCallback = pCallback;
<> 144:ef7eb2e8f9f7 751 break;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 754 hdma->XferAbortCallback = pCallback;
<> 144:ef7eb2e8f9f7 755 break;
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 default:
<> 144:ef7eb2e8f9f7 758 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 759 break;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 }
<> 144:ef7eb2e8f9f7 762 else
<> 144:ef7eb2e8f9f7 763 {
<> 144:ef7eb2e8f9f7 764 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 765 }
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Release Lock */
<> 144:ef7eb2e8f9f7 768 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 return status;
<> 144:ef7eb2e8f9f7 771 }
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /**
<> 144:ef7eb2e8f9f7 774 * @brief UnRegister callbacks
<> 144:ef7eb2e8f9f7 775 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 776 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 777 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 778 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 144:ef7eb2e8f9f7 779 * @retval HAL status
<> 144:ef7eb2e8f9f7 780 */
<> 144:ef7eb2e8f9f7 781 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /* Process locked */
<> 144:ef7eb2e8f9f7 786 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 switch (CallbackID)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 793 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 794 break;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 797 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 798 break;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 801 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 802 break;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 805 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 806 break;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 case HAL_DMA_XFER_ALL_CB_ID:
<> 144:ef7eb2e8f9f7 809 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 810 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 811 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 812 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 813 break;
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 default:
<> 144:ef7eb2e8f9f7 816 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 817 break;
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 else
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Release Lock */
<> 144:ef7eb2e8f9f7 826 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 return status;
<> 144:ef7eb2e8f9f7 829 }
AnnaBridge 167:e84263d55307 830
<> 144:ef7eb2e8f9f7 831 /**
<> 144:ef7eb2e8f9f7 832 * @}
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 838 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 839 *
<> 144:ef7eb2e8f9f7 840 @verbatim
<> 144:ef7eb2e8f9f7 841 ===============================================================================
<> 144:ef7eb2e8f9f7 842 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 843 ===============================================================================
<> 144:ef7eb2e8f9f7 844 [..]
<> 144:ef7eb2e8f9f7 845 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 846 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 847 (+) Get error code
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 @endverbatim
<> 144:ef7eb2e8f9f7 850 * @{
<> 144:ef7eb2e8f9f7 851 */
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /**
<> 144:ef7eb2e8f9f7 854 * @brief Return the DMA hande state.
<> 144:ef7eb2e8f9f7 855 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 856 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 857 * @retval HAL state
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Return DMA handle state */
<> 144:ef7eb2e8f9f7 862 return hdma->State;
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /**
<> 144:ef7eb2e8f9f7 866 * @brief Return the DMA error code.
<> 144:ef7eb2e8f9f7 867 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 868 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 869 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 870 */
<> 144:ef7eb2e8f9f7 871 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 872 {
<> 144:ef7eb2e8f9f7 873 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /**
<> 144:ef7eb2e8f9f7 877 * @}
<> 144:ef7eb2e8f9f7 878 */
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /**
<> 144:ef7eb2e8f9f7 881 * @}
<> 144:ef7eb2e8f9f7 882 */
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 885 * @{
<> 144:ef7eb2e8f9f7 886 */
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /**
<> 144:ef7eb2e8f9f7 889 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 890 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 891 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 892 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 893 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 894 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 895 * @retval HAL status
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 /* Clear all flags */
AnnaBridge 167:e84263d55307 900 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 903 hdma->Instance->CNDTR = DataLength;
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 906 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 907 {
<> 144:ef7eb2e8f9f7 908 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 909 hdma->Instance->CPAR = DstAddress;
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 912 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 915 else
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 918 hdma->Instance->CPAR = SrcAddress;
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 921 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 922 }
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /**
<> 144:ef7eb2e8f9f7 926 * @}
<> 144:ef7eb2e8f9f7 927 */
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /**
<> 144:ef7eb2e8f9f7 930 * @}
<> 144:ef7eb2e8f9f7 931 */
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 934 /**
<> 144:ef7eb2e8f9f7 935 * @}
<> 144:ef7eb2e8f9f7 936 */
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /**
<> 144:ef7eb2e8f9f7 939 * @}
<> 144:ef7eb2e8f9f7 940 */
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/