mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c@181:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
181:57724642e740
Parent:
167:e84263d55307 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 (#) Enable and configure the peripheral to be connected to the DMA Channel
AnnaBridge 181:57724642e740 17 (except for internal SRAM / FLASH memories: no initialization is
<> 144:ef7eb2e8f9f7 18 necessary). Please refer to the Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 19 and DMA requests.
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 (#) For a given Channel, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 22 Channel request, Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 23 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
<> 144:ef7eb2e8f9f7 24 using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 25
AnnaBridge 181:57724642e740 26 Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
AnnaBridge 181:57724642e740 27 thanks to:
AnnaBridge 181:57724642e740 28 (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ;
AnnaBridge 181:57724642e740 29 (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
AnnaBridge 167:e84263d55307 30
AnnaBridge 181:57724642e740 31 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 32 detection.
AnnaBridge 181:57724642e740 33
<> 144:ef7eb2e8f9f7 34 (#) Use HAL_DMA_Abort() function to abort the current transfer
AnnaBridge 181:57724642e740 35
<> 144:ef7eb2e8f9f7 36 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
AnnaBridge 181:57724642e740 37
<> 144:ef7eb2e8f9f7 38 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 39 =================================
<> 144:ef7eb2e8f9f7 40 [..]
<> 144:ef7eb2e8f9f7 41 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 42 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 43 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 44 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 47 ===================================
<> 144:ef7eb2e8f9f7 48 [..]
<> 144:ef7eb2e8f9f7 49 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 50 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 51 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 52 Source address and destination address and the Length of data to be transferred.
<> 144:ef7eb2e8f9f7 53 In this case the DMA interrupt is configured
<> 144:ef7eb2e8f9f7 54 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 55 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
AnnaBridge 181:57724642e740 56 add his own function to register callbacks with HAL_DMA_RegisterCallback().
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 *** DMA HAL driver macros list ***
AnnaBridge 181:57724642e740 59 =============================================
<> 144:ef7eb2e8f9f7 60 [..]
AnnaBridge 181:57724642e740 61 Below the list of macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 64 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 65 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 66 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 67 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 68 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
AnnaBridge 181:57724642e740 69 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
<> 144:ef7eb2e8f9f7 70
AnnaBridge 181:57724642e740 71 [..]
AnnaBridge 181:57724642e740 72 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 @endverbatim
<> 144:ef7eb2e8f9f7 75 ******************************************************************************
<> 144:ef7eb2e8f9f7 76 * @attention
<> 144:ef7eb2e8f9f7 77 *
AnnaBridge 167:e84263d55307 78 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 81 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 82 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 83 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 84 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 85 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 86 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 87 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 88 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 89 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 90 *
<> 144:ef7eb2e8f9f7 91 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 92 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 93 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 94 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 95 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 96 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 97 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 98 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 99 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 100 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 101 *
<> 144:ef7eb2e8f9f7 102 ******************************************************************************
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 106 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 113 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 122 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 124 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 181:57724642e740 128 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 129 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
AnnaBridge 181:57724642e740 130 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
AnnaBridge 181:57724642e740 131 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 132
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 181:57724642e740 144 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 145 *
<> 144:ef7eb2e8f9f7 146 @verbatim
<> 144:ef7eb2e8f9f7 147 ===============================================================================
<> 144:ef7eb2e8f9f7 148 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 149 ===============================================================================
<> 144:ef7eb2e8f9f7 150 [..]
<> 144:ef7eb2e8f9f7 151 This section provides functions allowing to initialize the DMA Channel source
AnnaBridge 181:57724642e740 152 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 153 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 144:ef7eb2e8f9f7 154 [..]
<> 144:ef7eb2e8f9f7 155 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
AnnaBridge 181:57724642e740 156 reference manual.
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 @endverbatim
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /**
<> 144:ef7eb2e8f9f7 163 * @brief Initialize the DMA according to the specified
<> 144:ef7eb2e8f9f7 164 * parameters in the DMA_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 165 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 166 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 167 * @retval HAL status
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 uint32_t tmp = 0;
AnnaBridge 167:e84263d55307 172
<> 144:ef7eb2e8f9f7 173 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 174 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Check the parameters */
<> 144:ef7eb2e8f9f7 180 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 183 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 185 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
AnnaBridge 167:e84263d55307 188
AnnaBridge 181:57724642e740 189 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
AnnaBridge 181:57724642e740 190
AnnaBridge 181:57724642e740 191 /* Compute the channel index */
<> 144:ef7eb2e8f9f7 192 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 /* DMA1 */
<> 144:ef7eb2e8f9f7 195 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 196 hdma->DmaBaseAddress = DMA1;
<> 144:ef7eb2e8f9f7 197 }
AnnaBridge 181:57724642e740 198 else
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 /* DMA2 */
<> 144:ef7eb2e8f9f7 201 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 202 hdma->DmaBaseAddress = DMA2;
<> 144:ef7eb2e8f9f7 203 }
AnnaBridge 167:e84263d55307 204
<> 144:ef7eb2e8f9f7 205 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 206 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 209 tmp = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 210
AnnaBridge 181:57724642e740 211 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
AnnaBridge 181:57724642e740 212 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
AnnaBridge 181:57724642e740 213 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
AnnaBridge 181:57724642e740 214 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 217 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 218 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 219 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 220 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Write to DMA Channel CR register */
<> 144:ef7eb2e8f9f7 223 hdma->Instance->CCR = tmp;
<> 144:ef7eb2e8f9f7 224
AnnaBridge 181:57724642e740 225
AnnaBridge 181:57724642e740 226 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 227 /* Initialize parameters for DMAMUX channel :
AnnaBridge 181:57724642e740 228 DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
AnnaBridge 181:57724642e740 229 */
AnnaBridge 181:57724642e740 230 DMA_CalcDMAMUXChannelBaseAndMask(hdma);
AnnaBridge 181:57724642e740 231
AnnaBridge 181:57724642e740 232 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
AnnaBridge 181:57724642e740 233 {
AnnaBridge 181:57724642e740 234 /* if memory to memory force the request to 0*/
AnnaBridge 181:57724642e740 235 hdma->Init.Request = DMA_REQUEST_MEM2MEM;
AnnaBridge 181:57724642e740 236 }
AnnaBridge 181:57724642e740 237
AnnaBridge 181:57724642e740 238 /* Set peripheral request to DMAMUX channel */
AnnaBridge 181:57724642e740 239 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
AnnaBridge 181:57724642e740 240
AnnaBridge 181:57724642e740 241 /* Clear the DMAMUX synchro overrun flag */
AnnaBridge 181:57724642e740 242 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
AnnaBridge 181:57724642e740 243
AnnaBridge 181:57724642e740 244 if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
AnnaBridge 181:57724642e740 245 {
AnnaBridge 181:57724642e740 246 /* Initialize parameters for DMAMUX request generator :
AnnaBridge 181:57724642e740 247 DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
AnnaBridge 181:57724642e740 248 */
AnnaBridge 181:57724642e740 249 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
AnnaBridge 181:57724642e740 250
AnnaBridge 181:57724642e740 251 /* Reset the DMAMUX request generator register*/
AnnaBridge 181:57724642e740 252 hdma->DMAmuxRequestGen->RGCR = 0U;
AnnaBridge 181:57724642e740 253
AnnaBridge 181:57724642e740 254 /* Clear the DMAMUX request generator overrun flag */
AnnaBridge 181:57724642e740 255 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
AnnaBridge 181:57724642e740 256 }
AnnaBridge 181:57724642e740 257 else
AnnaBridge 181:57724642e740 258 {
AnnaBridge 181:57724642e740 259 hdma->DMAmuxRequestGen = 0U;
AnnaBridge 181:57724642e740 260 hdma->DMAmuxRequestGenStatus = 0U;
AnnaBridge 181:57724642e740 261 hdma->DMAmuxRequestGenStatusMask = 0U;
AnnaBridge 181:57724642e740 262 }
AnnaBridge 181:57724642e740 263 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 264
AnnaBridge 181:57724642e740 265 #if !defined (DMAMUX1)
AnnaBridge 181:57724642e740 266
<> 144:ef7eb2e8f9f7 267 /* Set request selection */
<> 144:ef7eb2e8f9f7 268 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Write to DMA channel selection register */
<> 144:ef7eb2e8f9f7 271 if (DMA1 == hdma->DmaBaseAddress)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 /* Reset request selection for DMA1 Channelx */
<> 144:ef7eb2e8f9f7 274 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Configure request selection for DMA1 Channelx */
AnnaBridge 181:57724642e740 277 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 else /* DMA2 */
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 /* Reset request selection for DMA2 Channelx */
<> 144:ef7eb2e8f9f7 282 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
AnnaBridge 181:57724642e740 283
<> 144:ef7eb2e8f9f7 284 /* Configure request selection for DMA2 Channelx */
AnnaBridge 181:57724642e740 285 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
AnnaBridge 181:57724642e740 289 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
AnnaBridge 181:57724642e740 290 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
AnnaBridge 181:57724642e740 291 /* STM32L496xx || STM32L4A6xx */
AnnaBridge 181:57724642e740 292
<> 144:ef7eb2e8f9f7 293 /* Clean callbacks */
<> 144:ef7eb2e8f9f7 294 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 295 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 296 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 297 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 300 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Initialize the DMA state*/
<> 144:ef7eb2e8f9f7 303 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 306 hdma->Lock = HAL_UNLOCKED;
AnnaBridge 181:57724642e740 307
<> 144:ef7eb2e8f9f7 308 return HAL_OK;
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @brief DeInitialize the DMA peripheral.
<> 144:ef7eb2e8f9f7 313 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 314 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 315 * @retval HAL status
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 318 {
AnnaBridge 181:57724642e740 319
<> 144:ef7eb2e8f9f7 320 /* Check the DMA handle allocation */
AnnaBridge 181:57724642e740 321 if (NULL == hdma )
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 324 }
AnnaBridge 181:57724642e740 325
<> 144:ef7eb2e8f9f7 326 /* Check the parameters */
<> 144:ef7eb2e8f9f7 327 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Disable the selected DMA Channelx */
<> 144:ef7eb2e8f9f7 330 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 331
AnnaBridge 181:57724642e740 332 /* Compute the channel index */
<> 144:ef7eb2e8f9f7 333 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 /* DMA1 */
<> 144:ef7eb2e8f9f7 336 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 337 hdma->DmaBaseAddress = DMA1;
<> 144:ef7eb2e8f9f7 338 }
AnnaBridge 181:57724642e740 339 else
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 /* DMA2 */
<> 144:ef7eb2e8f9f7 342 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 144:ef7eb2e8f9f7 343 hdma->DmaBaseAddress = DMA2;
<> 144:ef7eb2e8f9f7 344 }
AnnaBridge 181:57724642e740 345
AnnaBridge 181:57724642e740 346 /* Reset DMA Channel control register */
AnnaBridge 181:57724642e740 347 hdma->Instance->CCR = 0;
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Clear all flags */
AnnaBridge 181:57724642e740 350 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
AnnaBridge 181:57724642e740 351
AnnaBridge 181:57724642e740 352 #if !defined (DMAMUX1)
AnnaBridge 167:e84263d55307 353
<> 144:ef7eb2e8f9f7 354 /* Reset DMA channel selection register */
<> 144:ef7eb2e8f9f7 355 if (DMA1 == hdma->DmaBaseAddress)
<> 144:ef7eb2e8f9f7 356 {
<> 144:ef7eb2e8f9f7 357 /* DMA1 */
AnnaBridge 181:57724642e740 358 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 359 }
AnnaBridge 181:57724642e740 360 else
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* DMA2 */
AnnaBridge 181:57724642e740 363 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex));
<> 144:ef7eb2e8f9f7 364 }
AnnaBridge 181:57724642e740 365 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
AnnaBridge 181:57724642e740 366 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
AnnaBridge 181:57724642e740 367 /* STM32L496xx || STM32L4A6xx */
<> 144:ef7eb2e8f9f7 368
AnnaBridge 181:57724642e740 369 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 370
AnnaBridge 181:57724642e740 371 /* Initialize parameters for DMAMUX channel :
AnnaBridge 181:57724642e740 372 DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
AnnaBridge 181:57724642e740 373
AnnaBridge 181:57724642e740 374 DMA_CalcDMAMUXChannelBaseAndMask(hdma);
AnnaBridge 181:57724642e740 375
AnnaBridge 181:57724642e740 376 /* Reset the DMAMUX channel that corresponds to the DMA channel */
AnnaBridge 181:57724642e740 377 hdma->DMAmuxChannel->CCR = 0;
AnnaBridge 181:57724642e740 378
AnnaBridge 181:57724642e740 379 /* Clear the DMAMUX synchro overrun flag */
AnnaBridge 181:57724642e740 380 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
AnnaBridge 181:57724642e740 381
AnnaBridge 181:57724642e740 382 /* Reset Request generator parameters if any */
AnnaBridge 181:57724642e740 383 if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
AnnaBridge 181:57724642e740 384 {
AnnaBridge 181:57724642e740 385 /* Initialize parameters for DMAMUX request generator :
AnnaBridge 181:57724642e740 386 DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
AnnaBridge 181:57724642e740 387 */
AnnaBridge 181:57724642e740 388 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
AnnaBridge 181:57724642e740 389
AnnaBridge 181:57724642e740 390 /* Reset the DMAMUX request generator register*/
AnnaBridge 181:57724642e740 391 hdma->DMAmuxRequestGen->RGCR = 0U;
AnnaBridge 181:57724642e740 392
AnnaBridge 181:57724642e740 393 /* Clear the DMAMUX request generator overrun flag */
AnnaBridge 181:57724642e740 394 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
AnnaBridge 181:57724642e740 395 }
AnnaBridge 181:57724642e740 396
AnnaBridge 181:57724642e740 397 hdma->DMAmuxRequestGen = 0U;
AnnaBridge 181:57724642e740 398 hdma->DMAmuxRequestGenStatus = 0U;
AnnaBridge 181:57724642e740 399 hdma->DMAmuxRequestGenStatusMask = 0U;
AnnaBridge 181:57724642e740 400
AnnaBridge 181:57724642e740 401 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 402
AnnaBridge 181:57724642e740 403 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 404 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 407 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Release Lock */
<> 144:ef7eb2e8f9f7 410 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 return HAL_OK;
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @}
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 420 * @brief Input and Output operation functions
<> 144:ef7eb2e8f9f7 421 *
<> 144:ef7eb2e8f9f7 422 @verbatim
<> 144:ef7eb2e8f9f7 423 ===============================================================================
<> 144:ef7eb2e8f9f7 424 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 425 ===============================================================================
<> 144:ef7eb2e8f9f7 426 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 427 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 428 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 429 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 430 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 431 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 432 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 @endverbatim
<> 144:ef7eb2e8f9f7 435 * @{
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @brief Start the DMA Transfer.
<> 144:ef7eb2e8f9f7 440 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 441 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 442 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 443 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 444 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 445 * @retval HAL status
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Check the parameters */
<> 144:ef7eb2e8f9f7 452 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Process locked */
<> 144:ef7eb2e8f9f7 455 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 460 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 461 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
AnnaBridge 181:57724642e740 462
<> 144:ef7eb2e8f9f7 463 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 464 __HAL_DMA_DISABLE(hdma);
AnnaBridge 181:57724642e740 465
<> 144:ef7eb2e8f9f7 466 /* Configure the source, destination address and the data length & clear flags*/
<> 144:ef7eb2e8f9f7 467 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
AnnaBridge 181:57724642e740 468
<> 144:ef7eb2e8f9f7 469 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 470 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472 else
<> 144:ef7eb2e8f9f7 473 {
AnnaBridge 181:57724642e740 474 /* Process Unlocked */
AnnaBridge 181:57724642e740 475 __HAL_UNLOCK(hdma);
AnnaBridge 181:57724642e740 476 status = HAL_BUSY;
AnnaBridge 181:57724642e740 477 }
<> 144:ef7eb2e8f9f7 478 return status;
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 483 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 484 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 485 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 486 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 487 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 488 * @retval HAL status
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Check the parameters */
<> 144:ef7eb2e8f9f7 495 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Process locked */
<> 144:ef7eb2e8f9f7 498 __HAL_LOCK(hdma);
AnnaBridge 181:57724642e740 499
<> 144:ef7eb2e8f9f7 500 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 503 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 504 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
AnnaBridge 181:57724642e740 505
<> 144:ef7eb2e8f9f7 506 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 507 __HAL_DMA_DISABLE(hdma);
AnnaBridge 181:57724642e740 508
<> 144:ef7eb2e8f9f7 509 /* Configure the source, destination address and the data length & clear flags*/
<> 144:ef7eb2e8f9f7 510 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
AnnaBridge 181:57724642e740 511
<> 144:ef7eb2e8f9f7 512 /* Enable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 513 /* Enable the transfer Error interrupt */
<> 144:ef7eb2e8f9f7 514 if(NULL != hdma->XferHalfCpltCallback )
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 /* Enable the Half transfer complete interrupt as well */
<> 144:ef7eb2e8f9f7 517 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 else
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 522 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 523 }
AnnaBridge 181:57724642e740 524
AnnaBridge 181:57724642e740 525 #ifdef DMAMUX1
AnnaBridge 181:57724642e740 526
AnnaBridge 181:57724642e740 527 /* Check if DMAMUX Synchronization is enabled*/
AnnaBridge 181:57724642e740 528 if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
AnnaBridge 181:57724642e740 529 {
AnnaBridge 181:57724642e740 530 /* Enable DMAMUX sync overrun IT*/
AnnaBridge 181:57724642e740 531 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
AnnaBridge 181:57724642e740 532 }
AnnaBridge 181:57724642e740 533
AnnaBridge 181:57724642e740 534 if(hdma->DMAmuxRequestGen != 0U)
AnnaBridge 181:57724642e740 535 {
AnnaBridge 181:57724642e740 536 /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
AnnaBridge 181:57724642e740 537 /* enable the request gen overrun IT*/
AnnaBridge 181:57724642e740 538 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
AnnaBridge 181:57724642e740 539 }
AnnaBridge 181:57724642e740 540
AnnaBridge 181:57724642e740 541 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 542
<> 144:ef7eb2e8f9f7 543 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 544 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546 else
AnnaBridge 181:57724642e740 547 {
<> 144:ef7eb2e8f9f7 548 /* Process Unlocked */
AnnaBridge 181:57724642e740 549 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Remain BUSY */
<> 144:ef7eb2e8f9f7 552 status = HAL_BUSY;
AnnaBridge 181:57724642e740 553 }
<> 144:ef7eb2e8f9f7 554 return status;
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @brief Abort the DMA Transfer.
<> 144:ef7eb2e8f9f7 559 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 560 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 561 * @retval HAL status
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 167:e84263d55307 566
AnnaBridge 181:57724642e740 567 /* Check the DMA peripheral handle */
AnnaBridge 181:57724642e740 568 if(NULL == hdma)
<> 144:ef7eb2e8f9f7 569 {
AnnaBridge 181:57724642e740 570 return HAL_ERROR;
AnnaBridge 181:57724642e740 571 }
AnnaBridge 181:57724642e740 572
AnnaBridge 181:57724642e740 573 /* Disable DMA IT */
AnnaBridge 181:57724642e740 574 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
AnnaBridge 181:57724642e740 575
AnnaBridge 181:57724642e740 576 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 577 /* disable the DMAMUX sync overrun IT*/
AnnaBridge 181:57724642e740 578 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
AnnaBridge 181:57724642e740 579 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 580
AnnaBridge 181:57724642e740 581 /* Disable the channel */
AnnaBridge 181:57724642e740 582 __HAL_DMA_DISABLE(hdma);
AnnaBridge 181:57724642e740 583
AnnaBridge 181:57724642e740 584 /* Clear all flags */
AnnaBridge 181:57724642e740 585 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 586
AnnaBridge 181:57724642e740 587 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 588 /* Clear the DMAMUX synchro overrun flag */
AnnaBridge 181:57724642e740 589 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
AnnaBridge 181:57724642e740 590
AnnaBridge 181:57724642e740 591 if(hdma->DMAmuxRequestGen != 0U)
AnnaBridge 181:57724642e740 592 {
AnnaBridge 181:57724642e740 593 /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
AnnaBridge 181:57724642e740 594 /* disable the request gen overrun IT*/
AnnaBridge 181:57724642e740 595 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
<> 144:ef7eb2e8f9f7 596
AnnaBridge 181:57724642e740 597 /* Clear the DMAMUX request generator overrun flag */
AnnaBridge 181:57724642e740 598 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
<> 144:ef7eb2e8f9f7 599 }
AnnaBridge 181:57724642e740 600
AnnaBridge 181:57724642e740 601 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 602
AnnaBridge 181:57724642e740 603 /* Change the DMA state */
AnnaBridge 181:57724642e740 604 hdma->State = HAL_DMA_STATE_READY;
AnnaBridge 181:57724642e740 605
AnnaBridge 181:57724642e740 606 /* Process Unlocked */
AnnaBridge 181:57724642e740 607 __HAL_UNLOCK(hdma);
AnnaBridge 181:57724642e740 608
AnnaBridge 181:57724642e740 609 return status;
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /**
<> 144:ef7eb2e8f9f7 613 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 144:ef7eb2e8f9f7 614 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 615 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 616 * @retval HAL status
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
AnnaBridge 181:57724642e740 619 {
<> 144:ef7eb2e8f9f7 620 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 181:57724642e740 621
<> 144:ef7eb2e8f9f7 622 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 625 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
AnnaBridge 181:57724642e740 626
<> 144:ef7eb2e8f9f7 627 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629 else
AnnaBridge 181:57724642e740 630 {
<> 144:ef7eb2e8f9f7 631 /* Disable DMA IT */
<> 144:ef7eb2e8f9f7 632 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
AnnaBridge 181:57724642e740 633
<> 144:ef7eb2e8f9f7 634 /* Disable the channel */
<> 144:ef7eb2e8f9f7 635 __HAL_DMA_DISABLE(hdma);
AnnaBridge 181:57724642e740 636
AnnaBridge 181:57724642e740 637 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 638 /* disable the DMAMUX sync overrun IT*/
AnnaBridge 181:57724642e740 639 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
AnnaBridge 181:57724642e740 640
<> 144:ef7eb2e8f9f7 641 /* Clear all flags */
AnnaBridge 167:e84263d55307 642 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
AnnaBridge 181:57724642e740 643
AnnaBridge 181:57724642e740 644 /* Clear the DMAMUX synchro overrun flag */
AnnaBridge 181:57724642e740 645 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
AnnaBridge 181:57724642e740 646
AnnaBridge 181:57724642e740 647 if(hdma->DMAmuxRequestGen != 0U)
AnnaBridge 181:57724642e740 648 {
AnnaBridge 181:57724642e740 649 /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
AnnaBridge 181:57724642e740 650 /* disable the request gen overrun IT*/
AnnaBridge 181:57724642e740 651 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
AnnaBridge 181:57724642e740 652
AnnaBridge 181:57724642e740 653 /* Clear the DMAMUX request generator overrun flag */
AnnaBridge 181:57724642e740 654 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
AnnaBridge 181:57724642e740 655 }
AnnaBridge 181:57724642e740 656
AnnaBridge 181:57724642e740 657 #else
AnnaBridge 181:57724642e740 658 /* Clear all flags */
AnnaBridge 181:57724642e740 659 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
AnnaBridge 181:57724642e740 660 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 661
<> 144:ef7eb2e8f9f7 662 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 663 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 666 __HAL_UNLOCK(hdma);
AnnaBridge 181:57724642e740 667
AnnaBridge 181:57724642e740 668 /* Call User Abort callback */
<> 144:ef7eb2e8f9f7 669 if(hdma->XferAbortCallback != NULL)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 hdma->XferAbortCallback(hdma);
AnnaBridge 181:57724642e740 672 }
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 return status;
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 679 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 680 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 681 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 682 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 683 * @retval HAL status
<> 144:ef7eb2e8f9f7 684 */
AnnaBridge 181:57724642e740 685 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 uint32_t temp;
<> 144:ef7eb2e8f9f7 688 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 693 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
AnnaBridge 181:57724642e740 694 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 695 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Polling mode not supported in circular mode */
<> 144:ef7eb2e8f9f7 699 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 144:ef7eb2e8f9f7 702 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 703 }
AnnaBridge 181:57724642e740 704
<> 144:ef7eb2e8f9f7 705 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 706 if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 709 temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711 else
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 714 temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /* Get tick */
<> 144:ef7eb2e8f9f7 718 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 719
AnnaBridge 181:57724642e740 720 while(RESET == (hdma->DmaBaseAddress->ISR & temp))
<> 144:ef7eb2e8f9f7 721 {
AnnaBridge 181:57724642e740 722 if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))))
<> 144:ef7eb2e8f9f7 723 {
<> 144:ef7eb2e8f9f7 724 /* When a DMA transfer error occurs */
<> 144:ef7eb2e8f9f7 725 /* A hardware clear of its EN bits is performed */
<> 144:ef7eb2e8f9f7 726 /* Clear all flags */
AnnaBridge 167:e84263d55307 727 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /* Update error code */
<> 144:ef7eb2e8f9f7 730 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 733 hdma->State= HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 736 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 739 }
<> 144:ef7eb2e8f9f7 740 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 741 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 /* Update error code */
<> 144:ef7eb2e8f9f7 746 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 749 hdma->State = HAL_DMA_STATE_READY;
AnnaBridge 181:57724642e740 750
<> 144:ef7eb2e8f9f7 751 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 752 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 755 }
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758
AnnaBridge 181:57724642e740 759 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 760 /*Check for DMAMUX Request generator (if used) overrun status */
AnnaBridge 181:57724642e740 761 if(hdma->DMAmuxRequestGen != 0U)
AnnaBridge 181:57724642e740 762 {
AnnaBridge 181:57724642e740 763 /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
AnnaBridge 181:57724642e740 764 if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
AnnaBridge 181:57724642e740 765 {
AnnaBridge 181:57724642e740 766 /* Disable the request gen overrun interrupt */
AnnaBridge 181:57724642e740 767 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
AnnaBridge 181:57724642e740 768
AnnaBridge 181:57724642e740 769 /* Clear the DMAMUX request generator overrun flag */
AnnaBridge 181:57724642e740 770 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
AnnaBridge 181:57724642e740 771
AnnaBridge 181:57724642e740 772 /* Update error code */
AnnaBridge 181:57724642e740 773 hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
AnnaBridge 181:57724642e740 774 }
AnnaBridge 181:57724642e740 775 }
AnnaBridge 181:57724642e740 776
AnnaBridge 181:57724642e740 777 /* Check for DMAMUX Synchronization overrun */
AnnaBridge 181:57724642e740 778 if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
AnnaBridge 181:57724642e740 779 {
AnnaBridge 181:57724642e740 780 /* Clear the DMAMUX synchro overrun flag */
AnnaBridge 181:57724642e740 781 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
AnnaBridge 181:57724642e740 782
AnnaBridge 181:57724642e740 783 /* Update error code */
AnnaBridge 181:57724642e740 784 hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
AnnaBridge 181:57724642e740 785 }
AnnaBridge 181:57724642e740 786 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 787
<> 144:ef7eb2e8f9f7 788 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 /* Clear the transfer complete flag */
AnnaBridge 167:e84263d55307 791 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 794 all transfers are complete) */
<> 144:ef7eb2e8f9f7 795 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797 else
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 /* Clear the half transfer complete flag */
AnnaBridge 167:e84263d55307 800 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 801 }
AnnaBridge 181:57724642e740 802
<> 144:ef7eb2e8f9f7 803 /* Process unlocked */
AnnaBridge 181:57724642e740 804 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 return HAL_OK;
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @brief Handle DMA interrupt request.
<> 144:ef7eb2e8f9f7 811 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 812 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 813 * @retval None
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
<> 144:ef7eb2e8f9f7 818 uint32_t source_it = hdma->Instance->CCR;
AnnaBridge 181:57724642e740 819
<> 144:ef7eb2e8f9f7 820 /* Half Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 821 if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 824 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 /* Disable the half transfer interrupt */
<> 144:ef7eb2e8f9f7 827 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829 /* Clear the half transfer complete flag */
AnnaBridge 167:e84263d55307 830 hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* DMA peripheral state is not updated in Half Transfer */
<> 144:ef7eb2e8f9f7 833 /* but in Transfer Complete case */
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 838 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840 }
AnnaBridge 181:57724642e740 841
<> 144:ef7eb2e8f9f7 842 /* Transfer Complete Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 843 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 /* Disable the transfer complete and error interrupt */
AnnaBridge 181:57724642e740 848 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 851 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853 /* Clear the transfer complete flag */
AnnaBridge 167:e84263d55307 854 hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 857 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 862 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /* Transfer Error Interrupt management **************************************/
<> 144:ef7eb2e8f9f7 867 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
<> 144:ef7eb2e8f9f7 868 {
<> 144:ef7eb2e8f9f7 869 /* When a DMA transfer error occurs */
<> 144:ef7eb2e8f9f7 870 /* A hardware clear of its EN bits is performed */
<> 144:ef7eb2e8f9f7 871 /* Disable ALL DMA IT */
<> 144:ef7eb2e8f9f7 872 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Clear all flags */
AnnaBridge 167:e84263d55307 875 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /* Update error code */
<> 144:ef7eb2e8f9f7 878 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 881 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 884 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 if (hdma->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 /* Transfer error callback */
<> 144:ef7eb2e8f9f7 889 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892 return;
<> 144:ef7eb2e8f9f7 893 }
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /**
<> 144:ef7eb2e8f9f7 896 * @brief Register callbacks
<> 144:ef7eb2e8f9f7 897 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 898 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 899 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 900 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
AnnaBridge 181:57724642e740 901 * @param pCallback: pointer to private callbacsk function which has pointer to
<> 144:ef7eb2e8f9f7 902 * a DMA_HandleTypeDef structure as parameter.
<> 144:ef7eb2e8f9f7 903 * @retval HAL status
AnnaBridge 181:57724642e740 904 */
<> 144:ef7eb2e8f9f7 905 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 181:57724642e740 908
<> 144:ef7eb2e8f9f7 909 /* Process locked */
<> 144:ef7eb2e8f9f7 910 __HAL_LOCK(hdma);
AnnaBridge 181:57724642e740 911
<> 144:ef7eb2e8f9f7 912 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 913 {
<> 144:ef7eb2e8f9f7 914 switch (CallbackID)
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 917 hdma->XferCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 918 break;
AnnaBridge 181:57724642e740 919
<> 144:ef7eb2e8f9f7 920 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 921 hdma->XferHalfCpltCallback = pCallback;
AnnaBridge 181:57724642e740 922 break;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 925 hdma->XferErrorCallback = pCallback;
AnnaBridge 181:57724642e740 926 break;
AnnaBridge 181:57724642e740 927
<> 144:ef7eb2e8f9f7 928 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 929 hdma->XferAbortCallback = pCallback;
AnnaBridge 181:57724642e740 930 break;
AnnaBridge 181:57724642e740 931
<> 144:ef7eb2e8f9f7 932 default:
<> 144:ef7eb2e8f9f7 933 status = HAL_ERROR;
AnnaBridge 181:57724642e740 934 break;
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937 else
<> 144:ef7eb2e8f9f7 938 {
<> 144:ef7eb2e8f9f7 939 status = HAL_ERROR;
AnnaBridge 181:57724642e740 940 }
AnnaBridge 181:57724642e740 941
<> 144:ef7eb2e8f9f7 942 /* Release Lock */
<> 144:ef7eb2e8f9f7 943 __HAL_UNLOCK(hdma);
AnnaBridge 181:57724642e740 944
<> 144:ef7eb2e8f9f7 945 return status;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /**
<> 144:ef7eb2e8f9f7 949 * @brief UnRegister callbacks
<> 144:ef7eb2e8f9f7 950 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 951 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 952 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 953 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 144:ef7eb2e8f9f7 954 * @retval HAL status
AnnaBridge 181:57724642e740 955 */
<> 144:ef7eb2e8f9f7 956 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /* Process locked */
<> 144:ef7eb2e8f9f7 961 __HAL_LOCK(hdma);
AnnaBridge 181:57724642e740 962
<> 144:ef7eb2e8f9f7 963 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 964 {
<> 144:ef7eb2e8f9f7 965 switch (CallbackID)
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 968 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 969 break;
AnnaBridge 181:57724642e740 970
<> 144:ef7eb2e8f9f7 971 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 972 hdma->XferHalfCpltCallback = NULL;
AnnaBridge 181:57724642e740 973 break;
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 976 hdma->XferErrorCallback = NULL;
AnnaBridge 181:57724642e740 977 break;
AnnaBridge 181:57724642e740 978
<> 144:ef7eb2e8f9f7 979 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 980 hdma->XferAbortCallback = NULL;
AnnaBridge 181:57724642e740 981 break;
AnnaBridge 181:57724642e740 982
<> 144:ef7eb2e8f9f7 983 case HAL_DMA_XFER_ALL_CB_ID:
<> 144:ef7eb2e8f9f7 984 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 985 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 986 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 987 hdma->XferAbortCallback = NULL;
AnnaBridge 181:57724642e740 988 break;
AnnaBridge 181:57724642e740 989
<> 144:ef7eb2e8f9f7 990 default:
<> 144:ef7eb2e8f9f7 991 status = HAL_ERROR;
AnnaBridge 181:57724642e740 992 break;
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994 }
<> 144:ef7eb2e8f9f7 995 else
<> 144:ef7eb2e8f9f7 996 {
<> 144:ef7eb2e8f9f7 997 status = HAL_ERROR;
AnnaBridge 181:57724642e740 998 }
AnnaBridge 181:57724642e740 999
<> 144:ef7eb2e8f9f7 1000 /* Release Lock */
<> 144:ef7eb2e8f9f7 1001 __HAL_UNLOCK(hdma);
AnnaBridge 181:57724642e740 1002
<> 144:ef7eb2e8f9f7 1003 return status;
<> 144:ef7eb2e8f9f7 1004 }
AnnaBridge 181:57724642e740 1005
<> 144:ef7eb2e8f9f7 1006 /**
<> 144:ef7eb2e8f9f7 1007 * @}
<> 144:ef7eb2e8f9f7 1008 */
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1013 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1014 *
<> 144:ef7eb2e8f9f7 1015 @verbatim
<> 144:ef7eb2e8f9f7 1016 ===============================================================================
<> 144:ef7eb2e8f9f7 1017 ##### Peripheral State and Errors functions #####
AnnaBridge 181:57724642e740 1018 ===============================================================================
<> 144:ef7eb2e8f9f7 1019 [..]
<> 144:ef7eb2e8f9f7 1020 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 1021 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 1022 (+) Get error code
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 @endverbatim
<> 144:ef7eb2e8f9f7 1025 * @{
<> 144:ef7eb2e8f9f7 1026 */
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /**
<> 144:ef7eb2e8f9f7 1029 * @brief Return the DMA hande state.
<> 144:ef7eb2e8f9f7 1030 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1031 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 1032 * @retval HAL state
<> 144:ef7eb2e8f9f7 1033 */
<> 144:ef7eb2e8f9f7 1034 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 /* Return DMA handle state */
<> 144:ef7eb2e8f9f7 1037 return hdma->State;
<> 144:ef7eb2e8f9f7 1038 }
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 /**
<> 144:ef7eb2e8f9f7 1041 * @brief Return the DMA error code.
<> 144:ef7eb2e8f9f7 1042 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1043 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 1044 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 1045 */
<> 144:ef7eb2e8f9f7 1046 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1047 {
<> 144:ef7eb2e8f9f7 1048 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /**
<> 144:ef7eb2e8f9f7 1052 * @}
<> 144:ef7eb2e8f9f7 1053 */
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /**
<> 144:ef7eb2e8f9f7 1056 * @}
<> 144:ef7eb2e8f9f7 1057 */
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 1060 * @{
<> 144:ef7eb2e8f9f7 1061 */
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /**
<> 144:ef7eb2e8f9f7 1064 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 1065 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1066 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 1067 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 1068 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 1069 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 1070 * @retval HAL status
<> 144:ef7eb2e8f9f7 1071 */
<> 144:ef7eb2e8f9f7 1072 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 1073 {
AnnaBridge 181:57724642e740 1074 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 1075 /* Clear the DMAMUX synchro overrun flag */
AnnaBridge 181:57724642e740 1076 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
AnnaBridge 181:57724642e740 1077
AnnaBridge 181:57724642e740 1078 if(hdma->DMAmuxRequestGen != 0U)
AnnaBridge 181:57724642e740 1079 {
AnnaBridge 181:57724642e740 1080 /* Clear the DMAMUX request generator overrun flag */
AnnaBridge 181:57724642e740 1081 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
AnnaBridge 181:57724642e740 1082 }
AnnaBridge 181:57724642e740 1083 #endif
AnnaBridge 181:57724642e740 1084
<> 144:ef7eb2e8f9f7 1085 /* Clear all flags */
AnnaBridge 167:e84263d55307 1086 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
AnnaBridge 181:57724642e740 1087
<> 144:ef7eb2e8f9f7 1088 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 1089 hdma->Instance->CNDTR = DataLength;
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 1092 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 1095 hdma->Instance->CPAR = DstAddress;
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 1098 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 1099 }
<> 144:ef7eb2e8f9f7 1100 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 1101 else
<> 144:ef7eb2e8f9f7 1102 {
<> 144:ef7eb2e8f9f7 1103 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 1104 hdma->Instance->CPAR = SrcAddress;
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 1107 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 1108 }
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
AnnaBridge 181:57724642e740 1111 #if defined(DMAMUX1)
AnnaBridge 181:57724642e740 1112
AnnaBridge 181:57724642e740 1113 /**
AnnaBridge 181:57724642e740 1114 * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number
AnnaBridge 181:57724642e740 1115 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 181:57724642e740 1116 * the configuration information for the specified DMA Stream.
AnnaBridge 181:57724642e740 1117 * @retval None
AnnaBridge 181:57724642e740 1118 */
AnnaBridge 181:57724642e740 1119 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
AnnaBridge 181:57724642e740 1120 {
AnnaBridge 181:57724642e740 1121 uint32_t channel_number = 0;
AnnaBridge 181:57724642e740 1122 DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
AnnaBridge 181:57724642e740 1123
AnnaBridge 181:57724642e740 1124 /* check if instance is not outside the DMA channel range */
AnnaBridge 181:57724642e740 1125 if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
AnnaBridge 181:57724642e740 1126 {
AnnaBridge 181:57724642e740 1127 /* DMA1 */
AnnaBridge 181:57724642e740 1128 DMAMUX1_ChannelBase = DMAMUX1_Channel0;
AnnaBridge 181:57724642e740 1129 }
AnnaBridge 181:57724642e740 1130 else
AnnaBridge 181:57724642e740 1131 {
AnnaBridge 181:57724642e740 1132 /* DMA2 */
AnnaBridge 181:57724642e740 1133 DMAMUX1_ChannelBase = DMAMUX1_Channel7;
AnnaBridge 181:57724642e740 1134 }
AnnaBridge 181:57724642e740 1135 channel_number = (((uint32_t)hdma->Instance & 0xFF) - 8) / 20;
AnnaBridge 181:57724642e740 1136 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + (hdma->ChannelIndex >> 2) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0));
AnnaBridge 181:57724642e740 1137 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
AnnaBridge 181:57724642e740 1138 hdma->DMAmuxChannelStatusMask = 1U << channel_number;
AnnaBridge 181:57724642e740 1139 }
AnnaBridge 181:57724642e740 1140
AnnaBridge 181:57724642e740 1141 /**
AnnaBridge 181:57724642e740 1142 * @brief Updates the DMA handle with the DMAMUX request generator params
AnnaBridge 181:57724642e740 1143 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 181:57724642e740 1144 * the configuration information for the specified DMA Stream.
AnnaBridge 181:57724642e740 1145 * @retval None
AnnaBridge 181:57724642e740 1146 */
AnnaBridge 181:57724642e740 1147
AnnaBridge 181:57724642e740 1148 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
AnnaBridge 181:57724642e740 1149 {
AnnaBridge 181:57724642e740 1150 uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
AnnaBridge 181:57724642e740 1151
AnnaBridge 181:57724642e740 1152 /* DMA Channels are connected to DMAMUX1 request generator blocks*/
AnnaBridge 181:57724642e740 1153 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
AnnaBridge 181:57724642e740 1154
AnnaBridge 181:57724642e740 1155 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
AnnaBridge 181:57724642e740 1156
AnnaBridge 181:57724642e740 1157 hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U);
AnnaBridge 181:57724642e740 1158 }
AnnaBridge 181:57724642e740 1159
AnnaBridge 181:57724642e740 1160 #endif /* DMAMUX1 */
AnnaBridge 181:57724642e740 1161
<> 144:ef7eb2e8f9f7 1162 /**
<> 144:ef7eb2e8f9f7 1163 * @}
<> 144:ef7eb2e8f9f7 1164 */
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 /**
<> 144:ef7eb2e8f9f7 1167 * @}
<> 144:ef7eb2e8f9f7 1168 */
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1171 /**
<> 144:ef7eb2e8f9f7 1172 * @}
<> 144:ef7eb2e8f9f7 1173 */
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /**
<> 144:ef7eb2e8f9f7 1176 * @}
<> 144:ef7eb2e8f9f7 1177 */
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/