mbed official / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32f30x.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 05-March-2014
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
bogdanm 0:9b334a45a8ff 8 * This file contains the system clock configuration for STM32F30x devices,
bogdanm 0:9b334a45a8ff 9 * and is generated by the clock configuration tool
bogdanm 0:9b334a45a8ff 10 * stm32f30x_Clock_Configuration_V1.0.0.xls
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 * 1. This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 13 * user application:
bogdanm 0:9b334a45a8ff 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
bogdanm 0:9b334a45a8ff 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
bogdanm 0:9b334a45a8ff 16 * depending on the configuration made in the clock xls tool.
bogdanm 0:9b334a45a8ff 17 * This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 18 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 19 * the "startup_stm32f30x.s" file.
bogdanm 0:9b334a45a8ff 20 *
bogdanm 0:9b334a45a8ff 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 22 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 23 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 24 *
bogdanm 0:9b334a45a8ff 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 26 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 27 * during program execution.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
bogdanm 0:9b334a45a8ff 30 * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
bogdanm 0:9b334a45a8ff 31 * configure the system clock before to branch to main program.
bogdanm 0:9b334a45a8ff 32 *
bogdanm 0:9b334a45a8ff 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
bogdanm 0:9b334a45a8ff 34 * function will do nothing and HSI still used as system clock source. User can
bogdanm 0:9b334a45a8ff 35 * add some code to deal with this issue inside the SetSysClock() function.
bogdanm 0:9b334a45a8ff 36 *
bogdanm 0:9b334a45a8ff 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
bogdanm 0:9b334a45a8ff 38 * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
bogdanm 0:9b334a45a8ff 39 * through PLL, and you are using different crystal you have to adapt the HSE
bogdanm 0:9b334a45a8ff 40 * value to your own configuration.
bogdanm 0:9b334a45a8ff 41 *
bogdanm 0:9b334a45a8ff 42 * 5. This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 43 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 44 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
bogdanm 0:9b334a45a8ff 45 * | (external 8 MHz clock) | (internal 8 MHz)
bogdanm 0:9b334a45a8ff 46 * | 2- PLL_HSE_XTAL |
bogdanm 0:9b334a45a8ff 47 * | (external 8 MHz xtal) |
bogdanm 0:9b334a45a8ff 48 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 49 * SYSCLK(MHz) | 72 | 64
bogdanm 0:9b334a45a8ff 50 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 51 * AHBCLK (MHz) | 72 | 64
bogdanm 0:9b334a45a8ff 52 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 53 * APB1CLK (MHz) | 36 | 32
bogdanm 0:9b334a45a8ff 54 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 55 * APB2CLK (MHz) | 72 | 64
bogdanm 0:9b334a45a8ff 56 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 57 * USB capable (48 MHz precise clock) | YES | NO
bogdanm 0:9b334a45a8ff 58 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 59 ******************************************************************************
bogdanm 0:9b334a45a8ff 60 * @attention
bogdanm 0:9b334a45a8ff 61 *
bogdanm 0:9b334a45a8ff 62 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 63 *
bogdanm 0:9b334a45a8ff 64 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 65 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 66 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 67 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 68 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 69 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 70 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 71 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 72 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 73 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 74 *
bogdanm 0:9b334a45a8ff 75 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 76 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 78 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 81 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 82 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 83 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 84 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 85 *
bogdanm 0:9b334a45a8ff 86 ******************************************************************************
bogdanm 0:9b334a45a8ff 87 */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 90 * @{
bogdanm 0:9b334a45a8ff 91 */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /** @addtogroup stm32f30x_system
bogdanm 0:9b334a45a8ff 94 * @{
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /** @addtogroup STM32F30x_System_Private_Includes
bogdanm 0:9b334a45a8ff 98 * @{
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 #include "stm32f30x.h"
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /**
bogdanm 0:9b334a45a8ff 104 * @}
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /** @addtogroup STM32F30x_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 108 * @{
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /**
bogdanm 0:9b334a45a8ff 112 * @}
bogdanm 0:9b334a45a8ff 113 */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /** @addtogroup STM32F30x_System_Private_Defines
bogdanm 0:9b334a45a8ff 116 * @{
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /*!< Uncomment the following line if you need to relocate your vector Table in
bogdanm 0:9b334a45a8ff 120 Internal SRAM. */
bogdanm 0:9b334a45a8ff 121 /* #define VECT_TAB_SRAM */
bogdanm 0:9b334a45a8ff 122 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
bogdanm 0:9b334a45a8ff 123 This value must be a multiple of 0x200. */
bogdanm 0:9b334a45a8ff 124 /**
bogdanm 0:9b334a45a8ff 125 * @}
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /** @addtogroup STM32F30x_System_Private_Macros
bogdanm 0:9b334a45a8ff 129 * @{
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
bogdanm 0:9b334a45a8ff 133 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
bogdanm 0:9b334a45a8ff 134 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /**
bogdanm 0:9b334a45a8ff 137 * @}
bogdanm 0:9b334a45a8ff 138 */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /** @addtogroup STM32F30x_System_Private_Variables
bogdanm 0:9b334a45a8ff 141 * @{
bogdanm 0:9b334a45a8ff 142 */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 /**
bogdanm 0:9b334a45a8ff 149 * @}
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 153 * @{
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 void SetSysClock(void);
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 159 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
bogdanm 0:9b334a45a8ff 160 #endif
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 uint8_t SetSysClock_PLL_HSI(void);
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /**
bogdanm 0:9b334a45a8ff 165 * @}
bogdanm 0:9b334a45a8ff 166 */
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /** @addtogroup STM32F30x_System_Private_Functions
bogdanm 0:9b334a45a8ff 169 * @{
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /**
bogdanm 0:9b334a45a8ff 173 * @brief Setup the microcontroller system
bogdanm 0:9b334a45a8ff 174 * Initialize the Embedded Flash Interface, the PLL and update the
bogdanm 0:9b334a45a8ff 175 * SystemFrequency variable.
bogdanm 0:9b334a45a8ff 176 * @param None
bogdanm 0:9b334a45a8ff 177 * @retval None
bogdanm 0:9b334a45a8ff 178 */
bogdanm 0:9b334a45a8ff 179 void SystemInit(void)
bogdanm 0:9b334a45a8ff 180 {
bogdanm 0:9b334a45a8ff 181 /* FPU settings ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 182 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 0:9b334a45a8ff 183 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
bogdanm 0:9b334a45a8ff 184 #endif
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* Reset the RCC clock configuration to the default reset state ------------*/
bogdanm 0:9b334a45a8ff 187 /* Set HSION bit */
bogdanm 0:9b334a45a8ff 188 RCC->CR |= (uint32_t)0x00000001;
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 191 RCC->CFGR &= 0xF87FC00C;
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /* Reset HSEON, CSSON and PLLON bits */
bogdanm 0:9b334a45a8ff 194 RCC->CR &= (uint32_t)0xFEF6FFFF;
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 197 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
bogdanm 0:9b334a45a8ff 200 RCC->CFGR &= (uint32_t)0xFF80FFFF;
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /* Reset PREDIV1[3:0] bits */
bogdanm 0:9b334a45a8ff 203 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
bogdanm 0:9b334a45a8ff 206 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 209 RCC->CIR = 0x00000000;
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /* Configure the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 212 AHB/APBx prescalers and Flash settings */
bogdanm 0:9b334a45a8ff 213 SetSysClock();
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* Configure the Vector Table location add offset address ------------------*/
bogdanm 0:9b334a45a8ff 216 #ifdef VECT_TAB_SRAM
bogdanm 0:9b334a45a8ff 217 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
bogdanm 0:9b334a45a8ff 218 #else
bogdanm 0:9b334a45a8ff 219 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
bogdanm 0:9b334a45a8ff 220 #endif
bogdanm 0:9b334a45a8ff 221 }
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /**
bogdanm 0:9b334a45a8ff 224 * @brief Update SystemCoreClock variable according to Clock Register Values.
bogdanm 0:9b334a45a8ff 225 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 226 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 227 * other parameters.
bogdanm 0:9b334a45a8ff 228 *
bogdanm 0:9b334a45a8ff 229 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 230 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 231 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 232 *
bogdanm 0:9b334a45a8ff 233 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 234 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 235 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 236 *
bogdanm 0:9b334a45a8ff 237 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 238 *
bogdanm 0:9b334a45a8ff 239 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 240 *
bogdanm 0:9b334a45a8ff 241 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 242 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 243 *
bogdanm 0:9b334a45a8ff 244 * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
bogdanm 0:9b334a45a8ff 245 * 8 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 246 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 247 *
bogdanm 0:9b334a45a8ff 248 * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
bogdanm 0:9b334a45a8ff 249 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 250 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 251 * have wrong result.
bogdanm 0:9b334a45a8ff 252 *
bogdanm 0:9b334a45a8ff 253 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 254 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 255 *
bogdanm 0:9b334a45a8ff 256 * @param None
bogdanm 0:9b334a45a8ff 257 * @retval None
bogdanm 0:9b334a45a8ff 258 */
bogdanm 0:9b334a45a8ff 259 void SystemCoreClockUpdate (void)
bogdanm 0:9b334a45a8ff 260 {
bogdanm 0:9b334a45a8ff 261 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
bogdanm 0:9b334a45a8ff 262
bogdanm 0:9b334a45a8ff 263 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 264 tmp = RCC->CFGR & RCC_CFGR_SWS;
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 switch (tmp)
bogdanm 0:9b334a45a8ff 267 {
bogdanm 0:9b334a45a8ff 268 case 0x00: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 269 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 270 break;
bogdanm 0:9b334a45a8ff 271 case 0x04: /* HSE used as system clock */
bogdanm 0:9b334a45a8ff 272 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 273 break;
bogdanm 0:9b334a45a8ff 274 case 0x08: /* PLL used as system clock */
bogdanm 0:9b334a45a8ff 275 /* Get PLL clock source and multiplication factor ----------------------*/
bogdanm 0:9b334a45a8ff 276 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
bogdanm 0:9b334a45a8ff 277 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
bogdanm 0:9b334a45a8ff 278 pllmull = ( pllmull >> 18) + 2;
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 if (pllsource == 0x00)
bogdanm 0:9b334a45a8ff 281 {
bogdanm 0:9b334a45a8ff 282 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
bogdanm 0:9b334a45a8ff 283 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
bogdanm 0:9b334a45a8ff 284 }
bogdanm 0:9b334a45a8ff 285 else
bogdanm 0:9b334a45a8ff 286 {
bogdanm 0:9b334a45a8ff 287 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
bogdanm 0:9b334a45a8ff 288 /* HSE oscillator clock selected as PREDIV1 clock entry */
bogdanm 0:9b334a45a8ff 289 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
bogdanm 0:9b334a45a8ff 290 }
bogdanm 0:9b334a45a8ff 291 break;
bogdanm 0:9b334a45a8ff 292 default: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 293 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 294 break;
bogdanm 0:9b334a45a8ff 295 }
bogdanm 0:9b334a45a8ff 296 /* Compute HCLK clock frequency ----------------*/
bogdanm 0:9b334a45a8ff 297 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 298 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 299 /* HCLK clock frequency */
bogdanm 0:9b334a45a8ff 300 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /**
bogdanm 0:9b334a45a8ff 304 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 305 * AHB/APBx prescalers and Flash settings
bogdanm 0:9b334a45a8ff 306 * @note This function should be called only once the RCC clock configuration
bogdanm 0:9b334a45a8ff 307 * is reset to the default reset state (done in SystemInit() function).
bogdanm 0:9b334a45a8ff 308 * @param None
bogdanm 0:9b334a45a8ff 309 * @retval None
bogdanm 0:9b334a45a8ff 310 */
bogdanm 0:9b334a45a8ff 311 void SetSysClock(void)
bogdanm 0:9b334a45a8ff 312 {
bogdanm 0:9b334a45a8ff 313 /* 1- Try to start with HSE and external clock */
bogdanm 0:9b334a45a8ff 314 #if USE_PLL_HSE_EXTC != 0
bogdanm 0:9b334a45a8ff 315 if (SetSysClock_PLL_HSE(1) == 0)
bogdanm 0:9b334a45a8ff 316 #endif
bogdanm 0:9b334a45a8ff 317 {
bogdanm 0:9b334a45a8ff 318 /* 2- If fail try to start with HSE and external xtal */
bogdanm 0:9b334a45a8ff 319 #if USE_PLL_HSE_XTAL != 0
bogdanm 0:9b334a45a8ff 320 if (SetSysClock_PLL_HSE(0) == 0)
bogdanm 0:9b334a45a8ff 321 #endif
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 /* 3- If fail start with HSI clock */
bogdanm 0:9b334a45a8ff 324 if (SetSysClock_PLL_HSI() == 0)
bogdanm 0:9b334a45a8ff 325 {
bogdanm 0:9b334a45a8ff 326 while(1)
bogdanm 0:9b334a45a8ff 327 {
bogdanm 0:9b334a45a8ff 328 // [TODO] Put something here to tell the user that a problem occured...
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330 }
bogdanm 0:9b334a45a8ff 331 }
bogdanm 0:9b334a45a8ff 332 }
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 335 /*
bogdanm 0:9b334a45a8ff 336 // Enable GPIOA clock
bogdanm 0:9b334a45a8ff 337 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
bogdanm 0:9b334a45a8ff 338 // Configure MCO pin (PA8)
bogdanm 0:9b334a45a8ff 339 GPIO_InitTypeDef GPIO_InitStructure;
bogdanm 0:9b334a45a8ff 340 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
bogdanm 0:9b334a45a8ff 341 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
bogdanm 0:9b334a45a8ff 342 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
bogdanm 0:9b334a45a8ff 343 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
bogdanm 0:9b334a45a8ff 344 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
bogdanm 0:9b334a45a8ff 345 GPIO_Init(GPIOA, &GPIO_InitStructure);
bogdanm 0:9b334a45a8ff 346 // Select the clock to output
bogdanm 0:9b334a45a8ff 347 RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
bogdanm 0:9b334a45a8ff 348 */
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 352 /******************************************************************************/
bogdanm 0:9b334a45a8ff 353 /* PLL (clocked by HSE) used as System clock source */
bogdanm 0:9b334a45a8ff 354 /******************************************************************************/
bogdanm 0:9b334a45a8ff 355 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
bogdanm 0:9b334a45a8ff 356 {
bogdanm 0:9b334a45a8ff 357 __IO uint32_t StartUpCounter = 0;
bogdanm 0:9b334a45a8ff 358 __IO uint32_t HSEStatus = 0;
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 /* Bypass HSE: can be done only if HSE is OFF */
bogdanm 0:9b334a45a8ff 361 RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
bogdanm 0:9b334a45a8ff 362 if (bypass != 0)
bogdanm 0:9b334a45a8ff 363 {
bogdanm 0:9b334a45a8ff 364 RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
bogdanm 0:9b334a45a8ff 365 }
bogdanm 0:9b334a45a8ff 366 else
bogdanm 0:9b334a45a8ff 367 {
bogdanm 0:9b334a45a8ff 368 RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
bogdanm 0:9b334a45a8ff 369 }
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 /* Enable HSE */
bogdanm 0:9b334a45a8ff 372 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /* Wait till HSE is ready */
bogdanm 0:9b334a45a8ff 375 do
bogdanm 0:9b334a45a8ff 376 {
bogdanm 0:9b334a45a8ff 377 HSEStatus = RCC->CR & RCC_CR_HSERDY;
bogdanm 0:9b334a45a8ff 378 StartUpCounter++;
bogdanm 0:9b334a45a8ff 379 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 /* Check if HSE has started correctly */
bogdanm 0:9b334a45a8ff 382 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 383 {
bogdanm 0:9b334a45a8ff 384 /* Enable prefetch buffer and set flash latency
bogdanm 0:9b334a45a8ff 385 0WS for 0 < SYSCLK <= 24 MHz
bogdanm 0:9b334a45a8ff 386 1WS for 24 < SYSCLK <= 48 MHz
bogdanm 0:9b334a45a8ff 387 2WS for 48 < SYSCLK <= 72 MHz */
bogdanm 0:9b334a45a8ff 388 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 /* Warning: values are obtained with external xtal or clock = 8 MHz */
bogdanm 0:9b334a45a8ff 391 /* SYSCLK = 72 MHz (8 MHz * 9) */
bogdanm 0:9b334a45a8ff 392 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
bogdanm 0:9b334a45a8ff 393 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9
bogdanm 0:9b334a45a8ff 394 | RCC_CFGR_HPRE_DIV1 /* HCLK = 72 MHz */
bogdanm 0:9b334a45a8ff 395 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 72 MHz */
bogdanm 0:9b334a45a8ff 396 | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 36 MHz */
bogdanm 0:9b334a45a8ff 397 /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 /* Enable PLL */
bogdanm 0:9b334a45a8ff 400 RCC->CR |= RCC_CR_PLLON;
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 403 while((RCC->CR & RCC_CR_PLLRDY) == 0)
bogdanm 0:9b334a45a8ff 404 {
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Select PLL as system clock source */
bogdanm 0:9b334a45a8ff 408 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
bogdanm 0:9b334a45a8ff 409 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /* Wait till PLL is used as system clock source */
bogdanm 0:9b334a45a8ff 412 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
bogdanm 0:9b334a45a8ff 413 {
bogdanm 0:9b334a45a8ff 414 }
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 return 1; // OK
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418 else
bogdanm 0:9b334a45a8ff 419 {
bogdanm 0:9b334a45a8ff 420 return 0; // FAIL
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422 }
bogdanm 0:9b334a45a8ff 423 #endif
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /******************************************************************************/
bogdanm 0:9b334a45a8ff 426 /* PLL (clocked by HSI) used as System clock source */
bogdanm 0:9b334a45a8ff 427 /******************************************************************************/
bogdanm 0:9b334a45a8ff 428 uint8_t SetSysClock_PLL_HSI(void)
bogdanm 0:9b334a45a8ff 429 {
bogdanm 0:9b334a45a8ff 430 /* At this stage the HSI is already enabled and used as System clock source */
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Enable prefetch buffer and set flash latency
bogdanm 0:9b334a45a8ff 433 0WS for 0 < SYSCLK <= 24 MHz
bogdanm 0:9b334a45a8ff 434 1WS for 24 < SYSCLK <= 48 MHz
bogdanm 0:9b334a45a8ff 435 2WS for 48 < SYSCLK <= 72 MHz */
bogdanm 0:9b334a45a8ff 436 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */
bogdanm 0:9b334a45a8ff 439 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
bogdanm 0:9b334a45a8ff 440 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16
bogdanm 0:9b334a45a8ff 441 | RCC_CFGR_HPRE_DIV1 /* HCLK = 64 MHz */
bogdanm 0:9b334a45a8ff 442 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 64 MHz */
bogdanm 0:9b334a45a8ff 443 | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 32 MHz */
bogdanm 0:9b334a45a8ff 444 /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Enable PLL */
bogdanm 0:9b334a45a8ff 447 RCC->CR |= RCC_CR_PLLON;
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 450 while((RCC->CR & RCC_CR_PLLRDY) == 0)
bogdanm 0:9b334a45a8ff 451 {
bogdanm 0:9b334a45a8ff 452 }
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 /* Select PLL as system clock source */
bogdanm 0:9b334a45a8ff 455 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
bogdanm 0:9b334a45a8ff 456 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /* Wait till PLL is used as system clock source */
bogdanm 0:9b334a45a8ff 459 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
bogdanm 0:9b334a45a8ff 460 {
bogdanm 0:9b334a45a8ff 461 }
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 return 1; // OK
bogdanm 0:9b334a45a8ff 464 }
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /**
bogdanm 0:9b334a45a8ff 467 * @}
bogdanm 0:9b334a45a8ff 468 */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /**
bogdanm 0:9b334a45a8ff 471 * @}
bogdanm 0:9b334a45a8ff 472 */
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /**
bogdanm 0:9b334a45a8ff 475 * @}
bogdanm 0:9b334a45a8ff 476 */
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/