mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_uart.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief UART HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ===============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ===============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The UART HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
<> 144:ef7eb2e8f9f7 23 (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
<> 144:ef7eb2e8f9f7 24 (++) Enable the USARTx interface clock.
<> 144:ef7eb2e8f9f7 25 (++) UART pins configuration:
<> 144:ef7eb2e8f9f7 26 (+++) Enable the clock for the UART GPIOs.
<> 144:ef7eb2e8f9f7 27 (+++) Configure these UART pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 28 (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
<> 144:ef7eb2e8f9f7 29 and HAL_UART_Receive_IT() APIs):
<> 144:ef7eb2e8f9f7 30 (+++) Configure the USARTx interrupt priority.
<> 144:ef7eb2e8f9f7 31 (+++) Enable the NVIC USART IRQ handle.
<> 144:ef7eb2e8f9f7 32 (++) UART interrupts handling:
<> 144:ef7eb2e8f9f7 33 -@@- The specific UART interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 34 RXNE interrupt and Error Interrupts) are managed using the macros
<> 144:ef7eb2e8f9f7 35 __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
<> 144:ef7eb2e8f9f7 36 (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
<> 144:ef7eb2e8f9f7 37 and HAL_UART_Receive_DMA() APIs):
<> 144:ef7eb2e8f9f7 38 (+++) Declare a DMA handle structure for the Tx/Rx channel.
<> 144:ef7eb2e8f9f7 39 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 40 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 41 (+++) Configure the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 42 (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 43 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
<> 144:ef7eb2e8f9f7 46 flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
<> 144:ef7eb2e8f9f7 49 in the huart handle AdvancedInit structure.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) For the UART asynchronous mode, initialize the UART registers by calling
<> 144:ef7eb2e8f9f7 52 the HAL_UART_Init() API.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 (#) For the UART Half duplex mode, initialize the UART registers by calling
<> 144:ef7eb2e8f9f7 55 the HAL_HalfDuplex_Init() API.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (#) For the UART Multiprocessor mode, initialize the UART registers
<> 144:ef7eb2e8f9f7 58 by calling the HAL_MultiProcessor_Init() API.
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
<> 144:ef7eb2e8f9f7 61 by calling the HAL_RS485Ex_Init() API.
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 [..]
<> 144:ef7eb2e8f9f7 64 (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
<> 144:ef7eb2e8f9f7 65 also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
<> 144:ef7eb2e8f9f7 66 calling the customized HAL_UART_MspInit() API.
<> 144:ef7eb2e8f9f7 67
<> 156:95d6b41a828b 68 [..]
<> 156:95d6b41a828b 69 [..] Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 72 =================================
<> 144:ef7eb2e8f9f7 73 [..]
<> 144:ef7eb2e8f9f7 74 (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
<> 144:ef7eb2e8f9f7 75 (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 78 ===================================
<> 144:ef7eb2e8f9f7 79 [..]
<> 144:ef7eb2e8f9f7 80 (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
<> 144:ef7eb2e8f9f7 81 (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 84 add his own code by customization of function pointer HAL_UART_TxCpltCallback
<> 144:ef7eb2e8f9f7 85 (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
<> 144:ef7eb2e8f9f7 86 (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 87 add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 88 (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 89 add his own code by customization of function pointer HAL_UART_RxCpltCallback
<> 144:ef7eb2e8f9f7 90 (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 91 add his own code by customization of function pointer HAL_UART_ErrorCallback
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 94 ==============================
<> 144:ef7eb2e8f9f7 95 [..]
<> 144:ef7eb2e8f9f7 96 (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
<> 144:ef7eb2e8f9f7 97 (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 98 add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 99 (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 100 add his own code by customization of function pointer HAL_UART_TxCpltCallback
<> 144:ef7eb2e8f9f7 101 (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
<> 144:ef7eb2e8f9f7 102 (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 103 add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 104 (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 105 add his own code by customization of function pointer HAL_UART_RxCpltCallback
<> 144:ef7eb2e8f9f7 106 (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 107 add his own code by customization of function pointer HAL_UART_ErrorCallback
<> 144:ef7eb2e8f9f7 108 (+) Pause the DMA Transfer using HAL_UART_DMAPause()
<> 144:ef7eb2e8f9f7 109 (+) Resume the DMA Transfer using HAL_UART_DMAResume()
<> 144:ef7eb2e8f9f7 110 (+) Stop the DMA Transfer using HAL_UART_DMAStop()
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 *** UART HAL driver macros list ***
<> 144:ef7eb2e8f9f7 113 =============================================
<> 144:ef7eb2e8f9f7 114 [..]
<> 144:ef7eb2e8f9f7 115 Below the list of most used macros in UART HAL driver.
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 (+) __HAL_UART_ENABLE: Enable the UART peripheral
<> 144:ef7eb2e8f9f7 118 (+) __HAL_UART_DISABLE: Disable the UART peripheral
<> 144:ef7eb2e8f9f7 119 (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
<> 144:ef7eb2e8f9f7 120 (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
<> 144:ef7eb2e8f9f7 121 (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
<> 144:ef7eb2e8f9f7 122 (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 [..]
<> 144:ef7eb2e8f9f7 125 (@) You can refer to the UART HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 @endverbatim
<> 144:ef7eb2e8f9f7 128 ******************************************************************************
<> 144:ef7eb2e8f9f7 129 * @attention
<> 144:ef7eb2e8f9f7 130 *
<> 144:ef7eb2e8f9f7 131 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 134 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 135 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 136 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 137 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 138 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 139 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 140 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 141 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 142 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 143 *
<> 144:ef7eb2e8f9f7 144 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 145 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 146 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 147 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 148 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 149 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 150 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 151 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 152 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 153 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 154 *
<> 144:ef7eb2e8f9f7 155 ******************************************************************************
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @defgroup UART UART
<> 144:ef7eb2e8f9f7 166 * @brief HAL UART module driver
<> 144:ef7eb2e8f9f7 167 * @{
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #ifdef HAL_UART_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 173 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 174 /** @defgroup UART_Private_Constants UART Private Constants
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
<> 144:ef7eb2e8f9f7 178 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @}
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 184 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 185 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 186 /** @addtogroup UART_Private_Functions
<> 144:ef7eb2e8f9f7 187 * @{
<> 144:ef7eb2e8f9f7 188 */
<> 156:95d6b41a828b 189 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 190 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 191 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 192 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 193 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 194 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 195 static void UART_DMAError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 196 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 197 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 198 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 199 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 200 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 201 HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 202 HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 203 HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @}
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /** @defgroup UART_Exported_Functions UART Exported Functions
<> 144:ef7eb2e8f9f7 211 * @{
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 215 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 216 *
<> 144:ef7eb2e8f9f7 217 @verbatim
<> 144:ef7eb2e8f9f7 218 ===============================================================================
<> 144:ef7eb2e8f9f7 219 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 220 ===============================================================================
<> 144:ef7eb2e8f9f7 221 [..]
<> 144:ef7eb2e8f9f7 222 This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
<> 144:ef7eb2e8f9f7 223 in asynchronous mode.
<> 144:ef7eb2e8f9f7 224 (+) For the asynchronous mode the parameters below can be configured:
<> 144:ef7eb2e8f9f7 225 (++) Baud Rate
<> 144:ef7eb2e8f9f7 226 (++) Word Length
<> 144:ef7eb2e8f9f7 227 (++) Stop Bit
<> 144:ef7eb2e8f9f7 228 (++) Parity
<> 144:ef7eb2e8f9f7 229 (++) Hardware flow control
<> 144:ef7eb2e8f9f7 230 (++) Receiver/transmitter modes
<> 144:ef7eb2e8f9f7 231 (++) Over Sampling Method
<> 144:ef7eb2e8f9f7 232 (++) One-Bit Sampling Method
<> 144:ef7eb2e8f9f7 233 (+) For the asynchronous mode, the following advanced features can be configured as well:
<> 144:ef7eb2e8f9f7 234 (++) TX and/or RX pin level inversion
<> 144:ef7eb2e8f9f7 235 (++) data logical level inversion
<> 144:ef7eb2e8f9f7 236 (++) RX and TX pins swap
<> 144:ef7eb2e8f9f7 237 (++) RX overrun detection disabling
<> 144:ef7eb2e8f9f7 238 (++) DMA disabling on RX error
<> 144:ef7eb2e8f9f7 239 (++) MSB first on communication line
<> 144:ef7eb2e8f9f7 240 (++) auto Baud rate detection
<> 144:ef7eb2e8f9f7 241 [..]
<> 144:ef7eb2e8f9f7 242 The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init()
<> 144:ef7eb2e8f9f7 243 API follow respectively the UART asynchronous, UART Half duplex and multiprocessor mode
<> 144:ef7eb2e8f9f7 244 configuration procedures (details for the procedures are available in reference manual).
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 @endverbatim
<> 144:ef7eb2e8f9f7 247 * @{
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /*
<> 144:ef7eb2e8f9f7 251 Additional Table: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 252 in the data register is transmitted but is changed by the parity bit.
<> 144:ef7eb2e8f9f7 253 According to device capability (support or not of 7-bit word length),
<> 144:ef7eb2e8f9f7 254 frame length is either defined by the M bit (8-bits or 9-bits)
<> 144:ef7eb2e8f9f7 255 or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
<> 144:ef7eb2e8f9f7 256 Possible UART frame formats are as listed in the following table:
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 Table 1. UART frame format.
<> 144:ef7eb2e8f9f7 259 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 260 | M bit | PCE bit | UART frame |
<> 144:ef7eb2e8f9f7 261 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 262 | 0 | 0 | | SB | 8-bit data | STB | |
<> 144:ef7eb2e8f9f7 263 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 264 | 0 | 1 | | SB | 7-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 265 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 266 | 1 | 0 | | SB | 9-bit data | STB | |
<> 144:ef7eb2e8f9f7 267 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 268 | 1 | 1 | | SB | 8-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 269 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 270 | M1 bit | M0 bit | PCE bit | UART frame |
<> 144:ef7eb2e8f9f7 271 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 272 | 0 | 0 | 0 | | SB | 8 bit data | STB | |
<> 144:ef7eb2e8f9f7 273 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 274 | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 275 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 276 | 0 | 1 | 0 | | SB | 9 bit data | STB | |
<> 144:ef7eb2e8f9f7 277 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 278 | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 279 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 280 | 1 | 0 | 0 | | SB | 7 bit data | STB | |
<> 144:ef7eb2e8f9f7 281 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 282 | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 283 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @brief Initialize the UART mode according to the specified
<> 156:95d6b41a828b 289 * parameters in the UART_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 290 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 291 * @retval HAL status
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 /* Check the UART handle allocation */
<> 144:ef7eb2e8f9f7 296 if(huart == NULL)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Check the parameters */
<> 144:ef7eb2e8f9f7 304 assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306 else
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 /* Check the parameters */
<> 144:ef7eb2e8f9f7 309 assert_param(IS_UART_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 if(huart->gState == HAL_UART_STATE_RESET)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 315 huart->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 318 HAL_UART_MspInit(huart);
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 324 __HAL_UART_DISABLE(huart);
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Set the UART Communication parameters */
<> 144:ef7eb2e8f9f7 327 if (UART_SetConfig(huart) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 UART_AdvFeatureConfig(huart);
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* In asynchronous mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 338 - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 339 - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
<> 144:ef7eb2e8f9f7 340 #if defined (USART_CR2_LINEN)
<> 156:95d6b41a828b 341 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
<> 144:ef7eb2e8f9f7 342 #else
<> 156:95d6b41a828b 343 CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 344 #endif
<> 144:ef7eb2e8f9f7 345 #if defined (USART_CR3_SCEN)
<> 144:ef7eb2e8f9f7 346 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 347 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
<> 144:ef7eb2e8f9f7 348 #else
<> 156:95d6b41a828b 349 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
<> 144:ef7eb2e8f9f7 350 #endif
<> 144:ef7eb2e8f9f7 351 #else
<> 144:ef7eb2e8f9f7 352 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 353 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
<> 144:ef7eb2e8f9f7 354 #else
<> 156:95d6b41a828b 355 CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 356 #endif
<> 144:ef7eb2e8f9f7 357 #endif
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 360 __HAL_UART_ENABLE(huart);
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 363 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @brief Initialize the half-duplex mode according to the specified
<> 156:95d6b41a828b 368 * parameters in the UART_InitTypeDef and creates the associated handle.
<> 144:ef7eb2e8f9f7 369 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 370 * @retval HAL status
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 373 {
<> 144:ef7eb2e8f9f7 374 /* Check the UART handle allocation */
<> 144:ef7eb2e8f9f7 375 if(huart == NULL)
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Check UART instance */
<> 144:ef7eb2e8f9f7 381 assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 if(huart->gState == HAL_UART_STATE_RESET)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 386 huart->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 389 HAL_UART_MspInit(huart);
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 395 __HAL_UART_DISABLE(huart);
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Set the UART Communication parameters */
<> 144:ef7eb2e8f9f7 398 if (UART_SetConfig(huart) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 UART_AdvFeatureConfig(huart);
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* In half-duplex mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 409 - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 410 - SCEN (if Smartcard is supported), and IREN (if IrDA is supported) bits in the USART_CR3 register. */
<> 144:ef7eb2e8f9f7 411 #if defined (USART_CR2_LINEN)
<> 156:95d6b41a828b 412 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
<> 144:ef7eb2e8f9f7 413 #else
<> 156:95d6b41a828b 414 CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 415 #endif
<> 144:ef7eb2e8f9f7 416 #if defined (USART_CR3_SCEN)
<> 144:ef7eb2e8f9f7 417 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 418 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
<> 144:ef7eb2e8f9f7 419 #else
<> 156:95d6b41a828b 420 CLEAR_BIT(huart->Instance->CR3, USART_CR3_SCEN);
<> 144:ef7eb2e8f9f7 421 #endif
<> 144:ef7eb2e8f9f7 422 #else
<> 144:ef7eb2e8f9f7 423 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 424 CLEAR_BIT(huart->Instance->CR3, USART_CR3_IREN);
<> 144:ef7eb2e8f9f7 425 #endif
<> 144:ef7eb2e8f9f7 426 #endif
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
<> 156:95d6b41a828b 429 SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 432 __HAL_UART_ENABLE(huart);
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 435 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /**
<> 144:ef7eb2e8f9f7 440 * @brief Initialize the multiprocessor mode according to the specified
<> 156:95d6b41a828b 441 * parameters in the UART_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 442 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 443 * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
<> 144:ef7eb2e8f9f7 444 * @param WakeUpMethod: specifies the UART wakeup method.
<> 144:ef7eb2e8f9f7 445 * This parameter can be one of the following values:
<> 156:95d6b41a828b 446 * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
<> 156:95d6b41a828b 447 * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
<> 144:ef7eb2e8f9f7 448 * @note If the user resorts to idle line detection wake up, the Address parameter
<> 144:ef7eb2e8f9f7 449 * is useless and ignored by the initialization function.
<> 144:ef7eb2e8f9f7 450 * @note If the user resorts to address mark wake up, the address length detection
<> 144:ef7eb2e8f9f7 451 * is configured by default to 4 bits only. For the UART to be able to
<> 144:ef7eb2e8f9f7 452 * manage 6-, 7- or 8-bit long addresses detection, the API
<> 144:ef7eb2e8f9f7 453 * HAL_MultiProcessorEx_AddressLength_Set() must be called after
<> 144:ef7eb2e8f9f7 454 * HAL_MultiProcessor_Init().
<> 144:ef7eb2e8f9f7 455 * @retval HAL status
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 /* Check the UART handle allocation */
<> 144:ef7eb2e8f9f7 460 if(huart == NULL)
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Check the wake up method parameter */
<> 144:ef7eb2e8f9f7 466 assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 if(huart->gState == HAL_UART_STATE_RESET)
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 471 huart->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 474 HAL_UART_MspInit(huart);
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 480 __HAL_UART_DISABLE(huart);
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Set the UART Communication parameters */
<> 144:ef7eb2e8f9f7 483 if (UART_SetConfig(huart) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 UART_AdvFeatureConfig(huart);
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* In multiprocessor mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 494 - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 495 - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
<> 144:ef7eb2e8f9f7 496 #if defined (USART_CR2_LINEN)
<> 156:95d6b41a828b 497 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
<> 144:ef7eb2e8f9f7 498 #else
<> 156:95d6b41a828b 499 CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 500 #endif
<> 144:ef7eb2e8f9f7 501 #if defined (USART_CR3_SCEN)
<> 144:ef7eb2e8f9f7 502 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 503 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
<> 144:ef7eb2e8f9f7 504 #else
<> 156:95d6b41a828b 505 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
<> 144:ef7eb2e8f9f7 506 #endif
<> 144:ef7eb2e8f9f7 507 #else
<> 144:ef7eb2e8f9f7 508 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 509 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
<> 144:ef7eb2e8f9f7 510 #else
<> 156:95d6b41a828b 511 CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 512 #endif
<> 144:ef7eb2e8f9f7 513 #endif
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 /* If address mark wake up method is chosen, set the USART address node */
<> 144:ef7eb2e8f9f7 518 MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Set the wake up method by setting the WAKE bit in the CR1 register */
<> 144:ef7eb2e8f9f7 522 MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 525 __HAL_UART_ENABLE(huart);
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 528 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 156:95d6b41a828b 531
<> 144:ef7eb2e8f9f7 532 /**
<> 144:ef7eb2e8f9f7 533 * @brief DeInitialize the UART peripheral.
<> 144:ef7eb2e8f9f7 534 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 535 * @retval HAL status
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 /* Check the UART handle allocation */
<> 144:ef7eb2e8f9f7 540 if(huart == NULL)
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Check the parameters */
<> 144:ef7eb2e8f9f7 546 assert_param(IS_UART_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 551 __HAL_UART_DISABLE(huart);
<> 144:ef7eb2e8f9f7 552
<> 156:95d6b41a828b 553 huart->Instance->CR1 = 0x0U;
<> 156:95d6b41a828b 554 huart->Instance->CR2 = 0x0U;
<> 156:95d6b41a828b 555 huart->Instance->CR3 = 0x0U;
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 558 HAL_UART_MspDeInit(huart);
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 561 huart->gState = HAL_UART_STATE_RESET;
<> 156:95d6b41a828b 562 huart->RxState = HAL_UART_STATE_RESET;
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Process Unlock */
<> 144:ef7eb2e8f9f7 565 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 return HAL_OK;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @brief Initialize the UART MSP.
<> 144:ef7eb2e8f9f7 572 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 573 * @retval None
<> 144:ef7eb2e8f9f7 574 */
<> 156:95d6b41a828b 575 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 578 UNUSED(huart);
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 581 the HAL_UART_MspInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /**
<> 144:ef7eb2e8f9f7 586 * @brief DeInitialize the UART MSP.
<> 144:ef7eb2e8f9f7 587 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 588 * @retval None
<> 144:ef7eb2e8f9f7 589 */
<> 156:95d6b41a828b 590 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 593 UNUSED(huart);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 596 the HAL_UART_MspDeInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /**
<> 144:ef7eb2e8f9f7 601 * @}
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
<> 156:95d6b41a828b 605 * @brief UART Transmit/Receive functions
<> 144:ef7eb2e8f9f7 606 *
<> 144:ef7eb2e8f9f7 607 @verbatim
<> 144:ef7eb2e8f9f7 608 ===============================================================================
<> 144:ef7eb2e8f9f7 609 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 610 ===============================================================================
<> 144:ef7eb2e8f9f7 611 This subsection provides a set of functions allowing to manage the UART asynchronous
<> 144:ef7eb2e8f9f7 612 and Half duplex data transfers.
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 (#) There are two mode of transfer:
<> 156:95d6b41a828b 615 (++) Blocking mode: The communication is performed in polling mode.
<> 156:95d6b41a828b 616 The HAL status of all data processing is returned by the same function
<> 156:95d6b41a828b 617 after finishing transfer.
<> 156:95d6b41a828b 618 (++) Non-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 619 or DMA, These API's return the HAL status.
<> 144:ef7eb2e8f9f7 620 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 621 dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 622 using DMA mode.
<> 144:ef7eb2e8f9f7 623 The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 624 will be executed respectively at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 625 The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 (#) Blocking mode API's are :
<> 156:95d6b41a828b 628 (++) HAL_UART_Transmit()
<> 156:95d6b41a828b 629 (++) HAL_UART_Receive()
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 (#) Non-Blocking mode API's with Interrupt are :
<> 156:95d6b41a828b 632 (++) HAL_UART_Transmit_IT()
<> 156:95d6b41a828b 633 (++) HAL_UART_Receive_IT()
<> 156:95d6b41a828b 634 (++) HAL_UART_IRQHandler()
<> 156:95d6b41a828b 635
<> 156:95d6b41a828b 636 (#) Non-Blocking mode API's with DMA are :
<> 156:95d6b41a828b 637 (++) HAL_UART_Transmit_DMA()
<> 156:95d6b41a828b 638 (++) HAL_UART_Receive_DMA()
<> 156:95d6b41a828b 639 (++) HAL_UART_DMAPause()
<> 156:95d6b41a828b 640 (++) HAL_UART_DMAResume()
<> 156:95d6b41a828b 641 (++) HAL_UART_DMAStop()
<> 156:95d6b41a828b 642
<> 156:95d6b41a828b 643 (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
<> 156:95d6b41a828b 644 (++) HAL_UART_TxHalfCpltCallback()
<> 156:95d6b41a828b 645 (++) HAL_UART_TxCpltCallback()
<> 156:95d6b41a828b 646 (++) HAL_UART_RxHalfCpltCallback()
<> 156:95d6b41a828b 647 (++) HAL_UART_RxCpltCallback()
<> 156:95d6b41a828b 648 (++) HAL_UART_ErrorCallback()
<> 156:95d6b41a828b 649
<> 156:95d6b41a828b 650 (#) Non-Blocking mode transfers could be aborted using Abort API's :
<> 156:95d6b41a828b 651 (++) HAL_UART_Abort()
<> 156:95d6b41a828b 652 (++) HAL_UART_AbortTransmit()
<> 156:95d6b41a828b 653 (++) HAL_UART_AbortReceive()
<> 156:95d6b41a828b 654 (++) HAL_UART_Abort_IT()
<> 156:95d6b41a828b 655 (++) HAL_UART_AbortTransmit_IT()
<> 156:95d6b41a828b 656 (++) HAL_UART_AbortReceive_IT()
<> 156:95d6b41a828b 657
<> 156:95d6b41a828b 658 (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
<> 156:95d6b41a828b 659 (++) HAL_UART_AbortCpltCallback()
<> 156:95d6b41a828b 660 (++) HAL_UART_AbortTransmitCpltCallback()
<> 156:95d6b41a828b 661 (++) HAL_UART_AbortReceiveCpltCallback()
<> 156:95d6b41a828b 662
<> 156:95d6b41a828b 663 (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
<> 156:95d6b41a828b 664 Errors are handled as follows :
<> 156:95d6b41a828b 665 (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
<> 156:95d6b41a828b 666 to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
<> 156:95d6b41a828b 667 Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
<> 156:95d6b41a828b 668 and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
<> 156:95d6b41a828b 669 If user wants to abort it, Abort services should be called by user.
<> 156:95d6b41a828b 670 (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
<> 156:95d6b41a828b 671 This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
<> 156:95d6b41a828b 672 Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 -@- In the Half duplex communication, it is forbidden to run the transmit
<> 144:ef7eb2e8f9f7 675 and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 @endverbatim
<> 144:ef7eb2e8f9f7 678 * @{
<> 144:ef7eb2e8f9f7 679 */
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @brief Send an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 683 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 684 * @param pData: Pointer to data buffer.
<> 144:ef7eb2e8f9f7 685 * @param Size: Amount of data to be sent.
<> 144:ef7eb2e8f9f7 686 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 687 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 688 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 689 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 690 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 691 * @retval HAL status
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 694 {
<> 156:95d6b41a828b 695 uint16_t* tmp;
<> 156:95d6b41a828b 696 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 699 if(huart->gState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 700 {
<> 156:95d6b41a828b 701 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 707 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 708 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 709 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 710 {
<> 156:95d6b41a828b 711 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /* Process Locked */
<> 144:ef7eb2e8f9f7 718 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 721 huart->gState = HAL_UART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 722
<> 156:95d6b41a828b 723 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 724 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 725
<> 144:ef7eb2e8f9f7 726 huart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 727 huart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 728 while(huart->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 huart->TxXferCount--;
<> 156:95d6b41a828b 731 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 tmp = (uint16_t*) pData;
<> 156:95d6b41a828b 738 huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 739 pData += 2;
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741 else
<> 144:ef7eb2e8f9f7 742 {
<> 156:95d6b41a828b 743 huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 744 }
<> 144:ef7eb2e8f9f7 745 }
<> 156:95d6b41a828b 746 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 747 {
<> 144:ef7eb2e8f9f7 748 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 749 }
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* At end of Tx process, restore huart->gState to Ready */
<> 144:ef7eb2e8f9f7 752 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 755 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 return HAL_OK;
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759 else
<> 144:ef7eb2e8f9f7 760 {
<> 144:ef7eb2e8f9f7 761 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763 }
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /**
<> 144:ef7eb2e8f9f7 766 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 767 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 768 * @param pData: pointer to data buffer.
<> 144:ef7eb2e8f9f7 769 * @param Size: amount of data to be received.
<> 144:ef7eb2e8f9f7 770 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 771 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 772 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 773 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 774 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 775 * @retval HAL status
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 780 uint16_t uhMask;
<> 156:95d6b41a828b 781 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 784 if(huart->RxState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 785 {
<> 156:95d6b41a828b 786 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 792 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 793 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 794 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 795 {
<> 156:95d6b41a828b 796 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Process Locked */
<> 144:ef7eb2e8f9f7 803 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 806 huart->RxState = HAL_UART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 807
<> 156:95d6b41a828b 808 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 809 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 810
<> 144:ef7eb2e8f9f7 811 huart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 812 huart->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Computation of UART mask to apply to RDR register */
<> 144:ef7eb2e8f9f7 815 UART_MASK_COMPUTATION(huart);
<> 144:ef7eb2e8f9f7 816 uhMask = huart->Mask;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* as long as data have to be received */
<> 156:95d6b41a828b 819 while(huart->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 huart->RxXferCount--;
<> 156:95d6b41a828b 822 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 827 {
<> 144:ef7eb2e8f9f7 828 tmp = (uint16_t*) pData ;
<> 144:ef7eb2e8f9f7 829 *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
<> 156:95d6b41a828b 830 pData +=2U;
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832 else
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* At end of Rx process, restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 839 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 842 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 return HAL_OK;
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846 else
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /**
<> 144:ef7eb2e8f9f7 853 * @brief Send an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 854 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 855 * @param pData: pointer to data buffer.
<> 144:ef7eb2e8f9f7 856 * @param Size: amount of data to be sent.
<> 144:ef7eb2e8f9f7 857 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 858 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 859 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 860 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 861 * @retval HAL status
<> 144:ef7eb2e8f9f7 862 */
<> 144:ef7eb2e8f9f7 863 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 866 if(huart->gState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 867 {
<> 156:95d6b41a828b 868 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 869 {
<> 144:ef7eb2e8f9f7 870 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 874 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 875 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 876 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 877 {
<> 156:95d6b41a828b 878 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /* Process Locked */
<> 144:ef7eb2e8f9f7 885 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 huart->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 888 huart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 889 huart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 892 huart->gState = HAL_UART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 895 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Enable the UART Transmit Data Register Empty Interrupt */
<> 156:95d6b41a828b 898 SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 return HAL_OK;
<> 144:ef7eb2e8f9f7 901 }
<> 144:ef7eb2e8f9f7 902 else
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 905 }
<> 144:ef7eb2e8f9f7 906 }
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /**
<> 144:ef7eb2e8f9f7 909 * @brief Receive an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 910 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 911 * @param pData: pointer to data buffer.
<> 144:ef7eb2e8f9f7 912 * @param Size: amount of data to be received.
<> 144:ef7eb2e8f9f7 913 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 914 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 915 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 916 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 917 * @retval HAL status
<> 144:ef7eb2e8f9f7 918 */
<> 144:ef7eb2e8f9f7 919 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 920 {
<> 144:ef7eb2e8f9f7 921 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 922 if(huart->RxState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 923 {
<> 156:95d6b41a828b 924 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 925 {
<> 144:ef7eb2e8f9f7 926 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 930 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 931 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 932 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 933 {
<> 156:95d6b41a828b 934 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 935 {
<> 144:ef7eb2e8f9f7 936 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938 }
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /* Process Locked */
<> 144:ef7eb2e8f9f7 941 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 huart->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 944 huart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 945 huart->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Computation of UART mask to apply to RDR register */
<> 144:ef7eb2e8f9f7 948 UART_MASK_COMPUTATION(huart);
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 951 huart->RxState = HAL_UART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 952
<> 156:95d6b41a828b 953 /* Process Unlocked */
<> 156:95d6b41a828b 954 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 957 SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 958
<> 156:95d6b41a828b 959 /* Enable the UART Parity Error and Data Register not empty Interrupts */
<> 156:95d6b41a828b 960 SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 return HAL_OK;
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964 else
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /**
<> 144:ef7eb2e8f9f7 971 * @brief Send an amount of data in DMA mode.
<> 144:ef7eb2e8f9f7 972 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 973 * @param pData: pointer to data buffer.
<> 144:ef7eb2e8f9f7 974 * @param Size: amount of data to be sent.
<> 144:ef7eb2e8f9f7 975 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 976 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 977 * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 978 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 979 * @retval HAL status
<> 144:ef7eb2e8f9f7 980 */
<> 144:ef7eb2e8f9f7 981 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 982 {
<> 144:ef7eb2e8f9f7 983 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 984 if(huart->gState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 985 {
<> 156:95d6b41a828b 986 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 987 {
<> 144:ef7eb2e8f9f7 988 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 989 }
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 992 should be aligned on a u16 frontier, as data copy into TDR will be
<> 144:ef7eb2e8f9f7 993 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 994 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 995 {
<> 156:95d6b41a828b 996 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 997 {
<> 144:ef7eb2e8f9f7 998 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* Process Locked */
<> 144:ef7eb2e8f9f7 1003 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 huart->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1006 huart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1007 huart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1010 huart->gState = HAL_UART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /* Set the UART DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1013 huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /* Set the UART DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1016 huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1019 huart->hdmatx->XferErrorCallback = UART_DMAError;
<> 144:ef7eb2e8f9f7 1020
<> 156:95d6b41a828b 1021 /* Set the DMA abort callback */
<> 156:95d6b41a828b 1022 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1023
<> 144:ef7eb2e8f9f7 1024 /* Enable the UART transmit DMA channel */
<> 156:95d6b41a828b 1025 HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Clear the TC flag in the ICR register */
<> 144:ef7eb2e8f9f7 1028 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
<> 144:ef7eb2e8f9f7 1029
<> 156:95d6b41a828b 1030 /* Process Unlocked */
<> 156:95d6b41a828b 1031 __HAL_UNLOCK(huart);
<> 156:95d6b41a828b 1032
<> 144:ef7eb2e8f9f7 1033 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 1034 in the UART CR3 register */
<> 156:95d6b41a828b 1035 SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 return HAL_OK;
<> 144:ef7eb2e8f9f7 1038 }
<> 144:ef7eb2e8f9f7 1039 else
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /**
<> 144:ef7eb2e8f9f7 1046 * @brief Receive an amount of data in DMA mode.
<> 144:ef7eb2e8f9f7 1047 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1048 * @param pData: pointer to data buffer.
<> 144:ef7eb2e8f9f7 1049 * @param Size: amount of data to be received.
<> 144:ef7eb2e8f9f7 1050 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 1051 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 1052 * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 1053 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 1054 * @retval HAL status
<> 144:ef7eb2e8f9f7 1055 */
<> 144:ef7eb2e8f9f7 1056 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1057 {
<> 144:ef7eb2e8f9f7 1058 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 1059 if(huart->RxState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 1060 {
<> 156:95d6b41a828b 1061 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1062 {
<> 144:ef7eb2e8f9f7 1063 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1064 }
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 1067 should be aligned on a u16 frontier, as data copy from RDR will be
<> 144:ef7eb2e8f9f7 1068 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 1069 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1070 {
<> 156:95d6b41a828b 1071 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 1072 {
<> 144:ef7eb2e8f9f7 1073 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075 }
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* Process Locked */
<> 144:ef7eb2e8f9f7 1078 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 huart->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1081 huart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1084 huart->RxState = HAL_UART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /* Set the UART DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1087 huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /* Set the UART DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1090 huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1093 huart->hdmarx->XferErrorCallback = UART_DMAError;
<> 144:ef7eb2e8f9f7 1094
<> 156:95d6b41a828b 1095 /* Set the DMA abort callback */
<> 156:95d6b41a828b 1096 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1097
<> 144:ef7eb2e8f9f7 1098 /* Enable the DMA channel */
<> 156:95d6b41a828b 1099 HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
<> 156:95d6b41a828b 1100
<> 156:95d6b41a828b 1101 /* Process Unlocked */
<> 156:95d6b41a828b 1102 __HAL_UNLOCK(huart);
<> 156:95d6b41a828b 1103
<> 156:95d6b41a828b 1104 /* Enable the UART Parity Error Interrupt */
<> 156:95d6b41a828b 1105 SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1106
<> 156:95d6b41a828b 1107 /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 1108 SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 1111 in the UART CR3 register */
<> 156:95d6b41a828b 1112 SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 return HAL_OK;
<> 144:ef7eb2e8f9f7 1115 }
<> 144:ef7eb2e8f9f7 1116 else
<> 144:ef7eb2e8f9f7 1117 {
<> 144:ef7eb2e8f9f7 1118 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1119 }
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 /**
<> 144:ef7eb2e8f9f7 1123 * @brief Pause the DMA Transfer.
<> 144:ef7eb2e8f9f7 1124 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1125 * @retval HAL status
<> 144:ef7eb2e8f9f7 1126 */
<> 144:ef7eb2e8f9f7 1127 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 /* Process Locked */
<> 144:ef7eb2e8f9f7 1130 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1131
<> 156:95d6b41a828b 1132 if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
<> 156:95d6b41a828b 1133 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
<> 144:ef7eb2e8f9f7 1134 {
<> 144:ef7eb2e8f9f7 1135 /* Disable the UART DMA Tx request */
<> 156:95d6b41a828b 1136 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1137 }
<> 156:95d6b41a828b 1138 if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
<> 156:95d6b41a828b 1139 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<> 144:ef7eb2e8f9f7 1140 {
<> 156:95d6b41a828b 1141 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1142 CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1143 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1144
<> 144:ef7eb2e8f9f7 1145 /* Disable the UART DMA Rx request */
<> 156:95d6b41a828b 1146 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1150 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 return HAL_OK;
<> 144:ef7eb2e8f9f7 1153 }
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /**
<> 144:ef7eb2e8f9f7 1156 * @brief Resume the DMA Transfer.
<> 144:ef7eb2e8f9f7 1157 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1158 * @retval HAL status
<> 144:ef7eb2e8f9f7 1159 */
<> 144:ef7eb2e8f9f7 1160 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1161 {
<> 144:ef7eb2e8f9f7 1162 /* Process Locked */
<> 144:ef7eb2e8f9f7 1163 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 if(huart->gState == HAL_UART_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1166 {
<> 144:ef7eb2e8f9f7 1167 /* Enable the UART DMA Tx request */
<> 156:95d6b41a828b 1168 SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1169 }
<> 144:ef7eb2e8f9f7 1170 if(huart->RxState == HAL_UART_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1171 {
<> 156:95d6b41a828b 1172 /* Clear the Overrun flag before resuming the Rx transfer */
<> 144:ef7eb2e8f9f7 1173 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
<> 144:ef7eb2e8f9f7 1174
<> 156:95d6b41a828b 1175 /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1176 SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1177 SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1178
<> 144:ef7eb2e8f9f7 1179 /* Enable the UART DMA Rx request */
<> 156:95d6b41a828b 1180 SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1181 }
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1184 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 return HAL_OK;
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /**
<> 144:ef7eb2e8f9f7 1190 * @brief Stop the DMA Transfer.
<> 144:ef7eb2e8f9f7 1191 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1192 * @retval HAL status
<> 144:ef7eb2e8f9f7 1193 */
<> 144:ef7eb2e8f9f7 1194 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 1197 to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
<> 156:95d6b41a828b 1198 HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
<> 156:95d6b41a828b 1199 indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
<> 156:95d6b41a828b 1200 interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
<> 156:95d6b41a828b 1201 the stream and the corresponding call back is executed. */
<> 156:95d6b41a828b 1202
<> 156:95d6b41a828b 1203 /* Stop UART DMA Tx request if ongoing */
<> 156:95d6b41a828b 1204 if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
<> 156:95d6b41a828b 1205 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
<> 156:95d6b41a828b 1206 {
<> 156:95d6b41a828b 1207 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1208
<> 156:95d6b41a828b 1209 /* Abort the UART DMA Tx channel */
<> 156:95d6b41a828b 1210 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1211 {
<> 156:95d6b41a828b 1212 HAL_DMA_Abort(huart->hdmatx);
<> 156:95d6b41a828b 1213 }
<> 156:95d6b41a828b 1214
<> 156:95d6b41a828b 1215 UART_EndTxTransfer(huart);
<> 156:95d6b41a828b 1216 }
<> 156:95d6b41a828b 1217
<> 156:95d6b41a828b 1218 /* Stop UART DMA Rx request if ongoing */
<> 156:95d6b41a828b 1219 if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
<> 156:95d6b41a828b 1220 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<> 156:95d6b41a828b 1221 {
<> 156:95d6b41a828b 1222 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1223
<> 156:95d6b41a828b 1224 /* Abort the UART DMA Rx channel */
<> 156:95d6b41a828b 1225 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1226 {
<> 156:95d6b41a828b 1227 HAL_DMA_Abort(huart->hdmarx);
<> 156:95d6b41a828b 1228 }
<> 156:95d6b41a828b 1229
<> 156:95d6b41a828b 1230 UART_EndRxTransfer(huart);
<> 156:95d6b41a828b 1231 }
<> 156:95d6b41a828b 1232
<> 156:95d6b41a828b 1233 return HAL_OK;
<> 156:95d6b41a828b 1234 }
<> 156:95d6b41a828b 1235
<> 156:95d6b41a828b 1236 /**
<> 156:95d6b41a828b 1237 * @brief Abort ongoing transfers (blocking mode).
<> 156:95d6b41a828b 1238 * @param huart UART handle.
<> 156:95d6b41a828b 1239 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1240 * This procedure performs following operations :
<> 156:95d6b41a828b 1241 * - Disable UART Interrupts (Tx and Rx)
<> 156:95d6b41a828b 1242 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1243 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1244 * - Set handle State to READY
<> 156:95d6b41a828b 1245 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1246 * @retval HAL status
<> 156:95d6b41a828b 1247 */
<> 156:95d6b41a828b 1248 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1249 {
<> 156:95d6b41a828b 1250 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1251 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1252 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1253
<> 156:95d6b41a828b 1254 /* Disable the UART DMA Tx request if enabled */
<> 156:95d6b41a828b 1255 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1256 {
<> 156:95d6b41a828b 1257 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1258
<> 156:95d6b41a828b 1259 /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1260 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1261 {
<> 156:95d6b41a828b 1262 /* Set the UART DMA Abort callback to Null.
<> 156:95d6b41a828b 1263 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1264 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1265
<> 156:95d6b41a828b 1266 HAL_DMA_Abort(huart->hdmatx);
<> 156:95d6b41a828b 1267 }
<> 156:95d6b41a828b 1268 }
<> 156:95d6b41a828b 1269
<> 156:95d6b41a828b 1270 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1271 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 144:ef7eb2e8f9f7 1272 {
<> 156:95d6b41a828b 1273 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1274
<> 156:95d6b41a828b 1275 /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1276 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1277 {
<> 156:95d6b41a828b 1278 /* Set the UART DMA Abort callback to Null.
<> 156:95d6b41a828b 1279 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1280 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1281
<> 156:95d6b41a828b 1282 HAL_DMA_Abort(huart->hdmarx);
<> 156:95d6b41a828b 1283 }
<> 144:ef7eb2e8f9f7 1284 }
<> 156:95d6b41a828b 1285
<> 156:95d6b41a828b 1286 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 1287 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1288 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1289
<> 156:95d6b41a828b 1290 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1291 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1292
<> 156:95d6b41a828b 1293 /* Restore huart->gState and huart->RxState to Ready */
<> 156:95d6b41a828b 1294 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1295 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1296
<> 156:95d6b41a828b 1297 /* Reset Handle ErrorCode to No Error */
<> 156:95d6b41a828b 1298 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 1299
<> 156:95d6b41a828b 1300 return HAL_OK;
<> 156:95d6b41a828b 1301 }
<> 156:95d6b41a828b 1302
<> 156:95d6b41a828b 1303 /**
<> 156:95d6b41a828b 1304 * @brief Abort ongoing Transmit transfer (blocking mode).
<> 156:95d6b41a828b 1305 * @param huart UART handle.
<> 156:95d6b41a828b 1306 * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1307 * This procedure performs following operations :
<> 156:95d6b41a828b 1308 * - Disable UART Interrupts (Tx)
<> 156:95d6b41a828b 1309 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1310 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1311 * - Set handle State to READY
<> 156:95d6b41a828b 1312 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1313 * @retval HAL status
<> 156:95d6b41a828b 1314 */
<> 156:95d6b41a828b 1315 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1316 {
<> 156:95d6b41a828b 1317 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 1318 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1319
<> 156:95d6b41a828b 1320 /* Disable the UART DMA Tx request if enabled */
<> 156:95d6b41a828b 1321 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 144:ef7eb2e8f9f7 1322 {
<> 156:95d6b41a828b 1323 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1324
<> 156:95d6b41a828b 1325 /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1326 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1327 {
<> 156:95d6b41a828b 1328 /* Set the UART DMA Abort callback to Null.
<> 156:95d6b41a828b 1329 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1330 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1331
<> 156:95d6b41a828b 1332 HAL_DMA_Abort(huart->hdmatx);
<> 156:95d6b41a828b 1333 }
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335
<> 156:95d6b41a828b 1336 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1337 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1338
<> 156:95d6b41a828b 1339 /* Restore huart->gState to Ready */
<> 144:ef7eb2e8f9f7 1340 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1341
<> 156:95d6b41a828b 1342 return HAL_OK;
<> 156:95d6b41a828b 1343 }
<> 156:95d6b41a828b 1344
<> 156:95d6b41a828b 1345 /**
<> 156:95d6b41a828b 1346 * @brief Abort ongoing Receive transfer (blocking mode).
<> 156:95d6b41a828b 1347 * @param huart UART handle.
<> 156:95d6b41a828b 1348 * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1349 * This procedure performs following operations :
<> 156:95d6b41a828b 1350 * - Disable UART Interrupts (Rx)
<> 156:95d6b41a828b 1351 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1352 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1353 * - Set handle State to READY
<> 156:95d6b41a828b 1354 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1355 * @retval HAL status
<> 156:95d6b41a828b 1356 */
<> 156:95d6b41a828b 1357 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1358 {
<> 156:95d6b41a828b 1359 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1360 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 1361 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1362
<> 156:95d6b41a828b 1363 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1364 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1365 {
<> 156:95d6b41a828b 1366 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1367
<> 156:95d6b41a828b 1368 /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1369 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1370 {
<> 156:95d6b41a828b 1371 /* Set the UART DMA Abort callback to Null.
<> 156:95d6b41a828b 1372 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1373 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1374
<> 156:95d6b41a828b 1375 HAL_DMA_Abort(huart->hdmarx);
<> 156:95d6b41a828b 1376 }
<> 156:95d6b41a828b 1377 }
<> 156:95d6b41a828b 1378
<> 156:95d6b41a828b 1379 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1380 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1381
<> 156:95d6b41a828b 1382 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1383 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1384
<> 156:95d6b41a828b 1385 /* Restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 1386 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 return HAL_OK;
<> 144:ef7eb2e8f9f7 1389 }
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /**
<> 156:95d6b41a828b 1392 * @brief Abort ongoing transfers (Interrupt mode).
<> 156:95d6b41a828b 1393 * @param huart UART handle.
<> 156:95d6b41a828b 1394 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1395 * This procedure performs following operations :
<> 156:95d6b41a828b 1396 * - Disable UART Interrupts (Tx and Rx)
<> 156:95d6b41a828b 1397 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1398 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1399 * - Set handle State to READY
<> 156:95d6b41a828b 1400 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1401 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1402 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1403 * @retval HAL status
<> 156:95d6b41a828b 1404 */
<> 156:95d6b41a828b 1405 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1406 {
<> 156:95d6b41a828b 1407 uint32_t abortcplt = 1U;
<> 156:95d6b41a828b 1408
<> 156:95d6b41a828b 1409 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1410 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1411 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1412
<> 156:95d6b41a828b 1413 /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
<> 156:95d6b41a828b 1414 before any call to DMA Abort functions */
<> 156:95d6b41a828b 1415 /* DMA Tx Handle is valid */
<> 156:95d6b41a828b 1416 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1417 {
<> 156:95d6b41a828b 1418 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
<> 156:95d6b41a828b 1419 Otherwise, set it to NULL */
<> 156:95d6b41a828b 1420 if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1421 {
<> 156:95d6b41a828b 1422 huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
<> 156:95d6b41a828b 1423 }
<> 156:95d6b41a828b 1424 else
<> 156:95d6b41a828b 1425 {
<> 156:95d6b41a828b 1426 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1427 }
<> 156:95d6b41a828b 1428 }
<> 156:95d6b41a828b 1429 /* DMA Rx Handle is valid */
<> 156:95d6b41a828b 1430 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1431 {
<> 156:95d6b41a828b 1432 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
<> 156:95d6b41a828b 1433 Otherwise, set it to NULL */
<> 156:95d6b41a828b 1434 if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1435 {
<> 156:95d6b41a828b 1436 huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
<> 156:95d6b41a828b 1437 }
<> 156:95d6b41a828b 1438 else
<> 156:95d6b41a828b 1439 {
<> 156:95d6b41a828b 1440 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1441 }
<> 156:95d6b41a828b 1442 }
<> 156:95d6b41a828b 1443
<> 156:95d6b41a828b 1444 /* Disable the UART DMA Tx request if enabled */
<> 156:95d6b41a828b 1445 if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1446 {
<> 156:95d6b41a828b 1447 /* Disable DMA Tx at UART level */
<> 156:95d6b41a828b 1448 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1449
<> 156:95d6b41a828b 1450 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1451 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1452 {
<> 156:95d6b41a828b 1453 /* UART Tx DMA Abort callback has already been initialised :
<> 156:95d6b41a828b 1454 will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1455
<> 156:95d6b41a828b 1456 /* Abort DMA TX */
<> 156:95d6b41a828b 1457 if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 1458 {
<> 156:95d6b41a828b 1459 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1460 }
<> 156:95d6b41a828b 1461 else
<> 156:95d6b41a828b 1462 {
<> 156:95d6b41a828b 1463 abortcplt = 0U;
<> 156:95d6b41a828b 1464 }
<> 156:95d6b41a828b 1465 }
<> 156:95d6b41a828b 1466 }
<> 156:95d6b41a828b 1467
<> 156:95d6b41a828b 1468 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1469 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1470 {
<> 156:95d6b41a828b 1471 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1472
<> 156:95d6b41a828b 1473 /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1474 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1475 {
<> 156:95d6b41a828b 1476 /* UART Rx DMA Abort callback has already been initialised :
<> 156:95d6b41a828b 1477 will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1478
<> 156:95d6b41a828b 1479 /* Abort DMA RX */
<> 156:95d6b41a828b 1480 if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1481 {
<> 156:95d6b41a828b 1482 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1483 abortcplt = 1U;
<> 156:95d6b41a828b 1484 }
<> 156:95d6b41a828b 1485 else
<> 156:95d6b41a828b 1486 {
<> 156:95d6b41a828b 1487 abortcplt = 0U;
<> 156:95d6b41a828b 1488 }
<> 156:95d6b41a828b 1489 }
<> 156:95d6b41a828b 1490 }
<> 156:95d6b41a828b 1491
<> 156:95d6b41a828b 1492 /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
<> 156:95d6b41a828b 1493 if (abortcplt == 1U)
<> 156:95d6b41a828b 1494 {
<> 156:95d6b41a828b 1495 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 1496 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1497 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1498
<> 156:95d6b41a828b 1499 /* Reset errorCode */
<> 156:95d6b41a828b 1500 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 1501
<> 156:95d6b41a828b 1502 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1503 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1504
<> 156:95d6b41a828b 1505 /* Restore huart->gState and huart->RxState to Ready */
<> 156:95d6b41a828b 1506 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1507 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1508
<> 156:95d6b41a828b 1509 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1510 HAL_UART_AbortCpltCallback(huart);
<> 156:95d6b41a828b 1511 }
<> 156:95d6b41a828b 1512
<> 156:95d6b41a828b 1513 return HAL_OK;
<> 156:95d6b41a828b 1514 }
<> 156:95d6b41a828b 1515
<> 156:95d6b41a828b 1516 /**
<> 156:95d6b41a828b 1517 * @brief Abort ongoing Transmit transfer (Interrupt mode).
<> 156:95d6b41a828b 1518 * @param huart UART handle.
<> 156:95d6b41a828b 1519 * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1520 * This procedure performs following operations :
<> 156:95d6b41a828b 1521 * - Disable UART Interrupts (Tx)
<> 156:95d6b41a828b 1522 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1523 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1524 * - Set handle State to READY
<> 156:95d6b41a828b 1525 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1526 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1527 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1528 * @retval HAL status
<> 156:95d6b41a828b 1529 */
<> 156:95d6b41a828b 1530 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1531 {
<> 156:95d6b41a828b 1532 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 1533 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1534
<> 156:95d6b41a828b 1535 /* Disable the UART DMA Tx request if enabled */
<> 156:95d6b41a828b 1536 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1537 {
<> 156:95d6b41a828b 1538 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1539
<> 156:95d6b41a828b 1540 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1541 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1542 {
<> 156:95d6b41a828b 1543 /* Set the UART DMA Abort callback :
<> 156:95d6b41a828b 1544 will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1545 huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
<> 156:95d6b41a828b 1546
<> 156:95d6b41a828b 1547 /* Abort DMA TX */
<> 156:95d6b41a828b 1548 if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 1549 {
<> 156:95d6b41a828b 1550 /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1551 huart->hdmatx->XferAbortCallback(huart->hdmatx);
<> 156:95d6b41a828b 1552 }
<> 156:95d6b41a828b 1553 }
<> 156:95d6b41a828b 1554 else
<> 156:95d6b41a828b 1555 {
<> 156:95d6b41a828b 1556 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1557 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1558
<> 156:95d6b41a828b 1559 /* Restore huart->gState to Ready */
<> 156:95d6b41a828b 1560 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1561
<> 156:95d6b41a828b 1562 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1563 HAL_UART_AbortTransmitCpltCallback(huart);
<> 156:95d6b41a828b 1564 }
<> 156:95d6b41a828b 1565 }
<> 156:95d6b41a828b 1566 else
<> 156:95d6b41a828b 1567 {
<> 156:95d6b41a828b 1568 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1569 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1570
<> 156:95d6b41a828b 1571 /* Restore huart->gState to Ready */
<> 156:95d6b41a828b 1572 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1573
<> 156:95d6b41a828b 1574 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1575 HAL_UART_AbortTransmitCpltCallback(huart);
<> 156:95d6b41a828b 1576 }
<> 156:95d6b41a828b 1577
<> 156:95d6b41a828b 1578 return HAL_OK;
<> 156:95d6b41a828b 1579 }
<> 156:95d6b41a828b 1580
<> 156:95d6b41a828b 1581 /**
<> 156:95d6b41a828b 1582 * @brief Abort ongoing Receive transfer (Interrupt mode).
<> 156:95d6b41a828b 1583 * @param huart UART handle.
<> 156:95d6b41a828b 1584 * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1585 * This procedure performs following operations :
<> 156:95d6b41a828b 1586 * - Disable UART Interrupts (Rx)
<> 156:95d6b41a828b 1587 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1588 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1589 * - Set handle State to READY
<> 156:95d6b41a828b 1590 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1591 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1592 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1593 * @retval HAL status
<> 156:95d6b41a828b 1594 */
<> 156:95d6b41a828b 1595 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1596 {
<> 156:95d6b41a828b 1597 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1598 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 1599 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1600
<> 156:95d6b41a828b 1601 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1602 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1603 {
<> 156:95d6b41a828b 1604 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1605
<> 156:95d6b41a828b 1606 /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1607 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1608 {
<> 156:95d6b41a828b 1609 /* Set the UART DMA Abort callback :
<> 156:95d6b41a828b 1610 will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1611 huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
<> 156:95d6b41a828b 1612
<> 156:95d6b41a828b 1613 /* Abort DMA RX */
<> 156:95d6b41a828b 1614 if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1615 {
<> 156:95d6b41a828b 1616 /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1617 huart->hdmarx->XferAbortCallback(huart->hdmarx);
<> 156:95d6b41a828b 1618 }
<> 156:95d6b41a828b 1619 }
<> 156:95d6b41a828b 1620 else
<> 156:95d6b41a828b 1621 {
<> 156:95d6b41a828b 1622 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1623 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1624
<> 156:95d6b41a828b 1625 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1626 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1627
<> 156:95d6b41a828b 1628 /* Restore huart->RxState to Ready */
<> 156:95d6b41a828b 1629 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1630
<> 156:95d6b41a828b 1631 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1632 HAL_UART_AbortReceiveCpltCallback(huart);
<> 156:95d6b41a828b 1633 }
<> 156:95d6b41a828b 1634 }
<> 156:95d6b41a828b 1635 else
<> 156:95d6b41a828b 1636 {
<> 156:95d6b41a828b 1637 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1638 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1639
<> 156:95d6b41a828b 1640 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1641 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1642
<> 156:95d6b41a828b 1643 /* Restore huart->RxState to Ready */
<> 156:95d6b41a828b 1644 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1645
<> 156:95d6b41a828b 1646 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1647 HAL_UART_AbortReceiveCpltCallback(huart);
<> 156:95d6b41a828b 1648 }
<> 156:95d6b41a828b 1649
<> 156:95d6b41a828b 1650 return HAL_OK;
<> 156:95d6b41a828b 1651 }
<> 156:95d6b41a828b 1652
<> 156:95d6b41a828b 1653 /**
<> 156:95d6b41a828b 1654 * @brief Handle UART interrupt request.
<> 156:95d6b41a828b 1655 * @param huart: UART handle.
<> 156:95d6b41a828b 1656 * @retval None
<> 156:95d6b41a828b 1657 */
<> 156:95d6b41a828b 1658 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1659 {
<> 156:95d6b41a828b 1660 uint32_t isrflags = READ_REG(huart->Instance->ISR);
<> 156:95d6b41a828b 1661 uint32_t cr1its = READ_REG(huart->Instance->CR1);
<> 156:95d6b41a828b 1662 uint32_t cr3its;
<> 156:95d6b41a828b 1663 uint32_t errorflags;
<> 156:95d6b41a828b 1664
<> 156:95d6b41a828b 1665 /* If no error occurs */
<> 156:95d6b41a828b 1666 errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
<> 156:95d6b41a828b 1667 if (errorflags == RESET)
<> 156:95d6b41a828b 1668 {
<> 156:95d6b41a828b 1669 /* UART in mode Receiver ---------------------------------------------------*/
<> 156:95d6b41a828b 1670 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 156:95d6b41a828b 1671 {
<> 156:95d6b41a828b 1672 UART_Receive_IT(huart);
<> 156:95d6b41a828b 1673 return;
<> 156:95d6b41a828b 1674 }
<> 156:95d6b41a828b 1675 }
<> 156:95d6b41a828b 1676
<> 156:95d6b41a828b 1677 /* If some errors occur */
<> 156:95d6b41a828b 1678 cr3its = READ_REG(huart->Instance->CR3);
<> 156:95d6b41a828b 1679 if( (errorflags != RESET)
<> 156:95d6b41a828b 1680 && ( ((cr3its & USART_CR3_EIE) != RESET)
<> 156:95d6b41a828b 1681 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
<> 156:95d6b41a828b 1682 {
<> 156:95d6b41a828b 1683 /* UART parity error interrupt occurred -------------------------------------*/
<> 156:95d6b41a828b 1684 if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<> 156:95d6b41a828b 1685 {
<> 156:95d6b41a828b 1686 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
<> 156:95d6b41a828b 1687
<> 156:95d6b41a828b 1688 huart->ErrorCode |= HAL_UART_ERROR_PE;
<> 156:95d6b41a828b 1689 }
<> 156:95d6b41a828b 1690
<> 156:95d6b41a828b 1691 /* UART frame error interrupt occurred --------------------------------------*/
<> 156:95d6b41a828b 1692 if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 156:95d6b41a828b 1693 {
<> 156:95d6b41a828b 1694 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
<> 156:95d6b41a828b 1695
<> 156:95d6b41a828b 1696 huart->ErrorCode |= HAL_UART_ERROR_FE;
<> 156:95d6b41a828b 1697 }
<> 156:95d6b41a828b 1698
<> 156:95d6b41a828b 1699 /* UART noise error interrupt occurred --------------------------------------*/
<> 156:95d6b41a828b 1700 if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 156:95d6b41a828b 1701 {
<> 156:95d6b41a828b 1702 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
<> 156:95d6b41a828b 1703
<> 156:95d6b41a828b 1704 huart->ErrorCode |= HAL_UART_ERROR_NE;
<> 156:95d6b41a828b 1705 }
<> 156:95d6b41a828b 1706
<> 156:95d6b41a828b 1707 /* UART Over-Run interrupt occurred -----------------------------------------*/
<> 156:95d6b41a828b 1708 if(((isrflags & USART_ISR_ORE) != RESET) &&
<> 156:95d6b41a828b 1709 (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
<> 156:95d6b41a828b 1710 {
<> 156:95d6b41a828b 1711 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
<> 156:95d6b41a828b 1712
<> 156:95d6b41a828b 1713 huart->ErrorCode |= HAL_UART_ERROR_ORE;
<> 156:95d6b41a828b 1714 }
<> 156:95d6b41a828b 1715
<> 156:95d6b41a828b 1716 /* Call UART Error Call back function if need be --------------------------*/
<> 156:95d6b41a828b 1717 if(huart->ErrorCode != HAL_UART_ERROR_NONE)
<> 156:95d6b41a828b 1718 {
<> 156:95d6b41a828b 1719 /* UART in mode Receiver ---------------------------------------------------*/
<> 156:95d6b41a828b 1720 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 156:95d6b41a828b 1721 {
<> 156:95d6b41a828b 1722 UART_Receive_IT(huart);
<> 156:95d6b41a828b 1723 }
<> 156:95d6b41a828b 1724
<> 156:95d6b41a828b 1725 /* If Overrun error occurs, or if any error occurs in DMA mode reception,
<> 156:95d6b41a828b 1726 consider error as blocking */
<> 156:95d6b41a828b 1727 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
<> 156:95d6b41a828b 1728 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<> 156:95d6b41a828b 1729 {
<> 156:95d6b41a828b 1730 /* Blocking error : transfer is aborted
<> 156:95d6b41a828b 1731 Set the UART state ready to be able to start again the process,
<> 156:95d6b41a828b 1732 Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<> 156:95d6b41a828b 1733 UART_EndRxTransfer(huart);
<> 156:95d6b41a828b 1734
<> 156:95d6b41a828b 1735 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1736 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1737 {
<> 156:95d6b41a828b 1738 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1739
<> 156:95d6b41a828b 1740 /* Abort the UART DMA Rx channel */
<> 156:95d6b41a828b 1741 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1742 {
<> 156:95d6b41a828b 1743 /* Set the UART DMA Abort callback :
<> 156:95d6b41a828b 1744 will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1745 huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
<> 156:95d6b41a828b 1746
<> 156:95d6b41a828b 1747 /* Abort DMA RX */
<> 156:95d6b41a828b 1748 if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1749 {
<> 156:95d6b41a828b 1750 /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1751 huart->hdmarx->XferAbortCallback(huart->hdmarx);
<> 156:95d6b41a828b 1752 }
<> 156:95d6b41a828b 1753 }
<> 156:95d6b41a828b 1754 else
<> 156:95d6b41a828b 1755 {
<> 156:95d6b41a828b 1756 /* Call user error callback */
<> 156:95d6b41a828b 1757 HAL_UART_ErrorCallback(huart);
<> 156:95d6b41a828b 1758 }
<> 156:95d6b41a828b 1759 }
<> 156:95d6b41a828b 1760 else
<> 156:95d6b41a828b 1761 {
<> 156:95d6b41a828b 1762 /* Call user error callback */
<> 156:95d6b41a828b 1763 HAL_UART_ErrorCallback(huart);
<> 156:95d6b41a828b 1764 }
<> 156:95d6b41a828b 1765 }
<> 156:95d6b41a828b 1766 else
<> 156:95d6b41a828b 1767 {
<> 156:95d6b41a828b 1768 /* Non Blocking error : transfer could go on.
<> 156:95d6b41a828b 1769 Error is notified to user through user error callback */
<> 156:95d6b41a828b 1770 HAL_UART_ErrorCallback(huart);
<> 156:95d6b41a828b 1771 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 1772 }
<> 156:95d6b41a828b 1773 }
<> 156:95d6b41a828b 1774 return;
<> 156:95d6b41a828b 1775
<> 156:95d6b41a828b 1776 } /* End if some error occurs */
<> 156:95d6b41a828b 1777
<> 156:95d6b41a828b 1778 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 156:95d6b41a828b 1779 /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
<> 156:95d6b41a828b 1780 if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
<> 156:95d6b41a828b 1781 {
<> 156:95d6b41a828b 1782 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
<> 156:95d6b41a828b 1783 /* Set the UART state ready to be able to start again the process */
<> 156:95d6b41a828b 1784 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1785 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1786 HAL_UARTEx_WakeupCallback(huart);
<> 156:95d6b41a828b 1787 return;
<> 156:95d6b41a828b 1788 }
<> 156:95d6b41a828b 1789 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 156:95d6b41a828b 1790
<> 156:95d6b41a828b 1791 /* UART in mode Transmitter ------------------------------------------------*/
<> 156:95d6b41a828b 1792 if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<> 156:95d6b41a828b 1793 {
<> 156:95d6b41a828b 1794 UART_Transmit_IT(huart);
<> 156:95d6b41a828b 1795 return;
<> 156:95d6b41a828b 1796 }
<> 156:95d6b41a828b 1797
<> 156:95d6b41a828b 1798 /* UART in mode Transmitter (transmission end) -----------------------------*/
<> 156:95d6b41a828b 1799 if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<> 156:95d6b41a828b 1800 {
<> 156:95d6b41a828b 1801 UART_EndTransmit_IT(huart);
<> 156:95d6b41a828b 1802 return;
<> 156:95d6b41a828b 1803 }
<> 156:95d6b41a828b 1804
<> 156:95d6b41a828b 1805 }
<> 156:95d6b41a828b 1806
<> 156:95d6b41a828b 1807 /**
<> 144:ef7eb2e8f9f7 1808 * @brief Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1809 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1810 * @retval None
<> 144:ef7eb2e8f9f7 1811 */
<> 156:95d6b41a828b 1812 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1813 {
<> 144:ef7eb2e8f9f7 1814 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1815 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1816
<> 144:ef7eb2e8f9f7 1817 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1818 the HAL_UART_TxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1819 */
<> 144:ef7eb2e8f9f7 1820 }
<> 144:ef7eb2e8f9f7 1821
<> 144:ef7eb2e8f9f7 1822 /**
<> 144:ef7eb2e8f9f7 1823 * @brief Tx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 1824 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1825 * @retval None
<> 144:ef7eb2e8f9f7 1826 */
<> 156:95d6b41a828b 1827 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1828 {
<> 144:ef7eb2e8f9f7 1829 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1830 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1831
<> 144:ef7eb2e8f9f7 1832 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1833 the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1834 */
<> 144:ef7eb2e8f9f7 1835 }
<> 144:ef7eb2e8f9f7 1836
<> 144:ef7eb2e8f9f7 1837 /**
<> 144:ef7eb2e8f9f7 1838 * @brief Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1839 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1840 * @retval None
<> 144:ef7eb2e8f9f7 1841 */
<> 144:ef7eb2e8f9f7 1842 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1843 {
<> 144:ef7eb2e8f9f7 1844 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1845 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1848 the HAL_UART_RxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1849 */
<> 144:ef7eb2e8f9f7 1850 }
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 /**
<> 144:ef7eb2e8f9f7 1853 * @brief Rx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 1854 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1855 * @retval None
<> 144:ef7eb2e8f9f7 1856 */
<> 144:ef7eb2e8f9f7 1857 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1858 {
<> 144:ef7eb2e8f9f7 1859 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1860 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1861
<> 144:ef7eb2e8f9f7 1862 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1863 the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1864 */
<> 144:ef7eb2e8f9f7 1865 }
<> 144:ef7eb2e8f9f7 1866
<> 144:ef7eb2e8f9f7 1867 /**
<> 144:ef7eb2e8f9f7 1868 * @brief UART error callback.
<> 144:ef7eb2e8f9f7 1869 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1870 * @retval None
<> 144:ef7eb2e8f9f7 1871 */
<> 156:95d6b41a828b 1872 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1873 {
<> 144:ef7eb2e8f9f7 1874 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1875 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1876
<> 144:ef7eb2e8f9f7 1877 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1878 the HAL_UART_ErrorCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1879 */
<> 144:ef7eb2e8f9f7 1880 }
<> 144:ef7eb2e8f9f7 1881
<> 144:ef7eb2e8f9f7 1882 /**
<> 156:95d6b41a828b 1883 * @brief UART Abort Complete callback.
<> 156:95d6b41a828b 1884 * @param huart UART handle.
<> 156:95d6b41a828b 1885 * @retval None
<> 156:95d6b41a828b 1886 */
<> 156:95d6b41a828b 1887 __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1888 {
<> 156:95d6b41a828b 1889 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1890 UNUSED(huart);
<> 156:95d6b41a828b 1891
<> 156:95d6b41a828b 1892 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1893 the HAL_UART_AbortCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1894 */
<> 156:95d6b41a828b 1895 }
<> 156:95d6b41a828b 1896
<> 156:95d6b41a828b 1897 /**
<> 156:95d6b41a828b 1898 * @brief UART Abort Complete callback.
<> 156:95d6b41a828b 1899 * @param huart UART handle.
<> 156:95d6b41a828b 1900 * @retval None
<> 156:95d6b41a828b 1901 */
<> 156:95d6b41a828b 1902 __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1903 {
<> 156:95d6b41a828b 1904 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1905 UNUSED(huart);
<> 156:95d6b41a828b 1906
<> 156:95d6b41a828b 1907 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1908 the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1909 */
<> 156:95d6b41a828b 1910 }
<> 156:95d6b41a828b 1911
<> 156:95d6b41a828b 1912 /**
<> 156:95d6b41a828b 1913 * @brief UART Abort Receive Complete callback.
<> 156:95d6b41a828b 1914 * @param huart UART handle.
<> 156:95d6b41a828b 1915 * @retval None
<> 156:95d6b41a828b 1916 */
<> 156:95d6b41a828b 1917 __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1918 {
<> 156:95d6b41a828b 1919 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1920 UNUSED(huart);
<> 156:95d6b41a828b 1921
<> 156:95d6b41a828b 1922 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1923 the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1924 */
<> 156:95d6b41a828b 1925 }
<> 156:95d6b41a828b 1926
<> 156:95d6b41a828b 1927 /**
<> 144:ef7eb2e8f9f7 1928 * @}
<> 144:ef7eb2e8f9f7 1929 */
<> 144:ef7eb2e8f9f7 1930
<> 144:ef7eb2e8f9f7 1931 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1932 * @brief UART control functions
<> 144:ef7eb2e8f9f7 1933 *
<> 144:ef7eb2e8f9f7 1934 @verbatim
<> 144:ef7eb2e8f9f7 1935 ===============================================================================
<> 144:ef7eb2e8f9f7 1936 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1937 ===============================================================================
<> 144:ef7eb2e8f9f7 1938 [..]
<> 144:ef7eb2e8f9f7 1939 This subsection provides a set of functions allowing to control the UART.
<> 144:ef7eb2e8f9f7 1940 (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
<> 144:ef7eb2e8f9f7 1941 (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
<> 144:ef7eb2e8f9f7 1942 (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
<> 144:ef7eb2e8f9f7 1943 (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
<> 144:ef7eb2e8f9f7 1944 (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
<> 144:ef7eb2e8f9f7 1945 @endverbatim
<> 144:ef7eb2e8f9f7 1946 * @{
<> 144:ef7eb2e8f9f7 1947 */
<> 144:ef7eb2e8f9f7 1948
<> 144:ef7eb2e8f9f7 1949 /**
<> 144:ef7eb2e8f9f7 1950 * @brief Enable UART in mute mode (does not mean UART enters mute mode;
<> 144:ef7eb2e8f9f7 1951 * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
<> 144:ef7eb2e8f9f7 1952 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1953 * @retval HAL status
<> 144:ef7eb2e8f9f7 1954 */
<> 144:ef7eb2e8f9f7 1955 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1956 {
<> 144:ef7eb2e8f9f7 1957 /* Process Locked */
<> 144:ef7eb2e8f9f7 1958 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1959
<> 144:ef7eb2e8f9f7 1960 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 /* Enable USART mute mode by setting the MME bit in the CR1 register */
<> 156:95d6b41a828b 1963 SET_BIT(huart->Instance->CR1, USART_CR1_MME);
<> 144:ef7eb2e8f9f7 1964
<> 144:ef7eb2e8f9f7 1965 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 1968 }
<> 144:ef7eb2e8f9f7 1969
<> 144:ef7eb2e8f9f7 1970 /**
<> 156:95d6b41a828b 1971 * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
<> 156:95d6b41a828b 1972 * as it may not have been in mute mode at this very moment).
<> 156:95d6b41a828b 1973 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1974 * @retval HAL status
<> 144:ef7eb2e8f9f7 1975 */
<> 144:ef7eb2e8f9f7 1976 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1977 {
<> 144:ef7eb2e8f9f7 1978 /* Process Locked */
<> 144:ef7eb2e8f9f7 1979 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1980
<> 144:ef7eb2e8f9f7 1981 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1982
<> 144:ef7eb2e8f9f7 1983 /* Disable USART mute mode by clearing the MME bit in the CR1 register */
<> 156:95d6b41a828b 1984 CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
<> 144:ef7eb2e8f9f7 1985
<> 144:ef7eb2e8f9f7 1986 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 1987
<> 144:ef7eb2e8f9f7 1988 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 1989 }
<> 144:ef7eb2e8f9f7 1990
<> 144:ef7eb2e8f9f7 1991 /**
<> 144:ef7eb2e8f9f7 1992 * @brief Enter UART mute mode (means UART actually enters mute mode).
<> 144:ef7eb2e8f9f7 1993 * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
<> 144:ef7eb2e8f9f7 1994 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 1995 * @retval None
<> 144:ef7eb2e8f9f7 1996 */
<> 144:ef7eb2e8f9f7 1997 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1998 {
<> 144:ef7eb2e8f9f7 1999 __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
<> 144:ef7eb2e8f9f7 2000 }
<> 144:ef7eb2e8f9f7 2001
<> 144:ef7eb2e8f9f7 2002 /**
<> 144:ef7eb2e8f9f7 2003 * @brief Enable the UART transmitter and disable the UART receiver.
<> 144:ef7eb2e8f9f7 2004 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 2005 * @retval HAL status
<> 144:ef7eb2e8f9f7 2006 */
<> 144:ef7eb2e8f9f7 2007 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2008 {
<> 144:ef7eb2e8f9f7 2009 /* Process Locked */
<> 144:ef7eb2e8f9f7 2010 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 2011 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2012
<> 144:ef7eb2e8f9f7 2013 /* Clear TE and RE bits */
<> 144:ef7eb2e8f9f7 2014 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
<> 144:ef7eb2e8f9f7 2015 /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
<> 144:ef7eb2e8f9f7 2016 SET_BIT(huart->Instance->CR1, USART_CR1_TE);
<> 144:ef7eb2e8f9f7 2017
<> 144:ef7eb2e8f9f7 2018 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2019
<> 144:ef7eb2e8f9f7 2020 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2021 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 2022
<> 144:ef7eb2e8f9f7 2023 return HAL_OK;
<> 144:ef7eb2e8f9f7 2024 }
<> 144:ef7eb2e8f9f7 2025
<> 144:ef7eb2e8f9f7 2026 /**
<> 144:ef7eb2e8f9f7 2027 * @brief Enable the UART receiver and disable the UART transmitter.
<> 144:ef7eb2e8f9f7 2028 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 2029 * @retval HAL status.
<> 144:ef7eb2e8f9f7 2030 */
<> 144:ef7eb2e8f9f7 2031 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2032 {
<> 144:ef7eb2e8f9f7 2033 /* Process Locked */
<> 144:ef7eb2e8f9f7 2034 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 2035 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2036
<> 144:ef7eb2e8f9f7 2037 /* Clear TE and RE bits */
<> 144:ef7eb2e8f9f7 2038 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
<> 144:ef7eb2e8f9f7 2039 /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
<> 144:ef7eb2e8f9f7 2040 SET_BIT(huart->Instance->CR1, USART_CR1_RE);
<> 144:ef7eb2e8f9f7 2041
<> 144:ef7eb2e8f9f7 2042 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2043 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2044 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 2045
<> 144:ef7eb2e8f9f7 2046 return HAL_OK;
<> 144:ef7eb2e8f9f7 2047 }
<> 144:ef7eb2e8f9f7 2048
<> 144:ef7eb2e8f9f7 2049 /**
<> 144:ef7eb2e8f9f7 2050 * @}
<> 144:ef7eb2e8f9f7 2051 */
<> 144:ef7eb2e8f9f7 2052
<> 144:ef7eb2e8f9f7 2053 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 2054 * @brief UART Peripheral State functions
<> 144:ef7eb2e8f9f7 2055 *
<> 144:ef7eb2e8f9f7 2056 @verbatim
<> 144:ef7eb2e8f9f7 2057 ==============================================================================
<> 144:ef7eb2e8f9f7 2058 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 2059 ==============================================================================
<> 144:ef7eb2e8f9f7 2060 [..]
<> 144:ef7eb2e8f9f7 2061 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 2062 (+) Return the UART handle state.
<> 144:ef7eb2e8f9f7 2063 (+) Return the UART handle error code
<> 144:ef7eb2e8f9f7 2064
<> 144:ef7eb2e8f9f7 2065 @endverbatim
<> 144:ef7eb2e8f9f7 2066 * @{
<> 144:ef7eb2e8f9f7 2067 */
<> 144:ef7eb2e8f9f7 2068
<> 144:ef7eb2e8f9f7 2069 /**
<> 144:ef7eb2e8f9f7 2070 * @brief Return the UART handle state.
<> 144:ef7eb2e8f9f7 2071 * @param huart Pointer to a UART_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2072 * the configuration information for the specified UART.
<> 144:ef7eb2e8f9f7 2073 * @retval HAL state
<> 144:ef7eb2e8f9f7 2074 */
<> 144:ef7eb2e8f9f7 2075 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2076 {
<> 156:95d6b41a828b 2077 uint32_t temp1= 0x00U, temp2 = 0x00U;
<> 144:ef7eb2e8f9f7 2078 temp1 = huart->gState;
<> 144:ef7eb2e8f9f7 2079 temp2 = huart->RxState;
<> 156:95d6b41a828b 2080
<> 144:ef7eb2e8f9f7 2081 return (HAL_UART_StateTypeDef)(temp1 | temp2);
<> 144:ef7eb2e8f9f7 2082 }
<> 144:ef7eb2e8f9f7 2083
<> 144:ef7eb2e8f9f7 2084 /**
<> 144:ef7eb2e8f9f7 2085 * @brief Return the UART handle error code.
<> 144:ef7eb2e8f9f7 2086 * @param huart Pointer to a UART_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2087 * the configuration information for the specified UART.
<> 144:ef7eb2e8f9f7 2088 * @retval UART Error Code
<> 144:ef7eb2e8f9f7 2089 */
<> 144:ef7eb2e8f9f7 2090 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2091 {
<> 144:ef7eb2e8f9f7 2092 return huart->ErrorCode;
<> 144:ef7eb2e8f9f7 2093 }
<> 144:ef7eb2e8f9f7 2094 /**
<> 144:ef7eb2e8f9f7 2095 * @}
<> 144:ef7eb2e8f9f7 2096 */
<> 144:ef7eb2e8f9f7 2097
<> 144:ef7eb2e8f9f7 2098 /**
<> 144:ef7eb2e8f9f7 2099 * @}
<> 144:ef7eb2e8f9f7 2100 */
<> 144:ef7eb2e8f9f7 2101
<> 144:ef7eb2e8f9f7 2102 /** @defgroup UART_Private_Functions UART Private Functions
<> 144:ef7eb2e8f9f7 2103 * @{
<> 144:ef7eb2e8f9f7 2104 */
<> 144:ef7eb2e8f9f7 2105
<> 144:ef7eb2e8f9f7 2106 /**
<> 144:ef7eb2e8f9f7 2107 * @brief Configure the UART peripheral.
<> 144:ef7eb2e8f9f7 2108 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 2109 * @retval HAL status
<> 144:ef7eb2e8f9f7 2110 */
<> 144:ef7eb2e8f9f7 2111 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2112 {
<> 156:95d6b41a828b 2113 uint32_t tmpreg = 0x00000000U;
<> 144:ef7eb2e8f9f7 2114 UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
<> 156:95d6b41a828b 2115 uint16_t brrtemp = 0x0000U;
<> 156:95d6b41a828b 2116 uint16_t usartdiv = 0x0000U;
<> 144:ef7eb2e8f9f7 2117 HAL_StatusTypeDef ret = HAL_OK;
<> 144:ef7eb2e8f9f7 2118
<> 144:ef7eb2e8f9f7 2119 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2120 assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2121 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
<> 144:ef7eb2e8f9f7 2122 assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
<> 144:ef7eb2e8f9f7 2123 assert_param(IS_UART_PARITY(huart->Init.Parity));
<> 144:ef7eb2e8f9f7 2124 assert_param(IS_UART_MODE(huart->Init.Mode));
<> 144:ef7eb2e8f9f7 2125 assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
<> 144:ef7eb2e8f9f7 2126 assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
<> 144:ef7eb2e8f9f7 2127 assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
<> 144:ef7eb2e8f9f7 2128
<> 144:ef7eb2e8f9f7 2129
<> 144:ef7eb2e8f9f7 2130 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2131 /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
<> 144:ef7eb2e8f9f7 2132 * the UART Word Length, Parity, Mode and oversampling:
<> 144:ef7eb2e8f9f7 2133 * set the M bits according to huart->Init.WordLength value
<> 144:ef7eb2e8f9f7 2134 * set PCE and PS bits according to huart->Init.Parity value
<> 144:ef7eb2e8f9f7 2135 * set TE and RE bits according to huart->Init.Mode value
<> 144:ef7eb2e8f9f7 2136 * set OVER8 bit according to huart->Init.OverSampling value */
<> 144:ef7eb2e8f9f7 2137 tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
<> 144:ef7eb2e8f9f7 2138 MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
<> 144:ef7eb2e8f9f7 2139
<> 144:ef7eb2e8f9f7 2140 /*-------------------------- USART CR2 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2141 /* Configure the UART Stop Bits: Set STOP[13:12] bits according
<> 144:ef7eb2e8f9f7 2142 * to huart->Init.StopBits value */
<> 144:ef7eb2e8f9f7 2143 MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
<> 144:ef7eb2e8f9f7 2144
<> 144:ef7eb2e8f9f7 2145 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2146 /* Configure
<> 144:ef7eb2e8f9f7 2147 * - UART HardWare Flow Control: set CTSE and RTSE bits according
<> 144:ef7eb2e8f9f7 2148 * to huart->Init.HwFlowCtl value
<> 144:ef7eb2e8f9f7 2149 * - one-bit sampling method versus three samples' majority rule according
<> 144:ef7eb2e8f9f7 2150 * to huart->Init.OneBitSampling */
<> 144:ef7eb2e8f9f7 2151 tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
<> 144:ef7eb2e8f9f7 2152 MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
<> 144:ef7eb2e8f9f7 2153
<> 144:ef7eb2e8f9f7 2154 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2155 UART_GETCLOCKSOURCE(huart, clocksource);
<> 144:ef7eb2e8f9f7 2156
<> 144:ef7eb2e8f9f7 2157 /* Check UART Over Sampling to set Baud Rate Register */
<> 144:ef7eb2e8f9f7 2158 if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
<> 144:ef7eb2e8f9f7 2159 {
<> 144:ef7eb2e8f9f7 2160 switch (clocksource)
<> 144:ef7eb2e8f9f7 2161 {
<> 144:ef7eb2e8f9f7 2162 case UART_CLOCKSOURCE_PCLK1:
<> 144:ef7eb2e8f9f7 2163 usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2164 break;
<> 144:ef7eb2e8f9f7 2165 case UART_CLOCKSOURCE_HSI:
<> 144:ef7eb2e8f9f7 2166 usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2167 break;
<> 144:ef7eb2e8f9f7 2168 case UART_CLOCKSOURCE_SYSCLK:
<> 144:ef7eb2e8f9f7 2169 usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2170 break;
<> 144:ef7eb2e8f9f7 2171 case UART_CLOCKSOURCE_LSE:
<> 144:ef7eb2e8f9f7 2172 usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2173 break;
<> 144:ef7eb2e8f9f7 2174 case UART_CLOCKSOURCE_UNDEFINED:
<> 144:ef7eb2e8f9f7 2175 default:
<> 144:ef7eb2e8f9f7 2176 ret = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2177 break;
<> 144:ef7eb2e8f9f7 2178 }
<> 144:ef7eb2e8f9f7 2179
<> 156:95d6b41a828b 2180 brrtemp = usartdiv & 0xFFF0U;
<> 156:95d6b41a828b 2181 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
<> 144:ef7eb2e8f9f7 2182 huart->Instance->BRR = brrtemp;
<> 144:ef7eb2e8f9f7 2183 }
<> 144:ef7eb2e8f9f7 2184 else
<> 144:ef7eb2e8f9f7 2185 {
<> 144:ef7eb2e8f9f7 2186 switch (clocksource)
<> 144:ef7eb2e8f9f7 2187 {
<> 144:ef7eb2e8f9f7 2188 case UART_CLOCKSOURCE_PCLK1:
<> 144:ef7eb2e8f9f7 2189 huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2190 break;
<> 144:ef7eb2e8f9f7 2191 case UART_CLOCKSOURCE_HSI:
<> 156:95d6b41a828b 2192 huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2193 break;
<> 144:ef7eb2e8f9f7 2194 case UART_CLOCKSOURCE_SYSCLK:
<> 144:ef7eb2e8f9f7 2195 huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2196 break;
<> 144:ef7eb2e8f9f7 2197 case UART_CLOCKSOURCE_LSE:
<> 156:95d6b41a828b 2198 huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2199 break;
<> 144:ef7eb2e8f9f7 2200 case UART_CLOCKSOURCE_UNDEFINED:
<> 144:ef7eb2e8f9f7 2201 default:
<> 144:ef7eb2e8f9f7 2202 ret = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2203 break;
<> 144:ef7eb2e8f9f7 2204 }
<> 144:ef7eb2e8f9f7 2205 }
<> 144:ef7eb2e8f9f7 2206
<> 144:ef7eb2e8f9f7 2207 return ret;
<> 144:ef7eb2e8f9f7 2208
<> 144:ef7eb2e8f9f7 2209 }
<> 144:ef7eb2e8f9f7 2210
<> 144:ef7eb2e8f9f7 2211 /**
<> 144:ef7eb2e8f9f7 2212 * @brief Configure the UART peripheral advanced features.
<> 144:ef7eb2e8f9f7 2213 * @param huart: UART handle.
<> 144:ef7eb2e8f9f7 2214 * @retval None
<> 144:ef7eb2e8f9f7 2215 */
<> 144:ef7eb2e8f9f7 2216 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2217 {
<> 144:ef7eb2e8f9f7 2218 /* Check whether the set of advanced features to configure is properly set */
<> 144:ef7eb2e8f9f7 2219 assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
<> 144:ef7eb2e8f9f7 2220
<> 144:ef7eb2e8f9f7 2221 /* if required, configure TX pin active level inversion */
<> 144:ef7eb2e8f9f7 2222 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
<> 144:ef7eb2e8f9f7 2223 {
<> 144:ef7eb2e8f9f7 2224 assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
<> 144:ef7eb2e8f9f7 2225 MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
<> 144:ef7eb2e8f9f7 2226 }
<> 144:ef7eb2e8f9f7 2227
<> 144:ef7eb2e8f9f7 2228 /* if required, configure RX pin active level inversion */
<> 144:ef7eb2e8f9f7 2229 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
<> 144:ef7eb2e8f9f7 2230 {
<> 144:ef7eb2e8f9f7 2231 assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
<> 144:ef7eb2e8f9f7 2232 MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
<> 144:ef7eb2e8f9f7 2233 }
<> 144:ef7eb2e8f9f7 2234
<> 144:ef7eb2e8f9f7 2235 /* if required, configure data inversion */
<> 144:ef7eb2e8f9f7 2236 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
<> 144:ef7eb2e8f9f7 2237 {
<> 144:ef7eb2e8f9f7 2238 assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
<> 144:ef7eb2e8f9f7 2239 MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
<> 144:ef7eb2e8f9f7 2240 }
<> 144:ef7eb2e8f9f7 2241
<> 144:ef7eb2e8f9f7 2242 /* if required, configure RX/TX pins swap */
<> 144:ef7eb2e8f9f7 2243 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
<> 144:ef7eb2e8f9f7 2244 {
<> 144:ef7eb2e8f9f7 2245 assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
<> 144:ef7eb2e8f9f7 2246 MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
<> 144:ef7eb2e8f9f7 2247 }
<> 144:ef7eb2e8f9f7 2248
<> 144:ef7eb2e8f9f7 2249 /* if required, configure RX overrun detection disabling */
<> 144:ef7eb2e8f9f7 2250 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
<> 144:ef7eb2e8f9f7 2251 {
<> 144:ef7eb2e8f9f7 2252 assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
<> 144:ef7eb2e8f9f7 2253 MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
<> 144:ef7eb2e8f9f7 2254 }
<> 144:ef7eb2e8f9f7 2255
<> 144:ef7eb2e8f9f7 2256 /* if required, configure DMA disabling on reception error */
<> 144:ef7eb2e8f9f7 2257 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
<> 144:ef7eb2e8f9f7 2258 {
<> 144:ef7eb2e8f9f7 2259 assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
<> 144:ef7eb2e8f9f7 2260 MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
<> 144:ef7eb2e8f9f7 2261 }
<> 144:ef7eb2e8f9f7 2262
<> 144:ef7eb2e8f9f7 2263 /* if required, configure auto Baud rate detection scheme */
<> 144:ef7eb2e8f9f7 2264 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
<> 144:ef7eb2e8f9f7 2265 {
<> 144:ef7eb2e8f9f7 2266 assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 2267 assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
<> 144:ef7eb2e8f9f7 2268 MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
<> 144:ef7eb2e8f9f7 2269 /* set auto Baudrate detection parameters if detection is enabled */
<> 144:ef7eb2e8f9f7 2270 if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
<> 144:ef7eb2e8f9f7 2271 {
<> 144:ef7eb2e8f9f7 2272 assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
<> 144:ef7eb2e8f9f7 2273 MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
<> 144:ef7eb2e8f9f7 2274 }
<> 144:ef7eb2e8f9f7 2275 }
<> 144:ef7eb2e8f9f7 2276
<> 144:ef7eb2e8f9f7 2277 /* if required, configure MSB first on communication line */
<> 144:ef7eb2e8f9f7 2278 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
<> 144:ef7eb2e8f9f7 2279 {
<> 144:ef7eb2e8f9f7 2280 assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
<> 144:ef7eb2e8f9f7 2281 MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
<> 144:ef7eb2e8f9f7 2282 }
<> 144:ef7eb2e8f9f7 2283 }
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 /**
<> 144:ef7eb2e8f9f7 2286 * @brief Check the UART Idle State.
<> 156:95d6b41a828b 2287 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2288 * @retval HAL status
<> 144:ef7eb2e8f9f7 2289 */
<> 144:ef7eb2e8f9f7 2290 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2291 {
<> 156:95d6b41a828b 2292 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 156:95d6b41a828b 2293 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2294 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 156:95d6b41a828b 2295
<> 144:ef7eb2e8f9f7 2296 /* Initialize the UART ErrorCode */
<> 144:ef7eb2e8f9f7 2297 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2298
<> 156:95d6b41a828b 2299 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 156:95d6b41a828b 2300 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 2301 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2302
<> 144:ef7eb2e8f9f7 2303 /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
<> 144:ef7eb2e8f9f7 2304 Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
<> 144:ef7eb2e8f9f7 2305 */
<> 144:ef7eb2e8f9f7 2306 if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance))
<> 144:ef7eb2e8f9f7 2307 {
<> 144:ef7eb2e8f9f7 2308 /* Check if the Transmitter is enabled */
<> 144:ef7eb2e8f9f7 2309 if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<> 144:ef7eb2e8f9f7 2310 {
<> 144:ef7eb2e8f9f7 2311 /* Wait until TEACK flag is set */
<> 156:95d6b41a828b 2312 if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2313 {
<> 144:ef7eb2e8f9f7 2314 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 2315 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2316 }
<> 144:ef7eb2e8f9f7 2317 }
<> 144:ef7eb2e8f9f7 2318
<> 144:ef7eb2e8f9f7 2319 /* Check if the Receiver is enabled */
<> 144:ef7eb2e8f9f7 2320 if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<> 144:ef7eb2e8f9f7 2321 {
<> 144:ef7eb2e8f9f7 2322 /* Wait until REACK flag is set */
<> 156:95d6b41a828b 2323 if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2324 {
<> 144:ef7eb2e8f9f7 2325 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 2326 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2327 }
<> 144:ef7eb2e8f9f7 2328 }
<> 144:ef7eb2e8f9f7 2329 }
<> 144:ef7eb2e8f9f7 2330 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 2331
<> 144:ef7eb2e8f9f7 2332 /* Initialize the UART State */
<> 156:95d6b41a828b 2333 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2334 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2335
<> 144:ef7eb2e8f9f7 2336 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2337 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 2338
<> 144:ef7eb2e8f9f7 2339 return HAL_OK;
<> 144:ef7eb2e8f9f7 2340 }
<> 144:ef7eb2e8f9f7 2341
<> 144:ef7eb2e8f9f7 2342 /**
<> 144:ef7eb2e8f9f7 2343 * @brief Handle UART Communication Timeout.
<> 156:95d6b41a828b 2344 * @param huart UART handle.
<> 156:95d6b41a828b 2345 * @param Flag Specifies the UART flag to check
<> 156:95d6b41a828b 2346 * @param Status Flag status (SET or RESET)
<> 156:95d6b41a828b 2347 * @param Tickstart Tick start value
<> 156:95d6b41a828b 2348 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 2349 * @retval HAL status
<> 144:ef7eb2e8f9f7 2350 */
<> 156:95d6b41a828b 2351 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2352 {
<> 144:ef7eb2e8f9f7 2353 /* Wait until flag is set */
<> 156:95d6b41a828b 2354 while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
<> 144:ef7eb2e8f9f7 2355 {
<> 156:95d6b41a828b 2356 /* Check for the Timeout */
<> 156:95d6b41a828b 2357 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2358 {
<> 156:95d6b41a828b 2359 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 2360 {
<> 156:95d6b41a828b 2361 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 156:95d6b41a828b 2362 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
<> 156:95d6b41a828b 2363 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 2364
<> 156:95d6b41a828b 2365 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2366 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2367
<> 156:95d6b41a828b 2368 /* Process Unlocked */
<> 156:95d6b41a828b 2369 __HAL_UNLOCK(huart);
<> 156:95d6b41a828b 2370 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2371 }
<> 144:ef7eb2e8f9f7 2372 }
<> 144:ef7eb2e8f9f7 2373 }
<> 144:ef7eb2e8f9f7 2374 return HAL_OK;
<> 144:ef7eb2e8f9f7 2375 }
<> 144:ef7eb2e8f9f7 2376
<> 156:95d6b41a828b 2377
<> 156:95d6b41a828b 2378 /**
<> 156:95d6b41a828b 2379 * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
<> 156:95d6b41a828b 2380 * @param huart UART handle.
<> 156:95d6b41a828b 2381 * @retval None
<> 156:95d6b41a828b 2382 */
<> 156:95d6b41a828b 2383 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 2384 {
<> 156:95d6b41a828b 2385 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 2386 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 2387
<> 156:95d6b41a828b 2388 /* At end of Tx process, restore huart->gState to Ready */
<> 156:95d6b41a828b 2389 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2390 }
<> 156:95d6b41a828b 2391
<> 156:95d6b41a828b 2392
<> 156:95d6b41a828b 2393 /**
<> 156:95d6b41a828b 2394 * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
<> 156:95d6b41a828b 2395 * @param huart UART handle.
<> 156:95d6b41a828b 2396 * @retval None
<> 156:95d6b41a828b 2397 */
<> 156:95d6b41a828b 2398 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 2399 {
<> 156:95d6b41a828b 2400 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 2401 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 2402 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 2403
<> 156:95d6b41a828b 2404 /* At end of Rx process, restore huart->RxState to Ready */
<> 156:95d6b41a828b 2405 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2406 }
<> 156:95d6b41a828b 2407
<> 156:95d6b41a828b 2408
<> 144:ef7eb2e8f9f7 2409 /**
<> 144:ef7eb2e8f9f7 2410 * @brief DMA UART transmit process complete callback.
<> 156:95d6b41a828b 2411 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2412 * @retval None
<> 144:ef7eb2e8f9f7 2413 */
<> 144:ef7eb2e8f9f7 2414 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2415 {
<> 156:95d6b41a828b 2416 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2417
<> 144:ef7eb2e8f9f7 2418 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 2419 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 156:95d6b41a828b 2420 {
<> 144:ef7eb2e8f9f7 2421 huart->TxXferCount = 0;
<> 156:95d6b41a828b 2422
<> 144:ef7eb2e8f9f7 2423 /* Disable the DMA transfer for transmit request by resetting the DMAT bit
<> 156:95d6b41a828b 2424 in the UART CR3 register */
<> 156:95d6b41a828b 2425 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 2426
<> 144:ef7eb2e8f9f7 2427 /* Enable the UART Transmit Complete Interrupt */
<> 156:95d6b41a828b 2428 SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2429 }
<> 144:ef7eb2e8f9f7 2430 /* DMA Circular mode */
<> 144:ef7eb2e8f9f7 2431 else
<> 144:ef7eb2e8f9f7 2432 {
<> 144:ef7eb2e8f9f7 2433 HAL_UART_TxCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2434 }
<> 144:ef7eb2e8f9f7 2435
<> 144:ef7eb2e8f9f7 2436 }
<> 144:ef7eb2e8f9f7 2437
<> 144:ef7eb2e8f9f7 2438 /**
<> 144:ef7eb2e8f9f7 2439 * @brief DMA UART transmit process half complete callback.
<> 156:95d6b41a828b 2440 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2441 * @retval None
<> 144:ef7eb2e8f9f7 2442 */
<> 144:ef7eb2e8f9f7 2443 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2444 {
<> 156:95d6b41a828b 2445 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2446
<> 144:ef7eb2e8f9f7 2447 HAL_UART_TxHalfCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2448 }
<> 144:ef7eb2e8f9f7 2449
<> 144:ef7eb2e8f9f7 2450 /**
<> 144:ef7eb2e8f9f7 2451 * @brief DMA UART receive process complete callback.
<> 156:95d6b41a828b 2452 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2453 * @retval None
<> 144:ef7eb2e8f9f7 2454 */
<> 144:ef7eb2e8f9f7 2455 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2456 {
<> 156:95d6b41a828b 2457 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2458
<> 144:ef7eb2e8f9f7 2459 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 2460 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 144:ef7eb2e8f9f7 2461 {
<> 156:95d6b41a828b 2462 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2463
<> 156:95d6b41a828b 2464 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 2465 CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 2466 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2467
<> 144:ef7eb2e8f9f7 2468 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
<> 144:ef7eb2e8f9f7 2469 in the UART CR3 register */
<> 156:95d6b41a828b 2470 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 2471
<> 144:ef7eb2e8f9f7 2472 /* At end of Rx process, restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 2473 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2474 }
<> 156:95d6b41a828b 2475
<> 144:ef7eb2e8f9f7 2476 HAL_UART_RxCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2477 }
<> 144:ef7eb2e8f9f7 2478
<> 144:ef7eb2e8f9f7 2479 /**
<> 144:ef7eb2e8f9f7 2480 * @brief DMA UART receive process half complete callback.
<> 156:95d6b41a828b 2481 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2482 * @retval None
<> 144:ef7eb2e8f9f7 2483 */
<> 144:ef7eb2e8f9f7 2484 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2485 {
<> 156:95d6b41a828b 2486 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2487
<> 144:ef7eb2e8f9f7 2488 HAL_UART_RxHalfCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2489 }
<> 144:ef7eb2e8f9f7 2490
<> 144:ef7eb2e8f9f7 2491 /**
<> 144:ef7eb2e8f9f7 2492 * @brief DMA UART communication error callback.
<> 156:95d6b41a828b 2493 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2494 * @retval None
<> 144:ef7eb2e8f9f7 2495 */
<> 144:ef7eb2e8f9f7 2496 static void UART_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2497 {
<> 156:95d6b41a828b 2498 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2499
<> 156:95d6b41a828b 2500 /* Stop UART DMA Tx request if ongoing */
<> 156:95d6b41a828b 2501 if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
<> 156:95d6b41a828b 2502 &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
<> 156:95d6b41a828b 2503 {
<> 156:95d6b41a828b 2504 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2505 UART_EndTxTransfer(huart);
<> 156:95d6b41a828b 2506 }
<> 156:95d6b41a828b 2507
<> 156:95d6b41a828b 2508 /* Stop UART DMA Rx request if ongoing */
<> 156:95d6b41a828b 2509 if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
<> 156:95d6b41a828b 2510 &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
<> 156:95d6b41a828b 2511 {
<> 156:95d6b41a828b 2512 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2513 UART_EndRxTransfer(huart);
<> 156:95d6b41a828b 2514 }
<> 156:95d6b41a828b 2515
<> 144:ef7eb2e8f9f7 2516 huart->ErrorCode |= HAL_UART_ERROR_DMA;
<> 144:ef7eb2e8f9f7 2517 HAL_UART_ErrorCallback(huart);
<> 144:ef7eb2e8f9f7 2518 }
<> 144:ef7eb2e8f9f7 2519
<> 144:ef7eb2e8f9f7 2520 /**
<> 156:95d6b41a828b 2521 * @brief DMA UART communication abort callback, when initiated by HAL services on Error
<> 156:95d6b41a828b 2522 * (To be called at end of DMA Abort procedure following error occurrence).
<> 156:95d6b41a828b 2523 * @param hdma DMA handle.
<> 156:95d6b41a828b 2524 * @retval None
<> 156:95d6b41a828b 2525 */
<> 156:95d6b41a828b 2526 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2527 {
<> 156:95d6b41a828b 2528 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2529 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2530 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2531
<> 156:95d6b41a828b 2532 HAL_UART_ErrorCallback(huart);
<> 156:95d6b41a828b 2533 }
<> 156:95d6b41a828b 2534
<> 156:95d6b41a828b 2535 /**
<> 156:95d6b41a828b 2536 * @brief DMA UART Tx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2537 * (To be called at end of DMA Tx Abort procedure following user abort request).
<> 156:95d6b41a828b 2538 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2539 * Abort still ongoing for Rx DMA Handle.
<> 156:95d6b41a828b 2540 * @param hdma DMA handle.
<> 156:95d6b41a828b 2541 * @retval None
<> 156:95d6b41a828b 2542 */
<> 156:95d6b41a828b 2543 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2544 {
<> 156:95d6b41a828b 2545 UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
<> 156:95d6b41a828b 2546
<> 156:95d6b41a828b 2547 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2548
<> 156:95d6b41a828b 2549 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2550 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 2551 {
<> 156:95d6b41a828b 2552 if(huart->hdmarx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2553 {
<> 156:95d6b41a828b 2554 return;
<> 156:95d6b41a828b 2555 }
<> 156:95d6b41a828b 2556 }
<> 156:95d6b41a828b 2557
<> 156:95d6b41a828b 2558 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2559 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2560 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2561
<> 156:95d6b41a828b 2562 /* Reset errorCode */
<> 156:95d6b41a828b 2563 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 2564
<> 156:95d6b41a828b 2565 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2566 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 2567
<> 156:95d6b41a828b 2568 /* Restore huart->gState and huart->RxState to Ready */
<> 156:95d6b41a828b 2569 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2570 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2571
<> 156:95d6b41a828b 2572 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2573 HAL_UART_AbortCpltCallback(huart);
<> 156:95d6b41a828b 2574 }
<> 156:95d6b41a828b 2575
<> 156:95d6b41a828b 2576
<> 156:95d6b41a828b 2577 /**
<> 156:95d6b41a828b 2578 * @brief DMA UART Rx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2579 * (To be called at end of DMA Rx Abort procedure following user abort request).
<> 156:95d6b41a828b 2580 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2581 * Abort still ongoing for Tx DMA Handle.
<> 156:95d6b41a828b 2582 * @param hdma DMA handle.
<> 156:95d6b41a828b 2583 * @retval None
<> 156:95d6b41a828b 2584 */
<> 156:95d6b41a828b 2585 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2586 {
<> 156:95d6b41a828b 2587 UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
<> 156:95d6b41a828b 2588
<> 156:95d6b41a828b 2589 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2590
<> 156:95d6b41a828b 2591 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2592 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 2593 {
<> 156:95d6b41a828b 2594 if(huart->hdmatx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2595 {
<> 156:95d6b41a828b 2596 return;
<> 156:95d6b41a828b 2597 }
<> 156:95d6b41a828b 2598 }
<> 156:95d6b41a828b 2599
<> 156:95d6b41a828b 2600 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2601 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2602 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2603
<> 156:95d6b41a828b 2604 /* Reset errorCode */
<> 156:95d6b41a828b 2605 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 2606
<> 156:95d6b41a828b 2607 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2608 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 2609
<> 156:95d6b41a828b 2610 /* Restore huart->gState and huart->RxState to Ready */
<> 156:95d6b41a828b 2611 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2612 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2613
<> 156:95d6b41a828b 2614 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2615 HAL_UART_AbortCpltCallback(huart);
<> 156:95d6b41a828b 2616 }
<> 156:95d6b41a828b 2617
<> 156:95d6b41a828b 2618
<> 156:95d6b41a828b 2619 /**
<> 156:95d6b41a828b 2620 * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
<> 156:95d6b41a828b 2621 * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
<> 156:95d6b41a828b 2622 * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
<> 156:95d6b41a828b 2623 * and leads to user Tx Abort Complete callback execution).
<> 156:95d6b41a828b 2624 * @param hdma DMA handle.
<> 156:95d6b41a828b 2625 * @retval None
<> 156:95d6b41a828b 2626 */
<> 156:95d6b41a828b 2627 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2628 {
<> 156:95d6b41a828b 2629 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2630
<> 156:95d6b41a828b 2631 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2632
<> 156:95d6b41a828b 2633 /* Restore huart->gState to Ready */
<> 156:95d6b41a828b 2634 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2635
<> 156:95d6b41a828b 2636 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2637 HAL_UART_AbortTransmitCpltCallback(huart);
<> 156:95d6b41a828b 2638 }
<> 156:95d6b41a828b 2639
<> 156:95d6b41a828b 2640 /**
<> 156:95d6b41a828b 2641 * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
<> 156:95d6b41a828b 2642 * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
<> 156:95d6b41a828b 2643 * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
<> 156:95d6b41a828b 2644 * and leads to user Rx Abort Complete callback execution).
<> 156:95d6b41a828b 2645 * @param hdma DMA handle.
<> 156:95d6b41a828b 2646 * @retval None
<> 156:95d6b41a828b 2647 */
<> 156:95d6b41a828b 2648 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2649 {
<> 156:95d6b41a828b 2650 UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 156:95d6b41a828b 2651
<> 156:95d6b41a828b 2652 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2653
<> 156:95d6b41a828b 2654 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2655 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 2656
<> 156:95d6b41a828b 2657 /* Restore huart->RxState to Ready */
<> 156:95d6b41a828b 2658 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2659
<> 156:95d6b41a828b 2660 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2661 HAL_UART_AbortReceiveCpltCallback(huart);
<> 156:95d6b41a828b 2662 }
<> 156:95d6b41a828b 2663
<> 156:95d6b41a828b 2664 /**
<> 156:95d6b41a828b 2665 * @brief Send an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 2666 * @note Function is called under interruption only, once
<> 144:ef7eb2e8f9f7 2667 * interruptions have been enabled by HAL_UART_Transmit_IT().
<> 156:95d6b41a828b 2668 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2669 * @retval HAL status
<> 144:ef7eb2e8f9f7 2670 */
<> 144:ef7eb2e8f9f7 2671 HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2672 {
<> 144:ef7eb2e8f9f7 2673 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 2674
<> 144:ef7eb2e8f9f7 2675 /* Check that a Tx process is ongoing */
<> 144:ef7eb2e8f9f7 2676 if (huart->gState == HAL_UART_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2677 {
<> 156:95d6b41a828b 2678 if(huart->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2679 {
<> 144:ef7eb2e8f9f7 2680 /* Disable the UART Transmit Data Register Empty Interrupt */
<> 156:95d6b41a828b 2681 CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 2682
<> 144:ef7eb2e8f9f7 2683 /* Enable the UART Transmit Complete Interrupt */
<> 156:95d6b41a828b 2684 SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2685
<> 144:ef7eb2e8f9f7 2686 return HAL_OK;
<> 144:ef7eb2e8f9f7 2687 }
<> 144:ef7eb2e8f9f7 2688 else
<> 144:ef7eb2e8f9f7 2689 {
<> 144:ef7eb2e8f9f7 2690 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2691 {
<> 144:ef7eb2e8f9f7 2692 tmp = (uint16_t*) huart->pTxBuffPtr;
<> 156:95d6b41a828b 2693 huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 156:95d6b41a828b 2694 huart->pTxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 2695 }
<> 144:ef7eb2e8f9f7 2696 else
<> 144:ef7eb2e8f9f7 2697 {
<> 156:95d6b41a828b 2698 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 2699 }
<> 144:ef7eb2e8f9f7 2700 huart->TxXferCount--;
<> 144:ef7eb2e8f9f7 2701
<> 144:ef7eb2e8f9f7 2702 return HAL_OK;
<> 144:ef7eb2e8f9f7 2703 }
<> 144:ef7eb2e8f9f7 2704 }
<> 144:ef7eb2e8f9f7 2705 else
<> 144:ef7eb2e8f9f7 2706 {
<> 144:ef7eb2e8f9f7 2707 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2708 }
<> 144:ef7eb2e8f9f7 2709 }
<> 144:ef7eb2e8f9f7 2710
<> 144:ef7eb2e8f9f7 2711 /**
<> 144:ef7eb2e8f9f7 2712 * @brief Wrap up transmission in non-blocking mode.
<> 156:95d6b41a828b 2713 * @param huart pointer to a UART_HandleTypeDef structure that contains
<> 156:95d6b41a828b 2714 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 2715 * @retval HAL status
<> 144:ef7eb2e8f9f7 2716 */
<> 144:ef7eb2e8f9f7 2717 HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2718 {
<> 144:ef7eb2e8f9f7 2719 /* Disable the UART Transmit Complete Interrupt */
<> 156:95d6b41a828b 2720 CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2721
<> 144:ef7eb2e8f9f7 2722 /* Tx process is ended, restore huart->gState to Ready */
<> 144:ef7eb2e8f9f7 2723 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2724
<> 144:ef7eb2e8f9f7 2725 HAL_UART_TxCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2726
<> 144:ef7eb2e8f9f7 2727 return HAL_OK;
<> 144:ef7eb2e8f9f7 2728 }
<> 144:ef7eb2e8f9f7 2729
<> 144:ef7eb2e8f9f7 2730 /**
<> 156:95d6b41a828b 2731 * @brief Receive an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 2732 * @note Function is called under interruption only, once
<> 144:ef7eb2e8f9f7 2733 * interruptions have been enabled by HAL_UART_Receive_IT()
<> 156:95d6b41a828b 2734 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2735 * @retval HAL status
<> 144:ef7eb2e8f9f7 2736 */
<> 144:ef7eb2e8f9f7 2737 HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2738 {
<> 144:ef7eb2e8f9f7 2739 uint16_t* tmp;
<> 156:95d6b41a828b 2740 uint16_t uhMask = huart->Mask;
<> 156:95d6b41a828b 2741 uint16_t uhdata;
<> 144:ef7eb2e8f9f7 2742
<> 144:ef7eb2e8f9f7 2743 /* Check that a Rx process is ongoing */
<> 144:ef7eb2e8f9f7 2744 if(huart->RxState == HAL_UART_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 2745 {
<> 156:95d6b41a828b 2746 uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
<> 144:ef7eb2e8f9f7 2747 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2748 {
<> 144:ef7eb2e8f9f7 2749 tmp = (uint16_t*) huart->pRxBuffPtr ;
<> 156:95d6b41a828b 2750 *tmp = (uint16_t)(uhdata & uhMask);
<> 156:95d6b41a828b 2751 huart->pRxBuffPtr +=2U;
<> 144:ef7eb2e8f9f7 2752 }
<> 144:ef7eb2e8f9f7 2753 else
<> 144:ef7eb2e8f9f7 2754 {
<> 156:95d6b41a828b 2755 *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 2756 }
<> 144:ef7eb2e8f9f7 2757
<> 156:95d6b41a828b 2758 if(--huart->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2759 {
<> 156:95d6b41a828b 2760 /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
<> 156:95d6b41a828b 2761 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 144:ef7eb2e8f9f7 2762
<> 144:ef7eb2e8f9f7 2763 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 2764 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2765
<> 144:ef7eb2e8f9f7 2766 /* Rx process is completed, restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 2767 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2768
<> 144:ef7eb2e8f9f7 2769 HAL_UART_RxCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2770
<> 144:ef7eb2e8f9f7 2771 return HAL_OK;
<> 144:ef7eb2e8f9f7 2772 }
<> 144:ef7eb2e8f9f7 2773
<> 144:ef7eb2e8f9f7 2774 return HAL_OK;
<> 144:ef7eb2e8f9f7 2775 }
<> 144:ef7eb2e8f9f7 2776 else
<> 144:ef7eb2e8f9f7 2777 {
<> 144:ef7eb2e8f9f7 2778 /* Clear RXNE interrupt flag */
<> 144:ef7eb2e8f9f7 2779 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
<> 144:ef7eb2e8f9f7 2780
<> 144:ef7eb2e8f9f7 2781 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2782 }
<> 144:ef7eb2e8f9f7 2783 }
<> 144:ef7eb2e8f9f7 2784
<> 144:ef7eb2e8f9f7 2785 /**
<> 144:ef7eb2e8f9f7 2786 * @}
<> 144:ef7eb2e8f9f7 2787 */
<> 144:ef7eb2e8f9f7 2788
<> 144:ef7eb2e8f9f7 2789 #endif /* HAL_UART_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2790 /**
<> 144:ef7eb2e8f9f7 2791 * @}
<> 144:ef7eb2e8f9f7 2792 */
<> 144:ef7eb2e8f9f7 2793
<> 144:ef7eb2e8f9f7 2794 /**
<> 144:ef7eb2e8f9f7 2795 * @}
<> 144:ef7eb2e8f9f7 2796 */
<> 144:ef7eb2e8f9f7 2797
<> 144:ef7eb2e8f9f7 2798 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/