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mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Parent:: targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c@144:ef7eb2e8f9f7
Child:: 156:95d6b41a828b

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f0xx_hal_tim.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.4.0
<>	144:ef7eb2e8f9f7	6	* @date 27-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief TIM HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Timer (TIM) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Time Base Initialization
<>	144:ef7eb2e8f9f7	11	* + Time Base Start
<>	144:ef7eb2e8f9f7	12	* + Time Base Start Interruption
<>	144:ef7eb2e8f9f7	13	* + Time Base Start DMA
<>	144:ef7eb2e8f9f7	14	* + Time Output Compare/PWM Initialization
<>	144:ef7eb2e8f9f7	15	* + Time Output Compare/PWM Channel Configuration
<>	144:ef7eb2e8f9f7	16	* + Time Output Compare/PWM Start
<>	144:ef7eb2e8f9f7	17	* + Time Output Compare/PWM Start Interruption
<>	144:ef7eb2e8f9f7	18	* + Time Output Compare/PWM Start DMA
<>	144:ef7eb2e8f9f7	19	* + Time Input Capture Initialization
<>	144:ef7eb2e8f9f7	20	* + Time Input Capture Channel Configuration
<>	144:ef7eb2e8f9f7	21	* + Time Input Capture Start
<>	144:ef7eb2e8f9f7	22	* + Time Input Capture Start Interruption
<>	144:ef7eb2e8f9f7	23	* + Time Input Capture Start DMA
<>	144:ef7eb2e8f9f7	24	* + Time One Pulse Initialization
<>	144:ef7eb2e8f9f7	25	* + Time One Pulse Channel Configuration
<>	144:ef7eb2e8f9f7	26	* + Time One Pulse Start
<>	144:ef7eb2e8f9f7	27	* + Time Encoder Interface Initialization
<>	144:ef7eb2e8f9f7	28	* + Time Encoder Interface Start
<>	144:ef7eb2e8f9f7	29	* + Time Encoder Interface Start Interruption
<>	144:ef7eb2e8f9f7	30	* + Time Encoder Interface Start DMA
<>	144:ef7eb2e8f9f7	31	* + Commutation Event configuration with Interruption and DMA
<>	144:ef7eb2e8f9f7	32	* + Time OCRef clear configuration
<>	144:ef7eb2e8f9f7	33	* + Time External Clock configuration
<>	144:ef7eb2e8f9f7	34	@verbatim
<>	144:ef7eb2e8f9f7	35	==============================================================================
<>	144:ef7eb2e8f9f7	36	##### TIMER Generic features #####
<>	144:ef7eb2e8f9f7	37	==============================================================================
<>	144:ef7eb2e8f9f7	38	[..] The Timer features include:
<>	144:ef7eb2e8f9f7	39	(#) 16-bit up, down, up/down auto-reload counter.
<>	144:ef7eb2e8f9f7	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<>	144:ef7eb2e8f9f7	41	counter clock frequency either by any factor between 1 and 65536.
<>	144:ef7eb2e8f9f7	42	(#) Up to 4 independent channels for:
<>	144:ef7eb2e8f9f7	43	(++) Input Capture
<>	144:ef7eb2e8f9f7	44	(++) Output Compare
<>	144:ef7eb2e8f9f7	45	(++) PWM generation (Edge and Center-aligned Mode)
<>	144:ef7eb2e8f9f7	46	(++) One-pulse mode output
<>	144:ef7eb2e8f9f7	47
<>	144:ef7eb2e8f9f7	48	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	49	==============================================================================
<>	144:ef7eb2e8f9f7	50	[..]
<>	144:ef7eb2e8f9f7	51	(#) Initialize the TIM low level resources by implementing the following functions
<>	144:ef7eb2e8f9f7	52	depending from feature used :
<>	144:ef7eb2e8f9f7	53	(++) Time Base : HAL_TIM_Base_MspInit()
<>	144:ef7eb2e8f9f7	54	(++) Input Capture : HAL_TIM_IC_MspInit()
<>	144:ef7eb2e8f9f7	55	(++) Output Compare : HAL_TIM_OC_MspInit()
<>	144:ef7eb2e8f9f7	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
<>	144:ef7eb2e8f9f7	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<>	144:ef7eb2e8f9f7	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	(#) Initialize the TIM low level resources :
<>	144:ef7eb2e8f9f7	61	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	62	(##) TIM pins configuration
<>	144:ef7eb2e8f9f7	63	(+++) Enable the clock for the TIM GPIOs using the following function:
<>	144:ef7eb2e8f9f7	64	__HAL_RCC_GPIOx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	(#) The external Clock can be configured, if needed (the default clock is the
<>	144:ef7eb2e8f9f7	68	internal clock from the APBx), using the following function:
<>	144:ef7eb2e8f9f7	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
<>	144:ef7eb2e8f9f7	70	any start function.
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	(#) Configure the TIM in the desired functioning mode using one of the
<>	144:ef7eb2e8f9f7	73	Initialization function of this driver:
<>	144:ef7eb2e8f9f7	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<>	144:ef7eb2e8f9f7	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<>	144:ef7eb2e8f9f7	76	Output Compare signal.
<>	144:ef7eb2e8f9f7	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<>	144:ef7eb2e8f9f7	78	PWM signal.
<>	144:ef7eb2e8f9f7	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<>	144:ef7eb2e8f9f7	80	external signal.
<>	144:ef7eb2e8f9f7	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<>	144:ef7eb2e8f9f7	82	in One Pulse Mode.
<>	144:ef7eb2e8f9f7	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<>	144:ef7eb2e8f9f7	84
<>	144:ef7eb2e8f9f7	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<>	144:ef7eb2e8f9f7	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<>	144:ef7eb2e8f9f7	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<>	144:ef7eb2e8f9f7	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<>	144:ef7eb2e8f9f7	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<>	144:ef7eb2e8f9f7	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<>	144:ef7eb2e8f9f7	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<>	144:ef7eb2e8f9f7	92
<>	144:ef7eb2e8f9f7	93	(#) The DMA Burst is managed with the two following functions:
<>	144:ef7eb2e8f9f7	94	HAL_TIM_DMABurst_WriteStart()
<>	144:ef7eb2e8f9f7	95	HAL_TIM_DMABurst_ReadStart()
<>	144:ef7eb2e8f9f7	96
<>	144:ef7eb2e8f9f7	97	@endverbatim
<>	144:ef7eb2e8f9f7	98	******************************************************************************
<>	144:ef7eb2e8f9f7	99	* @attention
<>	144:ef7eb2e8f9f7	100	*
<>	144:ef7eb2e8f9f7	101	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	102	*
<>	144:ef7eb2e8f9f7	103	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	104	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	105	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	106	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	108	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	109	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	111	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	112	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	113	*
<>	144:ef7eb2e8f9f7	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	124	*
<>	144:ef7eb2e8f9f7	125	******************************************************************************
<>	144:ef7eb2e8f9f7	126	*/
<>	144:ef7eb2e8f9f7	127
<>	144:ef7eb2e8f9f7	128	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	129	#include "stm32f0xx_hal.h"
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	/** @addtogroup STM32F0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	132	* @{
<>	144:ef7eb2e8f9f7	133	*/
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	/** @defgroup TIM TIM
<>	144:ef7eb2e8f9f7	136	* @brief TIM HAL module driver
<>	144:ef7eb2e8f9f7	137	* @{
<>	144:ef7eb2e8f9f7	138	*/
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	#ifdef HAL_TIM_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	143	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	144	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	145	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	146	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	147
<>	144:ef7eb2e8f9f7	148	/** @defgroup TIM_Private_Functions TIM_Private_Functions
<>	144:ef7eb2e8f9f7	149	* @{
<>	144:ef7eb2e8f9f7	150	*/
<>	144:ef7eb2e8f9f7	151	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	152	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	153	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	154	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	155	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	156	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	157	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	158	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	159	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	160	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	161	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	162	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
<>	144:ef7eb2e8f9f7	163	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	164	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	165	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	166	TIM_SlaveConfigTypeDef * sSlaveConfig);
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	/**
<>	144:ef7eb2e8f9f7	169	* @}
<>	144:ef7eb2e8f9f7	170	*/
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	173
<>	144:ef7eb2e8f9f7	174	/** @defgroup TIM_Exported_Functions TIM Exported Functions
<>	144:ef7eb2e8f9f7	175	* @{
<>	144:ef7eb2e8f9f7	176	*/
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<>	144:ef7eb2e8f9f7	179	* @brief Time Base functions
<>	144:ef7eb2e8f9f7	180	*
<>	144:ef7eb2e8f9f7	181	@verbatim
<>	144:ef7eb2e8f9f7	182	==============================================================================
<>	144:ef7eb2e8f9f7	183	##### Time Base functions #####
<>	144:ef7eb2e8f9f7	184	==============================================================================
<>	144:ef7eb2e8f9f7	185	[..]
<>	144:ef7eb2e8f9f7	186	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	187	(+) Initialize and configure the TIM base.
<>	144:ef7eb2e8f9f7	188	(+) De-initialize the TIM base.
<>	144:ef7eb2e8f9f7	189	(+) Start the Time Base.
<>	144:ef7eb2e8f9f7	190	(+) Stop the Time Base.
<>	144:ef7eb2e8f9f7	191	(+) Start the Time Base and enable interrupt.
<>	144:ef7eb2e8f9f7	192	(+) Stop the Time Base and disable interrupt.
<>	144:ef7eb2e8f9f7	193	(+) Start the Time Base and enable DMA transfer.
<>	144:ef7eb2e8f9f7	194	(+) Stop the Time Base and disable DMA transfer.
<>	144:ef7eb2e8f9f7	195
<>	144:ef7eb2e8f9f7	196	@endverbatim
<>	144:ef7eb2e8f9f7	197	* @{
<>	144:ef7eb2e8f9f7	198	*/
<>	144:ef7eb2e8f9f7	199	/**
<>	144:ef7eb2e8f9f7	200	* @brief Initializes the TIM Time base Unit according to the specified
<>	144:ef7eb2e8f9f7	201	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	202	* @param htim : TIM Base handle
<>	144:ef7eb2e8f9f7	203	* @retval HAL status
<>	144:ef7eb2e8f9f7	204	*/
<>	144:ef7eb2e8f9f7	205	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	206	{
<>	144:ef7eb2e8f9f7	207	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	208	if(htim == NULL)
<>	144:ef7eb2e8f9f7	209	{
<>	144:ef7eb2e8f9f7	210	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	211	}
<>	144:ef7eb2e8f9f7	212
<>	144:ef7eb2e8f9f7	213	/* Check the parameters */
<>	144:ef7eb2e8f9f7	214	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	215	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	216	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	219	{
<>	144:ef7eb2e8f9f7	220	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	221	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	224	HAL_TIM_Base_MspInit(htim);
<>	144:ef7eb2e8f9f7	225	}
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	228	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	229
<>	144:ef7eb2e8f9f7	230	/* Set the Time Base configuration */
<>	144:ef7eb2e8f9f7	231	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	234	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	return HAL_OK;
<>	144:ef7eb2e8f9f7	237	}
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	/**
<>	144:ef7eb2e8f9f7	240	* @brief DeInitializes the TIM Base peripheral
<>	144:ef7eb2e8f9f7	241	* @param htim : TIM Base handle
<>	144:ef7eb2e8f9f7	242	* @retval HAL status
<>	144:ef7eb2e8f9f7	243	*/
<>	144:ef7eb2e8f9f7	244	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	245	{
<>	144:ef7eb2e8f9f7	246	/* Check the parameters */
<>	144:ef7eb2e8f9f7	247	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	252	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	255	HAL_TIM_Base_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	/* Change TIM state */
<>	144:ef7eb2e8f9f7	258	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	/* Release Lock */
<>	144:ef7eb2e8f9f7	261	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	262
<>	144:ef7eb2e8f9f7	263	return HAL_OK;
<>	144:ef7eb2e8f9f7	264	}
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	/**
<>	144:ef7eb2e8f9f7	267	* @brief Initializes the TIM Base MSP.
<>	144:ef7eb2e8f9f7	268	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	269	* @retval None
<>	144:ef7eb2e8f9f7	270	*/
<>	144:ef7eb2e8f9f7	271	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	272	{
<>	144:ef7eb2e8f9f7	273	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	274	UNUSED(htim);
<>	144:ef7eb2e8f9f7	275
<>	144:ef7eb2e8f9f7	276	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	277	the HAL_TIM_Base_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	278	*/
<>	144:ef7eb2e8f9f7	279	}
<>	144:ef7eb2e8f9f7	280
<>	144:ef7eb2e8f9f7	281	/**
<>	144:ef7eb2e8f9f7	282	* @brief DeInitializes TIM Base MSP.
<>	144:ef7eb2e8f9f7	283	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	284	* @retval None
<>	144:ef7eb2e8f9f7	285	*/
<>	144:ef7eb2e8f9f7	286	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	287	{
<>	144:ef7eb2e8f9f7	288	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	289	UNUSED(htim);
<>	144:ef7eb2e8f9f7	290
<>	144:ef7eb2e8f9f7	291	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	292	the HAL_TIM_Base_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	293	*/
<>	144:ef7eb2e8f9f7	294	}
<>	144:ef7eb2e8f9f7	295
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297	/**
<>	144:ef7eb2e8f9f7	298	* @brief Starts the TIM Base generation.
<>	144:ef7eb2e8f9f7	299	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	300	* @retval HAL status
<>	144:ef7eb2e8f9f7	301	*/
<>	144:ef7eb2e8f9f7	302	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	303	{
<>	144:ef7eb2e8f9f7	304	/* Check the parameters */
<>	144:ef7eb2e8f9f7	305	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	306
<>	144:ef7eb2e8f9f7	307	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	308	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	311	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	/* Change the TIM state*/
<>	144:ef7eb2e8f9f7	314	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316	/* Return function status */
<>	144:ef7eb2e8f9f7	317	return HAL_OK;
<>	144:ef7eb2e8f9f7	318	}
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/**
<>	144:ef7eb2e8f9f7	321	* @brief Stops the TIM Base generation.
<>	144:ef7eb2e8f9f7	322	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	323	* @retval HAL status
<>	144:ef7eb2e8f9f7	324	*/
<>	144:ef7eb2e8f9f7	325	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	326	{
<>	144:ef7eb2e8f9f7	327	/* Check the parameters */
<>	144:ef7eb2e8f9f7	328	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	331	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	334	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/* Change the TIM state*/
<>	144:ef7eb2e8f9f7	337	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/* Return function status */
<>	144:ef7eb2e8f9f7	340	return HAL_OK;
<>	144:ef7eb2e8f9f7	341	}
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	/**
<>	144:ef7eb2e8f9f7	344	* @brief Starts the TIM Base generation in interrupt mode.
<>	144:ef7eb2e8f9f7	345	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	346	* @retval HAL status
<>	144:ef7eb2e8f9f7	347	*/
<>	144:ef7eb2e8f9f7	348	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	349	{
<>	144:ef7eb2e8f9f7	350	/* Check the parameters */
<>	144:ef7eb2e8f9f7	351	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	352
<>	144:ef7eb2e8f9f7	353	/* Enable the TIM Update interrupt */
<>	144:ef7eb2e8f9f7	354	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	357	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359	/* Return function status */
<>	144:ef7eb2e8f9f7	360	return HAL_OK;
<>	144:ef7eb2e8f9f7	361	}
<>	144:ef7eb2e8f9f7	362
<>	144:ef7eb2e8f9f7	363	/**
<>	144:ef7eb2e8f9f7	364	* @brief Stops the TIM Base generation in interrupt mode.
<>	144:ef7eb2e8f9f7	365	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	366	* @retval HAL status
<>	144:ef7eb2e8f9f7	367	*/
<>	144:ef7eb2e8f9f7	368	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	369	{
<>	144:ef7eb2e8f9f7	370	/* Check the parameters */
<>	144:ef7eb2e8f9f7	371	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	372	/* Disable the TIM Update interrupt */
<>	144:ef7eb2e8f9f7	373	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	376	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	377
<>	144:ef7eb2e8f9f7	378	/* Return function status */
<>	144:ef7eb2e8f9f7	379	return HAL_OK;
<>	144:ef7eb2e8f9f7	380	}
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/**
<>	144:ef7eb2e8f9f7	383	* @brief Starts the TIM Base generation in DMA mode.
<>	144:ef7eb2e8f9f7	384	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	385	* @param pData : The source Buffer address.
<>	144:ef7eb2e8f9f7	386	* @param Length : The length of data to be transferred from memory to peripheral.
<>	144:ef7eb2e8f9f7	387	* @retval HAL status
<>	144:ef7eb2e8f9f7	388	*/
<>	144:ef7eb2e8f9f7	389	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	390	{
<>	144:ef7eb2e8f9f7	391	/* Check the parameters */
<>	144:ef7eb2e8f9f7	392	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	395	{
<>	144:ef7eb2e8f9f7	396	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	397	}
<>	144:ef7eb2e8f9f7	398	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	399	{
<>	144:ef7eb2e8f9f7	400	if((pData == 0 ) && (Length > 0))
<>	144:ef7eb2e8f9f7	401	{
<>	144:ef7eb2e8f9f7	402	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	403	}
<>	144:ef7eb2e8f9f7	404	else
<>	144:ef7eb2e8f9f7	405	{
<>	144:ef7eb2e8f9f7	406	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	407	}
<>	144:ef7eb2e8f9f7	408	}
<>	144:ef7eb2e8f9f7	409	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	410	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	411
<>	144:ef7eb2e8f9f7	412	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	413	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	414
<>	144:ef7eb2e8f9f7	415	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	416	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/* Enable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	419	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	422	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/* Return function status */
<>	144:ef7eb2e8f9f7	425	return HAL_OK;
<>	144:ef7eb2e8f9f7	426	}
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/**
<>	144:ef7eb2e8f9f7	429	* @brief Stops the TIM Base generation in DMA mode.
<>	144:ef7eb2e8f9f7	430	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	431	* @retval HAL status
<>	144:ef7eb2e8f9f7	432	*/
<>	144:ef7eb2e8f9f7	433	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	434	{
<>	144:ef7eb2e8f9f7	435	/* Check the parameters */
<>	144:ef7eb2e8f9f7	436	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	439	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<>	144:ef7eb2e8f9f7	440
<>	144:ef7eb2e8f9f7	441	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	442	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	/* Change the htim state */
<>	144:ef7eb2e8f9f7	445	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	/* Return function status */
<>	144:ef7eb2e8f9f7	448	return HAL_OK;
<>	144:ef7eb2e8f9f7	449	}
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/**
<>	144:ef7eb2e8f9f7	452	* @}
<>	144:ef7eb2e8f9f7	453	*/
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<>	144:ef7eb2e8f9f7	456	* @brief Time Output Compare functions
<>	144:ef7eb2e8f9f7	457	*
<>	144:ef7eb2e8f9f7	458	@verbatim
<>	144:ef7eb2e8f9f7	459	==============================================================================
<>	144:ef7eb2e8f9f7	460	##### Time Output Compare functions #####
<>	144:ef7eb2e8f9f7	461	==============================================================================
<>	144:ef7eb2e8f9f7	462	[..]
<>	144:ef7eb2e8f9f7	463	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	464	(+) Initialize and configure the TIM Output Compare.
<>	144:ef7eb2e8f9f7	465	(+) De-initialize the TIM Output Compare.
<>	144:ef7eb2e8f9f7	466	(+) Start the Time Output Compare.
<>	144:ef7eb2e8f9f7	467	(+) Stop the Time Output Compare.
<>	144:ef7eb2e8f9f7	468	(+) Start the Time Output Compare and enable interrupt.
<>	144:ef7eb2e8f9f7	469	(+) Stop the Time Output Compare and disable interrupt.
<>	144:ef7eb2e8f9f7	470	(+) Start the Time Output Compare and enable DMA transfer.
<>	144:ef7eb2e8f9f7	471	(+) Stop the Time Output Compare and disable DMA transfer.
<>	144:ef7eb2e8f9f7	472
<>	144:ef7eb2e8f9f7	473	@endverbatim
<>	144:ef7eb2e8f9f7	474	* @{
<>	144:ef7eb2e8f9f7	475	*/
<>	144:ef7eb2e8f9f7	476	/**
<>	144:ef7eb2e8f9f7	477	* @brief Initializes the TIM Output Compare according to the specified
<>	144:ef7eb2e8f9f7	478	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	479	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	480	* @retval HAL status
<>	144:ef7eb2e8f9f7	481	*/
<>	144:ef7eb2e8f9f7	482	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<>	144:ef7eb2e8f9f7	483	{
<>	144:ef7eb2e8f9f7	484	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	485	if(htim == NULL)
<>	144:ef7eb2e8f9f7	486	{
<>	144:ef7eb2e8f9f7	487	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	488	}
<>	144:ef7eb2e8f9f7	489
<>	144:ef7eb2e8f9f7	490	/* Check the parameters */
<>	144:ef7eb2e8f9f7	491	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	492	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	493	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	494
<>	144:ef7eb2e8f9f7	495	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	496	{
<>	144:ef7eb2e8f9f7	497	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	498	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	499
<>	144:ef7eb2e8f9f7	500	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	501	HAL_TIM_OC_MspInit(htim);
<>	144:ef7eb2e8f9f7	502	}
<>	144:ef7eb2e8f9f7	503
<>	144:ef7eb2e8f9f7	504	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	505	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	/* Init the base time for the Output Compare */
<>	144:ef7eb2e8f9f7	508	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	509
<>	144:ef7eb2e8f9f7	510	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	511	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	return HAL_OK;
<>	144:ef7eb2e8f9f7	514	}
<>	144:ef7eb2e8f9f7	515
<>	144:ef7eb2e8f9f7	516	/**
<>	144:ef7eb2e8f9f7	517	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	518	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	519	* @retval HAL status
<>	144:ef7eb2e8f9f7	520	*/
<>	144:ef7eb2e8f9f7	521	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	522	{
<>	144:ef7eb2e8f9f7	523	/* Check the parameters */
<>	144:ef7eb2e8f9f7	524	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	527
<>	144:ef7eb2e8f9f7	528	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	529	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	532	HAL_TIM_OC_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	533
<>	144:ef7eb2e8f9f7	534	/* Change TIM state */
<>	144:ef7eb2e8f9f7	535	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	536
<>	144:ef7eb2e8f9f7	537	/* Release Lock */
<>	144:ef7eb2e8f9f7	538	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	539
<>	144:ef7eb2e8f9f7	540	return HAL_OK;
<>	144:ef7eb2e8f9f7	541	}
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	/**
<>	144:ef7eb2e8f9f7	544	* @brief Initializes the TIM Output Compare MSP.
<>	144:ef7eb2e8f9f7	545	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	546	* @retval None
<>	144:ef7eb2e8f9f7	547	*/
<>	144:ef7eb2e8f9f7	548	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	549	{
<>	144:ef7eb2e8f9f7	550	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	551	UNUSED(htim);
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	554	the HAL_TIM_OC_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	555	*/
<>	144:ef7eb2e8f9f7	556	}
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	/**
<>	144:ef7eb2e8f9f7	559	* @brief DeInitializes TIM Output Compare MSP.
<>	144:ef7eb2e8f9f7	560	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	561	* @retval None
<>	144:ef7eb2e8f9f7	562	*/
<>	144:ef7eb2e8f9f7	563	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	564	{
<>	144:ef7eb2e8f9f7	565	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	566	UNUSED(htim);
<>	144:ef7eb2e8f9f7	567
<>	144:ef7eb2e8f9f7	568	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	569	the HAL_TIM_OC_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	570	*/
<>	144:ef7eb2e8f9f7	571	}
<>	144:ef7eb2e8f9f7	572
<>	144:ef7eb2e8f9f7	573	/**
<>	144:ef7eb2e8f9f7	574	* @brief Starts the TIM Output Compare signal generation.
<>	144:ef7eb2e8f9f7	575	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	576	* @param Channel : TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	577	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	578	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	579	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	580	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	581	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	582	* @retval HAL status
<>	144:ef7eb2e8f9f7	583	*/
<>	144:ef7eb2e8f9f7	584	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	585	{
<>	144:ef7eb2e8f9f7	586	/* Check the parameters */
<>	144:ef7eb2e8f9f7	587	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	590	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	591
<>	144:ef7eb2e8f9f7	592	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	593	{
<>	144:ef7eb2e8f9f7	594	/* Enable the main output */
<>	144:ef7eb2e8f9f7	595	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	596	}
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	599	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	600
<>	144:ef7eb2e8f9f7	601	/* Return function status */
<>	144:ef7eb2e8f9f7	602	return HAL_OK;
<>	144:ef7eb2e8f9f7	603	}
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	/**
<>	144:ef7eb2e8f9f7	606	* @brief Stops the TIM Output Compare signal generation.
<>	144:ef7eb2e8f9f7	607	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	608	* @param Channel : TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	609	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	610	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	611	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	612	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	613	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	614	* @retval HAL status
<>	144:ef7eb2e8f9f7	615	*/
<>	144:ef7eb2e8f9f7	616	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	617	{
<>	144:ef7eb2e8f9f7	618	/* Check the parameters */
<>	144:ef7eb2e8f9f7	619	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	622	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	623
<>	144:ef7eb2e8f9f7	624	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	625	{
<>	144:ef7eb2e8f9f7	626	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	627	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	628	}
<>	144:ef7eb2e8f9f7	629
<>	144:ef7eb2e8f9f7	630	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	631	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	/* Return function status */
<>	144:ef7eb2e8f9f7	634	return HAL_OK;
<>	144:ef7eb2e8f9f7	635	}
<>	144:ef7eb2e8f9f7	636
<>	144:ef7eb2e8f9f7	637	/**
<>	144:ef7eb2e8f9f7	638	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	639	* @param htim : TIM OC handle
<>	144:ef7eb2e8f9f7	640	* @param Channel : TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	641	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	642	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	643	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	644	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	645	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	646	* @retval HAL status
<>	144:ef7eb2e8f9f7	647	*/
<>	144:ef7eb2e8f9f7	648	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	649	{
<>	144:ef7eb2e8f9f7	650	/* Check the parameters */
<>	144:ef7eb2e8f9f7	651	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	switch (Channel)
<>	144:ef7eb2e8f9f7	654	{
<>	144:ef7eb2e8f9f7	655	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	656	{
<>	144:ef7eb2e8f9f7	657	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	658	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	659	}
<>	144:ef7eb2e8f9f7	660	break;
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	663	{
<>	144:ef7eb2e8f9f7	664	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	665	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	666	}
<>	144:ef7eb2e8f9f7	667	break;
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	670	{
<>	144:ef7eb2e8f9f7	671	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	672	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	673	}
<>	144:ef7eb2e8f9f7	674	break;
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	677	{
<>	144:ef7eb2e8f9f7	678	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	679	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	680	}
<>	144:ef7eb2e8f9f7	681	break;
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	default:
<>	144:ef7eb2e8f9f7	684	break;
<>	144:ef7eb2e8f9f7	685	}
<>	144:ef7eb2e8f9f7	686
<>	144:ef7eb2e8f9f7	687	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	688	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	691	{
<>	144:ef7eb2e8f9f7	692	/* Enable the main output */
<>	144:ef7eb2e8f9f7	693	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	694	}
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	697	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	698
<>	144:ef7eb2e8f9f7	699	/* Return function status */
<>	144:ef7eb2e8f9f7	700	return HAL_OK;
<>	144:ef7eb2e8f9f7	701	}
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	/**
<>	144:ef7eb2e8f9f7	704	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	705	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	706	* @param Channel : TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	707	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	708	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	709	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	710	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	711	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	712	* @retval HAL status
<>	144:ef7eb2e8f9f7	713	*/
<>	144:ef7eb2e8f9f7	714	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	715	{
<>	144:ef7eb2e8f9f7	716	/* Check the parameters */
<>	144:ef7eb2e8f9f7	717	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	718
<>	144:ef7eb2e8f9f7	719	switch (Channel)
<>	144:ef7eb2e8f9f7	720	{
<>	144:ef7eb2e8f9f7	721	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	722	{
<>	144:ef7eb2e8f9f7	723	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	724	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	725	}
<>	144:ef7eb2e8f9f7	726	break;
<>	144:ef7eb2e8f9f7	727
<>	144:ef7eb2e8f9f7	728	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	729	{
<>	144:ef7eb2e8f9f7	730	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	731	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	732	}
<>	144:ef7eb2e8f9f7	733	break;
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	736	{
<>	144:ef7eb2e8f9f7	737	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	738	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	739	}
<>	144:ef7eb2e8f9f7	740	break;
<>	144:ef7eb2e8f9f7	741
<>	144:ef7eb2e8f9f7	742	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	743	{
<>	144:ef7eb2e8f9f7	744	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	745	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	746	}
<>	144:ef7eb2e8f9f7	747	break;
<>	144:ef7eb2e8f9f7	748
<>	144:ef7eb2e8f9f7	749	default:
<>	144:ef7eb2e8f9f7	750	break;
<>	144:ef7eb2e8f9f7	751	}
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	754	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	755
<>	144:ef7eb2e8f9f7	756	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	757	{
<>	144:ef7eb2e8f9f7	758	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	759	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	760	}
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	763	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	764
<>	144:ef7eb2e8f9f7	765	/* Return function status */
<>	144:ef7eb2e8f9f7	766	return HAL_OK;
<>	144:ef7eb2e8f9f7	767	}
<>	144:ef7eb2e8f9f7	768
<>	144:ef7eb2e8f9f7	769	/**
<>	144:ef7eb2e8f9f7	770	* @brief Starts the TIM Output Compare signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	771	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	772	* @param Channel : TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	773	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	774	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	775	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	776	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	777	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	778	* @param pData : The source Buffer address.
<>	144:ef7eb2e8f9f7	779	* @param Length : The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	780	* @retval HAL status
<>	144:ef7eb2e8f9f7	781	*/
<>	144:ef7eb2e8f9f7	782	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	783	{
<>	144:ef7eb2e8f9f7	784	/* Check the parameters */
<>	144:ef7eb2e8f9f7	785	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	786
<>	144:ef7eb2e8f9f7	787	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	788	{
<>	144:ef7eb2e8f9f7	789	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	790	}
<>	144:ef7eb2e8f9f7	791	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	792	{
<>	144:ef7eb2e8f9f7	793	if(((uint32_t)pData == 0 ) && (Length > 0))
<>	144:ef7eb2e8f9f7	794	{
<>	144:ef7eb2e8f9f7	795	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	796	}
<>	144:ef7eb2e8f9f7	797	else
<>	144:ef7eb2e8f9f7	798	{
<>	144:ef7eb2e8f9f7	799	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	800	}
<>	144:ef7eb2e8f9f7	801	}
<>	144:ef7eb2e8f9f7	802	switch (Channel)
<>	144:ef7eb2e8f9f7	803	{
<>	144:ef7eb2e8f9f7	804	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	805	{
<>	144:ef7eb2e8f9f7	806	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	807	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	810	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	813	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	814
<>	144:ef7eb2e8f9f7	815	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	816	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	817	}
<>	144:ef7eb2e8f9f7	818	break;
<>	144:ef7eb2e8f9f7	819
<>	144:ef7eb2e8f9f7	820	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	821	{
<>	144:ef7eb2e8f9f7	822	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	823	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	826	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	829	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	830
<>	144:ef7eb2e8f9f7	831	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	832	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	833	}
<>	144:ef7eb2e8f9f7	834	break;
<>	144:ef7eb2e8f9f7	835
<>	144:ef7eb2e8f9f7	836	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	837	{
<>	144:ef7eb2e8f9f7	838	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	839	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	842	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	843
<>	144:ef7eb2e8f9f7	844	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	845	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	846
<>	144:ef7eb2e8f9f7	847	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	848	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	849	}
<>	144:ef7eb2e8f9f7	850	break;
<>	144:ef7eb2e8f9f7	851
<>	144:ef7eb2e8f9f7	852	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	853	{
<>	144:ef7eb2e8f9f7	854	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	855	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	858	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	861	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	864	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	865	}
<>	144:ef7eb2e8f9f7	866	break;
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	default:
<>	144:ef7eb2e8f9f7	869	break;
<>	144:ef7eb2e8f9f7	870	}
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	873	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	876	{
<>	144:ef7eb2e8f9f7	877	/* Enable the main output */
<>	144:ef7eb2e8f9f7	878	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	879	}
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	882	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	/* Return function status */
<>	144:ef7eb2e8f9f7	885	return HAL_OK;
<>	144:ef7eb2e8f9f7	886	}
<>	144:ef7eb2e8f9f7	887
<>	144:ef7eb2e8f9f7	888	/**
<>	144:ef7eb2e8f9f7	889	* @brief Stops the TIM Output Compare signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	890	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	891	* @param Channel : TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	892	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	893	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	894	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	895	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	896	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	897	* @retval HAL status
<>	144:ef7eb2e8f9f7	898	*/
<>	144:ef7eb2e8f9f7	899	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	900	{
<>	144:ef7eb2e8f9f7	901	/* Check the parameters */
<>	144:ef7eb2e8f9f7	902	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	903
<>	144:ef7eb2e8f9f7	904	switch (Channel)
<>	144:ef7eb2e8f9f7	905	{
<>	144:ef7eb2e8f9f7	906	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	907	{
<>	144:ef7eb2e8f9f7	908	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	909	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	910	}
<>	144:ef7eb2e8f9f7	911	break;
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	914	{
<>	144:ef7eb2e8f9f7	915	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	916	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	917	}
<>	144:ef7eb2e8f9f7	918	break;
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	921	{
<>	144:ef7eb2e8f9f7	922	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	923	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	924	}
<>	144:ef7eb2e8f9f7	925	break;
<>	144:ef7eb2e8f9f7	926
<>	144:ef7eb2e8f9f7	927	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	928	{
<>	144:ef7eb2e8f9f7	929	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	930	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	931	}
<>	144:ef7eb2e8f9f7	932	break;
<>	144:ef7eb2e8f9f7	933
<>	144:ef7eb2e8f9f7	934	default:
<>	144:ef7eb2e8f9f7	935	break;
<>	144:ef7eb2e8f9f7	936	}
<>	144:ef7eb2e8f9f7	937
<>	144:ef7eb2e8f9f7	938	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	939	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	940
<>	144:ef7eb2e8f9f7	941	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	942	{
<>	144:ef7eb2e8f9f7	943	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	944	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	945	}
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	948	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	/* Change the htim state */
<>	144:ef7eb2e8f9f7	951	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	952
<>	144:ef7eb2e8f9f7	953	/* Return function status */
<>	144:ef7eb2e8f9f7	954	return HAL_OK;
<>	144:ef7eb2e8f9f7	955	}
<>	144:ef7eb2e8f9f7	956
<>	144:ef7eb2e8f9f7	957	/**
<>	144:ef7eb2e8f9f7	958	* @}
<>	144:ef7eb2e8f9f7	959	*/
<>	144:ef7eb2e8f9f7	960
<>	144:ef7eb2e8f9f7	961	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<>	144:ef7eb2e8f9f7	962	* @brief Time PWM functions
<>	144:ef7eb2e8f9f7	963	*
<>	144:ef7eb2e8f9f7	964	@verbatim
<>	144:ef7eb2e8f9f7	965	==============================================================================
<>	144:ef7eb2e8f9f7	966	##### Time PWM functions #####
<>	144:ef7eb2e8f9f7	967	==============================================================================
<>	144:ef7eb2e8f9f7	968	[..]
<>	144:ef7eb2e8f9f7	969	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	970	(+) Initialize and configure the TIM OPWM.
<>	144:ef7eb2e8f9f7	971	(+) De-initialize the TIM PWM.
<>	144:ef7eb2e8f9f7	972	(+) Start the Time PWM.
<>	144:ef7eb2e8f9f7	973	(+) Stop the Time PWM.
<>	144:ef7eb2e8f9f7	974	(+) Start the Time PWM and enable interrupt.
<>	144:ef7eb2e8f9f7	975	(+) Stop the Time PWM and disable interrupt.
<>	144:ef7eb2e8f9f7	976	(+) Start the Time PWM and enable DMA transfer.
<>	144:ef7eb2e8f9f7	977	(+) Stop the Time PWM and disable DMA transfer.
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	@endverbatim
<>	144:ef7eb2e8f9f7	980	* @{
<>	144:ef7eb2e8f9f7	981	*/
<>	144:ef7eb2e8f9f7	982	/**
<>	144:ef7eb2e8f9f7	983	* @brief Initializes the TIM PWM Time Base according to the specified
<>	144:ef7eb2e8f9f7	984	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	985	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	986	* @retval HAL status
<>	144:ef7eb2e8f9f7	987	*/
<>	144:ef7eb2e8f9f7	988	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	989	{
<>	144:ef7eb2e8f9f7	990	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	991	if(htim == NULL)
<>	144:ef7eb2e8f9f7	992	{
<>	144:ef7eb2e8f9f7	993	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	994	}
<>	144:ef7eb2e8f9f7	995
<>	144:ef7eb2e8f9f7	996	/* Check the parameters */
<>	144:ef7eb2e8f9f7	997	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	998	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	999	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1002	{
<>	144:ef7eb2e8f9f7	1003	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1004	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1007	HAL_TIM_PWM_MspInit(htim);
<>	144:ef7eb2e8f9f7	1008	}
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1011	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	/* Init the base time for the PWM */
<>	144:ef7eb2e8f9f7	1014	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	1017	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1018
<>	144:ef7eb2e8f9f7	1019	return HAL_OK;
<>	144:ef7eb2e8f9f7	1020	}
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022	/**
<>	144:ef7eb2e8f9f7	1023	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	1024	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1025	* @retval HAL status
<>	144:ef7eb2e8f9f7	1026	*/
<>	144:ef7eb2e8f9f7	1027	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1028	{
<>	144:ef7eb2e8f9f7	1029	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1030	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1035	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1038	HAL_TIM_PWM_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1039
<>	144:ef7eb2e8f9f7	1040	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1041	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1042
<>	144:ef7eb2e8f9f7	1043	/* Release Lock */
<>	144:ef7eb2e8f9f7	1044	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1045
<>	144:ef7eb2e8f9f7	1046	return HAL_OK;
<>	144:ef7eb2e8f9f7	1047	}
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	/**
<>	144:ef7eb2e8f9f7	1050	* @brief Initializes the TIM PWM MSP.
<>	144:ef7eb2e8f9f7	1051	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1052	* @retval None
<>	144:ef7eb2e8f9f7	1053	*/
<>	144:ef7eb2e8f9f7	1054	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1055	{
<>	144:ef7eb2e8f9f7	1056	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1057	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1058
<>	144:ef7eb2e8f9f7	1059	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1060	the HAL_TIM_PWM_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1061	*/
<>	144:ef7eb2e8f9f7	1062	}
<>	144:ef7eb2e8f9f7	1063
<>	144:ef7eb2e8f9f7	1064	/**
<>	144:ef7eb2e8f9f7	1065	* @brief DeInitializes TIM PWM MSP.
<>	144:ef7eb2e8f9f7	1066	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1067	* @retval None
<>	144:ef7eb2e8f9f7	1068	*/
<>	144:ef7eb2e8f9f7	1069	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1070	{
<>	144:ef7eb2e8f9f7	1071	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1072	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1073
<>	144:ef7eb2e8f9f7	1074	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1075	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1076	*/
<>	144:ef7eb2e8f9f7	1077	}
<>	144:ef7eb2e8f9f7	1078
<>	144:ef7eb2e8f9f7	1079	/**
<>	144:ef7eb2e8f9f7	1080	* @brief Starts the PWM signal generation.
<>	144:ef7eb2e8f9f7	1081	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1082	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1083	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1084	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1085	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1086	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1087	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1088	* @retval HAL status
<>	144:ef7eb2e8f9f7	1089	*/
<>	144:ef7eb2e8f9f7	1090	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1091	{
<>	144:ef7eb2e8f9f7	1092	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1093	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1094
<>	144:ef7eb2e8f9f7	1095	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1096	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1097
<>	144:ef7eb2e8f9f7	1098	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1099	{
<>	144:ef7eb2e8f9f7	1100	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1101	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1102	}
<>	144:ef7eb2e8f9f7	1103
<>	144:ef7eb2e8f9f7	1104	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1105	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1106
<>	144:ef7eb2e8f9f7	1107	/* Return function status */
<>	144:ef7eb2e8f9f7	1108	return HAL_OK;
<>	144:ef7eb2e8f9f7	1109	}
<>	144:ef7eb2e8f9f7	1110
<>	144:ef7eb2e8f9f7	1111	/**
<>	144:ef7eb2e8f9f7	1112	* @brief Stops the PWM signal generation.
<>	144:ef7eb2e8f9f7	1113	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1114	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1115	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1116	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1117	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1118	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1119	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1120	* @retval HAL status
<>	144:ef7eb2e8f9f7	1121	*/
<>	144:ef7eb2e8f9f7	1122	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1123	{
<>	144:ef7eb2e8f9f7	1124	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1125	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1126
<>	144:ef7eb2e8f9f7	1127	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1128	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1129
<>	144:ef7eb2e8f9f7	1130	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1131	{
<>	144:ef7eb2e8f9f7	1132	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1133	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1134	}
<>	144:ef7eb2e8f9f7	1135
<>	144:ef7eb2e8f9f7	1136	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1137	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1140	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	/* Return function status */
<>	144:ef7eb2e8f9f7	1143	return HAL_OK;
<>	144:ef7eb2e8f9f7	1144	}
<>	144:ef7eb2e8f9f7	1145
<>	144:ef7eb2e8f9f7	1146	/**
<>	144:ef7eb2e8f9f7	1147	* @brief Starts the PWM signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	1148	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1149	* @param Channel : TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	1150	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1151	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1152	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1153	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1154	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1155	* @retval HAL status
<>	144:ef7eb2e8f9f7	1156	*/
<>	144:ef7eb2e8f9f7	1157	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1158	{
<>	144:ef7eb2e8f9f7	1159	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1160	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1161
<>	144:ef7eb2e8f9f7	1162	switch (Channel)
<>	144:ef7eb2e8f9f7	1163	{
<>	144:ef7eb2e8f9f7	1164	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1165	{
<>	144:ef7eb2e8f9f7	1166	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1167	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1168	}
<>	144:ef7eb2e8f9f7	1169	break;
<>	144:ef7eb2e8f9f7	1170
<>	144:ef7eb2e8f9f7	1171	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1172	{
<>	144:ef7eb2e8f9f7	1173	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1174	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1175	}
<>	144:ef7eb2e8f9f7	1176	break;
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1179	{
<>	144:ef7eb2e8f9f7	1180	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1181	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1182	}
<>	144:ef7eb2e8f9f7	1183	break;
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1186	{
<>	144:ef7eb2e8f9f7	1187	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1188	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1189	}
<>	144:ef7eb2e8f9f7	1190	break;
<>	144:ef7eb2e8f9f7	1191
<>	144:ef7eb2e8f9f7	1192	default:
<>	144:ef7eb2e8f9f7	1193	break;
<>	144:ef7eb2e8f9f7	1194	}
<>	144:ef7eb2e8f9f7	1195
<>	144:ef7eb2e8f9f7	1196	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1197	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1200	{
<>	144:ef7eb2e8f9f7	1201	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1202	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1203	}
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1206	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1207
<>	144:ef7eb2e8f9f7	1208	/* Return function status */
<>	144:ef7eb2e8f9f7	1209	return HAL_OK;
<>	144:ef7eb2e8f9f7	1210	}
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	/**
<>	144:ef7eb2e8f9f7	1213	* @brief Stops the PWM signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	1214	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1215	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1216	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1217	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1218	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1219	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1220	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1221	* @retval HAL status
<>	144:ef7eb2e8f9f7	1222	*/
<>	144:ef7eb2e8f9f7	1223	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1224	{
<>	144:ef7eb2e8f9f7	1225	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1226	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1227
<>	144:ef7eb2e8f9f7	1228	switch (Channel)
<>	144:ef7eb2e8f9f7	1229	{
<>	144:ef7eb2e8f9f7	1230	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1231	{
<>	144:ef7eb2e8f9f7	1232	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1233	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1234	}
<>	144:ef7eb2e8f9f7	1235	break;
<>	144:ef7eb2e8f9f7	1236
<>	144:ef7eb2e8f9f7	1237	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1238	{
<>	144:ef7eb2e8f9f7	1239	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1240	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1241	}
<>	144:ef7eb2e8f9f7	1242	break;
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1245	{
<>	144:ef7eb2e8f9f7	1246	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1247	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1248	}
<>	144:ef7eb2e8f9f7	1249	break;
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1252	{
<>	144:ef7eb2e8f9f7	1253	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1254	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1255	}
<>	144:ef7eb2e8f9f7	1256	break;
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	default:
<>	144:ef7eb2e8f9f7	1259	break;
<>	144:ef7eb2e8f9f7	1260	}
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1263	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1264
<>	144:ef7eb2e8f9f7	1265	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1266	{
<>	144:ef7eb2e8f9f7	1267	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1268	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1269	}
<>	144:ef7eb2e8f9f7	1270
<>	144:ef7eb2e8f9f7	1271	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1272	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	/* Return function status */
<>	144:ef7eb2e8f9f7	1275	return HAL_OK;
<>	144:ef7eb2e8f9f7	1276	}
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	/**
<>	144:ef7eb2e8f9f7	1279	* @brief Starts the TIM PWM signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	1280	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1281	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1282	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1283	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1284	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1285	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1286	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1287	* @param pData : The source Buffer address.
<>	144:ef7eb2e8f9f7	1288	* @param Length : The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	1289	* @retval HAL status
<>	144:ef7eb2e8f9f7	1290	*/
<>	144:ef7eb2e8f9f7	1291	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1292	{
<>	144:ef7eb2e8f9f7	1293	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1294	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1295
<>	144:ef7eb2e8f9f7	1296	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1297	{
<>	144:ef7eb2e8f9f7	1298	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1299	}
<>	144:ef7eb2e8f9f7	1300	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1301	{
<>	144:ef7eb2e8f9f7	1302	if(((uint32_t)pData == 0 ) && (Length > 0))
<>	144:ef7eb2e8f9f7	1303	{
<>	144:ef7eb2e8f9f7	1304	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1305	}
<>	144:ef7eb2e8f9f7	1306	else
<>	144:ef7eb2e8f9f7	1307	{
<>	144:ef7eb2e8f9f7	1308	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1309	}
<>	144:ef7eb2e8f9f7	1310	}
<>	144:ef7eb2e8f9f7	1311	switch (Channel)
<>	144:ef7eb2e8f9f7	1312	{
<>	144:ef7eb2e8f9f7	1313	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1314	{
<>	144:ef7eb2e8f9f7	1315	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1316	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1319	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1320
<>	144:ef7eb2e8f9f7	1321	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1322	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1325	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1326	}
<>	144:ef7eb2e8f9f7	1327	break;
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1330	{
<>	144:ef7eb2e8f9f7	1331	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1332	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1333
<>	144:ef7eb2e8f9f7	1334	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1335	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1336
<>	144:ef7eb2e8f9f7	1337	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1338	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	1339
<>	144:ef7eb2e8f9f7	1340	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1341	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1342	}
<>	144:ef7eb2e8f9f7	1343	break;
<>	144:ef7eb2e8f9f7	1344
<>	144:ef7eb2e8f9f7	1345	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1346	{
<>	144:ef7eb2e8f9f7	1347	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1348	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1351	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1352
<>	144:ef7eb2e8f9f7	1353	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1354	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	1355
<>	144:ef7eb2e8f9f7	1356	/* Enable the TIM Output Capture/Compare 3 request */
<>	144:ef7eb2e8f9f7	1357	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1358	}
<>	144:ef7eb2e8f9f7	1359	break;
<>	144:ef7eb2e8f9f7	1360
<>	144:ef7eb2e8f9f7	1361	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1362	{
<>	144:ef7eb2e8f9f7	1363	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1364	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1365
<>	144:ef7eb2e8f9f7	1366	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1367	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1368
<>	144:ef7eb2e8f9f7	1369	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1370	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	1371
<>	144:ef7eb2e8f9f7	1372	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1373	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1374	}
<>	144:ef7eb2e8f9f7	1375	break;
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	default:
<>	144:ef7eb2e8f9f7	1378	break;
<>	144:ef7eb2e8f9f7	1379	}
<>	144:ef7eb2e8f9f7	1380
<>	144:ef7eb2e8f9f7	1381	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1382	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1383
<>	144:ef7eb2e8f9f7	1384	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1385	{
<>	144:ef7eb2e8f9f7	1386	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1387	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1388	}
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1391	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1392
<>	144:ef7eb2e8f9f7	1393	/* Return function status */
<>	144:ef7eb2e8f9f7	1394	return HAL_OK;
<>	144:ef7eb2e8f9f7	1395	}
<>	144:ef7eb2e8f9f7	1396
<>	144:ef7eb2e8f9f7	1397	/**
<>	144:ef7eb2e8f9f7	1398	* @brief Stops the TIM PWM signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	1399	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1400	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1401	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1402	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1403	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1404	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1405	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1406	* @retval HAL status
<>	144:ef7eb2e8f9f7	1407	*/
<>	144:ef7eb2e8f9f7	1408	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1409	{
<>	144:ef7eb2e8f9f7	1410	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1411	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413	switch (Channel)
<>	144:ef7eb2e8f9f7	1414	{
<>	144:ef7eb2e8f9f7	1415	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1416	{
<>	144:ef7eb2e8f9f7	1417	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1418	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1419	}
<>	144:ef7eb2e8f9f7	1420	break;
<>	144:ef7eb2e8f9f7	1421
<>	144:ef7eb2e8f9f7	1422	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1423	{
<>	144:ef7eb2e8f9f7	1424	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1425	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1426	}
<>	144:ef7eb2e8f9f7	1427	break;
<>	144:ef7eb2e8f9f7	1428
<>	144:ef7eb2e8f9f7	1429	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1430	{
<>	144:ef7eb2e8f9f7	1431	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1432	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1433	}
<>	144:ef7eb2e8f9f7	1434	break;
<>	144:ef7eb2e8f9f7	1435
<>	144:ef7eb2e8f9f7	1436	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1437	{
<>	144:ef7eb2e8f9f7	1438	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1439	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1440	}
<>	144:ef7eb2e8f9f7	1441	break;
<>	144:ef7eb2e8f9f7	1442
<>	144:ef7eb2e8f9f7	1443	default:
<>	144:ef7eb2e8f9f7	1444	break;
<>	144:ef7eb2e8f9f7	1445	}
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1448	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1451	{
<>	144:ef7eb2e8f9f7	1452	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1453	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1454	}
<>	144:ef7eb2e8f9f7	1455
<>	144:ef7eb2e8f9f7	1456	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1457	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1460	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462	/* Return function status */
<>	144:ef7eb2e8f9f7	1463	return HAL_OK;
<>	144:ef7eb2e8f9f7	1464	}
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	/**
<>	144:ef7eb2e8f9f7	1467	* @}
<>	144:ef7eb2e8f9f7	1468	*/
<>	144:ef7eb2e8f9f7	1469
<>	144:ef7eb2e8f9f7	1470	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<>	144:ef7eb2e8f9f7	1471	* @brief Time Input Capture functions
<>	144:ef7eb2e8f9f7	1472	*
<>	144:ef7eb2e8f9f7	1473	@verbatim
<>	144:ef7eb2e8f9f7	1474	==============================================================================
<>	144:ef7eb2e8f9f7	1475	##### Time Input Capture functions #####
<>	144:ef7eb2e8f9f7	1476	==============================================================================
<>	144:ef7eb2e8f9f7	1477	[..]
<>	144:ef7eb2e8f9f7	1478	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1479	(+) Initialize and configure the TIM Input Capture.
<>	144:ef7eb2e8f9f7	1480	(+) De-initialize the TIM Input Capture.
<>	144:ef7eb2e8f9f7	1481	(+) Start the Time Input Capture.
<>	144:ef7eb2e8f9f7	1482	(+) Stop the Time Input Capture.
<>	144:ef7eb2e8f9f7	1483	(+) Start the Time Input Capture and enable interrupt.
<>	144:ef7eb2e8f9f7	1484	(+) Stop the Time Input Capture and disable interrupt.
<>	144:ef7eb2e8f9f7	1485	(+) Start the Time Input Capture and enable DMA transfer.
<>	144:ef7eb2e8f9f7	1486	(+) Stop the Time Input Capture and disable DMA transfer.
<>	144:ef7eb2e8f9f7	1487
<>	144:ef7eb2e8f9f7	1488	@endverbatim
<>	144:ef7eb2e8f9f7	1489	* @{
<>	144:ef7eb2e8f9f7	1490	*/
<>	144:ef7eb2e8f9f7	1491	/**
<>	144:ef7eb2e8f9f7	1492	* @brief Initializes the TIM Input Capture Time base according to the specified
<>	144:ef7eb2e8f9f7	1493	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1494	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1495	* @retval HAL status
<>	144:ef7eb2e8f9f7	1496	*/
<>	144:ef7eb2e8f9f7	1497	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1498	{
<>	144:ef7eb2e8f9f7	1499	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	1500	if(htim == NULL)
<>	144:ef7eb2e8f9f7	1501	{
<>	144:ef7eb2e8f9f7	1502	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1503	}
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1506	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1507	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	1508	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	1509
<>	144:ef7eb2e8f9f7	1510	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1511	{
<>	144:ef7eb2e8f9f7	1512	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1513	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1514
<>	144:ef7eb2e8f9f7	1515	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1516	HAL_TIM_IC_MspInit(htim);
<>	144:ef7eb2e8f9f7	1517	}
<>	144:ef7eb2e8f9f7	1518
<>	144:ef7eb2e8f9f7	1519	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1520	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1521
<>	144:ef7eb2e8f9f7	1522	/* Init the base time for the input capture */
<>	144:ef7eb2e8f9f7	1523	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1524
<>	144:ef7eb2e8f9f7	1525	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	1526	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1527
<>	144:ef7eb2e8f9f7	1528	return HAL_OK;
<>	144:ef7eb2e8f9f7	1529	}
<>	144:ef7eb2e8f9f7	1530
<>	144:ef7eb2e8f9f7	1531	/**
<>	144:ef7eb2e8f9f7	1532	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	1533	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1534	* @retval HAL status
<>	144:ef7eb2e8f9f7	1535	*/
<>	144:ef7eb2e8f9f7	1536	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1537	{
<>	144:ef7eb2e8f9f7	1538	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1539	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1540
<>	144:ef7eb2e8f9f7	1541	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1544	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1547	HAL_TIM_IC_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1550	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	/* Release Lock */
<>	144:ef7eb2e8f9f7	1553	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1554
<>	144:ef7eb2e8f9f7	1555	return HAL_OK;
<>	144:ef7eb2e8f9f7	1556	}
<>	144:ef7eb2e8f9f7	1557
<>	144:ef7eb2e8f9f7	1558	/**
<>	144:ef7eb2e8f9f7	1559	* @brief Initializes the TIM Input Capture MSP.
<>	144:ef7eb2e8f9f7	1560	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1561	* @retval None
<>	144:ef7eb2e8f9f7	1562	*/
<>	144:ef7eb2e8f9f7	1563	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1564	{
<>	144:ef7eb2e8f9f7	1565	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1566	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1567
<>	144:ef7eb2e8f9f7	1568	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1569	the HAL_TIM_IC_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1570	*/
<>	144:ef7eb2e8f9f7	1571	}
<>	144:ef7eb2e8f9f7	1572
<>	144:ef7eb2e8f9f7	1573	/**
<>	144:ef7eb2e8f9f7	1574	* @brief DeInitializes TIM Input Capture MSP.
<>	144:ef7eb2e8f9f7	1575	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1576	* @retval None
<>	144:ef7eb2e8f9f7	1577	*/
<>	144:ef7eb2e8f9f7	1578	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1579	{
<>	144:ef7eb2e8f9f7	1580	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1581	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1582
<>	144:ef7eb2e8f9f7	1583	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1584	the HAL_TIM_IC_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1585	*/
<>	144:ef7eb2e8f9f7	1586	}
<>	144:ef7eb2e8f9f7	1587
<>	144:ef7eb2e8f9f7	1588	/**
<>	144:ef7eb2e8f9f7	1589	* @brief Starts the TIM Input Capture measurement.
<>	144:ef7eb2e8f9f7	1590	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1591	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1592	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1593	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1594	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1595	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1596	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1597	* @retval HAL status
<>	144:ef7eb2e8f9f7	1598	*/
<>	144:ef7eb2e8f9f7	1599	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1600	{
<>	144:ef7eb2e8f9f7	1601	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1602	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1603
<>	144:ef7eb2e8f9f7	1604	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1605	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1606
<>	144:ef7eb2e8f9f7	1607	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1608	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1609
<>	144:ef7eb2e8f9f7	1610	/* Return function status */
<>	144:ef7eb2e8f9f7	1611	return HAL_OK;
<>	144:ef7eb2e8f9f7	1612	}
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/**
<>	144:ef7eb2e8f9f7	1615	* @brief Stops the TIM Input Capture measurement.
<>	144:ef7eb2e8f9f7	1616	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1617	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1618	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1619	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1620	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1621	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1622	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1623	* @retval HAL status
<>	144:ef7eb2e8f9f7	1624	*/
<>	144:ef7eb2e8f9f7	1625	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1626	{
<>	144:ef7eb2e8f9f7	1627	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1628	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1629
<>	144:ef7eb2e8f9f7	1630	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1631	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1632
<>	144:ef7eb2e8f9f7	1633	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1634	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1635
<>	144:ef7eb2e8f9f7	1636	/* Return function status */
<>	144:ef7eb2e8f9f7	1637	return HAL_OK;
<>	144:ef7eb2e8f9f7	1638	}
<>	144:ef7eb2e8f9f7	1639
<>	144:ef7eb2e8f9f7	1640	/**
<>	144:ef7eb2e8f9f7	1641	* @brief Starts the TIM Input Capture measurement in interrupt mode.
<>	144:ef7eb2e8f9f7	1642	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1643	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1644	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1645	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1646	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1647	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1648	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1649	* @retval HAL status
<>	144:ef7eb2e8f9f7	1650	*/
<>	144:ef7eb2e8f9f7	1651	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1652	{
<>	144:ef7eb2e8f9f7	1653	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1654	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1655
<>	144:ef7eb2e8f9f7	1656	switch (Channel)
<>	144:ef7eb2e8f9f7	1657	{
<>	144:ef7eb2e8f9f7	1658	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1659	{
<>	144:ef7eb2e8f9f7	1660	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1661	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1662	}
<>	144:ef7eb2e8f9f7	1663	break;
<>	144:ef7eb2e8f9f7	1664
<>	144:ef7eb2e8f9f7	1665	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1666	{
<>	144:ef7eb2e8f9f7	1667	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1668	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1669	}
<>	144:ef7eb2e8f9f7	1670	break;
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1673	{
<>	144:ef7eb2e8f9f7	1674	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1675	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1676	}
<>	144:ef7eb2e8f9f7	1677	break;
<>	144:ef7eb2e8f9f7	1678
<>	144:ef7eb2e8f9f7	1679	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1680	{
<>	144:ef7eb2e8f9f7	1681	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1682	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1683	}
<>	144:ef7eb2e8f9f7	1684	break;
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	default:
<>	144:ef7eb2e8f9f7	1687	break;
<>	144:ef7eb2e8f9f7	1688	}
<>	144:ef7eb2e8f9f7	1689	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1690	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1691
<>	144:ef7eb2e8f9f7	1692	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1693	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/* Return function status */
<>	144:ef7eb2e8f9f7	1696	return HAL_OK;
<>	144:ef7eb2e8f9f7	1697	}
<>	144:ef7eb2e8f9f7	1698
<>	144:ef7eb2e8f9f7	1699	/**
<>	144:ef7eb2e8f9f7	1700	* @brief Stops the TIM Input Capture measurement in interrupt mode.
<>	144:ef7eb2e8f9f7	1701	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1702	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1703	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1704	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1705	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1706	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1707	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1708	* @retval HAL status
<>	144:ef7eb2e8f9f7	1709	*/
<>	144:ef7eb2e8f9f7	1710	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1711	{
<>	144:ef7eb2e8f9f7	1712	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1713	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1714
<>	144:ef7eb2e8f9f7	1715	switch (Channel)
<>	144:ef7eb2e8f9f7	1716	{
<>	144:ef7eb2e8f9f7	1717	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1718	{
<>	144:ef7eb2e8f9f7	1719	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1720	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1721	}
<>	144:ef7eb2e8f9f7	1722	break;
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1725	{
<>	144:ef7eb2e8f9f7	1726	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1727	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1728	}
<>	144:ef7eb2e8f9f7	1729	break;
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1732	{
<>	144:ef7eb2e8f9f7	1733	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1734	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1735	}
<>	144:ef7eb2e8f9f7	1736	break;
<>	144:ef7eb2e8f9f7	1737
<>	144:ef7eb2e8f9f7	1738	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1739	{
<>	144:ef7eb2e8f9f7	1740	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1741	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1742	}
<>	144:ef7eb2e8f9f7	1743	break;
<>	144:ef7eb2e8f9f7	1744
<>	144:ef7eb2e8f9f7	1745	default:
<>	144:ef7eb2e8f9f7	1746	break;
<>	144:ef7eb2e8f9f7	1747	}
<>	144:ef7eb2e8f9f7	1748
<>	144:ef7eb2e8f9f7	1749	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1750	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1751
<>	144:ef7eb2e8f9f7	1752	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1753	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1754
<>	144:ef7eb2e8f9f7	1755	/* Return function status */
<>	144:ef7eb2e8f9f7	1756	return HAL_OK;
<>	144:ef7eb2e8f9f7	1757	}
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	/**
<>	144:ef7eb2e8f9f7	1760	* @brief Starts the TIM Input Capture measurement in DMA mode.
<>	144:ef7eb2e8f9f7	1761	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1762	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1763	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1764	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1765	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1766	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1767	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1768	* @param pData : The destination Buffer address.
<>	144:ef7eb2e8f9f7	1769	* @param Length : The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	1770	* @retval HAL status
<>	144:ef7eb2e8f9f7	1771	*/
<>	144:ef7eb2e8f9f7	1772	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1773	{
<>	144:ef7eb2e8f9f7	1774	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1775	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1776	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1777
<>	144:ef7eb2e8f9f7	1778	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1779	{
<>	144:ef7eb2e8f9f7	1780	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1781	}
<>	144:ef7eb2e8f9f7	1782	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1783	{
<>	144:ef7eb2e8f9f7	1784	if((pData == 0 ) && (Length > 0))
<>	144:ef7eb2e8f9f7	1785	{
<>	144:ef7eb2e8f9f7	1786	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1787	}
<>	144:ef7eb2e8f9f7	1788	else
<>	144:ef7eb2e8f9f7	1789	{
<>	144:ef7eb2e8f9f7	1790	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1791	}
<>	144:ef7eb2e8f9f7	1792	}
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	switch (Channel)
<>	144:ef7eb2e8f9f7	1795	{
<>	144:ef7eb2e8f9f7	1796	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1797	{
<>	144:ef7eb2e8f9f7	1798	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1799	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1800
<>	144:ef7eb2e8f9f7	1801	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1802	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1803
<>	144:ef7eb2e8f9f7	1804	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1805	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1806
<>	144:ef7eb2e8f9f7	1807	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1808	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1809	}
<>	144:ef7eb2e8f9f7	1810	break;
<>	144:ef7eb2e8f9f7	1811
<>	144:ef7eb2e8f9f7	1812	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1813	{
<>	144:ef7eb2e8f9f7	1814	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1815	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1816
<>	144:ef7eb2e8f9f7	1817	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1818	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1819
<>	144:ef7eb2e8f9f7	1820	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1821	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1822
<>	144:ef7eb2e8f9f7	1823	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1824	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1825	}
<>	144:ef7eb2e8f9f7	1826	break;
<>	144:ef7eb2e8f9f7	1827
<>	144:ef7eb2e8f9f7	1828	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1829	{
<>	144:ef7eb2e8f9f7	1830	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1831	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1832
<>	144:ef7eb2e8f9f7	1833	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1834	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1837	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1838
<>	144:ef7eb2e8f9f7	1839	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1840	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1841	}
<>	144:ef7eb2e8f9f7	1842	break;
<>	144:ef7eb2e8f9f7	1843
<>	144:ef7eb2e8f9f7	1844	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1845	{
<>	144:ef7eb2e8f9f7	1846	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1847	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1848
<>	144:ef7eb2e8f9f7	1849	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1850	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1851
<>	144:ef7eb2e8f9f7	1852	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1853	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1854
<>	144:ef7eb2e8f9f7	1855	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1856	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1857	}
<>	144:ef7eb2e8f9f7	1858	break;
<>	144:ef7eb2e8f9f7	1859
<>	144:ef7eb2e8f9f7	1860	default:
<>	144:ef7eb2e8f9f7	1861	break;
<>	144:ef7eb2e8f9f7	1862	}
<>	144:ef7eb2e8f9f7	1863
<>	144:ef7eb2e8f9f7	1864	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1865	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1866
<>	144:ef7eb2e8f9f7	1867	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1868	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1869
<>	144:ef7eb2e8f9f7	1870	/* Return function status */
<>	144:ef7eb2e8f9f7	1871	return HAL_OK;
<>	144:ef7eb2e8f9f7	1872	}
<>	144:ef7eb2e8f9f7	1873
<>	144:ef7eb2e8f9f7	1874	/**
<>	144:ef7eb2e8f9f7	1875	* @brief Stops the TIM Input Capture measurement in DMA mode.
<>	144:ef7eb2e8f9f7	1876	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1877	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1878	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1879	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1880	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1881	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1882	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1883	* @retval HAL status
<>	144:ef7eb2e8f9f7	1884	*/
<>	144:ef7eb2e8f9f7	1885	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1886	{
<>	144:ef7eb2e8f9f7	1887	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1888	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1889	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1890
<>	144:ef7eb2e8f9f7	1891	switch (Channel)
<>	144:ef7eb2e8f9f7	1892	{
<>	144:ef7eb2e8f9f7	1893	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1894	{
<>	144:ef7eb2e8f9f7	1895	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1896	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1897	}
<>	144:ef7eb2e8f9f7	1898	break;
<>	144:ef7eb2e8f9f7	1899
<>	144:ef7eb2e8f9f7	1900	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1901	{
<>	144:ef7eb2e8f9f7	1902	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1903	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1904	}
<>	144:ef7eb2e8f9f7	1905	break;
<>	144:ef7eb2e8f9f7	1906
<>	144:ef7eb2e8f9f7	1907	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1908	{
<>	144:ef7eb2e8f9f7	1909	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1910	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1911	}
<>	144:ef7eb2e8f9f7	1912	break;
<>	144:ef7eb2e8f9f7	1913
<>	144:ef7eb2e8f9f7	1914	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1915	{
<>	144:ef7eb2e8f9f7	1916	/* Disable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1917	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1918	}
<>	144:ef7eb2e8f9f7	1919	break;
<>	144:ef7eb2e8f9f7	1920
<>	144:ef7eb2e8f9f7	1921	default:
<>	144:ef7eb2e8f9f7	1922	break;
<>	144:ef7eb2e8f9f7	1923	}
<>	144:ef7eb2e8f9f7	1924
<>	144:ef7eb2e8f9f7	1925	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1926	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1927
<>	144:ef7eb2e8f9f7	1928	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1929	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1930
<>	144:ef7eb2e8f9f7	1931	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1932	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1933
<>	144:ef7eb2e8f9f7	1934	/* Return function status */
<>	144:ef7eb2e8f9f7	1935	return HAL_OK;
<>	144:ef7eb2e8f9f7	1936	}
<>	144:ef7eb2e8f9f7	1937	/**
<>	144:ef7eb2e8f9f7	1938	* @}
<>	144:ef7eb2e8f9f7	1939	*/
<>	144:ef7eb2e8f9f7	1940
<>	144:ef7eb2e8f9f7	1941	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<>	144:ef7eb2e8f9f7	1942	* @brief Time One Pulse functions
<>	144:ef7eb2e8f9f7	1943	*
<>	144:ef7eb2e8f9f7	1944	@verbatim
<>	144:ef7eb2e8f9f7	1945	==============================================================================
<>	144:ef7eb2e8f9f7	1946	##### Time One Pulse functions #####
<>	144:ef7eb2e8f9f7	1947	==============================================================================
<>	144:ef7eb2e8f9f7	1948	[..]
<>	144:ef7eb2e8f9f7	1949	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1950	(+) Initialize and configure the TIM One Pulse.
<>	144:ef7eb2e8f9f7	1951	(+) De-initialize the TIM One Pulse.
<>	144:ef7eb2e8f9f7	1952	(+) Start the Time One Pulse.
<>	144:ef7eb2e8f9f7	1953	(+) Stop the Time One Pulse.
<>	144:ef7eb2e8f9f7	1954	(+) Start the Time One Pulse and enable interrupt.
<>	144:ef7eb2e8f9f7	1955	(+) Stop the Time One Pulse and disable interrupt.
<>	144:ef7eb2e8f9f7	1956	(+) Start the Time One Pulse and enable DMA transfer.
<>	144:ef7eb2e8f9f7	1957	(+) Stop the Time One Pulse and disable DMA transfer.
<>	144:ef7eb2e8f9f7	1958
<>	144:ef7eb2e8f9f7	1959	@endverbatim
<>	144:ef7eb2e8f9f7	1960	* @{
<>	144:ef7eb2e8f9f7	1961	*/
<>	144:ef7eb2e8f9f7	1962	/**
<>	144:ef7eb2e8f9f7	1963	* @brief Initializes the TIM One Pulse Time Base according to the specified
<>	144:ef7eb2e8f9f7	1964	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1965	* @param htim : TIM OnePulse handle
<>	144:ef7eb2e8f9f7	1966	* @param OnePulseMode : Select the One pulse mode.
<>	144:ef7eb2e8f9f7	1967	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1968	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<>	144:ef7eb2e8f9f7	1969	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
<>	144:ef7eb2e8f9f7	1970	* @retval HAL status
<>	144:ef7eb2e8f9f7	1971	*/
<>	144:ef7eb2e8f9f7	1972	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<>	144:ef7eb2e8f9f7	1973	{
<>	144:ef7eb2e8f9f7	1974	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	1975	if(htim == NULL)
<>	144:ef7eb2e8f9f7	1976	{
<>	144:ef7eb2e8f9f7	1977	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1978	}
<>	144:ef7eb2e8f9f7	1979
<>	144:ef7eb2e8f9f7	1980	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1981	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1982	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	1983	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	1984	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<>	144:ef7eb2e8f9f7	1985
<>	144:ef7eb2e8f9f7	1986	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1987	{
<>	144:ef7eb2e8f9f7	1988	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1989	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1990
<>	144:ef7eb2e8f9f7	1991	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1992	HAL_TIM_OnePulse_MspInit(htim);
<>	144:ef7eb2e8f9f7	1993	}
<>	144:ef7eb2e8f9f7	1994
<>	144:ef7eb2e8f9f7	1995	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1996	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1997
<>	144:ef7eb2e8f9f7	1998	/* Configure the Time base in the One Pulse Mode */
<>	144:ef7eb2e8f9f7	1999	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	2000
<>	144:ef7eb2e8f9f7	2001	/* Reset the OPM Bit */
<>	144:ef7eb2e8f9f7	2002	htim->Instance->CR1 &= ~TIM_CR1_OPM;
<>	144:ef7eb2e8f9f7	2003
<>	144:ef7eb2e8f9f7	2004	/* Configure the OPM Mode */
<>	144:ef7eb2e8f9f7	2005	htim->Instance->CR1 \|= OnePulseMode;
<>	144:ef7eb2e8f9f7	2006
<>	144:ef7eb2e8f9f7	2007	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	2008	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2009
<>	144:ef7eb2e8f9f7	2010	return HAL_OK;
<>	144:ef7eb2e8f9f7	2011	}
<>	144:ef7eb2e8f9f7	2012
<>	144:ef7eb2e8f9f7	2013	/**
<>	144:ef7eb2e8f9f7	2014	* @brief DeInitializes the TIM One Pulse
<>	144:ef7eb2e8f9f7	2015	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2016	* @retval HAL status
<>	144:ef7eb2e8f9f7	2017	*/
<>	144:ef7eb2e8f9f7	2018	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2019	{
<>	144:ef7eb2e8f9f7	2020	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2021	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2022
<>	144:ef7eb2e8f9f7	2023	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2024
<>	144:ef7eb2e8f9f7	2025	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	2026	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2027
<>	144:ef7eb2e8f9f7	2028	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	2029	HAL_TIM_OnePulse_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	2030
<>	144:ef7eb2e8f9f7	2031	/* Change TIM state */
<>	144:ef7eb2e8f9f7	2032	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	2033
<>	144:ef7eb2e8f9f7	2034	/* Release Lock */
<>	144:ef7eb2e8f9f7	2035	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2036
<>	144:ef7eb2e8f9f7	2037	return HAL_OK;
<>	144:ef7eb2e8f9f7	2038	}
<>	144:ef7eb2e8f9f7	2039
<>	144:ef7eb2e8f9f7	2040	/**
<>	144:ef7eb2e8f9f7	2041	* @brief Initializes the TIM One Pulse MSP.
<>	144:ef7eb2e8f9f7	2042	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2043	* @retval None
<>	144:ef7eb2e8f9f7	2044	*/
<>	144:ef7eb2e8f9f7	2045	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2046	{
<>	144:ef7eb2e8f9f7	2047	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2048	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2049
<>	144:ef7eb2e8f9f7	2050	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2051	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2052	*/
<>	144:ef7eb2e8f9f7	2053	}
<>	144:ef7eb2e8f9f7	2054
<>	144:ef7eb2e8f9f7	2055	/**
<>	144:ef7eb2e8f9f7	2056	* @brief DeInitializes TIM One Pulse MSP.
<>	144:ef7eb2e8f9f7	2057	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2058	* @retval None
<>	144:ef7eb2e8f9f7	2059	*/
<>	144:ef7eb2e8f9f7	2060	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2061	{
<>	144:ef7eb2e8f9f7	2062	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2063	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2064
<>	144:ef7eb2e8f9f7	2065	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2066	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2067	*/
<>	144:ef7eb2e8f9f7	2068	}
<>	144:ef7eb2e8f9f7	2069
<>	144:ef7eb2e8f9f7	2070	/**
<>	144:ef7eb2e8f9f7	2071	* @brief Starts the TIM One Pulse signal generation.
<>	144:ef7eb2e8f9f7	2072	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2073	* @param OutputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2074	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2075	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2076	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2077	* @retval HAL status
<>	144:ef7eb2e8f9f7	2078	*/
<>	144:ef7eb2e8f9f7	2079	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2080	{
<>	144:ef7eb2e8f9f7	2081	/* Enable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2082	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2083	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2084	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2085	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	144:ef7eb2e8f9f7	2086
<>	144:ef7eb2e8f9f7	2087	No need to enable the counter, it's enabled automatically by hardware
<>	144:ef7eb2e8f9f7	2088	(the counter starts in response to a stimulus and generate a pulse */
<>	144:ef7eb2e8f9f7	2089
<>	144:ef7eb2e8f9f7	2090	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2091	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2092
<>	144:ef7eb2e8f9f7	2093	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2094	{
<>	144:ef7eb2e8f9f7	2095	/* Enable the main output */
<>	144:ef7eb2e8f9f7	2096	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2097	}
<>	144:ef7eb2e8f9f7	2098
<>	144:ef7eb2e8f9f7	2099	/* Return function status */
<>	144:ef7eb2e8f9f7	2100	return HAL_OK;
<>	144:ef7eb2e8f9f7	2101	}
<>	144:ef7eb2e8f9f7	2102
<>	144:ef7eb2e8f9f7	2103	/**
<>	144:ef7eb2e8f9f7	2104	* @brief Stops the TIM One Pulse signal generation.
<>	144:ef7eb2e8f9f7	2105	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2106	* @param OutputChannel : TIM Channels to be disable
<>	144:ef7eb2e8f9f7	2107	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2108	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2109	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2110	* @retval HAL status
<>	144:ef7eb2e8f9f7	2111	*/
<>	144:ef7eb2e8f9f7	2112	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2113	{
<>	144:ef7eb2e8f9f7	2114	/* Disable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2115	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2116	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2117	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2118	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	144:ef7eb2e8f9f7	2119
<>	144:ef7eb2e8f9f7	2120	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2121	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2122
<>	144:ef7eb2e8f9f7	2123	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2124	{
<>	144:ef7eb2e8f9f7	2125	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	2126	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2127	}
<>	144:ef7eb2e8f9f7	2128
<>	144:ef7eb2e8f9f7	2129	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2130	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2131
<>	144:ef7eb2e8f9f7	2132	/* Return function status */
<>	144:ef7eb2e8f9f7	2133	return HAL_OK;
<>	144:ef7eb2e8f9f7	2134	}
<>	144:ef7eb2e8f9f7	2135
<>	144:ef7eb2e8f9f7	2136	/**
<>	144:ef7eb2e8f9f7	2137	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	2138	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2139	* @param OutputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2140	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2141	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2142	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2143	* @retval HAL status
<>	144:ef7eb2e8f9f7	2144	*/
<>	144:ef7eb2e8f9f7	2145	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2146	{
<>	144:ef7eb2e8f9f7	2147	/* Enable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2148	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2149	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2150	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2151	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	144:ef7eb2e8f9f7	2152
<>	144:ef7eb2e8f9f7	2153	No need to enable the counter, it's enabled automatically by hardware
<>	144:ef7eb2e8f9f7	2154	(the counter starts in response to a stimulus and generate a pulse */
<>	144:ef7eb2e8f9f7	2155
<>	144:ef7eb2e8f9f7	2156	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	2157	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2158
<>	144:ef7eb2e8f9f7	2159	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	2160	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2161
<>	144:ef7eb2e8f9f7	2162	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2163	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2164
<>	144:ef7eb2e8f9f7	2165	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2166	{
<>	144:ef7eb2e8f9f7	2167	/* Enable the main output */
<>	144:ef7eb2e8f9f7	2168	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2169	}
<>	144:ef7eb2e8f9f7	2170
<>	144:ef7eb2e8f9f7	2171	/* Return function status */
<>	144:ef7eb2e8f9f7	2172	return HAL_OK;
<>	144:ef7eb2e8f9f7	2173	}
<>	144:ef7eb2e8f9f7	2174
<>	144:ef7eb2e8f9f7	2175	/**
<>	144:ef7eb2e8f9f7	2176	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	2177	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2178	* @param OutputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2179	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2180	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2181	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2182	* @retval HAL status
<>	144:ef7eb2e8f9f7	2183	*/
<>	144:ef7eb2e8f9f7	2184	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2185	{
<>	144:ef7eb2e8f9f7	2186	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	2187	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2188
<>	144:ef7eb2e8f9f7	2189	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	2190	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2191
<>	144:ef7eb2e8f9f7	2192	/* Disable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2193	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2194	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2195	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2196	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	144:ef7eb2e8f9f7	2197	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2198	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2199
<>	144:ef7eb2e8f9f7	2200	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2201	{
<>	144:ef7eb2e8f9f7	2202	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	2203	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2204	}
<>	144:ef7eb2e8f9f7	2205
<>	144:ef7eb2e8f9f7	2206	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2207	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2208
<>	144:ef7eb2e8f9f7	2209	/* Return function status */
<>	144:ef7eb2e8f9f7	2210	return HAL_OK;
<>	144:ef7eb2e8f9f7	2211	}
<>	144:ef7eb2e8f9f7	2212
<>	144:ef7eb2e8f9f7	2213	/**
<>	144:ef7eb2e8f9f7	2214	* @}
<>	144:ef7eb2e8f9f7	2215	*/
<>	144:ef7eb2e8f9f7	2216
<>	144:ef7eb2e8f9f7	2217	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<>	144:ef7eb2e8f9f7	2218	* @brief Time Encoder functions
<>	144:ef7eb2e8f9f7	2219	*
<>	144:ef7eb2e8f9f7	2220	@verbatim
<>	144:ef7eb2e8f9f7	2221	==============================================================================
<>	144:ef7eb2e8f9f7	2222	##### Time Encoder functions #####
<>	144:ef7eb2e8f9f7	2223	==============================================================================
<>	144:ef7eb2e8f9f7	2224	[..]
<>	144:ef7eb2e8f9f7	2225	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2226	(+) Initialize and configure the TIM Encoder.
<>	144:ef7eb2e8f9f7	2227	(+) De-initialize the TIM Encoder.
<>	144:ef7eb2e8f9f7	2228	(+) Start the Time Encoder.
<>	144:ef7eb2e8f9f7	2229	(+) Stop the Time Encoder.
<>	144:ef7eb2e8f9f7	2230	(+) Start the Time Encoder and enable interrupt.
<>	144:ef7eb2e8f9f7	2231	(+) Stop the Time Encoder and disable interrupt.
<>	144:ef7eb2e8f9f7	2232	(+) Start the Time Encoder and enable DMA transfer.
<>	144:ef7eb2e8f9f7	2233	(+) Stop the Time Encoder and disable DMA transfer.
<>	144:ef7eb2e8f9f7	2234
<>	144:ef7eb2e8f9f7	2235	@endverbatim
<>	144:ef7eb2e8f9f7	2236	* @{
<>	144:ef7eb2e8f9f7	2237	*/
<>	144:ef7eb2e8f9f7	2238	/**
<>	144:ef7eb2e8f9f7	2239	* @brief Initializes the TIM Encoder Interface and create the associated handle.
<>	144:ef7eb2e8f9f7	2240	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2241	* @param sConfig : TIM Encoder Interface configuration structure
<>	144:ef7eb2e8f9f7	2242	* @retval HAL status
<>	144:ef7eb2e8f9f7	2243	*/
<>	144:ef7eb2e8f9f7	2244	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
<>	144:ef7eb2e8f9f7	2245	{
<>	144:ef7eb2e8f9f7	2246	uint32_t tmpsmcr = 0;
<>	144:ef7eb2e8f9f7	2247	uint32_t tmpccmr1 = 0;
<>	144:ef7eb2e8f9f7	2248	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	2249
<>	144:ef7eb2e8f9f7	2250	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	2251	if(htim == NULL)
<>	144:ef7eb2e8f9f7	2252	{
<>	144:ef7eb2e8f9f7	2253	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2254	}
<>	144:ef7eb2e8f9f7	2255
<>	144:ef7eb2e8f9f7	2256	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2257	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2258	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<>	144:ef7eb2e8f9f7	2259	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<>	144:ef7eb2e8f9f7	2260	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<>	144:ef7eb2e8f9f7	2261	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<>	144:ef7eb2e8f9f7	2262	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<>	144:ef7eb2e8f9f7	2263	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<>	144:ef7eb2e8f9f7	2264	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<>	144:ef7eb2e8f9f7	2265	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<>	144:ef7eb2e8f9f7	2266	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<>	144:ef7eb2e8f9f7	2267
<>	144:ef7eb2e8f9f7	2268	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	2269	{
<>	144:ef7eb2e8f9f7	2270	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	2271	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	2272
<>	144:ef7eb2e8f9f7	2273	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	2274	HAL_TIM_Encoder_MspInit(htim);
<>	144:ef7eb2e8f9f7	2275	}
<>	144:ef7eb2e8f9f7	2276
<>	144:ef7eb2e8f9f7	2277	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	2278	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2279
<>	144:ef7eb2e8f9f7	2280	/* Reset the SMS bits */
<>	144:ef7eb2e8f9f7	2281	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	2282
<>	144:ef7eb2e8f9f7	2283	/* Configure the Time base in the Encoder Mode */
<>	144:ef7eb2e8f9f7	2284	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	2285
<>	144:ef7eb2e8f9f7	2286	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	2287	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	2290	tmpccmr1 = htim->Instance->CCMR1;
<>	144:ef7eb2e8f9f7	2291
<>	144:ef7eb2e8f9f7	2292	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	2293	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	2294
<>	144:ef7eb2e8f9f7	2295	/* Set the encoder Mode */
<>	144:ef7eb2e8f9f7	2296	tmpsmcr \|= sConfig->EncoderMode;
<>	144:ef7eb2e8f9f7	2297
<>	144:ef7eb2e8f9f7	2298	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
<>	144:ef7eb2e8f9f7	2299	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
<>	144:ef7eb2e8f9f7	2300	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
<>	144:ef7eb2e8f9f7	2301
<>	144:ef7eb2e8f9f7	2302	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<>	144:ef7eb2e8f9f7	2303	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
<>	144:ef7eb2e8f9f7	2304	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
<>	144:ef7eb2e8f9f7	2305	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
<>	144:ef7eb2e8f9f7	2306	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
<>	144:ef7eb2e8f9f7	2307
<>	144:ef7eb2e8f9f7	2308	/* Set the TI1 and the TI2 Polarities */
<>	144:ef7eb2e8f9f7	2309	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
<>	144:ef7eb2e8f9f7	2310	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
<>	144:ef7eb2e8f9f7	2311	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
<>	144:ef7eb2e8f9f7	2312
<>	144:ef7eb2e8f9f7	2313	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	2314	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	2315
<>	144:ef7eb2e8f9f7	2316	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	2317	htim->Instance->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	2318
<>	144:ef7eb2e8f9f7	2319	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	2320	htim->Instance->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	2321
<>	144:ef7eb2e8f9f7	2322	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	2323	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2324
<>	144:ef7eb2e8f9f7	2325	return HAL_OK;
<>	144:ef7eb2e8f9f7	2326	}
<>	144:ef7eb2e8f9f7	2327
<>	144:ef7eb2e8f9f7	2328
<>	144:ef7eb2e8f9f7	2329	/**
<>	144:ef7eb2e8f9f7	2330	* @brief DeInitializes the TIM Encoder interface
<>	144:ef7eb2e8f9f7	2331	* @param htim : TIM Encoder handle
<>	144:ef7eb2e8f9f7	2332	* @retval HAL status
<>	144:ef7eb2e8f9f7	2333	*/
<>	144:ef7eb2e8f9f7	2334	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2335	{
<>	144:ef7eb2e8f9f7	2336	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2337	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2338
<>	144:ef7eb2e8f9f7	2339	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2340
<>	144:ef7eb2e8f9f7	2341	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	2342	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2343
<>	144:ef7eb2e8f9f7	2344	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	2345	HAL_TIM_Encoder_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	2346
<>	144:ef7eb2e8f9f7	2347	/* Change TIM state */
<>	144:ef7eb2e8f9f7	2348	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	2349
<>	144:ef7eb2e8f9f7	2350	/* Release Lock */
<>	144:ef7eb2e8f9f7	2351	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2352
<>	144:ef7eb2e8f9f7	2353	return HAL_OK;
<>	144:ef7eb2e8f9f7	2354	}
<>	144:ef7eb2e8f9f7	2355
<>	144:ef7eb2e8f9f7	2356	/**
<>	144:ef7eb2e8f9f7	2357	* @brief Initializes the TIM Encoder Interface MSP.
<>	144:ef7eb2e8f9f7	2358	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2359	* @retval None
<>	144:ef7eb2e8f9f7	2360	*/
<>	144:ef7eb2e8f9f7	2361	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2362	{
<>	144:ef7eb2e8f9f7	2363	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2364	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2367	the HAL_TIM_Encoder_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2368	*/
<>	144:ef7eb2e8f9f7	2369	}
<>	144:ef7eb2e8f9f7	2370
<>	144:ef7eb2e8f9f7	2371	/**
<>	144:ef7eb2e8f9f7	2372	* @brief DeInitializes TIM Encoder Interface MSP.
<>	144:ef7eb2e8f9f7	2373	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2374	* @retval None
<>	144:ef7eb2e8f9f7	2375	*/
<>	144:ef7eb2e8f9f7	2376	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2377	{
<>	144:ef7eb2e8f9f7	2378	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2379	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2380
<>	144:ef7eb2e8f9f7	2381	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2382	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2383	*/
<>	144:ef7eb2e8f9f7	2384	}
<>	144:ef7eb2e8f9f7	2385
<>	144:ef7eb2e8f9f7	2386	/**
<>	144:ef7eb2e8f9f7	2387	* @brief Starts the TIM Encoder Interface.
<>	144:ef7eb2e8f9f7	2388	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2389	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2390	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2391	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2392	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2393	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2394	* @retval HAL status
<>	144:ef7eb2e8f9f7	2395	*/
<>	144:ef7eb2e8f9f7	2396	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2397	{
<>	144:ef7eb2e8f9f7	2398	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2399	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2400
<>	144:ef7eb2e8f9f7	2401	/* Enable the encoder interface channels */
<>	144:ef7eb2e8f9f7	2402	switch (Channel)
<>	144:ef7eb2e8f9f7	2403	{
<>	144:ef7eb2e8f9f7	2404	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2405	{
<>	144:ef7eb2e8f9f7	2406	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2407	break;
<>	144:ef7eb2e8f9f7	2408	}
<>	144:ef7eb2e8f9f7	2409	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2410	{
<>	144:ef7eb2e8f9f7	2411	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2412	break;
<>	144:ef7eb2e8f9f7	2413	}
<>	144:ef7eb2e8f9f7	2414	default :
<>	144:ef7eb2e8f9f7	2415	{
<>	144:ef7eb2e8f9f7	2416	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2417	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2418	break;
<>	144:ef7eb2e8f9f7	2419	}
<>	144:ef7eb2e8f9f7	2420	}
<>	144:ef7eb2e8f9f7	2421	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2422	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2423
<>	144:ef7eb2e8f9f7	2424	/* Return function status */
<>	144:ef7eb2e8f9f7	2425	return HAL_OK;
<>	144:ef7eb2e8f9f7	2426	}
<>	144:ef7eb2e8f9f7	2427
<>	144:ef7eb2e8f9f7	2428	/**
<>	144:ef7eb2e8f9f7	2429	* @brief Stops the TIM Encoder Interface.
<>	144:ef7eb2e8f9f7	2430	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2431	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	2432	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2433	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2434	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2435	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2436	* @retval HAL status
<>	144:ef7eb2e8f9f7	2437	*/
<>	144:ef7eb2e8f9f7	2438	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2439	{
<>	144:ef7eb2e8f9f7	2440	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2441	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2442
<>	144:ef7eb2e8f9f7	2443	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2444	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2445	switch (Channel)
<>	144:ef7eb2e8f9f7	2446	{
<>	144:ef7eb2e8f9f7	2447	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2448	{
<>	144:ef7eb2e8f9f7	2449	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2450	break;
<>	144:ef7eb2e8f9f7	2451	}
<>	144:ef7eb2e8f9f7	2452	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2453	{
<>	144:ef7eb2e8f9f7	2454	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2455	break;
<>	144:ef7eb2e8f9f7	2456	}
<>	144:ef7eb2e8f9f7	2457	default :
<>	144:ef7eb2e8f9f7	2458	{
<>	144:ef7eb2e8f9f7	2459	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2460	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2461	break;
<>	144:ef7eb2e8f9f7	2462	}
<>	144:ef7eb2e8f9f7	2463	}
<>	144:ef7eb2e8f9f7	2464
<>	144:ef7eb2e8f9f7	2465	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2466	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2467
<>	144:ef7eb2e8f9f7	2468	/* Return function status */
<>	144:ef7eb2e8f9f7	2469	return HAL_OK;
<>	144:ef7eb2e8f9f7	2470	}
<>	144:ef7eb2e8f9f7	2471
<>	144:ef7eb2e8f9f7	2472	/**
<>	144:ef7eb2e8f9f7	2473	* @brief Starts the TIM Encoder Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	2474	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2475	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2476	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2477	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2478	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2479	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2480	* @retval HAL status
<>	144:ef7eb2e8f9f7	2481	*/
<>	144:ef7eb2e8f9f7	2482	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2483	{
<>	144:ef7eb2e8f9f7	2484	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2485	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2486
<>	144:ef7eb2e8f9f7	2487	/* Enable the encoder interface channels */
<>	144:ef7eb2e8f9f7	2488	/* Enable the capture compare Interrupts 1 and/or 2 */
<>	144:ef7eb2e8f9f7	2489	switch (Channel)
<>	144:ef7eb2e8f9f7	2490	{
<>	144:ef7eb2e8f9f7	2491	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2492	{
<>	144:ef7eb2e8f9f7	2493	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2494	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2495	break;
<>	144:ef7eb2e8f9f7	2496	}
<>	144:ef7eb2e8f9f7	2497	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2498	{
<>	144:ef7eb2e8f9f7	2499	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2500	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2501	break;
<>	144:ef7eb2e8f9f7	2502	}
<>	144:ef7eb2e8f9f7	2503	default :
<>	144:ef7eb2e8f9f7	2504	{
<>	144:ef7eb2e8f9f7	2505	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2506	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2507	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2508	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2509	break;
<>	144:ef7eb2e8f9f7	2510	}
<>	144:ef7eb2e8f9f7	2511	}
<>	144:ef7eb2e8f9f7	2512
<>	144:ef7eb2e8f9f7	2513	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2514	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2515
<>	144:ef7eb2e8f9f7	2516	/* Return function status */
<>	144:ef7eb2e8f9f7	2517	return HAL_OK;
<>	144:ef7eb2e8f9f7	2518	}
<>	144:ef7eb2e8f9f7	2519
<>	144:ef7eb2e8f9f7	2520	/**
<>	144:ef7eb2e8f9f7	2521	* @brief Stops the TIM Encoder Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	2522	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2523	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	2524	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2525	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2526	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2527	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2528	* @retval HAL status
<>	144:ef7eb2e8f9f7	2529	*/
<>	144:ef7eb2e8f9f7	2530	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2531	{
<>	144:ef7eb2e8f9f7	2532	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2533	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2534
<>	144:ef7eb2e8f9f7	2535	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2536	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2537	if(Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2538	{
<>	144:ef7eb2e8f9f7	2539	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2540
<>	144:ef7eb2e8f9f7	2541	/* Disable the capture compare Interrupts 1 */
<>	144:ef7eb2e8f9f7	2542	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2543	}
<>	144:ef7eb2e8f9f7	2544	else if(Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2545	{
<>	144:ef7eb2e8f9f7	2546	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2547
<>	144:ef7eb2e8f9f7	2548	/* Disable the capture compare Interrupts 2 */
<>	144:ef7eb2e8f9f7	2549	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2550	}
<>	144:ef7eb2e8f9f7	2551	else
<>	144:ef7eb2e8f9f7	2552	{
<>	144:ef7eb2e8f9f7	2553	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2554	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2555
<>	144:ef7eb2e8f9f7	2556	/* Disable the capture compare Interrupts 1 and 2 */
<>	144:ef7eb2e8f9f7	2557	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2558	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2559	}
<>	144:ef7eb2e8f9f7	2560
<>	144:ef7eb2e8f9f7	2561	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2562	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2563
<>	144:ef7eb2e8f9f7	2564	/* Change the htim state */
<>	144:ef7eb2e8f9f7	2565	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2566
<>	144:ef7eb2e8f9f7	2567	/* Return function status */
<>	144:ef7eb2e8f9f7	2568	return HAL_OK;
<>	144:ef7eb2e8f9f7	2569	}
<>	144:ef7eb2e8f9f7	2570
<>	144:ef7eb2e8f9f7	2571	/**
<>	144:ef7eb2e8f9f7	2572	* @brief Starts the TIM Encoder Interface in DMA mode.
<>	144:ef7eb2e8f9f7	2573	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2574	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2575	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2576	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2577	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2578	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2579	* @param pData1 : The destination Buffer address for IC1.
<>	144:ef7eb2e8f9f7	2580	* @param pData2 : The destination Buffer address for IC2.
<>	144:ef7eb2e8f9f7	2581	* @param Length : The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	2582	* @retval HAL status
<>	144:ef7eb2e8f9f7	2583	*/
<>	144:ef7eb2e8f9f7	2584	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
<>	144:ef7eb2e8f9f7	2585	{
<>	144:ef7eb2e8f9f7	2586	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2587	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2588
<>	144:ef7eb2e8f9f7	2589	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	2590	{
<>	144:ef7eb2e8f9f7	2591	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2592	}
<>	144:ef7eb2e8f9f7	2593	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	2594	{
<>	144:ef7eb2e8f9f7	2595	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
<>	144:ef7eb2e8f9f7	2596	{
<>	144:ef7eb2e8f9f7	2597	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2598	}
<>	144:ef7eb2e8f9f7	2599	else
<>	144:ef7eb2e8f9f7	2600	{
<>	144:ef7eb2e8f9f7	2601	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2602	}
<>	144:ef7eb2e8f9f7	2603	}
<>	144:ef7eb2e8f9f7	2604
<>	144:ef7eb2e8f9f7	2605	switch (Channel)
<>	144:ef7eb2e8f9f7	2606	{
<>	144:ef7eb2e8f9f7	2607	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2608	{
<>	144:ef7eb2e8f9f7	2609	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2610	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2611
<>	144:ef7eb2e8f9f7	2612	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2613	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2614
<>	144:ef7eb2e8f9f7	2615	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2616	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<>	144:ef7eb2e8f9f7	2617
<>	144:ef7eb2e8f9f7	2618	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2619	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2620
<>	144:ef7eb2e8f9f7	2621	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2622	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2623
<>	144:ef7eb2e8f9f7	2624	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2625	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2626	}
<>	144:ef7eb2e8f9f7	2627	break;
<>	144:ef7eb2e8f9f7	2628
<>	144:ef7eb2e8f9f7	2629	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2630	{
<>	144:ef7eb2e8f9f7	2631	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2632	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2633
<>	144:ef7eb2e8f9f7	2634	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2635	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<>	144:ef7eb2e8f9f7	2636	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2637	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	144:ef7eb2e8f9f7	2638
<>	144:ef7eb2e8f9f7	2639	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2640	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2641
<>	144:ef7eb2e8f9f7	2642	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2643	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2644
<>	144:ef7eb2e8f9f7	2645	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2646	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2647	}
<>	144:ef7eb2e8f9f7	2648	break;
<>	144:ef7eb2e8f9f7	2649
<>	144:ef7eb2e8f9f7	2650	case TIM_CHANNEL_ALL:
<>	144:ef7eb2e8f9f7	2651	{
<>	144:ef7eb2e8f9f7	2652	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2653	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2654
<>	144:ef7eb2e8f9f7	2655	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2656	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2657
<>	144:ef7eb2e8f9f7	2658	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2659	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<>	144:ef7eb2e8f9f7	2660
<>	144:ef7eb2e8f9f7	2661	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2662	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2663
<>	144:ef7eb2e8f9f7	2664	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2665	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2666
<>	144:ef7eb2e8f9f7	2667	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2668	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	144:ef7eb2e8f9f7	2669
<>	144:ef7eb2e8f9f7	2670	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2671	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2672
<>	144:ef7eb2e8f9f7	2673	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2674	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2675	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2676
<>	144:ef7eb2e8f9f7	2677	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2678	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2679	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2680	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2681	}
<>	144:ef7eb2e8f9f7	2682	break;
<>	144:ef7eb2e8f9f7	2683
<>	144:ef7eb2e8f9f7	2684	default:
<>	144:ef7eb2e8f9f7	2685	break;
<>	144:ef7eb2e8f9f7	2686	}
<>	144:ef7eb2e8f9f7	2687	/* Return function status */
<>	144:ef7eb2e8f9f7	2688	return HAL_OK;
<>	144:ef7eb2e8f9f7	2689	}
<>	144:ef7eb2e8f9f7	2690
<>	144:ef7eb2e8f9f7	2691	/**
<>	144:ef7eb2e8f9f7	2692	* @brief Stops the TIM Encoder Interface in DMA mode.
<>	144:ef7eb2e8f9f7	2693	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2694	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2695	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2696	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2697	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2698	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2699	* @retval HAL status
<>	144:ef7eb2e8f9f7	2700	*/
<>	144:ef7eb2e8f9f7	2701	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2702	{
<>	144:ef7eb2e8f9f7	2703	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2704	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2705
<>	144:ef7eb2e8f9f7	2706	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2707	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2708	if(Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2709	{
<>	144:ef7eb2e8f9f7	2710	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2711
<>	144:ef7eb2e8f9f7	2712	/* Disable the capture compare DMA Request 1 */
<>	144:ef7eb2e8f9f7	2713	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2714	}
<>	144:ef7eb2e8f9f7	2715	else if(Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2716	{
<>	144:ef7eb2e8f9f7	2717	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2718
<>	144:ef7eb2e8f9f7	2719	/* Disable the capture compare DMA Request 2 */
<>	144:ef7eb2e8f9f7	2720	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2721	}
<>	144:ef7eb2e8f9f7	2722	else
<>	144:ef7eb2e8f9f7	2723	{
<>	144:ef7eb2e8f9f7	2724	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2725	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2726
<>	144:ef7eb2e8f9f7	2727	/* Disable the capture compare DMA Request 1 and 2 */
<>	144:ef7eb2e8f9f7	2728	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2729	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2730	}
<>	144:ef7eb2e8f9f7	2731
<>	144:ef7eb2e8f9f7	2732	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2733	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2734
<>	144:ef7eb2e8f9f7	2735	/* Change the htim state */
<>	144:ef7eb2e8f9f7	2736	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2737
<>	144:ef7eb2e8f9f7	2738	/* Return function status */
<>	144:ef7eb2e8f9f7	2739	return HAL_OK;
<>	144:ef7eb2e8f9f7	2740	}
<>	144:ef7eb2e8f9f7	2741
<>	144:ef7eb2e8f9f7	2742	/**
<>	144:ef7eb2e8f9f7	2743	* @}
<>	144:ef7eb2e8f9f7	2744	*/
<>	144:ef7eb2e8f9f7	2745	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<>	144:ef7eb2e8f9f7	2746	* @brief IRQ handler management
<>	144:ef7eb2e8f9f7	2747	*
<>	144:ef7eb2e8f9f7	2748	@verbatim
<>	144:ef7eb2e8f9f7	2749	==============================================================================
<>	144:ef7eb2e8f9f7	2750	##### IRQ handler management #####
<>	144:ef7eb2e8f9f7	2751	==============================================================================
<>	144:ef7eb2e8f9f7	2752	[..]
<>	144:ef7eb2e8f9f7	2753	This section provides Timer IRQ handler function.
<>	144:ef7eb2e8f9f7	2754
<>	144:ef7eb2e8f9f7	2755	@endverbatim
<>	144:ef7eb2e8f9f7	2756	* @{
<>	144:ef7eb2e8f9f7	2757	*/
<>	144:ef7eb2e8f9f7	2758	/**
<>	144:ef7eb2e8f9f7	2759	* @brief This function handles TIM interrupts requests.
<>	144:ef7eb2e8f9f7	2760	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2761	* @retval None
<>	144:ef7eb2e8f9f7	2762	*/
<>	144:ef7eb2e8f9f7	2763	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2764	{
<>	144:ef7eb2e8f9f7	2765	/* Capture compare 1 event */
<>	144:ef7eb2e8f9f7	2766	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<>	144:ef7eb2e8f9f7	2767	{
<>	144:ef7eb2e8f9f7	2768	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<>	144:ef7eb2e8f9f7	2769	{
<>	144:ef7eb2e8f9f7	2770	{
<>	144:ef7eb2e8f9f7	2771	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2772	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	2773
<>	144:ef7eb2e8f9f7	2774	/* Input capture event */
<>	144:ef7eb2e8f9f7	2775	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
<>	144:ef7eb2e8f9f7	2776	{
<>	144:ef7eb2e8f9f7	2777	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2778	}
<>	144:ef7eb2e8f9f7	2779	/* Output compare event */
<>	144:ef7eb2e8f9f7	2780	else
<>	144:ef7eb2e8f9f7	2781	{
<>	144:ef7eb2e8f9f7	2782	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2783	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2784	}
<>	144:ef7eb2e8f9f7	2785	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2786	}
<>	144:ef7eb2e8f9f7	2787	}
<>	144:ef7eb2e8f9f7	2788	}
<>	144:ef7eb2e8f9f7	2789	/* Capture compare 2 event */
<>	144:ef7eb2e8f9f7	2790	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<>	144:ef7eb2e8f9f7	2791	{
<>	144:ef7eb2e8f9f7	2792	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<>	144:ef7eb2e8f9f7	2793	{
<>	144:ef7eb2e8f9f7	2794	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2795	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	2796	/* Input capture event */
<>	144:ef7eb2e8f9f7	2797	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
<>	144:ef7eb2e8f9f7	2798	{
<>	144:ef7eb2e8f9f7	2799	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2800	}
<>	144:ef7eb2e8f9f7	2801	/* Output compare event */
<>	144:ef7eb2e8f9f7	2802	else
<>	144:ef7eb2e8f9f7	2803	{
<>	144:ef7eb2e8f9f7	2804	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2805	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2806	}
<>	144:ef7eb2e8f9f7	2807	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2808	}
<>	144:ef7eb2e8f9f7	2809	}
<>	144:ef7eb2e8f9f7	2810	/* Capture compare 3 event */
<>	144:ef7eb2e8f9f7	2811	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<>	144:ef7eb2e8f9f7	2812	{
<>	144:ef7eb2e8f9f7	2813	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<>	144:ef7eb2e8f9f7	2814	{
<>	144:ef7eb2e8f9f7	2815	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	2816	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	2817	/* Input capture event */
<>	144:ef7eb2e8f9f7	2818	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
<>	144:ef7eb2e8f9f7	2819	{
<>	144:ef7eb2e8f9f7	2820	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2821	}
<>	144:ef7eb2e8f9f7	2822	/* Output compare event */
<>	144:ef7eb2e8f9f7	2823	else
<>	144:ef7eb2e8f9f7	2824	{
<>	144:ef7eb2e8f9f7	2825	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2826	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2827	}
<>	144:ef7eb2e8f9f7	2828	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2829	}
<>	144:ef7eb2e8f9f7	2830	}
<>	144:ef7eb2e8f9f7	2831	/* Capture compare 4 event */
<>	144:ef7eb2e8f9f7	2832	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<>	144:ef7eb2e8f9f7	2833	{
<>	144:ef7eb2e8f9f7	2834	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<>	144:ef7eb2e8f9f7	2835	{
<>	144:ef7eb2e8f9f7	2836	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	2837	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	2838	/* Input capture event */
<>	144:ef7eb2e8f9f7	2839	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
<>	144:ef7eb2e8f9f7	2840	{
<>	144:ef7eb2e8f9f7	2841	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2842	}
<>	144:ef7eb2e8f9f7	2843	/* Output compare event */
<>	144:ef7eb2e8f9f7	2844	else
<>	144:ef7eb2e8f9f7	2845	{
<>	144:ef7eb2e8f9f7	2846	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2847	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2848	}
<>	144:ef7eb2e8f9f7	2849	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2850	}
<>	144:ef7eb2e8f9f7	2851	}
<>	144:ef7eb2e8f9f7	2852	/* TIM Update event */
<>	144:ef7eb2e8f9f7	2853	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<>	144:ef7eb2e8f9f7	2854	{
<>	144:ef7eb2e8f9f7	2855	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<>	144:ef7eb2e8f9f7	2856	{
<>	144:ef7eb2e8f9f7	2857	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	2858	HAL_TIM_PeriodElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2859	}
<>	144:ef7eb2e8f9f7	2860	}
<>	144:ef7eb2e8f9f7	2861	/* TIM Break input event */
<>	144:ef7eb2e8f9f7	2862	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
<>	144:ef7eb2e8f9f7	2863	{
<>	144:ef7eb2e8f9f7	2864	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<>	144:ef7eb2e8f9f7	2865	{
<>	144:ef7eb2e8f9f7	2866	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<>	144:ef7eb2e8f9f7	2867	HAL_TIMEx_BreakCallback(htim);
<>	144:ef7eb2e8f9f7	2868	}
<>	144:ef7eb2e8f9f7	2869	}
<>	144:ef7eb2e8f9f7	2870	/* TIM Trigger detection event */
<>	144:ef7eb2e8f9f7	2871	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<>	144:ef7eb2e8f9f7	2872	{
<>	144:ef7eb2e8f9f7	2873	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<>	144:ef7eb2e8f9f7	2874	{
<>	144:ef7eb2e8f9f7	2875	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	2876	HAL_TIM_TriggerCallback(htim);
<>	144:ef7eb2e8f9f7	2877	}
<>	144:ef7eb2e8f9f7	2878	}
<>	144:ef7eb2e8f9f7	2879	/* TIM commutation event */
<>	144:ef7eb2e8f9f7	2880	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
<>	144:ef7eb2e8f9f7	2881	{
<>	144:ef7eb2e8f9f7	2882	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
<>	144:ef7eb2e8f9f7	2883	{
<>	144:ef7eb2e8f9f7	2884	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
<>	144:ef7eb2e8f9f7	2885	HAL_TIMEx_CommutationCallback(htim);
<>	144:ef7eb2e8f9f7	2886	}
<>	144:ef7eb2e8f9f7	2887	}
<>	144:ef7eb2e8f9f7	2888	}
<>	144:ef7eb2e8f9f7	2889
<>	144:ef7eb2e8f9f7	2890	/**
<>	144:ef7eb2e8f9f7	2891	* @}
<>	144:ef7eb2e8f9f7	2892	*/
<>	144:ef7eb2e8f9f7	2893
<>	144:ef7eb2e8f9f7	2894	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<>	144:ef7eb2e8f9f7	2895	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	2896	*
<>	144:ef7eb2e8f9f7	2897	@verbatim
<>	144:ef7eb2e8f9f7	2898	==============================================================================
<>	144:ef7eb2e8f9f7	2899	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	2900	==============================================================================
<>	144:ef7eb2e8f9f7	2901	[..]
<>	144:ef7eb2e8f9f7	2902	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2903	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<>	144:ef7eb2e8f9f7	2904	(+) Configure External Clock source.
<>	144:ef7eb2e8f9f7	2905	(+) Configure Complementary channels, break features and dead time.
<>	144:ef7eb2e8f9f7	2906	(+) Configure Master and the Slave synchronization.
<>	144:ef7eb2e8f9f7	2907	(+) Configure the DMA Burst Mode.
<>	144:ef7eb2e8f9f7	2908
<>	144:ef7eb2e8f9f7	2909	@endverbatim
<>	144:ef7eb2e8f9f7	2910	* @{
<>	144:ef7eb2e8f9f7	2911	*/
<>	144:ef7eb2e8f9f7	2912
<>	144:ef7eb2e8f9f7	2913	/**
<>	144:ef7eb2e8f9f7	2914	* @brief Initializes the TIM Output Compare Channels according to the specified
<>	144:ef7eb2e8f9f7	2915	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	2916	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	2917	* @param sConfig : TIM Output Compare configuration structure
<>	144:ef7eb2e8f9f7	2918	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2919	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2920	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2921	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2922	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	2923	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	2924	* @retval HAL status
<>	144:ef7eb2e8f9f7	2925	*/
<>	144:ef7eb2e8f9f7	2926	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2927	{
<>	144:ef7eb2e8f9f7	2928	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2929	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	2930	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	2931	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	2932
<>	144:ef7eb2e8f9f7	2933	/* Check input state */
<>	144:ef7eb2e8f9f7	2934	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2935
<>	144:ef7eb2e8f9f7	2936	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2937
<>	144:ef7eb2e8f9f7	2938	switch (Channel)
<>	144:ef7eb2e8f9f7	2939	{
<>	144:ef7eb2e8f9f7	2940	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2941	{
<>	144:ef7eb2e8f9f7	2942	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2943	/* Configure the TIM Channel 1 in Output Compare */
<>	144:ef7eb2e8f9f7	2944	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2945	}
<>	144:ef7eb2e8f9f7	2946	break;
<>	144:ef7eb2e8f9f7	2947
<>	144:ef7eb2e8f9f7	2948	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2949	{
<>	144:ef7eb2e8f9f7	2950	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2951	/* Configure the TIM Channel 2 in Output Compare */
<>	144:ef7eb2e8f9f7	2952	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2953	}
<>	144:ef7eb2e8f9f7	2954	break;
<>	144:ef7eb2e8f9f7	2955
<>	144:ef7eb2e8f9f7	2956	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	2957	{
<>	144:ef7eb2e8f9f7	2958	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2959	/* Configure the TIM Channel 3 in Output Compare */
<>	144:ef7eb2e8f9f7	2960	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2961	}
<>	144:ef7eb2e8f9f7	2962	break;
<>	144:ef7eb2e8f9f7	2963
<>	144:ef7eb2e8f9f7	2964	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	2965	{
<>	144:ef7eb2e8f9f7	2966	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2967	/* Configure the TIM Channel 4 in Output Compare */
<>	144:ef7eb2e8f9f7	2968	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2969	}
<>	144:ef7eb2e8f9f7	2970	break;
<>	144:ef7eb2e8f9f7	2971
<>	144:ef7eb2e8f9f7	2972	default:
<>	144:ef7eb2e8f9f7	2973	break;
<>	144:ef7eb2e8f9f7	2974	}
<>	144:ef7eb2e8f9f7	2975	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2976
<>	144:ef7eb2e8f9f7	2977	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2978
<>	144:ef7eb2e8f9f7	2979	return HAL_OK;
<>	144:ef7eb2e8f9f7	2980	}
<>	144:ef7eb2e8f9f7	2981
<>	144:ef7eb2e8f9f7	2982	/**
<>	144:ef7eb2e8f9f7	2983	* @brief Initializes the TIM Input Capture Channels according to the specified
<>	144:ef7eb2e8f9f7	2984	* parameters in the TIM_IC_InitTypeDef.
<>	144:ef7eb2e8f9f7	2985	* @param htim : TIM IC handle
<>	144:ef7eb2e8f9f7	2986	* @param sConfig : TIM Input Capture configuration structure
<>	144:ef7eb2e8f9f7	2987	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2988	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2989	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2990	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2991	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	2992	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	2993	* @retval HAL status
<>	144:ef7eb2e8f9f7	2994	*/
<>	144:ef7eb2e8f9f7	2995	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2996	{
<>	144:ef7eb2e8f9f7	2997	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2998	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2999	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<>	144:ef7eb2e8f9f7	3000	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<>	144:ef7eb2e8f9f7	3001	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<>	144:ef7eb2e8f9f7	3002	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<>	144:ef7eb2e8f9f7	3003
<>	144:ef7eb2e8f9f7	3004	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3005
<>	144:ef7eb2e8f9f7	3006	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3007
<>	144:ef7eb2e8f9f7	3008	if (Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	3009	{
<>	144:ef7eb2e8f9f7	3010	/* TI1 Configuration */
<>	144:ef7eb2e8f9f7	3011	TIM_TI1_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3012	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3013	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3014	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3015
<>	144:ef7eb2e8f9f7	3016	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	3017	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	3018
<>	144:ef7eb2e8f9f7	3019	/* Set the IC1PSC value */
<>	144:ef7eb2e8f9f7	3020	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
<>	144:ef7eb2e8f9f7	3021	}
<>	144:ef7eb2e8f9f7	3022	else if (Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	3023	{
<>	144:ef7eb2e8f9f7	3024	/* TI2 Configuration */
<>	144:ef7eb2e8f9f7	3025	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3026
<>	144:ef7eb2e8f9f7	3027	TIM_TI2_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3028	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3029	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3030	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3031
<>	144:ef7eb2e8f9f7	3032	/* Reset the IC2PSC Bits */
<>	144:ef7eb2e8f9f7	3033	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	144:ef7eb2e8f9f7	3034
<>	144:ef7eb2e8f9f7	3035	/* Set the IC2PSC value */
<>	144:ef7eb2e8f9f7	3036	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
<>	144:ef7eb2e8f9f7	3037	}
<>	144:ef7eb2e8f9f7	3038	else if (Channel == TIM_CHANNEL_3)
<>	144:ef7eb2e8f9f7	3039	{
<>	144:ef7eb2e8f9f7	3040	/* TI3 Configuration */
<>	144:ef7eb2e8f9f7	3041	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3042
<>	144:ef7eb2e8f9f7	3043	TIM_TI3_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3044	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3045	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3046	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3047
<>	144:ef7eb2e8f9f7	3048	/* Reset the IC3PSC Bits */
<>	144:ef7eb2e8f9f7	3049	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<>	144:ef7eb2e8f9f7	3050
<>	144:ef7eb2e8f9f7	3051	/* Set the IC3PSC value */
<>	144:ef7eb2e8f9f7	3052	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
<>	144:ef7eb2e8f9f7	3053	}
<>	144:ef7eb2e8f9f7	3054	else
<>	144:ef7eb2e8f9f7	3055	{
<>	144:ef7eb2e8f9f7	3056	/* TI4 Configuration */
<>	144:ef7eb2e8f9f7	3057	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3058
<>	144:ef7eb2e8f9f7	3059	TIM_TI4_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3060	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3061	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3062	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3063
<>	144:ef7eb2e8f9f7	3064	/* Reset the IC4PSC Bits */
<>	144:ef7eb2e8f9f7	3065	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<>	144:ef7eb2e8f9f7	3066
<>	144:ef7eb2e8f9f7	3067	/* Set the IC4PSC value */
<>	144:ef7eb2e8f9f7	3068	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
<>	144:ef7eb2e8f9f7	3069	}
<>	144:ef7eb2e8f9f7	3070
<>	144:ef7eb2e8f9f7	3071	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3072
<>	144:ef7eb2e8f9f7	3073	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3074
<>	144:ef7eb2e8f9f7	3075	return HAL_OK;
<>	144:ef7eb2e8f9f7	3076	}
<>	144:ef7eb2e8f9f7	3077
<>	144:ef7eb2e8f9f7	3078	/**
<>	144:ef7eb2e8f9f7	3079	* @brief Initializes the TIM PWM channels according to the specified
<>	144:ef7eb2e8f9f7	3080	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	3081	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3082	* @param sConfig : TIM PWM configuration structure
<>	144:ef7eb2e8f9f7	3083	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	3084	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3085	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3086	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3087	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	3088	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	3089	* @retval HAL status
<>	144:ef7eb2e8f9f7	3090	*/
<>	144:ef7eb2e8f9f7	3091	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3092	{
<>	144:ef7eb2e8f9f7	3093	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3094
<>	144:ef7eb2e8f9f7	3095	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3096	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	3097	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	3098	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	3099	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<>	144:ef7eb2e8f9f7	3100
<>	144:ef7eb2e8f9f7	3101	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3102
<>	144:ef7eb2e8f9f7	3103	switch (Channel)
<>	144:ef7eb2e8f9f7	3104	{
<>	144:ef7eb2e8f9f7	3105	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3106	{
<>	144:ef7eb2e8f9f7	3107	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3108	/* Configure the Channel 1 in PWM mode */
<>	144:ef7eb2e8f9f7	3109	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3110
<>	144:ef7eb2e8f9f7	3111	/* Set the Preload enable bit for channel1 */
<>	144:ef7eb2e8f9f7	3112	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
<>	144:ef7eb2e8f9f7	3113
<>	144:ef7eb2e8f9f7	3114	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3115	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<>	144:ef7eb2e8f9f7	3116	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	3117	}
<>	144:ef7eb2e8f9f7	3118	break;
<>	144:ef7eb2e8f9f7	3119
<>	144:ef7eb2e8f9f7	3120	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3121	{
<>	144:ef7eb2e8f9f7	3122	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3123	/* Configure the Channel 2 in PWM mode */
<>	144:ef7eb2e8f9f7	3124	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3125
<>	144:ef7eb2e8f9f7	3126	/* Set the Preload enable bit for channel2 */
<>	144:ef7eb2e8f9f7	3127	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
<>	144:ef7eb2e8f9f7	3128
<>	144:ef7eb2e8f9f7	3129	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3130	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<>	144:ef7eb2e8f9f7	3131	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
<>	144:ef7eb2e8f9f7	3132	}
<>	144:ef7eb2e8f9f7	3133	break;
<>	144:ef7eb2e8f9f7	3134
<>	144:ef7eb2e8f9f7	3135	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3136	{
<>	144:ef7eb2e8f9f7	3137	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3138	/* Configure the Channel 3 in PWM mode */
<>	144:ef7eb2e8f9f7	3139	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3140
<>	144:ef7eb2e8f9f7	3141	/* Set the Preload enable bit for channel3 */
<>	144:ef7eb2e8f9f7	3142	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
<>	144:ef7eb2e8f9f7	3143
<>	144:ef7eb2e8f9f7	3144	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3145	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<>	144:ef7eb2e8f9f7	3146	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	3147	}
<>	144:ef7eb2e8f9f7	3148	break;
<>	144:ef7eb2e8f9f7	3149
<>	144:ef7eb2e8f9f7	3150	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3151	{
<>	144:ef7eb2e8f9f7	3152	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3153	/* Configure the Channel 4 in PWM mode */
<>	144:ef7eb2e8f9f7	3154	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3155
<>	144:ef7eb2e8f9f7	3156	/* Set the Preload enable bit for channel4 */
<>	144:ef7eb2e8f9f7	3157	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
<>	144:ef7eb2e8f9f7	3158
<>	144:ef7eb2e8f9f7	3159	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3160	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<>	144:ef7eb2e8f9f7	3161	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
<>	144:ef7eb2e8f9f7	3162	}
<>	144:ef7eb2e8f9f7	3163	break;
<>	144:ef7eb2e8f9f7	3164
<>	144:ef7eb2e8f9f7	3165	default:
<>	144:ef7eb2e8f9f7	3166	break;
<>	144:ef7eb2e8f9f7	3167	}
<>	144:ef7eb2e8f9f7	3168
<>	144:ef7eb2e8f9f7	3169	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3170
<>	144:ef7eb2e8f9f7	3171	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3172
<>	144:ef7eb2e8f9f7	3173	return HAL_OK;
<>	144:ef7eb2e8f9f7	3174	}
<>	144:ef7eb2e8f9f7	3175
<>	144:ef7eb2e8f9f7	3176	/**
<>	144:ef7eb2e8f9f7	3177	* @brief Initializes the TIM One Pulse Channels according to the specified
<>	144:ef7eb2e8f9f7	3178	* parameters in the TIM_OnePulse_InitTypeDef.
<>	144:ef7eb2e8f9f7	3179	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	3180	* @param sConfig : TIM One Pulse configuration structure
<>	144:ef7eb2e8f9f7	3181	* @param OutputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	3182	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3183	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3184	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3185	* @param InputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	3186	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3187	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3188	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3189	* @retval HAL status
<>	144:ef7eb2e8f9f7	3190	*/
<>	144:ef7eb2e8f9f7	3191	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<>	144:ef7eb2e8f9f7	3192	{
<>	144:ef7eb2e8f9f7	3193	TIM_OC_InitTypeDef temp1;
<>	144:ef7eb2e8f9f7	3194
<>	144:ef7eb2e8f9f7	3195	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3196	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<>	144:ef7eb2e8f9f7	3197	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<>	144:ef7eb2e8f9f7	3198
<>	144:ef7eb2e8f9f7	3199	if(OutputChannel != InputChannel)
<>	144:ef7eb2e8f9f7	3200	{
<>	144:ef7eb2e8f9f7	3201	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3202
<>	144:ef7eb2e8f9f7	3203	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3204
<>	144:ef7eb2e8f9f7	3205	/* Extract the Ouput compare configuration from sConfig structure */
<>	144:ef7eb2e8f9f7	3206	temp1.OCMode = sConfig->OCMode;
<>	144:ef7eb2e8f9f7	3207	temp1.Pulse = sConfig->Pulse;
<>	144:ef7eb2e8f9f7	3208	temp1.OCPolarity = sConfig->OCPolarity;
<>	144:ef7eb2e8f9f7	3209	temp1.OCNPolarity = sConfig->OCNPolarity;
<>	144:ef7eb2e8f9f7	3210	temp1.OCIdleState = sConfig->OCIdleState;
<>	144:ef7eb2e8f9f7	3211	temp1.OCNIdleState = sConfig->OCNIdleState;
<>	144:ef7eb2e8f9f7	3212
<>	144:ef7eb2e8f9f7	3213	switch (OutputChannel)
<>	144:ef7eb2e8f9f7	3214	{
<>	144:ef7eb2e8f9f7	3215	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3216	{
<>	144:ef7eb2e8f9f7	3217	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3218
<>	144:ef7eb2e8f9f7	3219	TIM_OC1_SetConfig(htim->Instance, &temp1);
<>	144:ef7eb2e8f9f7	3220	}
<>	144:ef7eb2e8f9f7	3221	break;
<>	144:ef7eb2e8f9f7	3222	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3223	{
<>	144:ef7eb2e8f9f7	3224	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3225
<>	144:ef7eb2e8f9f7	3226	TIM_OC2_SetConfig(htim->Instance, &temp1);
<>	144:ef7eb2e8f9f7	3227	}
<>	144:ef7eb2e8f9f7	3228	break;
<>	144:ef7eb2e8f9f7	3229	default:
<>	144:ef7eb2e8f9f7	3230	break;
<>	144:ef7eb2e8f9f7	3231	}
<>	144:ef7eb2e8f9f7	3232	switch (InputChannel)
<>	144:ef7eb2e8f9f7	3233	{
<>	144:ef7eb2e8f9f7	3234	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3235	{
<>	144:ef7eb2e8f9f7	3236	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3237
<>	144:ef7eb2e8f9f7	3238	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3239	sConfig->ICSelection, sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3240
<>	144:ef7eb2e8f9f7	3241	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	3242	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	3243
<>	144:ef7eb2e8f9f7	3244	/* Select the Trigger source */
<>	144:ef7eb2e8f9f7	3245	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	3246	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
<>	144:ef7eb2e8f9f7	3247
<>	144:ef7eb2e8f9f7	3248	/* Select the Slave Mode */
<>	144:ef7eb2e8f9f7	3249	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3250	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	144:ef7eb2e8f9f7	3251	}
<>	144:ef7eb2e8f9f7	3252	break;
<>	144:ef7eb2e8f9f7	3253	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3254	{
<>	144:ef7eb2e8f9f7	3255	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3256
<>	144:ef7eb2e8f9f7	3257	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3258	sConfig->ICSelection, sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3259
<>	144:ef7eb2e8f9f7	3260	/* Reset the IC2PSC Bits */
<>	144:ef7eb2e8f9f7	3261	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	144:ef7eb2e8f9f7	3262
<>	144:ef7eb2e8f9f7	3263	/* Select the Trigger source */
<>	144:ef7eb2e8f9f7	3264	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	3265	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
<>	144:ef7eb2e8f9f7	3266
<>	144:ef7eb2e8f9f7	3267	/* Select the Slave Mode */
<>	144:ef7eb2e8f9f7	3268	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3269	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	144:ef7eb2e8f9f7	3270	}
<>	144:ef7eb2e8f9f7	3271	break;
<>	144:ef7eb2e8f9f7	3272
<>	144:ef7eb2e8f9f7	3273	default:
<>	144:ef7eb2e8f9f7	3274	break;
<>	144:ef7eb2e8f9f7	3275	}
<>	144:ef7eb2e8f9f7	3276
<>	144:ef7eb2e8f9f7	3277	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3278
<>	144:ef7eb2e8f9f7	3279	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3280
<>	144:ef7eb2e8f9f7	3281	return HAL_OK;
<>	144:ef7eb2e8f9f7	3282	}
<>	144:ef7eb2e8f9f7	3283	else
<>	144:ef7eb2e8f9f7	3284	{
<>	144:ef7eb2e8f9f7	3285	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3286	}
<>	144:ef7eb2e8f9f7	3287	}
<>	144:ef7eb2e8f9f7	3288
<>	144:ef7eb2e8f9f7	3289	/**
<>	144:ef7eb2e8f9f7	3290	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<>	144:ef7eb2e8f9f7	3291	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3292	* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
<>	144:ef7eb2e8f9f7	3293	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3294	* @arg TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	3295	* @arg TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	3296	* @arg TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	3297	* @arg TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	3298	* @arg TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	3299	* @arg TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	3300	* @arg TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	3301	* @arg TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	3302	* @arg TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	3303	* @arg TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	3304	* @arg TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	3305	* @arg TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	3306	* @arg TIM_DMABASE_RCR
<>	144:ef7eb2e8f9f7	3307	* @arg TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	3308	* @arg TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	3309	* @arg TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	3310	* @arg TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	3311	* @arg TIM_DMABASE_BDTR
<>	144:ef7eb2e8f9f7	3312	* @arg TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	3313	* @param BurstRequestSrc : TIM DMA Request sources
<>	144:ef7eb2e8f9f7	3314	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3315	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	144:ef7eb2e8f9f7	3316	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	144:ef7eb2e8f9f7	3317	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	144:ef7eb2e8f9f7	3318	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	144:ef7eb2e8f9f7	3319	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	144:ef7eb2e8f9f7	3320	* @arg TIM_DMA_COM: TIM Commutation DMA source
<>	144:ef7eb2e8f9f7	3321	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	144:ef7eb2e8f9f7	3322	* @param BurstBuffer : The Buffer address.
<>	144:ef7eb2e8f9f7	3323	* @param BurstLength : DMA Burst length. This parameter can be one value
<>	144:ef7eb2e8f9f7	3324	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<>	144:ef7eb2e8f9f7	3325	* @retval HAL status
<>	144:ef7eb2e8f9f7	3326	*/
<>	144:ef7eb2e8f9f7	3327	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	144:ef7eb2e8f9f7	3328	uint32_t* BurstBuffer, uint32_t BurstLength)
<>	144:ef7eb2e8f9f7	3329	{
<>	144:ef7eb2e8f9f7	3330	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3331	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3332	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	144:ef7eb2e8f9f7	3333	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3334	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	144:ef7eb2e8f9f7	3335
<>	144:ef7eb2e8f9f7	3336	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	3337	{
<>	144:ef7eb2e8f9f7	3338	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3339	}
<>	144:ef7eb2e8f9f7	3340	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	3341	{
<>	144:ef7eb2e8f9f7	3342	if((BurstBuffer == 0 ) && (BurstLength > 0))
<>	144:ef7eb2e8f9f7	3343	{
<>	144:ef7eb2e8f9f7	3344	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3345	}
<>	144:ef7eb2e8f9f7	3346	else
<>	144:ef7eb2e8f9f7	3347	{
<>	144:ef7eb2e8f9f7	3348	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3349	}
<>	144:ef7eb2e8f9f7	3350	}
<>	144:ef7eb2e8f9f7	3351	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3352	{
<>	144:ef7eb2e8f9f7	3353	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3354	{
<>	144:ef7eb2e8f9f7	3355	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3356	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	3357
<>	144:ef7eb2e8f9f7	3358	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3359	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3360
<>	144:ef7eb2e8f9f7	3361	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3362	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3363	}
<>	144:ef7eb2e8f9f7	3364	break;
<>	144:ef7eb2e8f9f7	3365	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3366	{
<>	144:ef7eb2e8f9f7	3367	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3368	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3369
<>	144:ef7eb2e8f9f7	3370	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3371	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3372
<>	144:ef7eb2e8f9f7	3373	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3374	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3375	}
<>	144:ef7eb2e8f9f7	3376	break;
<>	144:ef7eb2e8f9f7	3377	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3378	{
<>	144:ef7eb2e8f9f7	3379	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3380	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3381
<>	144:ef7eb2e8f9f7	3382	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3383	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3384
<>	144:ef7eb2e8f9f7	3385	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3386	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3387	}
<>	144:ef7eb2e8f9f7	3388	break;
<>	144:ef7eb2e8f9f7	3389	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3390	{
<>	144:ef7eb2e8f9f7	3391	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3392	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3393
<>	144:ef7eb2e8f9f7	3394	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3395	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3396
<>	144:ef7eb2e8f9f7	3397	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3398	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3399	}
<>	144:ef7eb2e8f9f7	3400	break;
<>	144:ef7eb2e8f9f7	3401	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3402	{
<>	144:ef7eb2e8f9f7	3403	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3404	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3405
<>	144:ef7eb2e8f9f7	3406	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3407	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3408
<>	144:ef7eb2e8f9f7	3409	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3410	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3411	}
<>	144:ef7eb2e8f9f7	3412	break;
<>	144:ef7eb2e8f9f7	3413	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3414	{
<>	144:ef7eb2e8f9f7	3415	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3416	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<>	144:ef7eb2e8f9f7	3417
<>	144:ef7eb2e8f9f7	3418	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3419	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3420
<>	144:ef7eb2e8f9f7	3421	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3422	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3423	}
<>	144:ef7eb2e8f9f7	3424	break;
<>	144:ef7eb2e8f9f7	3425	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3426	{
<>	144:ef7eb2e8f9f7	3427	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3428	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	144:ef7eb2e8f9f7	3429
<>	144:ef7eb2e8f9f7	3430	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3431	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3432
<>	144:ef7eb2e8f9f7	3433	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3434	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3435	}
<>	144:ef7eb2e8f9f7	3436	break;
<>	144:ef7eb2e8f9f7	3437	default:
<>	144:ef7eb2e8f9f7	3438	break;
<>	144:ef7eb2e8f9f7	3439	}
<>	144:ef7eb2e8f9f7	3440	/* configure the DMA Burst Mode */
<>	144:ef7eb2e8f9f7	3441	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	144:ef7eb2e8f9f7	3442
<>	144:ef7eb2e8f9f7	3443	/* Enable the TIM DMA Request */
<>	144:ef7eb2e8f9f7	3444	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3445
<>	144:ef7eb2e8f9f7	3446	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3447
<>	144:ef7eb2e8f9f7	3448	/* Return function status */
<>	144:ef7eb2e8f9f7	3449	return HAL_OK;
<>	144:ef7eb2e8f9f7	3450	}
<>	144:ef7eb2e8f9f7	3451
<>	144:ef7eb2e8f9f7	3452	/**
<>	144:ef7eb2e8f9f7	3453	* @brief Stops the TIM DMA Burst mode
<>	144:ef7eb2e8f9f7	3454	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3455	* @param BurstRequestSrc : TIM DMA Request sources to disable
<>	144:ef7eb2e8f9f7	3456	* @retval HAL status
<>	144:ef7eb2e8f9f7	3457	*/
<>	144:ef7eb2e8f9f7	3458	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3459	{
<>	144:ef7eb2e8f9f7	3460	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3461	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3462
<>	144:ef7eb2e8f9f7	3463	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	144:ef7eb2e8f9f7	3464	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3465	{
<>	144:ef7eb2e8f9f7	3466	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3467	{
<>	144:ef7eb2e8f9f7	3468	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	144:ef7eb2e8f9f7	3469	}
<>	144:ef7eb2e8f9f7	3470	break;
<>	144:ef7eb2e8f9f7	3471	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3472	{
<>	144:ef7eb2e8f9f7	3473	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	144:ef7eb2e8f9f7	3474	}
<>	144:ef7eb2e8f9f7	3475	break;
<>	144:ef7eb2e8f9f7	3476	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3477	{
<>	144:ef7eb2e8f9f7	3478	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	144:ef7eb2e8f9f7	3479	}
<>	144:ef7eb2e8f9f7	3480	break;
<>	144:ef7eb2e8f9f7	3481	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3482	{
<>	144:ef7eb2e8f9f7	3483	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	144:ef7eb2e8f9f7	3484	}
<>	144:ef7eb2e8f9f7	3485	break;
<>	144:ef7eb2e8f9f7	3486	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3487	{
<>	144:ef7eb2e8f9f7	3488	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	144:ef7eb2e8f9f7	3489	}
<>	144:ef7eb2e8f9f7	3490	break;
<>	144:ef7eb2e8f9f7	3491	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3492	{
<>	144:ef7eb2e8f9f7	3493	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<>	144:ef7eb2e8f9f7	3494	}
<>	144:ef7eb2e8f9f7	3495	break;
<>	144:ef7eb2e8f9f7	3496	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3497	{
<>	144:ef7eb2e8f9f7	3498	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	144:ef7eb2e8f9f7	3499	}
<>	144:ef7eb2e8f9f7	3500	break;
<>	144:ef7eb2e8f9f7	3501	default:
<>	144:ef7eb2e8f9f7	3502	break;
<>	144:ef7eb2e8f9f7	3503	}
<>	144:ef7eb2e8f9f7	3504
<>	144:ef7eb2e8f9f7	3505	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	3506	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3507
<>	144:ef7eb2e8f9f7	3508	/* Return function status */
<>	144:ef7eb2e8f9f7	3509	return HAL_OK;
<>	144:ef7eb2e8f9f7	3510	}
<>	144:ef7eb2e8f9f7	3511
<>	144:ef7eb2e8f9f7	3512	/**
<>	144:ef7eb2e8f9f7	3513	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<>	144:ef7eb2e8f9f7	3514	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3515	* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
<>	144:ef7eb2e8f9f7	3516	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3517	* @arg TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	3518	* @arg TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	3519	* @arg TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	3520	* @arg TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	3521	* @arg TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	3522	* @arg TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	3523	* @arg TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	3524	* @arg TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	3525	* @arg TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	3526	* @arg TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	3527	* @arg TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	3528	* @arg TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	3529	* @arg TIM_DMABASE_RCR
<>	144:ef7eb2e8f9f7	3530	* @arg TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	3531	* @arg TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	3532	* @arg TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	3533	* @arg TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	3534	* @arg TIM_DMABASE_BDTR
<>	144:ef7eb2e8f9f7	3535	* @arg TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	3536	* @param BurstRequestSrc : TIM DMA Request sources
<>	144:ef7eb2e8f9f7	3537	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3538	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	144:ef7eb2e8f9f7	3539	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	144:ef7eb2e8f9f7	3540	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	144:ef7eb2e8f9f7	3541	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	144:ef7eb2e8f9f7	3542	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	144:ef7eb2e8f9f7	3543	* @arg TIM_DMA_COM: TIM Commutation DMA source
<>	144:ef7eb2e8f9f7	3544	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	144:ef7eb2e8f9f7	3545	* @param BurstBuffer : The Buffer address.
<>	144:ef7eb2e8f9f7	3546	* @param BurstLength : DMA Burst length. This parameter can be one value
<>	144:ef7eb2e8f9f7	3547	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<>	144:ef7eb2e8f9f7	3548	* @retval HAL status
<>	144:ef7eb2e8f9f7	3549	*/
<>	144:ef7eb2e8f9f7	3550	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	144:ef7eb2e8f9f7	3551	uint32_t *BurstBuffer, uint32_t BurstLength)
<>	144:ef7eb2e8f9f7	3552	{
<>	144:ef7eb2e8f9f7	3553	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3554	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3555	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	144:ef7eb2e8f9f7	3556	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3557	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	144:ef7eb2e8f9f7	3558
<>	144:ef7eb2e8f9f7	3559	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	3560	{
<>	144:ef7eb2e8f9f7	3561	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3562	}
<>	144:ef7eb2e8f9f7	3563	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	3564	{
<>	144:ef7eb2e8f9f7	3565	if((BurstBuffer == 0 ) && (BurstLength > 0))
<>	144:ef7eb2e8f9f7	3566	{
<>	144:ef7eb2e8f9f7	3567	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3568	}
<>	144:ef7eb2e8f9f7	3569	else
<>	144:ef7eb2e8f9f7	3570	{
<>	144:ef7eb2e8f9f7	3571	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3572	}
<>	144:ef7eb2e8f9f7	3573	}
<>	144:ef7eb2e8f9f7	3574	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3575	{
<>	144:ef7eb2e8f9f7	3576	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3577	{
<>	144:ef7eb2e8f9f7	3578	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3579	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	3580
<>	144:ef7eb2e8f9f7	3581	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3582	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3583
<>	144:ef7eb2e8f9f7	3584	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3585	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3586	}
<>	144:ef7eb2e8f9f7	3587	break;
<>	144:ef7eb2e8f9f7	3588	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3589	{
<>	144:ef7eb2e8f9f7	3590	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3591	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3592
<>	144:ef7eb2e8f9f7	3593	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3594	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3595
<>	144:ef7eb2e8f9f7	3596	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3597	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3598	}
<>	144:ef7eb2e8f9f7	3599	break;
<>	144:ef7eb2e8f9f7	3600	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3601	{
<>	144:ef7eb2e8f9f7	3602	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3603	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3604
<>	144:ef7eb2e8f9f7	3605	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3606	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3607
<>	144:ef7eb2e8f9f7	3608	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3609	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3610	}
<>	144:ef7eb2e8f9f7	3611	break;
<>	144:ef7eb2e8f9f7	3612	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3613	{
<>	144:ef7eb2e8f9f7	3614	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3615	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3616
<>	144:ef7eb2e8f9f7	3617	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3618	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3619
<>	144:ef7eb2e8f9f7	3620	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3621	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3622	}
<>	144:ef7eb2e8f9f7	3623	break;
<>	144:ef7eb2e8f9f7	3624	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3625	{
<>	144:ef7eb2e8f9f7	3626	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3627	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3628
<>	144:ef7eb2e8f9f7	3629	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3630	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3631
<>	144:ef7eb2e8f9f7	3632	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3633	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3634	}
<>	144:ef7eb2e8f9f7	3635	break;
<>	144:ef7eb2e8f9f7	3636	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3637	{
<>	144:ef7eb2e8f9f7	3638	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3639	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<>	144:ef7eb2e8f9f7	3640
<>	144:ef7eb2e8f9f7	3641	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3642	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3643
<>	144:ef7eb2e8f9f7	3644	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3645	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3646	}
<>	144:ef7eb2e8f9f7	3647	break;
<>	144:ef7eb2e8f9f7	3648	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3649	{
<>	144:ef7eb2e8f9f7	3650	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3651	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	144:ef7eb2e8f9f7	3652
<>	144:ef7eb2e8f9f7	3653	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3654	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3655
<>	144:ef7eb2e8f9f7	3656	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3657	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<>	144:ef7eb2e8f9f7	3658	}
<>	144:ef7eb2e8f9f7	3659	break;
<>	144:ef7eb2e8f9f7	3660	default:
<>	144:ef7eb2e8f9f7	3661	break;
<>	144:ef7eb2e8f9f7	3662	}
<>	144:ef7eb2e8f9f7	3663
<>	144:ef7eb2e8f9f7	3664	/* configure the DMA Burst Mode */
<>	144:ef7eb2e8f9f7	3665	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	144:ef7eb2e8f9f7	3666
<>	144:ef7eb2e8f9f7	3667	/* Enable the TIM DMA Request */
<>	144:ef7eb2e8f9f7	3668	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3669
<>	144:ef7eb2e8f9f7	3670	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3671
<>	144:ef7eb2e8f9f7	3672	/* Return function status */
<>	144:ef7eb2e8f9f7	3673	return HAL_OK;
<>	144:ef7eb2e8f9f7	3674	}
<>	144:ef7eb2e8f9f7	3675
<>	144:ef7eb2e8f9f7	3676	/**
<>	144:ef7eb2e8f9f7	3677	* @brief Stop the DMA burst reading
<>	144:ef7eb2e8f9f7	3678	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3679	* @param BurstRequestSrc : TIM DMA Request sources to disable.
<>	144:ef7eb2e8f9f7	3680	* @retval HAL status
<>	144:ef7eb2e8f9f7	3681	*/
<>	144:ef7eb2e8f9f7	3682	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3683	{
<>	144:ef7eb2e8f9f7	3684	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3685	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3686
<>	144:ef7eb2e8f9f7	3687	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	144:ef7eb2e8f9f7	3688	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3689	{
<>	144:ef7eb2e8f9f7	3690	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3691	{
<>	144:ef7eb2e8f9f7	3692	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	144:ef7eb2e8f9f7	3693	}
<>	144:ef7eb2e8f9f7	3694	break;
<>	144:ef7eb2e8f9f7	3695	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3696	{
<>	144:ef7eb2e8f9f7	3697	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	144:ef7eb2e8f9f7	3698	}
<>	144:ef7eb2e8f9f7	3699	break;
<>	144:ef7eb2e8f9f7	3700	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3701	{
<>	144:ef7eb2e8f9f7	3702	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	144:ef7eb2e8f9f7	3703	}
<>	144:ef7eb2e8f9f7	3704	break;
<>	144:ef7eb2e8f9f7	3705	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3706	{
<>	144:ef7eb2e8f9f7	3707	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	144:ef7eb2e8f9f7	3708	}
<>	144:ef7eb2e8f9f7	3709	break;
<>	144:ef7eb2e8f9f7	3710	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3711	{
<>	144:ef7eb2e8f9f7	3712	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	144:ef7eb2e8f9f7	3713	}
<>	144:ef7eb2e8f9f7	3714	break;
<>	144:ef7eb2e8f9f7	3715	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3716	{
<>	144:ef7eb2e8f9f7	3717	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<>	144:ef7eb2e8f9f7	3718	}
<>	144:ef7eb2e8f9f7	3719	break;
<>	144:ef7eb2e8f9f7	3720	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3721	{
<>	144:ef7eb2e8f9f7	3722	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	144:ef7eb2e8f9f7	3723	}
<>	144:ef7eb2e8f9f7	3724	break;
<>	144:ef7eb2e8f9f7	3725	default:
<>	144:ef7eb2e8f9f7	3726	break;
<>	144:ef7eb2e8f9f7	3727	}
<>	144:ef7eb2e8f9f7	3728
<>	144:ef7eb2e8f9f7	3729	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	3730	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3731
<>	144:ef7eb2e8f9f7	3732	/* Return function status */
<>	144:ef7eb2e8f9f7	3733	return HAL_OK;
<>	144:ef7eb2e8f9f7	3734	}
<>	144:ef7eb2e8f9f7	3735
<>	144:ef7eb2e8f9f7	3736	/**
<>	144:ef7eb2e8f9f7	3737	* @brief Generate a software event
<>	144:ef7eb2e8f9f7	3738	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3739	* @param EventSource : specifies the event source.
<>	144:ef7eb2e8f9f7	3740	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3741	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<>	144:ef7eb2e8f9f7	3742	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<>	144:ef7eb2e8f9f7	3743	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<>	144:ef7eb2e8f9f7	3744	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<>	144:ef7eb2e8f9f7	3745	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<>	144:ef7eb2e8f9f7	3746	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
<>	144:ef7eb2e8f9f7	3747	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<>	144:ef7eb2e8f9f7	3748	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
<>	144:ef7eb2e8f9f7	3749	* @note TIM6 and TIM7 can only generate an update event.
<>	144:ef7eb2e8f9f7	3750	* @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
<>	144:ef7eb2e8f9f7	3751	* @retval HAL status
<>	144:ef7eb2e8f9f7	3752	*/
<>	144:ef7eb2e8f9f7	3753
<>	144:ef7eb2e8f9f7	3754	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<>	144:ef7eb2e8f9f7	3755	{
<>	144:ef7eb2e8f9f7	3756	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3757	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3758	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<>	144:ef7eb2e8f9f7	3759
<>	144:ef7eb2e8f9f7	3760	/* Process Locked */
<>	144:ef7eb2e8f9f7	3761	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3762
<>	144:ef7eb2e8f9f7	3763	/* Change the TIM state */
<>	144:ef7eb2e8f9f7	3764	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3765
<>	144:ef7eb2e8f9f7	3766	/* Set the event sources */
<>	144:ef7eb2e8f9f7	3767	htim->Instance->EGR = EventSource;
<>	144:ef7eb2e8f9f7	3768
<>	144:ef7eb2e8f9f7	3769	/* Change the TIM state */
<>	144:ef7eb2e8f9f7	3770	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3771
<>	144:ef7eb2e8f9f7	3772	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3773
<>	144:ef7eb2e8f9f7	3774	/* Return function status */
<>	144:ef7eb2e8f9f7	3775	return HAL_OK;
<>	144:ef7eb2e8f9f7	3776	}
<>	144:ef7eb2e8f9f7	3777
<>	144:ef7eb2e8f9f7	3778	/**
<>	144:ef7eb2e8f9f7	3779	* @brief Configures the OCRef clear feature
<>	144:ef7eb2e8f9f7	3780	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3781	* @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3782	* contains the OCREF clear feature and parameters for the TIM peripheral.
<>	144:ef7eb2e8f9f7	3783	* @param Channel : specifies the TIM Channel
<>	144:ef7eb2e8f9f7	3784	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3785	* @arg TIM_CHANNEL_1: TIM Channel 1
<>	144:ef7eb2e8f9f7	3786	* @arg TIM_CHANNEL_2: TIM Channel 2
<>	144:ef7eb2e8f9f7	3787	* @arg TIM_CHANNEL_3: TIM Channel 3
<>	144:ef7eb2e8f9f7	3788	* @arg TIM_CHANNEL_4: TIM Channel 4
<>	144:ef7eb2e8f9f7	3789	* @retval HAL status
<>	144:ef7eb2e8f9f7	3790	*/
<>	144:ef7eb2e8f9f7	3791	__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3792	{
<>	144:ef7eb2e8f9f7	3793	uint32_t tmpsmcr = 0;
<>	144:ef7eb2e8f9f7	3794
<>	144:ef7eb2e8f9f7	3795	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3796	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3797	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<>	144:ef7eb2e8f9f7	3798	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<>	144:ef7eb2e8f9f7	3799	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<>	144:ef7eb2e8f9f7	3800	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<>	144:ef7eb2e8f9f7	3801
<>	144:ef7eb2e8f9f7	3802	/* Process Locked */
<>	144:ef7eb2e8f9f7	3803	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3804
<>	144:ef7eb2e8f9f7	3805	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3806
<>	144:ef7eb2e8f9f7	3807	switch (sClearInputConfig->ClearInputSource)
<>	144:ef7eb2e8f9f7	3808	{
<>	144:ef7eb2e8f9f7	3809	case TIM_CLEARINPUTSOURCE_NONE:
<>	144:ef7eb2e8f9f7	3810	{
<>	144:ef7eb2e8f9f7	3811	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	3812	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	3813
<>	144:ef7eb2e8f9f7	3814	/* Clear the OCREF clear selection bit */
<>	144:ef7eb2e8f9f7	3815	tmpsmcr &= ~TIM_SMCR_OCCS;
<>	144:ef7eb2e8f9f7	3816
<>	144:ef7eb2e8f9f7	3817	/* Clear the ETR Bits */
<>	144:ef7eb2e8f9f7	3818	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	3819
<>	144:ef7eb2e8f9f7	3820	/* Set TIMx_SMCR */
<>	144:ef7eb2e8f9f7	3821	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3822	}
<>	144:ef7eb2e8f9f7	3823	break;
<>	144:ef7eb2e8f9f7	3824
<>	144:ef7eb2e8f9f7	3825	case TIM_CLEARINPUTSOURCE_ETR:
<>	144:ef7eb2e8f9f7	3826	{
<>	144:ef7eb2e8f9f7	3827	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3828	sClearInputConfig->ClearInputPrescaler,
<>	144:ef7eb2e8f9f7	3829	sClearInputConfig->ClearInputPolarity,
<>	144:ef7eb2e8f9f7	3830	sClearInputConfig->ClearInputFilter);
<>	144:ef7eb2e8f9f7	3831
<>	144:ef7eb2e8f9f7	3832	/* Set the OCREF clear selection bit */
<>	144:ef7eb2e8f9f7	3833	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
<>	144:ef7eb2e8f9f7	3834	}
<>	144:ef7eb2e8f9f7	3835	break;
<>	144:ef7eb2e8f9f7	3836	default:
<>	144:ef7eb2e8f9f7	3837	break;
<>	144:ef7eb2e8f9f7	3838	}
<>	144:ef7eb2e8f9f7	3839
<>	144:ef7eb2e8f9f7	3840	switch (Channel)
<>	144:ef7eb2e8f9f7	3841	{
<>	144:ef7eb2e8f9f7	3842	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3843	{
<>	144:ef7eb2e8f9f7	3844	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3845	{
<>	144:ef7eb2e8f9f7	3846	/* Enable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	3847	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	3848	}
<>	144:ef7eb2e8f9f7	3849	else
<>	144:ef7eb2e8f9f7	3850	{
<>	144:ef7eb2e8f9f7	3851	/* Disable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	3852	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	3853	}
<>	144:ef7eb2e8f9f7	3854	}
<>	144:ef7eb2e8f9f7	3855	break;
<>	144:ef7eb2e8f9f7	3856	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3857	{
<>	144:ef7eb2e8f9f7	3858	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3859	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3860	{
<>	144:ef7eb2e8f9f7	3861	/* Enable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	3862	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	3863	}
<>	144:ef7eb2e8f9f7	3864	else
<>	144:ef7eb2e8f9f7	3865	{
<>	144:ef7eb2e8f9f7	3866	/* Disable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	3867	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	3868	}
<>	144:ef7eb2e8f9f7	3869	}
<>	144:ef7eb2e8f9f7	3870	break;
<>	144:ef7eb2e8f9f7	3871	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3872	{
<>	144:ef7eb2e8f9f7	3873	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3874	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3875	{
<>	144:ef7eb2e8f9f7	3876	/* Enable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	3877	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	3878	}
<>	144:ef7eb2e8f9f7	3879	else
<>	144:ef7eb2e8f9f7	3880	{
<>	144:ef7eb2e8f9f7	3881	/* Disable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	3882	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	3883	}
<>	144:ef7eb2e8f9f7	3884	}
<>	144:ef7eb2e8f9f7	3885	break;
<>	144:ef7eb2e8f9f7	3886	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3887	{
<>	144:ef7eb2e8f9f7	3888	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3889	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3890	{
<>	144:ef7eb2e8f9f7	3891	/* Enable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	3892	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	3893	}
<>	144:ef7eb2e8f9f7	3894	else
<>	144:ef7eb2e8f9f7	3895	{
<>	144:ef7eb2e8f9f7	3896	/* Disable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	3897	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	3898	}
<>	144:ef7eb2e8f9f7	3899	}
<>	144:ef7eb2e8f9f7	3900	break;
<>	144:ef7eb2e8f9f7	3901	default:
<>	144:ef7eb2e8f9f7	3902	break;
<>	144:ef7eb2e8f9f7	3903	}
<>	144:ef7eb2e8f9f7	3904
<>	144:ef7eb2e8f9f7	3905	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3906
<>	144:ef7eb2e8f9f7	3907	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3908
<>	144:ef7eb2e8f9f7	3909	return HAL_OK;
<>	144:ef7eb2e8f9f7	3910	}
<>	144:ef7eb2e8f9f7	3911
<>	144:ef7eb2e8f9f7	3912	/**
<>	144:ef7eb2e8f9f7	3913	* @brief Configures the clock source to be used
<>	144:ef7eb2e8f9f7	3914	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3915	* @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3916	* contains the clock source information for the TIM peripheral.
<>	144:ef7eb2e8f9f7	3917	* @retval HAL status
<>	144:ef7eb2e8f9f7	3918	*/
<>	144:ef7eb2e8f9f7	3919	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
<>	144:ef7eb2e8f9f7	3920	{
<>	144:ef7eb2e8f9f7	3921	uint32_t tmpsmcr = 0;
<>	144:ef7eb2e8f9f7	3922
<>	144:ef7eb2e8f9f7	3923	/* Process Locked */
<>	144:ef7eb2e8f9f7	3924	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3925
<>	144:ef7eb2e8f9f7	3926	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3927
<>	144:ef7eb2e8f9f7	3928	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3929	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<>	144:ef7eb2e8f9f7	3930
<>	144:ef7eb2e8f9f7	3931	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<>	144:ef7eb2e8f9f7	3932	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	3933	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	144:ef7eb2e8f9f7	3934	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	3935	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3936
<>	144:ef7eb2e8f9f7	3937	switch (sClockSourceConfig->ClockSource)
<>	144:ef7eb2e8f9f7	3938	{
<>	144:ef7eb2e8f9f7	3939	case TIM_CLOCKSOURCE_INTERNAL:
<>	144:ef7eb2e8f9f7	3940	{
<>	144:ef7eb2e8f9f7	3941	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3942	/* Disable slave mode to clock the prescaler directly with the internal clock */
<>	144:ef7eb2e8f9f7	3943	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3944	}
<>	144:ef7eb2e8f9f7	3945	break;
<>	144:ef7eb2e8f9f7	3946
<>	144:ef7eb2e8f9f7	3947	case TIM_CLOCKSOURCE_ETRMODE1:
<>	144:ef7eb2e8f9f7	3948	{
<>	144:ef7eb2e8f9f7	3949	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
<>	144:ef7eb2e8f9f7	3950	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3951
<>	144:ef7eb2e8f9f7	3952	/* Check ETR input conditioning related parameters */
<>	144:ef7eb2e8f9f7	3953	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	144:ef7eb2e8f9f7	3954	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3955	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3956
<>	144:ef7eb2e8f9f7	3957	/* Configure the ETR Clock source */
<>	144:ef7eb2e8f9f7	3958	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3959	sClockSourceConfig->ClockPrescaler,
<>	144:ef7eb2e8f9f7	3960	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3961	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3962	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	3963	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	3964	/* Reset the SMS and TS Bits */
<>	144:ef7eb2e8f9f7	3965	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	144:ef7eb2e8f9f7	3966	/* Select the External clock mode1 and the ETRF trigger */
<>	144:ef7eb2e8f9f7	3967	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
<>	144:ef7eb2e8f9f7	3968	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	3969	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3970	}
<>	144:ef7eb2e8f9f7	3971	break;
<>	144:ef7eb2e8f9f7	3972
<>	144:ef7eb2e8f9f7	3973	case TIM_CLOCKSOURCE_ETRMODE2:
<>	144:ef7eb2e8f9f7	3974	{
<>	144:ef7eb2e8f9f7	3975	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
<>	144:ef7eb2e8f9f7	3976	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3977
<>	144:ef7eb2e8f9f7	3978	/* Check ETR input conditioning related parameters */
<>	144:ef7eb2e8f9f7	3979	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	144:ef7eb2e8f9f7	3980	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3981	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3982
<>	144:ef7eb2e8f9f7	3983	/* Configure the ETR Clock source */
<>	144:ef7eb2e8f9f7	3984	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3985	sClockSourceConfig->ClockPrescaler,
<>	144:ef7eb2e8f9f7	3986	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3987	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3988	/* Enable the External clock mode2 */
<>	144:ef7eb2e8f9f7	3989	htim->Instance->SMCR \|= TIM_SMCR_ECE;
<>	144:ef7eb2e8f9f7	3990	}
<>	144:ef7eb2e8f9f7	3991	break;
<>	144:ef7eb2e8f9f7	3992
<>	144:ef7eb2e8f9f7	3993	case TIM_CLOCKSOURCE_TI1:
<>	144:ef7eb2e8f9f7	3994	{
<>	144:ef7eb2e8f9f7	3995	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	3996	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3997
<>	144:ef7eb2e8f9f7	3998	/* Check TI1 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	3999	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4000	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4001
<>	144:ef7eb2e8f9f7	4002	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4003	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4004	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4005	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<>	144:ef7eb2e8f9f7	4006	}
<>	144:ef7eb2e8f9f7	4007	break;
<>	144:ef7eb2e8f9f7	4008	case TIM_CLOCKSOURCE_TI2:
<>	144:ef7eb2e8f9f7	4009	{
<>	144:ef7eb2e8f9f7	4010	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
<>	144:ef7eb2e8f9f7	4011	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4012
<>	144:ef7eb2e8f9f7	4013	/* Check TI2 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	4014	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4015	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4016
<>	144:ef7eb2e8f9f7	4017	TIM_TI2_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4018	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4019	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4020	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<>	144:ef7eb2e8f9f7	4021	}
<>	144:ef7eb2e8f9f7	4022	break;
<>	144:ef7eb2e8f9f7	4023	case TIM_CLOCKSOURCE_TI1ED:
<>	144:ef7eb2e8f9f7	4024	{
<>	144:ef7eb2e8f9f7	4025	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4026	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4027
<>	144:ef7eb2e8f9f7	4028	/* Check TI1 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	4029	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4030	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4031
<>	144:ef7eb2e8f9f7	4032	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4033	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4034	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4035	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<>	144:ef7eb2e8f9f7	4036	}
<>	144:ef7eb2e8f9f7	4037	break;
<>	144:ef7eb2e8f9f7	4038	case TIM_CLOCKSOURCE_ITR0:
<>	144:ef7eb2e8f9f7	4039	{
<>	144:ef7eb2e8f9f7	4040	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4041	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4042
<>	144:ef7eb2e8f9f7	4043	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<>	144:ef7eb2e8f9f7	4044	}
<>	144:ef7eb2e8f9f7	4045	break;
<>	144:ef7eb2e8f9f7	4046	case TIM_CLOCKSOURCE_ITR1:
<>	144:ef7eb2e8f9f7	4047	{
<>	144:ef7eb2e8f9f7	4048	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4049	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4050
<>	144:ef7eb2e8f9f7	4051	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<>	144:ef7eb2e8f9f7	4052	}
<>	144:ef7eb2e8f9f7	4053	break;
<>	144:ef7eb2e8f9f7	4054	case TIM_CLOCKSOURCE_ITR2:
<>	144:ef7eb2e8f9f7	4055	{
<>	144:ef7eb2e8f9f7	4056	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4057	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4058
<>	144:ef7eb2e8f9f7	4059	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<>	144:ef7eb2e8f9f7	4060	}
<>	144:ef7eb2e8f9f7	4061	break;
<>	144:ef7eb2e8f9f7	4062	case TIM_CLOCKSOURCE_ITR3:
<>	144:ef7eb2e8f9f7	4063	{
<>	144:ef7eb2e8f9f7	4064	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4065	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4066
<>	144:ef7eb2e8f9f7	4067	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<>	144:ef7eb2e8f9f7	4068	}
<>	144:ef7eb2e8f9f7	4069	break;
<>	144:ef7eb2e8f9f7	4070
<>	144:ef7eb2e8f9f7	4071	default:
<>	144:ef7eb2e8f9f7	4072	break;
<>	144:ef7eb2e8f9f7	4073	}
<>	144:ef7eb2e8f9f7	4074	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4075
<>	144:ef7eb2e8f9f7	4076	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4077
<>	144:ef7eb2e8f9f7	4078	return HAL_OK;
<>	144:ef7eb2e8f9f7	4079	}
<>	144:ef7eb2e8f9f7	4080
<>	144:ef7eb2e8f9f7	4081	/**
<>	144:ef7eb2e8f9f7	4082	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
<>	144:ef7eb2e8f9f7	4083	* or a XOR combination between CH1_input, CH2_input & CH3_input
<>	144:ef7eb2e8f9f7	4084	* @param htim : TIM handle.
<>	144:ef7eb2e8f9f7	4085	* @param TI1_Selection : Indicate whether or not channel 1 is connected to the
<>	144:ef7eb2e8f9f7	4086	* output of a XOR gate.
<>	144:ef7eb2e8f9f7	4087	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4088	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<>	144:ef7eb2e8f9f7	4089	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<>	144:ef7eb2e8f9f7	4090	* pins are connected to the TI1 input (XOR combination)
<>	144:ef7eb2e8f9f7	4091	* @retval HAL status
<>	144:ef7eb2e8f9f7	4092	*/
<>	144:ef7eb2e8f9f7	4093	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<>	144:ef7eb2e8f9f7	4094	{
<>	144:ef7eb2e8f9f7	4095	uint32_t tmpcr2 = 0;
<>	144:ef7eb2e8f9f7	4096
<>	144:ef7eb2e8f9f7	4097	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4098	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4099	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<>	144:ef7eb2e8f9f7	4100
<>	144:ef7eb2e8f9f7	4101	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4102	tmpcr2 = htim->Instance->CR2;
<>	144:ef7eb2e8f9f7	4103
<>	144:ef7eb2e8f9f7	4104	/* Reset the TI1 selection */
<>	144:ef7eb2e8f9f7	4105	tmpcr2 &= ~TIM_CR2_TI1S;
<>	144:ef7eb2e8f9f7	4106
<>	144:ef7eb2e8f9f7	4107	/* Set the the TI1 selection */
<>	144:ef7eb2e8f9f7	4108	tmpcr2 \|= TI1_Selection;
<>	144:ef7eb2e8f9f7	4109
<>	144:ef7eb2e8f9f7	4110	/* Write to TIMxCR2 */
<>	144:ef7eb2e8f9f7	4111	htim->Instance->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4112
<>	144:ef7eb2e8f9f7	4113	return HAL_OK;
<>	144:ef7eb2e8f9f7	4114	}
<>	144:ef7eb2e8f9f7	4115
<>	144:ef7eb2e8f9f7	4116	/**
<>	144:ef7eb2e8f9f7	4117	* @brief Configures the TIM in Slave mode
<>	144:ef7eb2e8f9f7	4118	* @param htim : TIM handle.
<>	144:ef7eb2e8f9f7	4119	* @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	4120	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	4121	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	4122	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	4123	* @retval HAL status
<>	144:ef7eb2e8f9f7	4124	*/
<>	144:ef7eb2e8f9f7	4125	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
<>	144:ef7eb2e8f9f7	4126	{
<>	144:ef7eb2e8f9f7	4127	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4128	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4129	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	144:ef7eb2e8f9f7	4130	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	144:ef7eb2e8f9f7	4131
<>	144:ef7eb2e8f9f7	4132	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4133
<>	144:ef7eb2e8f9f7	4134	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	4135
<>	144:ef7eb2e8f9f7	4136	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	144:ef7eb2e8f9f7	4137
<>	144:ef7eb2e8f9f7	4138	/* Disable Trigger Interrupt */
<>	144:ef7eb2e8f9f7	4139	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	4140
<>	144:ef7eb2e8f9f7	4141	/* Disable Trigger DMA request */
<>	144:ef7eb2e8f9f7	4142	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	144:ef7eb2e8f9f7	4143
<>	144:ef7eb2e8f9f7	4144	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4145
<>	144:ef7eb2e8f9f7	4146	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4147
<>	144:ef7eb2e8f9f7	4148	return HAL_OK;
<>	144:ef7eb2e8f9f7	4149	}
<>	144:ef7eb2e8f9f7	4150
<>	144:ef7eb2e8f9f7	4151	/**
<>	144:ef7eb2e8f9f7	4152	* @brief Configures the TIM in Slave mode in interrupt mode
<>	144:ef7eb2e8f9f7	4153	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	4154	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	4155	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	4156	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	4157	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	4158	* @retval HAL status
<>	144:ef7eb2e8f9f7	4159	*/
<>	144:ef7eb2e8f9f7	4160	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	4161	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	144:ef7eb2e8f9f7	4162	{
<>	144:ef7eb2e8f9f7	4163	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4164	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4165	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	144:ef7eb2e8f9f7	4166	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	144:ef7eb2e8f9f7	4167
<>	144:ef7eb2e8f9f7	4168	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4169
<>	144:ef7eb2e8f9f7	4170	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	4171
<>	144:ef7eb2e8f9f7	4172	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	144:ef7eb2e8f9f7	4173
<>	144:ef7eb2e8f9f7	4174	/* Enable Trigger Interrupt */
<>	144:ef7eb2e8f9f7	4175	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	4176
<>	144:ef7eb2e8f9f7	4177	/* Disable Trigger DMA request */
<>	144:ef7eb2e8f9f7	4178	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	144:ef7eb2e8f9f7	4179
<>	144:ef7eb2e8f9f7	4180	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4181
<>	144:ef7eb2e8f9f7	4182	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4183
<>	144:ef7eb2e8f9f7	4184	return HAL_OK;
<>	144:ef7eb2e8f9f7	4185	}
<>	144:ef7eb2e8f9f7	4186
<>	144:ef7eb2e8f9f7	4187	/**
<>	144:ef7eb2e8f9f7	4188	* @brief Read the captured value from Capture Compare unit
<>	144:ef7eb2e8f9f7	4189	* @param htim : TIM handle.
<>	144:ef7eb2e8f9f7	4190	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	4191	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4192	* @arg TIM_CHANNEL_1 : TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	4193	* @arg TIM_CHANNEL_2 : TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	4194	* @arg TIM_CHANNEL_3 : TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	4195	* @arg TIM_CHANNEL_4 : TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	4196	* @retval Captured value
<>	144:ef7eb2e8f9f7	4197	*/
<>	144:ef7eb2e8f9f7	4198	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	4199	{
<>	144:ef7eb2e8f9f7	4200	uint32_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	4201
<>	144:ef7eb2e8f9f7	4202	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4203
<>	144:ef7eb2e8f9f7	4204	switch (Channel)
<>	144:ef7eb2e8f9f7	4205	{
<>	144:ef7eb2e8f9f7	4206	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	4207	{
<>	144:ef7eb2e8f9f7	4208	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4209	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4210
<>	144:ef7eb2e8f9f7	4211	/* Return the capture 1 value */
<>	144:ef7eb2e8f9f7	4212	tmpreg = htim->Instance->CCR1;
<>	144:ef7eb2e8f9f7	4213
<>	144:ef7eb2e8f9f7	4214	break;
<>	144:ef7eb2e8f9f7	4215	}
<>	144:ef7eb2e8f9f7	4216	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	4217	{
<>	144:ef7eb2e8f9f7	4218	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4219	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4220
<>	144:ef7eb2e8f9f7	4221	/* Return the capture 2 value */
<>	144:ef7eb2e8f9f7	4222	tmpreg = htim->Instance->CCR2;
<>	144:ef7eb2e8f9f7	4223
<>	144:ef7eb2e8f9f7	4224	break;
<>	144:ef7eb2e8f9f7	4225	}
<>	144:ef7eb2e8f9f7	4226
<>	144:ef7eb2e8f9f7	4227	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	4228	{
<>	144:ef7eb2e8f9f7	4229	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4230	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4231
<>	144:ef7eb2e8f9f7	4232	/* Return the capture 3 value */
<>	144:ef7eb2e8f9f7	4233	tmpreg = htim->Instance->CCR3;
<>	144:ef7eb2e8f9f7	4234
<>	144:ef7eb2e8f9f7	4235	break;
<>	144:ef7eb2e8f9f7	4236	}
<>	144:ef7eb2e8f9f7	4237
<>	144:ef7eb2e8f9f7	4238	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	4239	{
<>	144:ef7eb2e8f9f7	4240	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4241	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4242
<>	144:ef7eb2e8f9f7	4243	/* Return the capture 4 value */
<>	144:ef7eb2e8f9f7	4244	tmpreg = htim->Instance->CCR4;
<>	144:ef7eb2e8f9f7	4245
<>	144:ef7eb2e8f9f7	4246	break;
<>	144:ef7eb2e8f9f7	4247	}
<>	144:ef7eb2e8f9f7	4248
<>	144:ef7eb2e8f9f7	4249	default:
<>	144:ef7eb2e8f9f7	4250	break;
<>	144:ef7eb2e8f9f7	4251	}
<>	144:ef7eb2e8f9f7	4252
<>	144:ef7eb2e8f9f7	4253	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4254	return tmpreg;
<>	144:ef7eb2e8f9f7	4255	}
<>	144:ef7eb2e8f9f7	4256
<>	144:ef7eb2e8f9f7	4257	/**
<>	144:ef7eb2e8f9f7	4258	* @}
<>	144:ef7eb2e8f9f7	4259	*/
<>	144:ef7eb2e8f9f7	4260
<>	144:ef7eb2e8f9f7	4261	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<>	144:ef7eb2e8f9f7	4262	* @brief TIM Callbacks functions
<>	144:ef7eb2e8f9f7	4263	*
<>	144:ef7eb2e8f9f7	4264	@verbatim
<>	144:ef7eb2e8f9f7	4265	==============================================================================
<>	144:ef7eb2e8f9f7	4266	##### TIM Callbacks functions #####
<>	144:ef7eb2e8f9f7	4267	==============================================================================
<>	144:ef7eb2e8f9f7	4268	[..]
<>	144:ef7eb2e8f9f7	4269	This section provides TIM callback functions:
<>	144:ef7eb2e8f9f7	4270	(+) Timer Period elapsed callback
<>	144:ef7eb2e8f9f7	4271	(+) Timer Output Compare callback
<>	144:ef7eb2e8f9f7	4272	(+) Timer Input capture callback
<>	144:ef7eb2e8f9f7	4273	(+) Timer Trigger callback
<>	144:ef7eb2e8f9f7	4274	(+) Timer Error callback
<>	144:ef7eb2e8f9f7	4275
<>	144:ef7eb2e8f9f7	4276	@endverbatim
<>	144:ef7eb2e8f9f7	4277	* @{
<>	144:ef7eb2e8f9f7	4278	*/
<>	144:ef7eb2e8f9f7	4279
<>	144:ef7eb2e8f9f7	4280	/**
<>	144:ef7eb2e8f9f7	4281	* @brief Period elapsed callback in non blocking mode
<>	144:ef7eb2e8f9f7	4282	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4283	* @retval None
<>	144:ef7eb2e8f9f7	4284	*/
<>	144:ef7eb2e8f9f7	4285	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4286	{
<>	144:ef7eb2e8f9f7	4287	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4288	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4289
<>	144:ef7eb2e8f9f7	4290	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4291	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4292	*/
<>	144:ef7eb2e8f9f7	4293
<>	144:ef7eb2e8f9f7	4294	}
<>	144:ef7eb2e8f9f7	4295	/**
<>	144:ef7eb2e8f9f7	4296	* @brief Output Compare callback in non blocking mode
<>	144:ef7eb2e8f9f7	4297	* @param htim : TIM OC handle
<>	144:ef7eb2e8f9f7	4298	* @retval None
<>	144:ef7eb2e8f9f7	4299	*/
<>	144:ef7eb2e8f9f7	4300	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4301	{
<>	144:ef7eb2e8f9f7	4302	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4303	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4304
<>	144:ef7eb2e8f9f7	4305	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4306	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4307	*/
<>	144:ef7eb2e8f9f7	4308	}
<>	144:ef7eb2e8f9f7	4309	/**
<>	144:ef7eb2e8f9f7	4310	* @brief Input Capture callback in non blocking mode
<>	144:ef7eb2e8f9f7	4311	* @param htim : TIM IC handle
<>	144:ef7eb2e8f9f7	4312	* @retval None
<>	144:ef7eb2e8f9f7	4313	*/
<>	144:ef7eb2e8f9f7	4314	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4315	{
<>	144:ef7eb2e8f9f7	4316	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4317	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4318
<>	144:ef7eb2e8f9f7	4319	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4320	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4321	*/
<>	144:ef7eb2e8f9f7	4322	}
<>	144:ef7eb2e8f9f7	4323
<>	144:ef7eb2e8f9f7	4324	/**
<>	144:ef7eb2e8f9f7	4325	* @brief PWM Pulse finished callback in non blocking mode
<>	144:ef7eb2e8f9f7	4326	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4327	* @retval None
<>	144:ef7eb2e8f9f7	4328	*/
<>	144:ef7eb2e8f9f7	4329	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4330	{
<>	144:ef7eb2e8f9f7	4331	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4332	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4333
<>	144:ef7eb2e8f9f7	4334	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4335	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4336	*/
<>	144:ef7eb2e8f9f7	4337	}
<>	144:ef7eb2e8f9f7	4338
<>	144:ef7eb2e8f9f7	4339	/**
<>	144:ef7eb2e8f9f7	4340	* @brief Hall Trigger detection callback in non blocking mode
<>	144:ef7eb2e8f9f7	4341	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4342	* @retval None
<>	144:ef7eb2e8f9f7	4343	*/
<>	144:ef7eb2e8f9f7	4344	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4345	{
<>	144:ef7eb2e8f9f7	4346	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4347	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4348
<>	144:ef7eb2e8f9f7	4349	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4350	the HAL_TIM_TriggerCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4351	*/
<>	144:ef7eb2e8f9f7	4352	}
<>	144:ef7eb2e8f9f7	4353
<>	144:ef7eb2e8f9f7	4354	/**
<>	144:ef7eb2e8f9f7	4355	* @brief Timer error callback in non blocking mode
<>	144:ef7eb2e8f9f7	4356	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4357	* @retval None
<>	144:ef7eb2e8f9f7	4358	*/
<>	144:ef7eb2e8f9f7	4359	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4360	{
<>	144:ef7eb2e8f9f7	4361	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4362	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4363
<>	144:ef7eb2e8f9f7	4364	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4365	the HAL_TIM_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4366	*/
<>	144:ef7eb2e8f9f7	4367	}
<>	144:ef7eb2e8f9f7	4368
<>	144:ef7eb2e8f9f7	4369	/**
<>	144:ef7eb2e8f9f7	4370	* @}
<>	144:ef7eb2e8f9f7	4371	*/
<>	144:ef7eb2e8f9f7	4372
<>	144:ef7eb2e8f9f7	4373	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<>	144:ef7eb2e8f9f7	4374	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	4375	*
<>	144:ef7eb2e8f9f7	4376	@verbatim
<>	144:ef7eb2e8f9f7	4377	==============================================================================
<>	144:ef7eb2e8f9f7	4378	##### Peripheral State functions #####
<>	144:ef7eb2e8f9f7	4379	==============================================================================
<>	144:ef7eb2e8f9f7	4380	[..]
<>	144:ef7eb2e8f9f7	4381	This subsection permit to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	4382	and the data flow.
<>	144:ef7eb2e8f9f7	4383
<>	144:ef7eb2e8f9f7	4384	@endverbatim
<>	144:ef7eb2e8f9f7	4385	* @{
<>	144:ef7eb2e8f9f7	4386	*/
<>	144:ef7eb2e8f9f7	4387
<>	144:ef7eb2e8f9f7	4388	/**
<>	144:ef7eb2e8f9f7	4389	* @brief Return the TIM Base state
<>	144:ef7eb2e8f9f7	4390	* @param htim : TIM Base handle
<>	144:ef7eb2e8f9f7	4391	* @retval HAL state
<>	144:ef7eb2e8f9f7	4392	*/
<>	144:ef7eb2e8f9f7	4393	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4394	{
<>	144:ef7eb2e8f9f7	4395	return htim->State;
<>	144:ef7eb2e8f9f7	4396	}
<>	144:ef7eb2e8f9f7	4397
<>	144:ef7eb2e8f9f7	4398	/**
<>	144:ef7eb2e8f9f7	4399	* @brief Return the TIM OC state
<>	144:ef7eb2e8f9f7	4400	* @param htim : TIM Ouput Compare handle
<>	144:ef7eb2e8f9f7	4401	* @retval HAL state
<>	144:ef7eb2e8f9f7	4402	*/
<>	144:ef7eb2e8f9f7	4403	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4404	{
<>	144:ef7eb2e8f9f7	4405	return htim->State;
<>	144:ef7eb2e8f9f7	4406	}
<>	144:ef7eb2e8f9f7	4407
<>	144:ef7eb2e8f9f7	4408	/**
<>	144:ef7eb2e8f9f7	4409	* @brief Return the TIM PWM state
<>	144:ef7eb2e8f9f7	4410	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4411	* @retval HAL state
<>	144:ef7eb2e8f9f7	4412	*/
<>	144:ef7eb2e8f9f7	4413	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4414	{
<>	144:ef7eb2e8f9f7	4415	return htim->State;
<>	144:ef7eb2e8f9f7	4416	}
<>	144:ef7eb2e8f9f7	4417
<>	144:ef7eb2e8f9f7	4418	/**
<>	144:ef7eb2e8f9f7	4419	* @brief Return the TIM Input Capture state
<>	144:ef7eb2e8f9f7	4420	* @param htim : TIM IC handle
<>	144:ef7eb2e8f9f7	4421	* @retval HAL state
<>	144:ef7eb2e8f9f7	4422	*/
<>	144:ef7eb2e8f9f7	4423	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4424	{
<>	144:ef7eb2e8f9f7	4425	return htim->State;
<>	144:ef7eb2e8f9f7	4426	}
<>	144:ef7eb2e8f9f7	4427
<>	144:ef7eb2e8f9f7	4428	/**
<>	144:ef7eb2e8f9f7	4429	* @brief Return the TIM One Pulse Mode state
<>	144:ef7eb2e8f9f7	4430	* @param htim : TIM OPM handle
<>	144:ef7eb2e8f9f7	4431	* @retval HAL state
<>	144:ef7eb2e8f9f7	4432	*/
<>	144:ef7eb2e8f9f7	4433	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4434	{
<>	144:ef7eb2e8f9f7	4435	return htim->State;
<>	144:ef7eb2e8f9f7	4436	}
<>	144:ef7eb2e8f9f7	4437
<>	144:ef7eb2e8f9f7	4438	/**
<>	144:ef7eb2e8f9f7	4439	* @brief Return the TIM Encoder Mode state
<>	144:ef7eb2e8f9f7	4440	* @param htim : TIM Encoder handle
<>	144:ef7eb2e8f9f7	4441	* @retval HAL state
<>	144:ef7eb2e8f9f7	4442	*/
<>	144:ef7eb2e8f9f7	4443	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4444	{
<>	144:ef7eb2e8f9f7	4445	return htim->State;
<>	144:ef7eb2e8f9f7	4446	}
<>	144:ef7eb2e8f9f7	4447
<>	144:ef7eb2e8f9f7	4448	/**
<>	144:ef7eb2e8f9f7	4449	* @}
<>	144:ef7eb2e8f9f7	4450	*/
<>	144:ef7eb2e8f9f7	4451
<>	144:ef7eb2e8f9f7	4452	/**
<>	144:ef7eb2e8f9f7	4453	* @}
<>	144:ef7eb2e8f9f7	4454	*/
<>	144:ef7eb2e8f9f7	4455
<>	144:ef7eb2e8f9f7	4456	/** @addtogroup TIM_Private_Functions TIM_Private_Functions
<>	144:ef7eb2e8f9f7	4457	* @{
<>	144:ef7eb2e8f9f7	4458	*/
<>	144:ef7eb2e8f9f7	4459
<>	144:ef7eb2e8f9f7	4460	/**
<>	144:ef7eb2e8f9f7	4461	* @brief TIM DMA error callback
<>	144:ef7eb2e8f9f7	4462	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4463	* @retval None
<>	144:ef7eb2e8f9f7	4464	*/
<>	144:ef7eb2e8f9f7	4465	void TIM_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4466	{
<>	144:ef7eb2e8f9f7	4467	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4468
<>	144:ef7eb2e8f9f7	4469	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4470
<>	144:ef7eb2e8f9f7	4471	HAL_TIM_ErrorCallback(htim);
<>	144:ef7eb2e8f9f7	4472	}
<>	144:ef7eb2e8f9f7	4473
<>	144:ef7eb2e8f9f7	4474	/**
<>	144:ef7eb2e8f9f7	4475	* @brief TIM DMA Delay Pulse complete callback.
<>	144:ef7eb2e8f9f7	4476	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4477	* @retval None
<>	144:ef7eb2e8f9f7	4478	*/
<>	144:ef7eb2e8f9f7	4479	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4480	{
<>	144:ef7eb2e8f9f7	4481	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4482
<>	144:ef7eb2e8f9f7	4483	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4484
<>	144:ef7eb2e8f9f7	4485	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	144:ef7eb2e8f9f7	4486	{
<>	144:ef7eb2e8f9f7	4487	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	4488	}
<>	144:ef7eb2e8f9f7	4489	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	144:ef7eb2e8f9f7	4490	{
<>	144:ef7eb2e8f9f7	4491	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	4492	}
<>	144:ef7eb2e8f9f7	4493	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	144:ef7eb2e8f9f7	4494	{
<>	144:ef7eb2e8f9f7	4495	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	4496	}
<>	144:ef7eb2e8f9f7	4497	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	144:ef7eb2e8f9f7	4498	{
<>	144:ef7eb2e8f9f7	4499	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	4500	}
<>	144:ef7eb2e8f9f7	4501
<>	144:ef7eb2e8f9f7	4502	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	4503
<>	144:ef7eb2e8f9f7	4504	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	4505	}
<>	144:ef7eb2e8f9f7	4506	/**
<>	144:ef7eb2e8f9f7	4507	* @brief TIM DMA Capture complete callback.
<>	144:ef7eb2e8f9f7	4508	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4509	* @retval None
<>	144:ef7eb2e8f9f7	4510	*/
<>	144:ef7eb2e8f9f7	4511	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4512	{
<>	144:ef7eb2e8f9f7	4513	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4514
<>	144:ef7eb2e8f9f7	4515	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4516
<>	144:ef7eb2e8f9f7	4517	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	144:ef7eb2e8f9f7	4518	{
<>	144:ef7eb2e8f9f7	4519	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	4520	}
<>	144:ef7eb2e8f9f7	4521	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	144:ef7eb2e8f9f7	4522	{
<>	144:ef7eb2e8f9f7	4523	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	4524	}
<>	144:ef7eb2e8f9f7	4525	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	144:ef7eb2e8f9f7	4526	{
<>	144:ef7eb2e8f9f7	4527	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	4528	}
<>	144:ef7eb2e8f9f7	4529	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	144:ef7eb2e8f9f7	4530	{
<>	144:ef7eb2e8f9f7	4531	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	4532	}
<>	144:ef7eb2e8f9f7	4533
<>	144:ef7eb2e8f9f7	4534	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	4535
<>	144:ef7eb2e8f9f7	4536	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	4537	}
<>	144:ef7eb2e8f9f7	4538
<>	144:ef7eb2e8f9f7	4539	/**
<>	144:ef7eb2e8f9f7	4540	* @brief TIM DMA Period Elapse complete callback.
<>	144:ef7eb2e8f9f7	4541	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4542	* @retval None
<>	144:ef7eb2e8f9f7	4543	*/
<>	144:ef7eb2e8f9f7	4544	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4545	{
<>	144:ef7eb2e8f9f7	4546	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4547
<>	144:ef7eb2e8f9f7	4548	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4549
<>	144:ef7eb2e8f9f7	4550	HAL_TIM_PeriodElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	4551	}
<>	144:ef7eb2e8f9f7	4552
<>	144:ef7eb2e8f9f7	4553	/**
<>	144:ef7eb2e8f9f7	4554	* @brief TIM DMA Trigger callback.
<>	144:ef7eb2e8f9f7	4555	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4556	* @retval None
<>	144:ef7eb2e8f9f7	4557	*/
<>	144:ef7eb2e8f9f7	4558	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4559	{
<>	144:ef7eb2e8f9f7	4560	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4561
<>	144:ef7eb2e8f9f7	4562	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4563
<>	144:ef7eb2e8f9f7	4564	HAL_TIM_TriggerCallback(htim);
<>	144:ef7eb2e8f9f7	4565	}
<>	144:ef7eb2e8f9f7	4566
<>	144:ef7eb2e8f9f7	4567	/**
<>	144:ef7eb2e8f9f7	4568	* @brief Time Base configuration
<>	144:ef7eb2e8f9f7	4569	* @param TIMx : TIM periheral
<>	144:ef7eb2e8f9f7	4570	* @param Structure : TIM Base configuration structure
<>	144:ef7eb2e8f9f7	4571	* @retval None
<>	144:ef7eb2e8f9f7	4572	*/
<>	144:ef7eb2e8f9f7	4573	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
<>	144:ef7eb2e8f9f7	4574	{
<>	144:ef7eb2e8f9f7	4575	uint32_t tmpcr1 = 0;
<>	144:ef7eb2e8f9f7	4576	tmpcr1 = TIMx->CR1;
<>	144:ef7eb2e8f9f7	4577
<>	144:ef7eb2e8f9f7	4578	/* Set TIM Time Base Unit parameters ---------------------------------------*/
<>	144:ef7eb2e8f9f7	4579	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4580	{
<>	144:ef7eb2e8f9f7	4581	/* Select the Counter Mode */
<>	144:ef7eb2e8f9f7	4582	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
<>	144:ef7eb2e8f9f7	4583	tmpcr1 \|= Structure->CounterMode;
<>	144:ef7eb2e8f9f7	4584	}
<>	144:ef7eb2e8f9f7	4585
<>	144:ef7eb2e8f9f7	4586	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4587	{
<>	144:ef7eb2e8f9f7	4588	/* Set the clock division */
<>	144:ef7eb2e8f9f7	4589	tmpcr1 &= ~TIM_CR1_CKD;
<>	144:ef7eb2e8f9f7	4590	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
<>	144:ef7eb2e8f9f7	4591	}
<>	144:ef7eb2e8f9f7	4592
<>	144:ef7eb2e8f9f7	4593	TIMx->CR1 = tmpcr1;
<>	144:ef7eb2e8f9f7	4594
<>	144:ef7eb2e8f9f7	4595	/* Set the Autoreload value */
<>	144:ef7eb2e8f9f7	4596	TIMx->ARR = (uint32_t)Structure->Period ;
<>	144:ef7eb2e8f9f7	4597
<>	144:ef7eb2e8f9f7	4598	/* Set the Prescaler value */
<>	144:ef7eb2e8f9f7	4599	TIMx->PSC = (uint32_t)Structure->Prescaler;
<>	144:ef7eb2e8f9f7	4600
<>	144:ef7eb2e8f9f7	4601	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4602	{
<>	144:ef7eb2e8f9f7	4603	/* Set the Repetition Counter value */
<>	144:ef7eb2e8f9f7	4604	TIMx->RCR = Structure->RepetitionCounter;
<>	144:ef7eb2e8f9f7	4605	}
<>	144:ef7eb2e8f9f7	4606
<>	144:ef7eb2e8f9f7	4607	/* Generate an update event to reload the Prescaler
<>	144:ef7eb2e8f9f7	4608	and the repetition counter(only for TIM1 and TIM8) value immediatly */
<>	144:ef7eb2e8f9f7	4609	TIMx->EGR = TIM_EGR_UG;
<>	144:ef7eb2e8f9f7	4610	}
<>	144:ef7eb2e8f9f7	4611
<>	144:ef7eb2e8f9f7	4612	/**
<>	144:ef7eb2e8f9f7	4613	* @brief Time Ouput Compare 1 configuration
<>	144:ef7eb2e8f9f7	4614	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4615	* @param OC_Config : The ouput configuration structure
<>	144:ef7eb2e8f9f7	4616	* @retval None
<>	144:ef7eb2e8f9f7	4617	*/
<>	144:ef7eb2e8f9f7	4618	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4619	{
<>	144:ef7eb2e8f9f7	4620	uint32_t tmpccmrx = 0;
<>	144:ef7eb2e8f9f7	4621	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	4622	uint32_t tmpcr2 = 0;
<>	144:ef7eb2e8f9f7	4623
<>	144:ef7eb2e8f9f7	4624	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4625	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4626
<>	144:ef7eb2e8f9f7	4627	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4628	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4629	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4630	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4631
<>	144:ef7eb2e8f9f7	4632	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	4633	tmpccmrx = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4634
<>	144:ef7eb2e8f9f7	4635	/* Reset the Output Compare Mode Bits */
<>	144:ef7eb2e8f9f7	4636	tmpccmrx &= ~TIM_CCMR1_OC1M;
<>	144:ef7eb2e8f9f7	4637	tmpccmrx &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	4638	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4639	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	4640
<>	144:ef7eb2e8f9f7	4641	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4642	tmpccer &= ~TIM_CCER_CC1P;
<>	144:ef7eb2e8f9f7	4643	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4644	tmpccer \|= OC_Config->OCPolarity;
<>	144:ef7eb2e8f9f7	4645
<>	144:ef7eb2e8f9f7	4646	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
<>	144:ef7eb2e8f9f7	4647	{
<>	144:ef7eb2e8f9f7	4648	/* Check parameters */
<>	144:ef7eb2e8f9f7	4649	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<>	144:ef7eb2e8f9f7	4650
<>	144:ef7eb2e8f9f7	4651	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4652	tmpccer &= ~TIM_CCER_CC1NP;
<>	144:ef7eb2e8f9f7	4653	/* Set the Output N Polarity */
<>	144:ef7eb2e8f9f7	4654	tmpccer \|= OC_Config->OCNPolarity;
<>	144:ef7eb2e8f9f7	4655	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4656	tmpccer &= ~TIM_CCER_CC1NE;
<>	144:ef7eb2e8f9f7	4657	}
<>	144:ef7eb2e8f9f7	4658
<>	144:ef7eb2e8f9f7	4659	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4660	{
<>	144:ef7eb2e8f9f7	4661	/* Check parameters */
<>	144:ef7eb2e8f9f7	4662	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<>	144:ef7eb2e8f9f7	4663	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4664
<>	144:ef7eb2e8f9f7	4665	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4666	tmpcr2 &= ~TIM_CR2_OIS1;
<>	144:ef7eb2e8f9f7	4667	tmpcr2 &= ~TIM_CR2_OIS1N;
<>	144:ef7eb2e8f9f7	4668	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4669	tmpcr2 \|= OC_Config->OCIdleState;
<>	144:ef7eb2e8f9f7	4670	/* Set the Output N Idle state */
<>	144:ef7eb2e8f9f7	4671	tmpcr2 \|= OC_Config->OCNIdleState;
<>	144:ef7eb2e8f9f7	4672	}
<>	144:ef7eb2e8f9f7	4673	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4674	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4675
<>	144:ef7eb2e8f9f7	4676	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	4677	TIMx->CCMR1 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4678
<>	144:ef7eb2e8f9f7	4679	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4680	TIMx->CCR1 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4681
<>	144:ef7eb2e8f9f7	4682	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4683	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4684	}
<>	144:ef7eb2e8f9f7	4685
<>	144:ef7eb2e8f9f7	4686	/**
<>	144:ef7eb2e8f9f7	4687	* @brief Time Ouput Compare 2 configuration
<>	144:ef7eb2e8f9f7	4688	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4689	* @param OC_Config : The ouput configuration structure
<>	144:ef7eb2e8f9f7	4690	* @retval None
<>	144:ef7eb2e8f9f7	4691	*/
<>	144:ef7eb2e8f9f7	4692	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4693	{
<>	144:ef7eb2e8f9f7	4694	uint32_t tmpccmrx = 0;
<>	144:ef7eb2e8f9f7	4695	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	4696	uint32_t tmpcr2 = 0;
<>	144:ef7eb2e8f9f7	4697
<>	144:ef7eb2e8f9f7	4698	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4699	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	4700
<>	144:ef7eb2e8f9f7	4701	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4702	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4703	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4704	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4705
<>	144:ef7eb2e8f9f7	4706	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	4707	tmpccmrx = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4708
<>	144:ef7eb2e8f9f7	4709	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4710	tmpccmrx &= ~TIM_CCMR1_OC2M;
<>	144:ef7eb2e8f9f7	4711	tmpccmrx &= ~TIM_CCMR1_CC2S;
<>	144:ef7eb2e8f9f7	4712
<>	144:ef7eb2e8f9f7	4713	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4714	tmpccmrx \|= (OC_Config->OCMode << 8);
<>	144:ef7eb2e8f9f7	4715
<>	144:ef7eb2e8f9f7	4716	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4717	tmpccer &= ~TIM_CCER_CC2P;
<>	144:ef7eb2e8f9f7	4718	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4719	tmpccer \|= (OC_Config->OCPolarity << 4);
<>	144:ef7eb2e8f9f7	4720
<>	144:ef7eb2e8f9f7	4721	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
<>	144:ef7eb2e8f9f7	4722	{
<>	144:ef7eb2e8f9f7	4723	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<>	144:ef7eb2e8f9f7	4724
<>	144:ef7eb2e8f9f7	4725	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4726	tmpccer &= ~TIM_CCER_CC2NP;
<>	144:ef7eb2e8f9f7	4727	/* Set the Output N Polarity */
<>	144:ef7eb2e8f9f7	4728	tmpccer \|= (OC_Config->OCNPolarity << 4);
<>	144:ef7eb2e8f9f7	4729	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4730	tmpccer &= ~TIM_CCER_CC2NE;
<>	144:ef7eb2e8f9f7	4731
<>	144:ef7eb2e8f9f7	4732	}
<>	144:ef7eb2e8f9f7	4733
<>	144:ef7eb2e8f9f7	4734	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4735	{
<>	144:ef7eb2e8f9f7	4736	/* Check parameters */
<>	144:ef7eb2e8f9f7	4737	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<>	144:ef7eb2e8f9f7	4738	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4739
<>	144:ef7eb2e8f9f7	4740	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4741	tmpcr2 &= ~TIM_CR2_OIS2;
<>	144:ef7eb2e8f9f7	4742	tmpcr2 &= ~TIM_CR2_OIS2N;
<>	144:ef7eb2e8f9f7	4743	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4744	tmpcr2 \|= (OC_Config->OCIdleState << 2);
<>	144:ef7eb2e8f9f7	4745	/* Set the Output N Idle state */
<>	144:ef7eb2e8f9f7	4746	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
<>	144:ef7eb2e8f9f7	4747	}
<>	144:ef7eb2e8f9f7	4748
<>	144:ef7eb2e8f9f7	4749	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4750	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4751
<>	144:ef7eb2e8f9f7	4752	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	4753	TIMx->CCMR1 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4754
<>	144:ef7eb2e8f9f7	4755	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4756	TIMx->CCR2 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4757
<>	144:ef7eb2e8f9f7	4758	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4759	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4760	}
<>	144:ef7eb2e8f9f7	4761
<>	144:ef7eb2e8f9f7	4762	/**
<>	144:ef7eb2e8f9f7	4763	* @brief Time Ouput Compare 3 configuration
<>	144:ef7eb2e8f9f7	4764	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4765	* @param OC_Config : The ouput configuration structure
<>	144:ef7eb2e8f9f7	4766	* @retval None
<>	144:ef7eb2e8f9f7	4767	*/
<>	144:ef7eb2e8f9f7	4768	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4769	{
<>	144:ef7eb2e8f9f7	4770	uint32_t tmpccmrx = 0;
<>	144:ef7eb2e8f9f7	4771	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	4772	uint32_t tmpcr2 = 0;
<>	144:ef7eb2e8f9f7	4773
<>	144:ef7eb2e8f9f7	4774	/* Disable the Channel 3: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4775	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	144:ef7eb2e8f9f7	4776
<>	144:ef7eb2e8f9f7	4777	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4778	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4779	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4780	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4781
<>	144:ef7eb2e8f9f7	4782	/* Get the TIMx CCMR2 register value */
<>	144:ef7eb2e8f9f7	4783	tmpccmrx = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4784
<>	144:ef7eb2e8f9f7	4785	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4786	tmpccmrx &= ~TIM_CCMR2_OC3M;
<>	144:ef7eb2e8f9f7	4787	tmpccmrx &= ~TIM_CCMR2_CC3S;
<>	144:ef7eb2e8f9f7	4788	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4789	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	4790
<>	144:ef7eb2e8f9f7	4791	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4792	tmpccer &= ~TIM_CCER_CC3P;
<>	144:ef7eb2e8f9f7	4793	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4794	tmpccer \|= (OC_Config->OCPolarity << 8);
<>	144:ef7eb2e8f9f7	4795
<>	144:ef7eb2e8f9f7	4796	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
<>	144:ef7eb2e8f9f7	4797	{
<>	144:ef7eb2e8f9f7	4798	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<>	144:ef7eb2e8f9f7	4799
<>	144:ef7eb2e8f9f7	4800	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4801	tmpccer &= ~TIM_CCER_CC3NP;
<>	144:ef7eb2e8f9f7	4802	/* Set the Output N Polarity */
<>	144:ef7eb2e8f9f7	4803	tmpccer \|= (OC_Config->OCNPolarity << 8);
<>	144:ef7eb2e8f9f7	4804	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4805	tmpccer &= ~TIM_CCER_CC3NE;
<>	144:ef7eb2e8f9f7	4806	}
<>	144:ef7eb2e8f9f7	4807
<>	144:ef7eb2e8f9f7	4808	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4809	{
<>	144:ef7eb2e8f9f7	4810	/* Check parameters */
<>	144:ef7eb2e8f9f7	4811	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<>	144:ef7eb2e8f9f7	4812	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4813
<>	144:ef7eb2e8f9f7	4814	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4815	tmpcr2 &= ~TIM_CR2_OIS3;
<>	144:ef7eb2e8f9f7	4816	tmpcr2 &= ~TIM_CR2_OIS3N;
<>	144:ef7eb2e8f9f7	4817	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4818	tmpcr2 \|= (OC_Config->OCIdleState << 4);
<>	144:ef7eb2e8f9f7	4819	/* Set the Output N Idle state */
<>	144:ef7eb2e8f9f7	4820	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
<>	144:ef7eb2e8f9f7	4821	}
<>	144:ef7eb2e8f9f7	4822
<>	144:ef7eb2e8f9f7	4823	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4824	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4825
<>	144:ef7eb2e8f9f7	4826	/* Write to TIMx CCMR2 */
<>	144:ef7eb2e8f9f7	4827	TIMx->CCMR2 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4828
<>	144:ef7eb2e8f9f7	4829	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4830	TIMx->CCR3 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4831
<>	144:ef7eb2e8f9f7	4832	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4833	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4834	}
<>	144:ef7eb2e8f9f7	4835
<>	144:ef7eb2e8f9f7	4836	/**
<>	144:ef7eb2e8f9f7	4837	* @brief Time Ouput Compare 4 configuration
<>	144:ef7eb2e8f9f7	4838	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4839	* @param OC_Config : The ouput configuration structure
<>	144:ef7eb2e8f9f7	4840	* @retval None
<>	144:ef7eb2e8f9f7	4841	*/
<>	144:ef7eb2e8f9f7	4842	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4843	{
<>	144:ef7eb2e8f9f7	4844	uint32_t tmpccmrx = 0;
<>	144:ef7eb2e8f9f7	4845	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	4846	uint32_t tmpcr2 = 0;
<>	144:ef7eb2e8f9f7	4847
<>	144:ef7eb2e8f9f7	4848	/* Disable the Channel 4: Reset the CC4E Bit */
<>	144:ef7eb2e8f9f7	4849	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	144:ef7eb2e8f9f7	4850
<>	144:ef7eb2e8f9f7	4851	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4852	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4853	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4854	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4855
<>	144:ef7eb2e8f9f7	4856	/* Get the TIMx CCMR2 register value */
<>	144:ef7eb2e8f9f7	4857	tmpccmrx = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4858
<>	144:ef7eb2e8f9f7	4859	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4860	tmpccmrx &= ~TIM_CCMR2_OC4M;
<>	144:ef7eb2e8f9f7	4861	tmpccmrx &= ~TIM_CCMR2_CC4S;
<>	144:ef7eb2e8f9f7	4862
<>	144:ef7eb2e8f9f7	4863	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4864	tmpccmrx \|= (OC_Config->OCMode << 8);
<>	144:ef7eb2e8f9f7	4865
<>	144:ef7eb2e8f9f7	4866	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4867	tmpccer &= ~TIM_CCER_CC4P;
<>	144:ef7eb2e8f9f7	4868	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4869	tmpccer \|= (OC_Config->OCPolarity << 12);
<>	144:ef7eb2e8f9f7	4870
<>	144:ef7eb2e8f9f7	4871	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4872	{
<>	144:ef7eb2e8f9f7	4873	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4874
<>	144:ef7eb2e8f9f7	4875	/* Reset the Output Compare IDLE State */
<>	144:ef7eb2e8f9f7	4876	tmpcr2 &= ~TIM_CR2_OIS4;
<>	144:ef7eb2e8f9f7	4877	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4878	tmpcr2 \|= (OC_Config->OCIdleState << 6);
<>	144:ef7eb2e8f9f7	4879	}
<>	144:ef7eb2e8f9f7	4880
<>	144:ef7eb2e8f9f7	4881	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4882	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4883
<>	144:ef7eb2e8f9f7	4884	/* Write to TIMx CCMR2 */
<>	144:ef7eb2e8f9f7	4885	TIMx->CCMR2 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4886
<>	144:ef7eb2e8f9f7	4887	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4888	TIMx->CCR4 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4889
<>	144:ef7eb2e8f9f7	4890	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4891	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4892	}
<>	144:ef7eb2e8f9f7	4893
<>	144:ef7eb2e8f9f7	4894	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	4895	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	144:ef7eb2e8f9f7	4896	{
<>	144:ef7eb2e8f9f7	4897	uint32_t tmpsmcr = 0;
<>	144:ef7eb2e8f9f7	4898	uint32_t tmpccmr1 = 0;
<>	144:ef7eb2e8f9f7	4899	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	4900
<>	144:ef7eb2e8f9f7	4901	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	4902	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	4903
<>	144:ef7eb2e8f9f7	4904	/* Reset the Trigger Selection Bits */
<>	144:ef7eb2e8f9f7	4905	tmpsmcr &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	4906	/* Set the Input Trigger source */
<>	144:ef7eb2e8f9f7	4907	tmpsmcr \|= sSlaveConfig->InputTrigger;
<>	144:ef7eb2e8f9f7	4908
<>	144:ef7eb2e8f9f7	4909	/* Reset the slave mode Bits */
<>	144:ef7eb2e8f9f7	4910	tmpsmcr &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	4911	/* Set the slave mode */
<>	144:ef7eb2e8f9f7	4912	tmpsmcr \|= sSlaveConfig->SlaveMode;
<>	144:ef7eb2e8f9f7	4913
<>	144:ef7eb2e8f9f7	4914	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	4915	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	4916
<>	144:ef7eb2e8f9f7	4917	/* Configure the trigger prescaler, filter, and polarity */
<>	144:ef7eb2e8f9f7	4918	switch (sSlaveConfig->InputTrigger)
<>	144:ef7eb2e8f9f7	4919	{
<>	144:ef7eb2e8f9f7	4920	case TIM_TS_ETRF:
<>	144:ef7eb2e8f9f7	4921	{
<>	144:ef7eb2e8f9f7	4922	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4923	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4924	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<>	144:ef7eb2e8f9f7	4925	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	4926	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4927	/* Configure the ETR Trigger source */
<>	144:ef7eb2e8f9f7	4928	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	4929	sSlaveConfig->TriggerPrescaler,
<>	144:ef7eb2e8f9f7	4930	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	4931	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	4932	}
<>	144:ef7eb2e8f9f7	4933	break;
<>	144:ef7eb2e8f9f7	4934
<>	144:ef7eb2e8f9f7	4935	case TIM_TS_TI1F_ED:
<>	144:ef7eb2e8f9f7	4936	{
<>	144:ef7eb2e8f9f7	4937	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4938	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4939	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4940
<>	144:ef7eb2e8f9f7	4941	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4942	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	4943	htim->Instance->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4944	tmpccmr1 = htim->Instance->CCMR1;
<>	144:ef7eb2e8f9f7	4945
<>	144:ef7eb2e8f9f7	4946	/* Set the filter */
<>	144:ef7eb2e8f9f7	4947	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	144:ef7eb2e8f9f7	4948	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
<>	144:ef7eb2e8f9f7	4949
<>	144:ef7eb2e8f9f7	4950	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	4951	htim->Instance->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	4952	htim->Instance->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4953
<>	144:ef7eb2e8f9f7	4954	}
<>	144:ef7eb2e8f9f7	4955	break;
<>	144:ef7eb2e8f9f7	4956
<>	144:ef7eb2e8f9f7	4957	case TIM_TS_TI1FP1:
<>	144:ef7eb2e8f9f7	4958	{
<>	144:ef7eb2e8f9f7	4959	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4960	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4961	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	4962	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4963
<>	144:ef7eb2e8f9f7	4964	/* Configure TI1 Filter and Polarity */
<>	144:ef7eb2e8f9f7	4965	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4966	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	4967	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	4968	}
<>	144:ef7eb2e8f9f7	4969	break;
<>	144:ef7eb2e8f9f7	4970
<>	144:ef7eb2e8f9f7	4971	case TIM_TS_TI2FP2:
<>	144:ef7eb2e8f9f7	4972	{
<>	144:ef7eb2e8f9f7	4973	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4974	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4975	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	4976	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4977
<>	144:ef7eb2e8f9f7	4978	/* Configure TI2 Filter and Polarity */
<>	144:ef7eb2e8f9f7	4979	TIM_TI2_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4980	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	4981	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	4982	}
<>	144:ef7eb2e8f9f7	4983	break;
<>	144:ef7eb2e8f9f7	4984
<>	144:ef7eb2e8f9f7	4985	case TIM_TS_ITR0:
<>	144:ef7eb2e8f9f7	4986	{
<>	144:ef7eb2e8f9f7	4987	/* Check the parameter */
<>	144:ef7eb2e8f9f7	4988	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4989	}
<>	144:ef7eb2e8f9f7	4990	break;
<>	144:ef7eb2e8f9f7	4991
<>	144:ef7eb2e8f9f7	4992	case TIM_TS_ITR1:
<>	144:ef7eb2e8f9f7	4993	{
<>	144:ef7eb2e8f9f7	4994	/* Check the parameter */
<>	144:ef7eb2e8f9f7	4995	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4996	}
<>	144:ef7eb2e8f9f7	4997	break;
<>	144:ef7eb2e8f9f7	4998
<>	144:ef7eb2e8f9f7	4999	case TIM_TS_ITR2:
<>	144:ef7eb2e8f9f7	5000	{
<>	144:ef7eb2e8f9f7	5001	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5002	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5003	}
<>	144:ef7eb2e8f9f7	5004	break;
<>	144:ef7eb2e8f9f7	5005
<>	144:ef7eb2e8f9f7	5006	case TIM_TS_ITR3:
<>	144:ef7eb2e8f9f7	5007	{
<>	144:ef7eb2e8f9f7	5008	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5009	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5010	}
<>	144:ef7eb2e8f9f7	5011	break;
<>	144:ef7eb2e8f9f7	5012
<>	144:ef7eb2e8f9f7	5013	default:
<>	144:ef7eb2e8f9f7	5014	break;
<>	144:ef7eb2e8f9f7	5015	}
<>	144:ef7eb2e8f9f7	5016	}
<>	144:ef7eb2e8f9f7	5017
<>	144:ef7eb2e8f9f7	5018	/**
<>	144:ef7eb2e8f9f7	5019	* @brief Configure the TI1 as Input.
<>	144:ef7eb2e8f9f7	5020	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	5021	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5022	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5023	* @arg TIM_ICPOLARITY_RISING
<>	144:ef7eb2e8f9f7	5024	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5025	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	5026	* @param TIM_ICSelection : specifies the input to be used.
<>	144:ef7eb2e8f9f7	5027	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5028	* @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
<>	144:ef7eb2e8f9f7	5029	* @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
<>	144:ef7eb2e8f9f7	5030	* @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5031	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5032	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5033	* @retval None
<>	144:ef7eb2e8f9f7	5034	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<>	144:ef7eb2e8f9f7	5035	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<>	144:ef7eb2e8f9f7	5036	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5037	*/
<>	144:ef7eb2e8f9f7	5038	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5039	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5040	{
<>	144:ef7eb2e8f9f7	5041	uint32_t tmpccmr1 = 0;
<>	144:ef7eb2e8f9f7	5042	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	5043
<>	144:ef7eb2e8f9f7	5044	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	5045	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	5046	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5047	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5048
<>	144:ef7eb2e8f9f7	5049	/* Select the Input */
<>	144:ef7eb2e8f9f7	5050	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	5051	{
<>	144:ef7eb2e8f9f7	5052	tmpccmr1 &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	5053	tmpccmr1 \|= TIM_ICSelection;
<>	144:ef7eb2e8f9f7	5054	}
<>	144:ef7eb2e8f9f7	5055	else
<>	144:ef7eb2e8f9f7	5056	{
<>	144:ef7eb2e8f9f7	5057	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
<>	144:ef7eb2e8f9f7	5058	}
<>	144:ef7eb2e8f9f7	5059
<>	144:ef7eb2e8f9f7	5060	/* Set the filter */
<>	144:ef7eb2e8f9f7	5061	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	144:ef7eb2e8f9f7	5062	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
<>	144:ef7eb2e8f9f7	5063
<>	144:ef7eb2e8f9f7	5064	/* Select the Polarity and set the CC1E Bit */
<>	144:ef7eb2e8f9f7	5065	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	144:ef7eb2e8f9f7	5066	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
<>	144:ef7eb2e8f9f7	5067
<>	144:ef7eb2e8f9f7	5068	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5069	TIMx->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	5070	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5071	}
<>	144:ef7eb2e8f9f7	5072
<>	144:ef7eb2e8f9f7	5073	/**
<>	144:ef7eb2e8f9f7	5074	* @brief Configure the Polarity and Filter for TI1.
<>	144:ef7eb2e8f9f7	5075	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	5076	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5077	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5078	* @arg TIM_ICPOLARITY_RISING
<>	144:ef7eb2e8f9f7	5079	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5080	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	5081	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5082	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5083	* @retval None
<>	144:ef7eb2e8f9f7	5084	*/
<>	144:ef7eb2e8f9f7	5085	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5086	{
<>	144:ef7eb2e8f9f7	5087	uint32_t tmpccmr1 = 0;
<>	144:ef7eb2e8f9f7	5088	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	5089
<>	144:ef7eb2e8f9f7	5090	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	5091	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5092	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	5093	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5094
<>	144:ef7eb2e8f9f7	5095	/* Set the filter */
<>	144:ef7eb2e8f9f7	5096	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	144:ef7eb2e8f9f7	5097	tmpccmr1 \|= (TIM_ICFilter << 4);
<>	144:ef7eb2e8f9f7	5098
<>	144:ef7eb2e8f9f7	5099	/* Select the Polarity and set the CC1E Bit */
<>	144:ef7eb2e8f9f7	5100	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	144:ef7eb2e8f9f7	5101	tmpccer \|= TIM_ICPolarity;
<>	144:ef7eb2e8f9f7	5102
<>	144:ef7eb2e8f9f7	5103	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5104	TIMx->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	5105	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5106	}
<>	144:ef7eb2e8f9f7	5107
<>	144:ef7eb2e8f9f7	5108	/**
<>	144:ef7eb2e8f9f7	5109	* @brief Configure the TI2 as Input.
<>	144:ef7eb2e8f9f7	5110	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5111	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5112	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5113	* @arg TIM_ICPOLARITY_RISING
<>	144:ef7eb2e8f9f7	5114	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5115	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	5116	* @param TIM_ICSelection : specifies the input to be used.
<>	144:ef7eb2e8f9f7	5117	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5118	* @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
<>	144:ef7eb2e8f9f7	5119	* @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
<>	144:ef7eb2e8f9f7	5120	* @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5121	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5122	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5123	* @retval None
<>	144:ef7eb2e8f9f7	5124	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<>	144:ef7eb2e8f9f7	5125	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<>	144:ef7eb2e8f9f7	5126	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5127	*/
<>	144:ef7eb2e8f9f7	5128	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5129	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5130	{
<>	144:ef7eb2e8f9f7	5131	uint32_t tmpccmr1 = 0;
<>	144:ef7eb2e8f9f7	5132	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	5133
<>	144:ef7eb2e8f9f7	5134	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	5135	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	5136	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5137	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5138
<>	144:ef7eb2e8f9f7	5139	/* Select the Input */
<>	144:ef7eb2e8f9f7	5140	tmpccmr1 &= ~TIM_CCMR1_CC2S;
<>	144:ef7eb2e8f9f7	5141	tmpccmr1 \|= (TIM_ICSelection << 8);
<>	144:ef7eb2e8f9f7	5142
<>	144:ef7eb2e8f9f7	5143	/* Set the filter */
<>	144:ef7eb2e8f9f7	5144	tmpccmr1 &= ~TIM_CCMR1_IC2F;
<>	144:ef7eb2e8f9f7	5145	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
<>	144:ef7eb2e8f9f7	5146
<>	144:ef7eb2e8f9f7	5147	/* Select the Polarity and set the CC2E Bit */
<>	144:ef7eb2e8f9f7	5148	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	144:ef7eb2e8f9f7	5149	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
<>	144:ef7eb2e8f9f7	5150
<>	144:ef7eb2e8f9f7	5151	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5152	TIMx->CCMR1 = tmpccmr1 ;
<>	144:ef7eb2e8f9f7	5153	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5154	}
<>	144:ef7eb2e8f9f7	5155
<>	144:ef7eb2e8f9f7	5156	/**
<>	144:ef7eb2e8f9f7	5157	* @brief Configure the Polarity and Filter for TI2.
<>	144:ef7eb2e8f9f7	5158	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	5159	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5160	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5161	* @arg TIM_ICPOLARITY_RISING
<>	144:ef7eb2e8f9f7	5162	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5163	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	5164	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5165	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5166	* @retval None
<>	144:ef7eb2e8f9f7	5167	*/
<>	144:ef7eb2e8f9f7	5168	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5169	{
<>	144:ef7eb2e8f9f7	5170	uint32_t tmpccmr1 = 0;
<>	144:ef7eb2e8f9f7	5171	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	5172
<>	144:ef7eb2e8f9f7	5173	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	5174	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	5175	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5176	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5177
<>	144:ef7eb2e8f9f7	5178	/* Set the filter */
<>	144:ef7eb2e8f9f7	5179	tmpccmr1 &= ~TIM_CCMR1_IC2F;
<>	144:ef7eb2e8f9f7	5180	tmpccmr1 \|= (TIM_ICFilter << 12);
<>	144:ef7eb2e8f9f7	5181
<>	144:ef7eb2e8f9f7	5182	/* Select the Polarity and set the CC2E Bit */
<>	144:ef7eb2e8f9f7	5183	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	144:ef7eb2e8f9f7	5184	tmpccer \|= (TIM_ICPolarity << 4);
<>	144:ef7eb2e8f9f7	5185
<>	144:ef7eb2e8f9f7	5186	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5187	TIMx->CCMR1 = tmpccmr1 ;
<>	144:ef7eb2e8f9f7	5188	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5189	}
<>	144:ef7eb2e8f9f7	5190
<>	144:ef7eb2e8f9f7	5191	/**
<>	144:ef7eb2e8f9f7	5192	* @brief Configure the TI3 as Input.
<>	144:ef7eb2e8f9f7	5193	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5194	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5195	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5196	* @arg TIM_ICPOLARITY_RISING
<>	144:ef7eb2e8f9f7	5197	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5198	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	5199	* @param TIM_ICSelection : specifies the input to be used.
<>	144:ef7eb2e8f9f7	5200	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5201	* @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
<>	144:ef7eb2e8f9f7	5202	* @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
<>	144:ef7eb2e8f9f7	5203	* @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5204	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5205	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5206	* @retval None
<>	144:ef7eb2e8f9f7	5207	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<>	144:ef7eb2e8f9f7	5208	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<>	144:ef7eb2e8f9f7	5209	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5210	*/
<>	144:ef7eb2e8f9f7	5211	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5212	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5213	{
<>	144:ef7eb2e8f9f7	5214	uint32_t tmpccmr2 = 0;
<>	144:ef7eb2e8f9f7	5215	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	5216
<>	144:ef7eb2e8f9f7	5217	/* Disable the Channel 3: Reset the CC3E Bit */
<>	144:ef7eb2e8f9f7	5218	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	144:ef7eb2e8f9f7	5219	tmpccmr2 = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	5220	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5221
<>	144:ef7eb2e8f9f7	5222	/* Select the Input */
<>	144:ef7eb2e8f9f7	5223	tmpccmr2 &= ~TIM_CCMR2_CC3S;
<>	144:ef7eb2e8f9f7	5224	tmpccmr2 \|= TIM_ICSelection;
<>	144:ef7eb2e8f9f7	5225
<>	144:ef7eb2e8f9f7	5226	/* Set the filter */
<>	144:ef7eb2e8f9f7	5227	tmpccmr2 &= ~TIM_CCMR2_IC3F;
<>	144:ef7eb2e8f9f7	5228	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
<>	144:ef7eb2e8f9f7	5229
<>	144:ef7eb2e8f9f7	5230	/* Select the Polarity and set the CC3E Bit */
<>	144:ef7eb2e8f9f7	5231	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
<>	144:ef7eb2e8f9f7	5232	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
<>	144:ef7eb2e8f9f7	5233
<>	144:ef7eb2e8f9f7	5234	/* Write to TIMx CCMR2 and CCER registers */
<>	144:ef7eb2e8f9f7	5235	TIMx->CCMR2 = tmpccmr2;
<>	144:ef7eb2e8f9f7	5236	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5237	}
<>	144:ef7eb2e8f9f7	5238
<>	144:ef7eb2e8f9f7	5239	/**
<>	144:ef7eb2e8f9f7	5240	* @brief Configure the TI4 as Input.
<>	144:ef7eb2e8f9f7	5241	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5242	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5243	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5244	* @arg TIM_ICPOLARITY_RISING
<>	144:ef7eb2e8f9f7	5245	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5246	* @arg TIM_ICPOLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	5247	* @param TIM_ICSelection : specifies the input to be used.
<>	144:ef7eb2e8f9f7	5248	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5249	* @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
<>	144:ef7eb2e8f9f7	5250	* @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
<>	144:ef7eb2e8f9f7	5251	* @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5252	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5253	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5254	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<>	144:ef7eb2e8f9f7	5255	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<>	144:ef7eb2e8f9f7	5256	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5257	* @retval None
<>	144:ef7eb2e8f9f7	5258	*/
<>	144:ef7eb2e8f9f7	5259	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5260	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5261	{
<>	144:ef7eb2e8f9f7	5262	uint32_t tmpccmr2 = 0;
<>	144:ef7eb2e8f9f7	5263	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	5264
<>	144:ef7eb2e8f9f7	5265	/* Disable the Channel 4: Reset the CC4E Bit */
<>	144:ef7eb2e8f9f7	5266	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	144:ef7eb2e8f9f7	5267	tmpccmr2 = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	5268	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5269
<>	144:ef7eb2e8f9f7	5270	/* Select the Input */
<>	144:ef7eb2e8f9f7	5271	tmpccmr2 &= ~TIM_CCMR2_CC4S;
<>	144:ef7eb2e8f9f7	5272	tmpccmr2 \|= (TIM_ICSelection << 8);
<>	144:ef7eb2e8f9f7	5273
<>	144:ef7eb2e8f9f7	5274	/* Set the filter */
<>	144:ef7eb2e8f9f7	5275	tmpccmr2 &= ~TIM_CCMR2_IC4F;
<>	144:ef7eb2e8f9f7	5276	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
<>	144:ef7eb2e8f9f7	5277
<>	144:ef7eb2e8f9f7	5278	/* Select the Polarity and set the CC4E Bit */
<>	144:ef7eb2e8f9f7	5279	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
<>	144:ef7eb2e8f9f7	5280	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
<>	144:ef7eb2e8f9f7	5281
<>	144:ef7eb2e8f9f7	5282	/* Write to TIMx CCMR2 and CCER registers */
<>	144:ef7eb2e8f9f7	5283	TIMx->CCMR2 = tmpccmr2;
<>	144:ef7eb2e8f9f7	5284	TIMx->CCER = tmpccer ;
<>	144:ef7eb2e8f9f7	5285	}
<>	144:ef7eb2e8f9f7	5286
<>	144:ef7eb2e8f9f7	5287	/**
<>	144:ef7eb2e8f9f7	5288	* @brief Selects the Input Trigger source
<>	144:ef7eb2e8f9f7	5289	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5290	* @param InputTriggerSource : The Input Trigger source.
<>	144:ef7eb2e8f9f7	5291	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5292	* @arg TIM_TS_ITR0 : Internal Trigger 0
<>	144:ef7eb2e8f9f7	5293	* @arg TIM_TS_ITR1 : Internal Trigger 1
<>	144:ef7eb2e8f9f7	5294	* @arg TIM_TS_ITR2 : Internal Trigger 2
<>	144:ef7eb2e8f9f7	5295	* @arg TIM_TS_ITR3 : Internal Trigger 3
<>	144:ef7eb2e8f9f7	5296	* @arg TIM_TS_TI1F_ED : TI1 Edge Detector
<>	144:ef7eb2e8f9f7	5297	* @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
<>	144:ef7eb2e8f9f7	5298	* @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
<>	144:ef7eb2e8f9f7	5299	* @arg TIM_TS_ETRF : External Trigger input
<>	144:ef7eb2e8f9f7	5300	* @retval None
<>	144:ef7eb2e8f9f7	5301	*/
<>	144:ef7eb2e8f9f7	5302	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
<>	144:ef7eb2e8f9f7	5303	{
<>	144:ef7eb2e8f9f7	5304	uint32_t tmpsmcr = 0;
<>	144:ef7eb2e8f9f7	5305
<>	144:ef7eb2e8f9f7	5306	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	5307	tmpsmcr = TIMx->SMCR;
<>	144:ef7eb2e8f9f7	5308	/* Reset the TS Bits */
<>	144:ef7eb2e8f9f7	5309	tmpsmcr &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	5310	/* Set the Input Trigger source and the slave mode*/
<>	144:ef7eb2e8f9f7	5311	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
<>	144:ef7eb2e8f9f7	5312	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	5313	TIMx->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	5314	}
<>	144:ef7eb2e8f9f7	5315	/**
<>	144:ef7eb2e8f9f7	5316	* @brief Configures the TIMx External Trigger (ETR).
<>	144:ef7eb2e8f9f7	5317	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5318	* @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
<>	144:ef7eb2e8f9f7	5319	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5320	* @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
<>	144:ef7eb2e8f9f7	5321	* @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
<>	144:ef7eb2e8f9f7	5322	* @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
<>	144:ef7eb2e8f9f7	5323	* @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
<>	144:ef7eb2e8f9f7	5324	* @param TIM_ExtTRGPolarity : The external Trigger Polarity.
<>	144:ef7eb2e8f9f7	5325	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5326	* @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
<>	144:ef7eb2e8f9f7	5327	* @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
<>	144:ef7eb2e8f9f7	5328	* @param ExtTRGFilter : External Trigger Filter.
<>	144:ef7eb2e8f9f7	5329	* This parameter must be a value between 0x00 and 0x0F
<>	144:ef7eb2e8f9f7	5330	* @retval None
<>	144:ef7eb2e8f9f7	5331	*/
<>	144:ef7eb2e8f9f7	5332	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<>	144:ef7eb2e8f9f7	5333	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<>	144:ef7eb2e8f9f7	5334	{
<>	144:ef7eb2e8f9f7	5335	uint32_t tmpsmcr = 0;
<>	144:ef7eb2e8f9f7	5336
<>	144:ef7eb2e8f9f7	5337	tmpsmcr = TIMx->SMCR;
<>	144:ef7eb2e8f9f7	5338
<>	144:ef7eb2e8f9f7	5339	/* Reset the ETR Bits */
<>	144:ef7eb2e8f9f7	5340	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	5341
<>	144:ef7eb2e8f9f7	5342	/* Set the Prescaler, the Filter value and the Polarity */
<>	144:ef7eb2e8f9f7	5343	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
<>	144:ef7eb2e8f9f7	5344
<>	144:ef7eb2e8f9f7	5345	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	5346	TIMx->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	5347	}
<>	144:ef7eb2e8f9f7	5348
<>	144:ef7eb2e8f9f7	5349	/**
<>	144:ef7eb2e8f9f7	5350	* @brief Enables or disables the TIM Capture Compare Channel x.
<>	144:ef7eb2e8f9f7	5351	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5352	* @param Channel : specifies the TIM Channel
<>	144:ef7eb2e8f9f7	5353	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5354	* @arg TIM_CHANNEL_1 : TIM Channel 1
<>	144:ef7eb2e8f9f7	5355	* @arg TIM_CHANNEL_2 : TIM Channel 2
<>	144:ef7eb2e8f9f7	5356	* @arg TIM_CHANNEL_3 : TIM Channel 3
<>	144:ef7eb2e8f9f7	5357	* @arg TIM_CHANNEL_4 : TIM Channel 4
<>	144:ef7eb2e8f9f7	5358	* @param ChannelState : specifies the TIM Channel CCxE bit new state.
<>	144:ef7eb2e8f9f7	5359	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<>	144:ef7eb2e8f9f7	5360	* @retval None
<>	144:ef7eb2e8f9f7	5361	*/
<>	144:ef7eb2e8f9f7	5362	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<>	144:ef7eb2e8f9f7	5363	{
<>	144:ef7eb2e8f9f7	5364	uint32_t tmp = 0;
<>	144:ef7eb2e8f9f7	5365
<>	144:ef7eb2e8f9f7	5366	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5367	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	144:ef7eb2e8f9f7	5368	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	5369
<>	144:ef7eb2e8f9f7	5370	tmp = TIM_CCER_CC1E << Channel;
<>	144:ef7eb2e8f9f7	5371
<>	144:ef7eb2e8f9f7	5372	/* Reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	5373	TIMx->CCER &= ~tmp;
<>	144:ef7eb2e8f9f7	5374
<>	144:ef7eb2e8f9f7	5375	/* Set or reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	5376	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
<>	144:ef7eb2e8f9f7	5377	}
<>	144:ef7eb2e8f9f7	5378
<>	144:ef7eb2e8f9f7	5379
<>	144:ef7eb2e8f9f7	5380	/**
<>	144:ef7eb2e8f9f7	5381	* @}
<>	144:ef7eb2e8f9f7	5382	*/
<>	144:ef7eb2e8f9f7	5383
<>	144:ef7eb2e8f9f7	5384	#endif /* HAL_TIM_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	5385	/**
<>	144:ef7eb2e8f9f7	5386	* @}
<>	144:ef7eb2e8f9f7	5387	*/
<>	144:ef7eb2e8f9f7	5388
<>	144:ef7eb2e8f9f7	5389	/**
<>	144:ef7eb2e8f9f7	5390	* @}
<>	144:ef7eb2e8f9f7	5391	*/
<>	144:ef7eb2e8f9f7	5392	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/