mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_spi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief SPI HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The SPI HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SPI_HandleTypeDef hspi;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
<> 144:ef7eb2e8f9f7 26 (##) Enable the SPIx interface clock
<> 144:ef7eb2e8f9f7 27 (##) SPI pins configuration
<> 144:ef7eb2e8f9f7 28 (+++) Enable the clock for the SPI GPIOs
<> 144:ef7eb2e8f9f7 29 (+++) Configure these SPI pins as alternate function push-pull
<> 144:ef7eb2e8f9f7 30 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 31 (+++) Configure the SPIx interrupt priority
<> 144:ef7eb2e8f9f7 32 (+++) Enable the NVIC SPI IRQ handle
<> 144:ef7eb2e8f9f7 33 (##) DMA Configuration if you need to use DMA process
<> 156:95d6b41a828b 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
<> 144:ef7eb2e8f9f7 35 (+++) Enable the DMAx clock
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA handle parameters
<> 156:95d6b41a828b 37 (+++) Configure the DMA Tx or Rx Stream/Channel
<> 144:ef7eb2e8f9f7 38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
<> 156:95d6b41a828b 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
<> 144:ef7eb2e8f9f7 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<> 144:ef7eb2e8f9f7 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 46 by calling the customized HAL_SPI_MspInit() API.
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 Circular mode restriction:
<> 144:ef7eb2e8f9f7 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<> 144:ef7eb2e8f9f7 50 (##) Master 2Lines RxOnly
<> 144:ef7eb2e8f9f7 51 (##) Master 1Line Rx
<> 144:ef7eb2e8f9f7 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
<> 144:ef7eb2e8f9f7 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<> 144:ef7eb2e8f9f7 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<> 156:95d6b41a828b 55 [..]
<> 156:95d6b41a828b 56 Master Receive mode restriction:
<> 156:95d6b41a828b 57 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
<> 156:95d6b41a828b 58 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
<> 156:95d6b41a828b 59 does not initiate a new transfer the following procedure has to be respected:
<> 156:95d6b41a828b 60 (##) HAL_SPI_DeInit()
<> 156:95d6b41a828b 61 (##) HAL_SPI_Init()
<> 156:95d6b41a828b 62 [..]
<> 156:95d6b41a828b 63 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
<> 156:95d6b41a828b 64 the following table resume the max SPI frequency reached with data size 8bits/16bits,
<> 156:95d6b41a828b 65 according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
<> 156:95d6b41a828b 66
<> 156:95d6b41a828b 67 DataSize = SPI_DATASIZE_8BIT:
<> 156:95d6b41a828b 68 +----------------------------------------------------------------------------------------------+
<> 156:95d6b41a828b 69 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 156:95d6b41a828b 70 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 156:95d6b41a828b 71 | | | Master | Slave | Master | Slave | Master | Slave |
<> 156:95d6b41a828b 72 |==============================================================================================|
<> 156:95d6b41a828b 73 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 156:95d6b41a828b 74 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 75 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
<> 156:95d6b41a828b 76 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 77 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
<> 156:95d6b41a828b 78 |=========|================|==========|==========|===========|==========|===========|==========|
<> 156:95d6b41a828b 79 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
<> 156:95d6b41a828b 80 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 81 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
<> 156:95d6b41a828b 82 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 83 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
<> 156:95d6b41a828b 84 |=========|================|==========|==========|===========|==========|===========|==========|
<> 156:95d6b41a828b 85 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
<> 156:95d6b41a828b 86 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 87 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
<> 156:95d6b41a828b 88 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 89 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
<> 156:95d6b41a828b 90 +----------------------------------------------------------------------------------------------+
<> 156:95d6b41a828b 91
<> 156:95d6b41a828b 92 DataSize = SPI_DATASIZE_16BIT:
<> 156:95d6b41a828b 93 +----------------------------------------------------------------------------------------------+
<> 156:95d6b41a828b 94 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 156:95d6b41a828b 95 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 156:95d6b41a828b 96 | | | Master | Slave | Master | Slave | Master | Slave |
<> 156:95d6b41a828b 97 |==============================================================================================|
<> 156:95d6b41a828b 98 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 156:95d6b41a828b 99 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 100 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
<> 156:95d6b41a828b 101 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 102 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
<> 156:95d6b41a828b 103 |=========|================|==========|==========|===========|==========|===========|==========|
<> 156:95d6b41a828b 104 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
<> 156:95d6b41a828b 105 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 106 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
<> 156:95d6b41a828b 107 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 108 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
<> 156:95d6b41a828b 109 |=========|================|==========|==========|===========|==========|===========|==========|
<> 156:95d6b41a828b 110 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
<> 156:95d6b41a828b 111 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 112 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
<> 156:95d6b41a828b 113 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 114 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
<> 156:95d6b41a828b 115 +----------------------------------------------------------------------------------------------+
<> 156:95d6b41a828b 116 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
<> 156:95d6b41a828b 117 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
<> 156:95d6b41a828b 118 @note
<> 156:95d6b41a828b 119 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
<> 156:95d6b41a828b 120 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
<> 156:95d6b41a828b 121 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 @endverbatim
<> 144:ef7eb2e8f9f7 124 ******************************************************************************
<> 144:ef7eb2e8f9f7 125 * @attention
<> 144:ef7eb2e8f9f7 126 *
<> 144:ef7eb2e8f9f7 127 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 130 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 131 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 132 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 133 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 134 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 135 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 136 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 137 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 138 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 139 *
<> 144:ef7eb2e8f9f7 140 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 141 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 142 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 143 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 144 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 145 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 146 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 147 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 148 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 149 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 150 *
<> 144:ef7eb2e8f9f7 151 ******************************************************************************
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 155 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup SPI SPI
<> 144:ef7eb2e8f9f7 162 * @brief SPI HAL module driver
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 168 /* Private defines -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 169 /** @defgroup SPI_Private_Constants SPI Private Constants
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 156:95d6b41a828b 172 #define SPI_DEFAULT_TIMEOUT 100U
<> 144:ef7eb2e8f9f7 173 /**
<> 144:ef7eb2e8f9f7 174 * @}
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 178 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 179 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 180 /** @defgroup SPI_Private_Functions SPI Private Functions
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 184 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 185 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 186 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 187 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 188 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 189 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 190 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 191 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 192 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 193 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
<> 156:95d6b41a828b 194 uint32_t Timeout, uint32_t Tickstart);
<> 156:95d6b41a828b 195 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
<> 156:95d6b41a828b 196 uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 197 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 198 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 199 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 200 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 201 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 202 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 203 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 204 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 205 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 206 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 207 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 208 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 209 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 210 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 211 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 212 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 213 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 214 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 215 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 216 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<> 156:95d6b41a828b 217 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @}
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221
<> 156:95d6b41a828b 222 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 223 /** @defgroup SPI_Exported_Functions SPI Exported Functions
<> 144:ef7eb2e8f9f7 224 * @{
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 228 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 229 *
<> 144:ef7eb2e8f9f7 230 @verbatim
<> 144:ef7eb2e8f9f7 231 ===============================================================================
<> 144:ef7eb2e8f9f7 232 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 233 ===============================================================================
<> 144:ef7eb2e8f9f7 234 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 235 de-initialize the SPIx peripheral:
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 (+) User must implement HAL_SPI_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 238 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 (+) Call the function HAL_SPI_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 241 the selected configuration:
<> 144:ef7eb2e8f9f7 242 (++) Mode
<> 144:ef7eb2e8f9f7 243 (++) Direction
<> 144:ef7eb2e8f9f7 244 (++) Data Size
<> 144:ef7eb2e8f9f7 245 (++) Clock Polarity and Phase
<> 144:ef7eb2e8f9f7 246 (++) NSS Management
<> 144:ef7eb2e8f9f7 247 (++) BaudRate Prescaler
<> 144:ef7eb2e8f9f7 248 (++) FirstBit
<> 144:ef7eb2e8f9f7 249 (++) TIMode
<> 144:ef7eb2e8f9f7 250 (++) CRC Calculation
<> 144:ef7eb2e8f9f7 251 (++) CRC Polynomial if CRC enabled
<> 144:ef7eb2e8f9f7 252 (++) CRC Length, used only with Data8 and Data16
<> 144:ef7eb2e8f9f7 253 (++) FIFO reception threshold
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 256 of the selected SPIx peripheral.
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 @endverbatim
<> 144:ef7eb2e8f9f7 259 * @{
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief Initialize the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 264 * in the SPI_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 265 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 266 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 267 * @retval HAL status
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 uint32_t frxth;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Check the SPI handle allocation */
<> 156:95d6b41a828b 274 if (hspi == NULL)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Check the parameters */
<> 144:ef7eb2e8f9f7 280 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 281 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 144:ef7eb2e8f9f7 282 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 283 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 284 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 285 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
<> 144:ef7eb2e8f9f7 286 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 287 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 144:ef7eb2e8f9f7 288 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<> 156:95d6b41a828b 289 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
<> 156:95d6b41a828b 290 {
<> 156:95d6b41a828b 291 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 156:95d6b41a828b 292 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 156:95d6b41a828b 293 }
<> 156:95d6b41a828b 294 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 295 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<> 156:95d6b41a828b 296 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 156:95d6b41a828b 297 {
<> 156:95d6b41a828b 298 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<> 156:95d6b41a828b 299 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
<> 156:95d6b41a828b 300 }
<> 156:95d6b41a828b 301 #else
<> 156:95d6b41a828b 302 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 156:95d6b41a828b 303 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 304
<> 156:95d6b41a828b 305 if (hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 308 hspi->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 311 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Disable the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 317 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Align by default the rs fifo threshold on the data size */
<> 156:95d6b41a828b 320 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 frxth = SPI_RXFIFO_THRESHOLD_HF;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 else
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 frxth = SPI_RXFIFO_THRESHOLD_QF;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* CRC calculation is valid only for 16Bit and 8 Bit */
<> 156:95d6b41a828b 330 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 /* CRC must be disabled */
<> 144:ef7eb2e8f9f7 333 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Align the CRC Length on the data size */
<> 156:95d6b41a828b 337 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 /* CRC Length aligned on the data size : value set by default */
<> 156:95d6b41a828b 340 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344 else
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349
<> 156:95d6b41a828b 350 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 351 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
<> 156:95d6b41a828b 352 Communication speed, First bit, CRC calculation state */
<> 156:95d6b41a828b 353 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
<> 156:95d6b41a828b 354 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 156:95d6b41a828b 355 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
<> 156:95d6b41a828b 356 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 357 /* Configure : CRC Length */
<> 156:95d6b41a828b 358 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 359 {
<> 156:95d6b41a828b 360 hspi->Instance->CR1 |= SPI_CR1_CRCL;
<> 144:ef7eb2e8f9f7 361 }
<> 156:95d6b41a828b 362 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 363
<> 156:95d6b41a828b 364 /* Configure : NSS management, TI Mode and Rx Fifo Threshold */
<> 156:95d6b41a828b 365 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
<> 156:95d6b41a828b 366 hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
<> 156:95d6b41a828b 367
<> 156:95d6b41a828b 368 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 369 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 144:ef7eb2e8f9f7 370 /* Configure : CRC Polynomial */
<> 156:95d6b41a828b 371 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 156:95d6b41a828b 372 {
<> 156:95d6b41a828b 373 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
<> 156:95d6b41a828b 374 }
<> 156:95d6b41a828b 375 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 376
<> 156:95d6b41a828b 377 #if defined(SPI_I2SCFGR_I2SMOD)
<> 144:ef7eb2e8f9f7 378 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 156:95d6b41a828b 379 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 156:95d6b41a828b 380 #endif /* SPI_I2SCFGR_I2SMOD */
<> 156:95d6b41a828b 381
<> 144:ef7eb2e8f9f7 382 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 383 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 return HAL_OK;
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 156:95d6b41a828b 389 * @brief De-Initialize the SPI peripheral.
<> 144:ef7eb2e8f9f7 390 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 391 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 392 * @retval HAL status
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 /* Check the SPI handle allocation */
<> 156:95d6b41a828b 397 if (hspi == NULL)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401
<> 156:95d6b41a828b 402 /* Check SPI Instance parameter */
<> 144:ef7eb2e8f9f7 403 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 156:95d6b41a828b 404
<> 144:ef7eb2e8f9f7 405 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Disable the SPI Peripheral Clock */
<> 144:ef7eb2e8f9f7 408 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 411 HAL_SPI_MspDeInit(hspi);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 414 hspi->State = HAL_SPI_STATE_RESET;
<> 144:ef7eb2e8f9f7 415
<> 156:95d6b41a828b 416 /* Release Lock */
<> 144:ef7eb2e8f9f7 417 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 return HAL_OK;
<> 144:ef7eb2e8f9f7 420 }
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @brief Initialize the SPI MSP.
<> 144:ef7eb2e8f9f7 424 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 425 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 426 * @retval None
<> 144:ef7eb2e8f9f7 427 */
<> 144:ef7eb2e8f9f7 428 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 431 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 432
<> 156:95d6b41a828b 433 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 434 the HAL_SPI_MspInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 156:95d6b41a828b 439 * @brief De-Initialize the SPI MSP.
<> 144:ef7eb2e8f9f7 440 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 441 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 442 * @retval None
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 447 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 450 the HAL_SPI_MspDeInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @}
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 459 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 460 *
<> 144:ef7eb2e8f9f7 461 @verbatim
<> 144:ef7eb2e8f9f7 462 ==============================================================================
<> 144:ef7eb2e8f9f7 463 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 464 ===============================================================================
<> 144:ef7eb2e8f9f7 465 [..]
<> 144:ef7eb2e8f9f7 466 This subsection provides a set of functions allowing to manage the SPI
<> 144:ef7eb2e8f9f7 467 data transfers.
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 [..] The SPI supports master and slave mode :
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 472 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 473 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 474 after finishing transfer.
<> 144:ef7eb2e8f9f7 475 (++) No-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 476 or DMA, These APIs return the HAL status.
<> 144:ef7eb2e8f9f7 477 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 478 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 479 using DMA mode.
<> 144:ef7eb2e8f9f7 480 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 481 will be executed respectively at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 482 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<> 144:ef7eb2e8f9f7 485 exist for 1Line (simplex) and 2Lines (full duplex) modes.
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 @endverbatim
<> 144:ef7eb2e8f9f7 488 * @{
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /**
<> 144:ef7eb2e8f9f7 492 * @brief Transmit an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 493 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 494 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 495 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 496 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 497 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 498 * @retval HAL status
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 501 {
<> 156:95d6b41a828b 502 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 503 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 504
<> 156:95d6b41a828b 505 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 506 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Process Locked */
<> 144:ef7eb2e8f9f7 509 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 510
<> 156:95d6b41a828b 511 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 512 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 513
<> 156:95d6b41a828b 514 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 517 goto error;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519
<> 156:95d6b41a828b 520 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 523 goto error;
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 527 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 528 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 529 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 530 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 531 hspi->TxXferCount = Size;
<> 156:95d6b41a828b 532
<> 156:95d6b41a828b 533 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 534 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 535 hspi->RxXferSize = 0U;
<> 156:95d6b41a828b 536 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 537 hspi->TxISR = NULL;
<> 156:95d6b41a828b 538 hspi->RxISR = NULL;
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 541 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545
<> 156:95d6b41a828b 546 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 547 /* Reset CRC Calculation */
<> 156:95d6b41a828b 548 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 549 {
<> 144:ef7eb2e8f9f7 550 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 551 }
<> 156:95d6b41a828b 552 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 555 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 558 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* Transmit data in 16 Bit mode */
<> 156:95d6b41a828b 562 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 563 {
<> 156:95d6b41a828b 564 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
<> 156:95d6b41a828b 565 {
<> 156:95d6b41a828b 566 hspi->Instance->DR = *((uint16_t *)pData);
<> 156:95d6b41a828b 567 pData += sizeof(uint16_t);
<> 156:95d6b41a828b 568 hspi->TxXferCount--;
<> 156:95d6b41a828b 569 }
<> 144:ef7eb2e8f9f7 570 /* Transmit data in 16 Bit mode */
<> 156:95d6b41a828b 571 while (hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 /* Wait until TXE flag is set to send data */
<> 156:95d6b41a828b 574 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 575 {
<> 156:95d6b41a828b 576 hspi->Instance->DR = *((uint16_t *)pData);
<> 156:95d6b41a828b 577 pData += sizeof(uint16_t);
<> 156:95d6b41a828b 578 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580 else
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 /* Timeout management */
<> 156:95d6b41a828b 583 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 586 goto error;
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 592 else
<> 144:ef7eb2e8f9f7 593 {
<> 156:95d6b41a828b 594 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
<> 156:95d6b41a828b 595 {
<> 156:95d6b41a828b 596 if (hspi->TxXferCount > 1U)
<> 156:95d6b41a828b 597 {
<> 156:95d6b41a828b 598 /* write on the data register in packing mode */
<> 156:95d6b41a828b 599 hspi->Instance->DR = *((uint16_t *)pData);
<> 156:95d6b41a828b 600 pData += sizeof(uint16_t);
<> 156:95d6b41a828b 601 hspi->TxXferCount -= 2U;
<> 156:95d6b41a828b 602 }
<> 156:95d6b41a828b 603 else
<> 156:95d6b41a828b 604 {
<> 156:95d6b41a828b 605 *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
<> 156:95d6b41a828b 606 hspi->TxXferCount--;
<> 156:95d6b41a828b 607 }
<> 156:95d6b41a828b 608 }
<> 156:95d6b41a828b 609 while (hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 610 {
<> 144:ef7eb2e8f9f7 611 /* Wait until TXE flag is set to send data */
<> 156:95d6b41a828b 612 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 613 {
<> 156:95d6b41a828b 614 if (hspi->TxXferCount > 1U)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 /* write on the data register in packing mode */
<> 156:95d6b41a828b 617 hspi->Instance->DR = *((uint16_t *)pData);
<> 156:95d6b41a828b 618 pData += sizeof(uint16_t);
<> 156:95d6b41a828b 619 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621 else
<> 144:ef7eb2e8f9f7 622 {
<> 156:95d6b41a828b 623 *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
<> 144:ef7eb2e8f9f7 624 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 else
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* Timeout management */
<> 156:95d6b41a828b 630 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 633 goto error;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636 }
<> 144:ef7eb2e8f9f7 637 }
<> 156:95d6b41a828b 638 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 639 /* Enable CRC Transmission */
<> 156:95d6b41a828b 640 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 641 {
<> 156:95d6b41a828b 642 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 643 }
<> 156:95d6b41a828b 644 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Check the end of the transaction */
<> 156:95d6b41a828b 647 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 650 }
<> 156:95d6b41a828b 651
<> 144:ef7eb2e8f9f7 652 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 156:95d6b41a828b 653 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
<> 156:95d6b41a828b 658 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 659 {
<> 144:ef7eb2e8f9f7 660 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 error:
<> 144:ef7eb2e8f9f7 664 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 665 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 666 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 667 return errorcode;
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 672 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 673 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 674 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 675 * @param Size: amount of data to be received
<> 144:ef7eb2e8f9f7 676 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 677 * @retval HAL status
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 680 {
<> 156:95d6b41a828b 681 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 682 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 683 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 684 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 685 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 686
<> 156:95d6b41a828b 687 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 688 {
<> 156:95d6b41a828b 689 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 156:95d6b41a828b 690 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 156:95d6b41a828b 691 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Process Locked */
<> 144:ef7eb2e8f9f7 695 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 696
<> 156:95d6b41a828b 697 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 698 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 699
<> 156:95d6b41a828b 700 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 703 goto error;
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705
<> 156:95d6b41a828b 706 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 709 goto error;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711
<> 156:95d6b41a828b 712 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 713 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 714 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 715 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 716 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 717 hspi->RxXferCount = Size;
<> 156:95d6b41a828b 718
<> 156:95d6b41a828b 719 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 720 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 721 hspi->TxXferSize = 0U;
<> 156:95d6b41a828b 722 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 723 hspi->RxISR = NULL;
<> 156:95d6b41a828b 724 hspi->TxISR = NULL;
<> 156:95d6b41a828b 725
<> 156:95d6b41a828b 726 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 727 /* Reset CRC Calculation */
<> 156:95d6b41a828b 728 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 731 /* this is done to handle the CRCNEXT before the latest data */
<> 144:ef7eb2e8f9f7 732 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 733 }
<> 156:95d6b41a828b 734 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Set the Rx Fido threshold */
<> 156:95d6b41a828b 737 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 /* set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 740 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742 else
<> 144:ef7eb2e8f9f7 743 {
<> 144:ef7eb2e8f9f7 744 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 745 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 746 }
<> 144:ef7eb2e8f9f7 747
<> 156:95d6b41a828b 748 /* Configure communication direction: 1Line */
<> 156:95d6b41a828b 749 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 750 {
<> 144:ef7eb2e8f9f7 751 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 755 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 758 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760
<> 156:95d6b41a828b 761 /* Receive data in 8 Bit mode */
<> 156:95d6b41a828b 762 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 763 {
<> 144:ef7eb2e8f9f7 764 /* Transfer loop */
<> 156:95d6b41a828b 765 while (hspi->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 /* Check the RXNE flag */
<> 156:95d6b41a828b 768 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 /* read the received data */
<> 156:95d6b41a828b 771 (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 156:95d6b41a828b 772 pData += sizeof(uint8_t);
<> 144:ef7eb2e8f9f7 773 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775 else
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 /* Timeout management */
<> 156:95d6b41a828b 778 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 781 goto error;
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784 }
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786 else
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 /* Transfer loop */
<> 156:95d6b41a828b 789 while (hspi->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 /* Check the RXNE flag */
<> 156:95d6b41a828b 792 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 793 {
<> 156:95d6b41a828b 794 *((uint16_t *)pData) = hspi->Instance->DR;
<> 156:95d6b41a828b 795 pData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 796 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798 else
<> 144:ef7eb2e8f9f7 799 {
<> 144:ef7eb2e8f9f7 800 /* Timeout management */
<> 156:95d6b41a828b 801 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 804 goto error;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809
<> 156:95d6b41a828b 810 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 811 /* Handle the CRC Transmission */
<> 156:95d6b41a828b 812 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 813 {
<> 144:ef7eb2e8f9f7 814 /* freeze the CRC before the latest data */
<> 156:95d6b41a828b 815 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Read the latest data */
<> 156:95d6b41a828b 818 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 819 {
<> 144:ef7eb2e8f9f7 820 /* the latest data has not been received */
<> 144:ef7eb2e8f9f7 821 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 822 goto error;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Receive last data in 16 Bit mode */
<> 156:95d6b41a828b 826 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 827 {
<> 156:95d6b41a828b 828 *((uint16_t *)pData) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 829 }
<> 144:ef7eb2e8f9f7 830 /* Receive last data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 831 else
<> 144:ef7eb2e8f9f7 832 {
<> 156:95d6b41a828b 833 (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 156:95d6b41a828b 836 /* Wait the CRC data */
<> 156:95d6b41a828b 837 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 838 {
<> 156:95d6b41a828b 839 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 840 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 841 goto error;
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843
<> 156:95d6b41a828b 844 /* Read CRC to Flush DR and RXNE flag */
<> 156:95d6b41a828b 845 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 848 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 849 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851 else
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 854 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 855 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 856
<> 156:95d6b41a828b 857 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 858 {
<> 156:95d6b41a828b 859 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Error on the CRC reception */
<> 156:95d6b41a828b 862 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 863 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 864 goto error;
<> 144:ef7eb2e8f9f7 865 }
<> 144:ef7eb2e8f9f7 866 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 867 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 868 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871 }
<> 156:95d6b41a828b 872 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 873
<> 144:ef7eb2e8f9f7 874 /* Check the end of the transaction */
<> 156:95d6b41a828b 875 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 878 }
<> 144:ef7eb2e8f9f7 879
<> 156:95d6b41a828b 880 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 881 /* Check if CRC error occurred */
<> 156:95d6b41a828b 882 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 883 {
<> 156:95d6b41a828b 884 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 885 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 886 }
<> 156:95d6b41a828b 887 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 888
<> 156:95d6b41a828b 889 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 890 {
<> 144:ef7eb2e8f9f7 891 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 892 }
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 error :
<> 144:ef7eb2e8f9f7 895 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 896 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 897 return errorcode;
<> 144:ef7eb2e8f9f7 898 }
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /**
<> 144:ef7eb2e8f9f7 901 * @brief Transmit and Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 902 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 903 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 904 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 905 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 906 * @param Size: amount of data to be sent and received
<> 144:ef7eb2e8f9f7 907 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 908 * @retval HAL status
<> 144:ef7eb2e8f9f7 909 */
<> 156:95d6b41a828b 910 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
<> 156:95d6b41a828b 911 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 912 {
<> 156:95d6b41a828b 913 uint32_t tmp = 0U, tmp1 = 0U;
<> 156:95d6b41a828b 914 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 915 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 916 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 917 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 918 /* Variable used to alternate Rx and Tx during transfer */
<> 156:95d6b41a828b 919 uint32_t txallowed = 1U;
<> 144:ef7eb2e8f9f7 920 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 921
<> 156:95d6b41a828b 922 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 923 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /* Process Locked */
<> 144:ef7eb2e8f9f7 926 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 927
<> 156:95d6b41a828b 928 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 929 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 930
<> 156:95d6b41a828b 931 tmp = hspi->State;
<> 156:95d6b41a828b 932 tmp1 = hspi->Init.Mode;
<> 156:95d6b41a828b 933
<> 156:95d6b41a828b 934 if (!((tmp == HAL_SPI_STATE_READY) || \
<> 156:95d6b41a828b 935 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 936 {
<> 144:ef7eb2e8f9f7 937 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 938 goto error;
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940
<> 156:95d6b41a828b 941 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 942 {
<> 144:ef7eb2e8f9f7 943 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 944 goto error;
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946
<> 156:95d6b41a828b 947 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 156:95d6b41a828b 948 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 156:95d6b41a828b 949 {
<> 156:95d6b41a828b 950 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 156:95d6b41a828b 951 }
<> 156:95d6b41a828b 952
<> 156:95d6b41a828b 953 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 954 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 955 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 956 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 957 hspi->RxXferSize = Size;
<> 156:95d6b41a828b 958 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 959 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 960 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 961
<> 156:95d6b41a828b 962 /*Init field not used in handle to zero */
<> 156:95d6b41a828b 963 hspi->RxISR = NULL;
<> 156:95d6b41a828b 964 hspi->TxISR = NULL;
<> 156:95d6b41a828b 965
<> 156:95d6b41a828b 966 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 967 /* Reset CRC Calculation */
<> 156:95d6b41a828b 968 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 969 {
<> 144:ef7eb2e8f9f7 970 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 971 }
<> 156:95d6b41a828b 972 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /* Set the Rx Fido threshold */
<> 156:95d6b41a828b 975 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 978 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 979 }
<> 144:ef7eb2e8f9f7 980 else
<> 144:ef7eb2e8f9f7 981 {
<> 144:ef7eb2e8f9f7 982 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 983 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 984 }
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 987 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 990 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /* Transmit and Receive data in 16 Bit mode */
<> 156:95d6b41a828b 994 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 995 {
<> 156:95d6b41a828b 996 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
<> 156:95d6b41a828b 997 {
<> 156:95d6b41a828b 998 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 156:95d6b41a828b 999 pTxData += sizeof(uint16_t);
<> 156:95d6b41a828b 1000 hspi->TxXferCount--;
<> 156:95d6b41a828b 1001 }
<> 156:95d6b41a828b 1002 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 /* Check TXE flag */
<> 156:95d6b41a828b 1005 if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<> 144:ef7eb2e8f9f7 1006 {
<> 156:95d6b41a828b 1007 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 156:95d6b41a828b 1008 pTxData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 1009 hspi->TxXferCount--;
<> 156:95d6b41a828b 1010 /* Next Data is a reception (Rx). Tx not allowed */
<> 156:95d6b41a828b 1011 txallowed = 0U;
<> 156:95d6b41a828b 1012
<> 156:95d6b41a828b 1013 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1014 /* Enable CRC Transmission */
<> 156:95d6b41a828b 1015 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 1016 {
<> 144:ef7eb2e8f9f7 1017 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
<> 156:95d6b41a828b 1018 if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
<> 144:ef7eb2e8f9f7 1019 {
<> 156:95d6b41a828b 1020 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
<> 144:ef7eb2e8f9f7 1021 }
<> 156:95d6b41a828b 1022 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 1023 }
<> 156:95d6b41a828b 1024 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1025 }
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Check RXNE flag */
<> 156:95d6b41a828b 1028 if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<> 144:ef7eb2e8f9f7 1029 {
<> 156:95d6b41a828b 1030 *((uint16_t *)pRxData) = hspi->Instance->DR;
<> 156:95d6b41a828b 1031 pRxData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 1032 hspi->RxXferCount--;
<> 156:95d6b41a828b 1033 /* Next Data is a Transmission (Tx). Tx is allowed */
<> 156:95d6b41a828b 1034 txallowed = 1U;
<> 144:ef7eb2e8f9f7 1035 }
<> 156:95d6b41a828b 1036 if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1039 goto error;
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043 /* Transmit and Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 1044 else
<> 144:ef7eb2e8f9f7 1045 {
<> 156:95d6b41a828b 1046 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
<> 156:95d6b41a828b 1047 {
<> 156:95d6b41a828b 1048 if (hspi->TxXferCount > 1U)
<> 156:95d6b41a828b 1049 {
<> 156:95d6b41a828b 1050 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 156:95d6b41a828b 1051 pTxData += sizeof(uint16_t);
<> 156:95d6b41a828b 1052 hspi->TxXferCount -= 2U;
<> 156:95d6b41a828b 1053 }
<> 156:95d6b41a828b 1054 else
<> 156:95d6b41a828b 1055 {
<> 156:95d6b41a828b 1056 *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
<> 156:95d6b41a828b 1057 hspi->TxXferCount--;
<> 156:95d6b41a828b 1058 }
<> 156:95d6b41a828b 1059 }
<> 156:95d6b41a828b 1060 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
<> 144:ef7eb2e8f9f7 1061 {
<> 144:ef7eb2e8f9f7 1062 /* check TXE flag */
<> 156:95d6b41a828b 1063 if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<> 144:ef7eb2e8f9f7 1064 {
<> 156:95d6b41a828b 1065 if (hspi->TxXferCount > 1U)
<> 144:ef7eb2e8f9f7 1066 {
<> 156:95d6b41a828b 1067 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 156:95d6b41a828b 1068 pTxData += sizeof(uint16_t);
<> 156:95d6b41a828b 1069 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 1070 }
<> 144:ef7eb2e8f9f7 1071 else
<> 144:ef7eb2e8f9f7 1072 {
<> 156:95d6b41a828b 1073 *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
<> 144:ef7eb2e8f9f7 1074 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 1075 }
<> 156:95d6b41a828b 1076 /* Next Data is a reception (Rx). Tx not allowed */
<> 156:95d6b41a828b 1077 txallowed = 0U;
<> 156:95d6b41a828b 1078
<> 156:95d6b41a828b 1079 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1080 /* Enable CRC Transmission */
<> 156:95d6b41a828b 1081 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 1082 {
<> 144:ef7eb2e8f9f7 1083 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
<> 156:95d6b41a828b 1084 if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
<> 144:ef7eb2e8f9f7 1085 {
<> 156:95d6b41a828b 1086 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
<> 144:ef7eb2e8f9f7 1087 }
<> 156:95d6b41a828b 1088 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 1089 }
<> 156:95d6b41a828b 1090 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Wait until RXNE flag is reset */
<> 156:95d6b41a828b 1094 if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<> 144:ef7eb2e8f9f7 1095 {
<> 156:95d6b41a828b 1096 if (hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 1097 {
<> 156:95d6b41a828b 1098 *((uint16_t *)pRxData) = hspi->Instance->DR;
<> 156:95d6b41a828b 1099 pRxData += sizeof(uint16_t);
<> 156:95d6b41a828b 1100 hspi->RxXferCount -= 2U;
<> 156:95d6b41a828b 1101 if (hspi->RxXferCount <= 1U)
<> 144:ef7eb2e8f9f7 1102 {
<> 144:ef7eb2e8f9f7 1103 /* set fiforxthresold before to switch on 8 bit data size */
<> 144:ef7eb2e8f9f7 1104 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106 }
<> 144:ef7eb2e8f9f7 1107 else
<> 144:ef7eb2e8f9f7 1108 {
<> 156:95d6b41a828b 1109 (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1110 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 1111 }
<> 156:95d6b41a828b 1112 /* Next Data is a Transmission (Tx). Tx is allowed */
<> 156:95d6b41a828b 1113 txallowed = 1U;
<> 144:ef7eb2e8f9f7 1114 }
<> 156:95d6b41a828b 1115 if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 1116 {
<> 144:ef7eb2e8f9f7 1117 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1118 goto error;
<> 144:ef7eb2e8f9f7 1119 }
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 }
<> 144:ef7eb2e8f9f7 1122
<> 156:95d6b41a828b 1123 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1124 /* Read CRC from DR to close CRC calculation process */
<> 156:95d6b41a828b 1125 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 /* Wait until TXE flag */
<> 156:95d6b41a828b 1128 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 /* Error on the CRC reception */
<> 156:95d6b41a828b 1131 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1132 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1133 goto error;
<> 144:ef7eb2e8f9f7 1134 }
<> 156:95d6b41a828b 1135 /* Read CRC */
<> 156:95d6b41a828b 1136 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 1137 {
<> 144:ef7eb2e8f9f7 1138 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1139 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 1140 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1141 }
<> 144:ef7eb2e8f9f7 1142 else
<> 144:ef7eb2e8f9f7 1143 {
<> 144:ef7eb2e8f9f7 1144 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1145 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 1146 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1147
<> 156:95d6b41a828b 1148 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 1149 {
<> 156:95d6b41a828b 1150 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 /* Error on the CRC reception */
<> 156:95d6b41a828b 1153 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1154 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1155 goto error;
<> 144:ef7eb2e8f9f7 1156 }
<> 144:ef7eb2e8f9f7 1157 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1158 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 1159 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1160 }
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162 }
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /* Check if CRC error occurred */
<> 156:95d6b41a828b 1165 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 1166 {
<> 156:95d6b41a828b 1167 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1168 /* Clear CRC Flag */
<> 144:ef7eb2e8f9f7 1169 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1172 }
<> 156:95d6b41a828b 1173 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* Check the end of the transaction */
<> 156:95d6b41a828b 1176 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1177 {
<> 144:ef7eb2e8f9f7 1178 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 1179 }
<> 144:ef7eb2e8f9f7 1180
<> 156:95d6b41a828b 1181 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1182 {
<> 144:ef7eb2e8f9f7 1183 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 error :
<> 144:ef7eb2e8f9f7 1187 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1188 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1189 return errorcode;
<> 144:ef7eb2e8f9f7 1190 }
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /**
<> 144:ef7eb2e8f9f7 1193 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1194 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1195 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1196 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1197 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1198 * @retval HAL status
<> 144:ef7eb2e8f9f7 1199 */
<> 144:ef7eb2e8f9f7 1200 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1201 {
<> 144:ef7eb2e8f9f7 1202 HAL_StatusTypeDef errorcode = HAL_OK;
<> 156:95d6b41a828b 1203
<> 156:95d6b41a828b 1204 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1205 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /* Process Locked */
<> 144:ef7eb2e8f9f7 1208 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1209
<> 156:95d6b41a828b 1210 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1211 {
<> 144:ef7eb2e8f9f7 1212 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1213 goto error;
<> 144:ef7eb2e8f9f7 1214 }
<> 144:ef7eb2e8f9f7 1215
<> 156:95d6b41a828b 1216 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1217 {
<> 144:ef7eb2e8f9f7 1218 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1219 goto error;
<> 144:ef7eb2e8f9f7 1220 }
<> 144:ef7eb2e8f9f7 1221
<> 156:95d6b41a828b 1222 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1223 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1224 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1225 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1226 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1227 hspi->TxXferCount = Size;
<> 156:95d6b41a828b 1228
<> 156:95d6b41a828b 1229 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1230 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 1231 hspi->RxXferSize = 0U;
<> 156:95d6b41a828b 1232 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 1233 hspi->RxISR = NULL;
<> 156:95d6b41a828b 1234
<> 144:ef7eb2e8f9f7 1235 /* Set the function for IT treatment */
<> 156:95d6b41a828b 1236 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1237 {
<> 144:ef7eb2e8f9f7 1238 hspi->TxISR = SPI_TxISR_16BIT;
<> 144:ef7eb2e8f9f7 1239 }
<> 144:ef7eb2e8f9f7 1240 else
<> 144:ef7eb2e8f9f7 1241 {
<> 144:ef7eb2e8f9f7 1242 hspi->TxISR = SPI_TxISR_8BIT;
<> 144:ef7eb2e8f9f7 1243 }
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 1246 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1247 {
<> 144:ef7eb2e8f9f7 1248 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1249 }
<> 144:ef7eb2e8f9f7 1250
<> 156:95d6b41a828b 1251 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1252 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1253 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1254 {
<> 144:ef7eb2e8f9f7 1255 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1256 }
<> 156:95d6b41a828b 1257 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /* Enable TXE and ERR interrupt */
<> 156:95d6b41a828b 1260 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1264 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1265 {
<> 144:ef7eb2e8f9f7 1266 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1267 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1268 }
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 error :
<> 144:ef7eb2e8f9f7 1271 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1272 return errorcode;
<> 144:ef7eb2e8f9f7 1273 }
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /**
<> 144:ef7eb2e8f9f7 1276 * @brief Receive an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1277 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1278 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1279 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1280 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1281 * @retval HAL status
<> 144:ef7eb2e8f9f7 1282 */
<> 144:ef7eb2e8f9f7 1283 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1284 {
<> 144:ef7eb2e8f9f7 1285 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1286
<> 156:95d6b41a828b 1287 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<> 156:95d6b41a828b 1288 {
<> 156:95d6b41a828b 1289 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 156:95d6b41a828b 1290 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 156:95d6b41a828b 1291 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<> 156:95d6b41a828b 1292 }
<> 156:95d6b41a828b 1293
<> 144:ef7eb2e8f9f7 1294 /* Process Locked */
<> 144:ef7eb2e8f9f7 1295 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1296
<> 156:95d6b41a828b 1297 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1298 {
<> 144:ef7eb2e8f9f7 1299 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1300 goto error;
<> 144:ef7eb2e8f9f7 1301 }
<> 156:95d6b41a828b 1302
<> 156:95d6b41a828b 1303 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1304 {
<> 144:ef7eb2e8f9f7 1305 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1306 goto error;
<> 144:ef7eb2e8f9f7 1307 }
<> 144:ef7eb2e8f9f7 1308
<> 156:95d6b41a828b 1309 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1310 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1311 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1312 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1313 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1314 hspi->RxXferCount = Size;
<> 156:95d6b41a828b 1315
<> 156:95d6b41a828b 1316 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1317 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 1318 hspi->TxXferSize = 0U;
<> 156:95d6b41a828b 1319 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 1320 hspi->TxISR = NULL;
<> 156:95d6b41a828b 1321
<> 144:ef7eb2e8f9f7 1322 /* check the data size to adapt Rx threshold and the set the function for IT treatment */
<> 156:95d6b41a828b 1323 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 /* set fiforxthresold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1326 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1327 hspi->RxISR = SPI_RxISR_16BIT;
<> 144:ef7eb2e8f9f7 1328 }
<> 144:ef7eb2e8f9f7 1329 else
<> 144:ef7eb2e8f9f7 1330 {
<> 144:ef7eb2e8f9f7 1331 /* set fiforxthresold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1332 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1333 hspi->RxISR = SPI_RxISR_8BIT;
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 1337 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1338 {
<> 144:ef7eb2e8f9f7 1339 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1340 }
<> 144:ef7eb2e8f9f7 1341
<> 156:95d6b41a828b 1342 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1343 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1344 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1345 {
<> 156:95d6b41a828b 1346 hspi->CRCSize = 1U;
<> 156:95d6b41a828b 1347 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 156:95d6b41a828b 1348 {
<> 156:95d6b41a828b 1349 hspi->CRCSize = 2U;
<> 156:95d6b41a828b 1350 }
<> 144:ef7eb2e8f9f7 1351 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1352 }
<> 156:95d6b41a828b 1353 else
<> 156:95d6b41a828b 1354 {
<> 156:95d6b41a828b 1355 hspi->CRCSize = 0U;
<> 156:95d6b41a828b 1356 }
<> 156:95d6b41a828b 1357 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1360 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1361
<> 156:95d6b41a828b 1362 /* Note : The SPI must be enabled after unlocking current process
<> 156:95d6b41a828b 1363 to avoid the risk of SPI interrupt handle execution before current
<> 156:95d6b41a828b 1364 process unlock */
<> 156:95d6b41a828b 1365
<> 144:ef7eb2e8f9f7 1366 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1367 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1368 {
<> 144:ef7eb2e8f9f7 1369 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1370 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1371 }
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 error :
<> 144:ef7eb2e8f9f7 1374 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1375 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1376 return errorcode;
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 /**
<> 144:ef7eb2e8f9f7 1380 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1381 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1382 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1383 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1384 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1385 * @param Size: amount of data to be sent and received
<> 144:ef7eb2e8f9f7 1386 * @retval HAL status
<> 144:ef7eb2e8f9f7 1387 */
<> 144:ef7eb2e8f9f7 1388 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1389 {
<> 156:95d6b41a828b 1390 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 1391 HAL_StatusTypeDef errorcode = HAL_OK;
<> 156:95d6b41a828b 1392
<> 156:95d6b41a828b 1393 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1394 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* Process locked */
<> 144:ef7eb2e8f9f7 1397 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1398
<> 156:95d6b41a828b 1399 tmp = hspi->State;
<> 156:95d6b41a828b 1400 tmp1 = hspi->Init.Mode;
<> 156:95d6b41a828b 1401
<> 156:95d6b41a828b 1402 if (!((tmp == HAL_SPI_STATE_READY) || \
<> 156:95d6b41a828b 1403 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1404 {
<> 144:ef7eb2e8f9f7 1405 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1406 goto error;
<> 144:ef7eb2e8f9f7 1407 }
<> 144:ef7eb2e8f9f7 1408
<> 156:95d6b41a828b 1409 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1410 {
<> 144:ef7eb2e8f9f7 1411 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1412 goto error;
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414
<> 156:95d6b41a828b 1415 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 156:95d6b41a828b 1416 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1417 {
<> 144:ef7eb2e8f9f7 1418 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1419 }
<> 144:ef7eb2e8f9f7 1420
<> 156:95d6b41a828b 1421 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1422 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1423 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1424 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1425 hspi->TxXferCount = Size;
<> 156:95d6b41a828b 1426 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1427 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1428 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1429
<> 144:ef7eb2e8f9f7 1430 /* Set the function for IT treatment */
<> 156:95d6b41a828b 1431 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1432 {
<> 156:95d6b41a828b 1433 hspi->RxISR = SPI_2linesRxISR_16BIT;
<> 156:95d6b41a828b 1434 hspi->TxISR = SPI_2linesTxISR_16BIT;
<> 144:ef7eb2e8f9f7 1435 }
<> 144:ef7eb2e8f9f7 1436 else
<> 144:ef7eb2e8f9f7 1437 {
<> 156:95d6b41a828b 1438 hspi->RxISR = SPI_2linesRxISR_8BIT;
<> 156:95d6b41a828b 1439 hspi->TxISR = SPI_2linesTxISR_8BIT;
<> 144:ef7eb2e8f9f7 1440 }
<> 144:ef7eb2e8f9f7 1441
<> 156:95d6b41a828b 1442 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1443 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1444 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1445 {
<> 156:95d6b41a828b 1446 hspi->CRCSize = 1U;
<> 156:95d6b41a828b 1447 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 156:95d6b41a828b 1448 {
<> 156:95d6b41a828b 1449 hspi->CRCSize = 2U;
<> 156:95d6b41a828b 1450 }
<> 144:ef7eb2e8f9f7 1451 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1452 }
<> 156:95d6b41a828b 1453 else
<> 156:95d6b41a828b 1454 {
<> 156:95d6b41a828b 1455 hspi->CRCSize = 0U;
<> 156:95d6b41a828b 1456 }
<> 156:95d6b41a828b 1457 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 /* check if packing mode is enabled and if there is more than 2 data to receive */
<> 156:95d6b41a828b 1460 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
<> 144:ef7eb2e8f9f7 1461 {
<> 144:ef7eb2e8f9f7 1462 /* set fiforxthresold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1463 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1464 }
<> 144:ef7eb2e8f9f7 1465 else
<> 144:ef7eb2e8f9f7 1466 {
<> 144:ef7eb2e8f9f7 1467 /* set fiforxthresold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1468 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1469 }
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 /* Enable TXE, RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1472 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1473
<> 144:ef7eb2e8f9f7 1474 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1475 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1476 {
<> 144:ef7eb2e8f9f7 1477 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1478 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1479 }
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 error :
<> 144:ef7eb2e8f9f7 1482 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1483 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1484 return errorcode;
<> 144:ef7eb2e8f9f7 1485 }
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /**
<> 144:ef7eb2e8f9f7 1488 * @brief Transmit an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1489 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1490 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1491 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1492 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1493 * @retval HAL status
<> 144:ef7eb2e8f9f7 1494 */
<> 144:ef7eb2e8f9f7 1495 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1496 {
<> 144:ef7eb2e8f9f7 1497 HAL_StatusTypeDef errorcode = HAL_OK;
<> 156:95d6b41a828b 1498
<> 156:95d6b41a828b 1499 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1500 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 /* Process Locked */
<> 144:ef7eb2e8f9f7 1503 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1504
<> 156:95d6b41a828b 1505 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1506 {
<> 144:ef7eb2e8f9f7 1507 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1508 goto error;
<> 144:ef7eb2e8f9f7 1509 }
<> 144:ef7eb2e8f9f7 1510
<> 156:95d6b41a828b 1511 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1512 {
<> 144:ef7eb2e8f9f7 1513 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1514 goto error;
<> 144:ef7eb2e8f9f7 1515 }
<> 144:ef7eb2e8f9f7 1516
<> 156:95d6b41a828b 1517 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1518 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1519 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1520 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1521 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1522 hspi->TxXferCount = Size;
<> 156:95d6b41a828b 1523
<> 156:95d6b41a828b 1524 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1525 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 1526 hspi->TxISR = NULL;
<> 156:95d6b41a828b 1527 hspi->RxISR = NULL;
<> 156:95d6b41a828b 1528 hspi->RxXferSize = 0U;
<> 156:95d6b41a828b 1529 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1530
<> 144:ef7eb2e8f9f7 1531 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 1532 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1533 {
<> 144:ef7eb2e8f9f7 1534 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1535 }
<> 144:ef7eb2e8f9f7 1536
<> 156:95d6b41a828b 1537 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1538 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1539 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1540 {
<> 144:ef7eb2e8f9f7 1541 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1542 }
<> 156:95d6b41a828b 1543 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 /* Set the SPI TxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1546 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /* Set the SPI TxDMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1549 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1552 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1553
<> 156:95d6b41a828b 1554 /* Set the DMA AbortCpltCallback */
<> 156:95d6b41a828b 1555 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1556
<> 144:ef7eb2e8f9f7 1557 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 144:ef7eb2e8f9f7 1558 /* packing mode is enabled only if the DMA setting is HALWORD */
<> 156:95d6b41a828b 1559 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1560 {
<> 144:ef7eb2e8f9f7 1561 /* Check the even/odd of the data size + crc if enabled */
<> 156:95d6b41a828b 1562 if ((hspi->TxXferCount & 0x1U) == 0U)
<> 144:ef7eb2e8f9f7 1563 {
<> 144:ef7eb2e8f9f7 1564 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 156:95d6b41a828b 1565 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
<> 144:ef7eb2e8f9f7 1566 }
<> 144:ef7eb2e8f9f7 1567 else
<> 144:ef7eb2e8f9f7 1568 {
<> 144:ef7eb2e8f9f7 1569 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 156:95d6b41a828b 1570 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1571 }
<> 144:ef7eb2e8f9f7 1572 }
<> 144:ef7eb2e8f9f7 1573
<> 156:95d6b41a828b 1574 /* Enable the Tx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1575 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1578 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1579 {
<> 144:ef7eb2e8f9f7 1580 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1581 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1582 }
<> 144:ef7eb2e8f9f7 1583
<> 156:95d6b41a828b 1584 /* Enable the SPI Error Interrupt Bit */
<> 156:95d6b41a828b 1585 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 156:95d6b41a828b 1586
<> 144:ef7eb2e8f9f7 1587 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1588 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 error :
<> 144:ef7eb2e8f9f7 1591 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1592 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1593 return errorcode;
<> 144:ef7eb2e8f9f7 1594 }
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 /**
<> 144:ef7eb2e8f9f7 1597 * @brief Receive an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1598 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1599 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1600 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1601 * @note When the CRC feature is enabled the pData Length must be Size + 1.
<> 144:ef7eb2e8f9f7 1602 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1603 * @retval HAL status
<> 144:ef7eb2e8f9f7 1604 */
<> 144:ef7eb2e8f9f7 1605 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1606 {
<> 144:ef7eb2e8f9f7 1607 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1608
<> 156:95d6b41a828b 1609 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<> 156:95d6b41a828b 1610 {
<> 156:95d6b41a828b 1611 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 156:95d6b41a828b 1612 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 156:95d6b41a828b 1613 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<> 156:95d6b41a828b 1614 }
<> 156:95d6b41a828b 1615
<> 144:ef7eb2e8f9f7 1616 /* Process Locked */
<> 144:ef7eb2e8f9f7 1617 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1618
<> 156:95d6b41a828b 1619 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1620 {
<> 144:ef7eb2e8f9f7 1621 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1622 goto error;
<> 144:ef7eb2e8f9f7 1623 }
<> 144:ef7eb2e8f9f7 1624
<> 156:95d6b41a828b 1625 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1626 {
<> 144:ef7eb2e8f9f7 1627 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1628 goto error;
<> 144:ef7eb2e8f9f7 1629 }
<> 144:ef7eb2e8f9f7 1630
<> 156:95d6b41a828b 1631 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1632 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1633 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1634 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1635 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1636 hspi->RxXferCount = Size;
<> 156:95d6b41a828b 1637
<> 156:95d6b41a828b 1638 /*Init field not used in handle to zero */
<> 156:95d6b41a828b 1639 hspi->RxISR = NULL;
<> 156:95d6b41a828b 1640 hspi->TxISR = NULL;
<> 156:95d6b41a828b 1641 hspi->TxXferSize = 0U;
<> 156:95d6b41a828b 1642 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1643
<> 144:ef7eb2e8f9f7 1644 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 1645 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1646 {
<> 144:ef7eb2e8f9f7 1647 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1648 }
<> 144:ef7eb2e8f9f7 1649
<> 156:95d6b41a828b 1650 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1651 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1652 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1653 {
<> 144:ef7eb2e8f9f7 1654 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1655 }
<> 156:95d6b41a828b 1656 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 1657
<> 156:95d6b41a828b 1658 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6)|| defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 1659 /* packing mode management is enabled by the DMA settings */
<> 156:95d6b41a828b 1660 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1661 {
<> 144:ef7eb2e8f9f7 1662 /* Restriction the DMA data received is not allowed in this mode */
<> 144:ef7eb2e8f9f7 1663 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1664 goto error;
<> 144:ef7eb2e8f9f7 1665 }
<> 156:95d6b41a828b 1666 #endif
<> 144:ef7eb2e8f9f7 1667
<> 144:ef7eb2e8f9f7 1668 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1669 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1670 {
<> 144:ef7eb2e8f9f7 1671 /* set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1672 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1673 }
<> 144:ef7eb2e8f9f7 1674 else
<> 144:ef7eb2e8f9f7 1675 {
<> 144:ef7eb2e8f9f7 1676 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1677 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 156:95d6b41a828b 1678
<> 156:95d6b41a828b 1679 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 156:95d6b41a828b 1680 {
<> 156:95d6b41a828b 1681 /* set fiforxthresold according the reception data length: 16bit */
<> 156:95d6b41a828b 1682 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 156:95d6b41a828b 1683
<> 156:95d6b41a828b 1684 if ((hspi->RxXferCount & 0x1U) == 0x0U)
<> 156:95d6b41a828b 1685 {
<> 156:95d6b41a828b 1686 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1687 hspi->RxXferCount = hspi->RxXferCount >> 1U;
<> 156:95d6b41a828b 1688 }
<> 156:95d6b41a828b 1689 else
<> 156:95d6b41a828b 1690 {
<> 156:95d6b41a828b 1691 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1692 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
<> 156:95d6b41a828b 1693 }
<> 156:95d6b41a828b 1694 }
<> 144:ef7eb2e8f9f7 1695 }
<> 144:ef7eb2e8f9f7 1696
<> 144:ef7eb2e8f9f7 1697 /* Set the SPI RxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1698 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /* Set the SPI Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1701 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1702
<> 144:ef7eb2e8f9f7 1703 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1704 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1705
<> 156:95d6b41a828b 1706 /* Set the DMA AbortCpltCallback */
<> 156:95d6b41a828b 1707 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1708
<> 156:95d6b41a828b 1709 /* Enable the Rx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1710 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1711
<> 144:ef7eb2e8f9f7 1712 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1713 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1714 {
<> 144:ef7eb2e8f9f7 1715 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1716 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1717 }
<> 144:ef7eb2e8f9f7 1718
<> 156:95d6b41a828b 1719 /* Enable the SPI Error Interrupt Bit */
<> 156:95d6b41a828b 1720 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 156:95d6b41a828b 1721
<> 156:95d6b41a828b 1722 /* Enable Rx DMA Request */
<> 156:95d6b41a828b 1723 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 156:95d6b41a828b 1724
<> 144:ef7eb2e8f9f7 1725 error:
<> 144:ef7eb2e8f9f7 1726 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1727 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1728 return errorcode;
<> 144:ef7eb2e8f9f7 1729 }
<> 144:ef7eb2e8f9f7 1730
<> 144:ef7eb2e8f9f7 1731 /**
<> 144:ef7eb2e8f9f7 1732 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1733 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1734 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1735 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1736 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1737 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
<> 144:ef7eb2e8f9f7 1738 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1739 * @retval HAL status
<> 144:ef7eb2e8f9f7 1740 */
<> 156:95d6b41a828b 1741 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 156:95d6b41a828b 1742 uint16_t Size)
<> 144:ef7eb2e8f9f7 1743 {
<> 156:95d6b41a828b 1744 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 1745 HAL_StatusTypeDef errorcode = HAL_OK;
<> 156:95d6b41a828b 1746
<> 156:95d6b41a828b 1747 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1748 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1749
<> 144:ef7eb2e8f9f7 1750 /* Process locked */
<> 144:ef7eb2e8f9f7 1751 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1752
<> 156:95d6b41a828b 1753 tmp = hspi->State;
<> 156:95d6b41a828b 1754 tmp1 = hspi->Init.Mode;
<> 156:95d6b41a828b 1755 if (!((tmp == HAL_SPI_STATE_READY) ||
<> 156:95d6b41a828b 1756 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1757 {
<> 144:ef7eb2e8f9f7 1758 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1759 goto error;
<> 144:ef7eb2e8f9f7 1760 }
<> 144:ef7eb2e8f9f7 1761
<> 156:95d6b41a828b 1762 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1763 {
<> 144:ef7eb2e8f9f7 1764 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1765 goto error;
<> 144:ef7eb2e8f9f7 1766 }
<> 144:ef7eb2e8f9f7 1767
<> 156:95d6b41a828b 1768 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 156:95d6b41a828b 1769 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1770 {
<> 144:ef7eb2e8f9f7 1771 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1772 }
<> 144:ef7eb2e8f9f7 1773
<> 156:95d6b41a828b 1774 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1775 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1776 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1777 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1778 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1779 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1780 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1781 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1782
<> 156:95d6b41a828b 1783 /* Init field not used in handle to zero */
<> 156:95d6b41a828b 1784 hspi->RxISR = NULL;
<> 156:95d6b41a828b 1785 hspi->TxISR = NULL;
<> 156:95d6b41a828b 1786
<> 156:95d6b41a828b 1787 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 1788 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1789 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1790 {
<> 144:ef7eb2e8f9f7 1791 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1792 }
<> 156:95d6b41a828b 1793 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 1794
<> 156:95d6b41a828b 1795 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
<> 156:95d6b41a828b 1796 /* packing mode management is enabled by the DMA settings */
<> 156:95d6b41a828b 1797 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 156:95d6b41a828b 1798 {
<> 156:95d6b41a828b 1799 /* Restriction the DMA data received is not allowed in this mode */
<> 156:95d6b41a828b 1800 errorcode = HAL_ERROR;
<> 156:95d6b41a828b 1801 goto error;
<> 156:95d6b41a828b 1802 }
<> 156:95d6b41a828b 1803 #endif
<> 144:ef7eb2e8f9f7 1804
<> 144:ef7eb2e8f9f7 1805 /* Reset the threshold bit */
<> 144:ef7eb2e8f9f7 1806 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /* the packing mode management is enabled by the DMA settings according the spi data size */
<> 156:95d6b41a828b 1809 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1810 {
<> 144:ef7eb2e8f9f7 1811 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1812 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1813 }
<> 144:ef7eb2e8f9f7 1814 else
<> 144:ef7eb2e8f9f7 1815 {
<> 144:ef7eb2e8f9f7 1816 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1817 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1818
<> 156:95d6b41a828b 1819 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1820 {
<> 156:95d6b41a828b 1821 if ((hspi->TxXferSize & 0x1U) == 0x0U)
<> 144:ef7eb2e8f9f7 1822 {
<> 144:ef7eb2e8f9f7 1823 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 156:95d6b41a828b 1824 hspi->TxXferCount = hspi->TxXferCount >> 1U;
<> 144:ef7eb2e8f9f7 1825 }
<> 144:ef7eb2e8f9f7 1826 else
<> 144:ef7eb2e8f9f7 1827 {
<> 144:ef7eb2e8f9f7 1828 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 156:95d6b41a828b 1829 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1830 }
<> 144:ef7eb2e8f9f7 1831 }
<> 144:ef7eb2e8f9f7 1832
<> 156:95d6b41a828b 1833 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1834 {
<> 144:ef7eb2e8f9f7 1835 /* set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1836 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1837
<> 156:95d6b41a828b 1838 if ((hspi->RxXferCount & 0x1U) == 0x0U)
<> 144:ef7eb2e8f9f7 1839 {
<> 144:ef7eb2e8f9f7 1840 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1841 hspi->RxXferCount = hspi->RxXferCount >> 1U;
<> 144:ef7eb2e8f9f7 1842 }
<> 144:ef7eb2e8f9f7 1843 else
<> 144:ef7eb2e8f9f7 1844 {
<> 144:ef7eb2e8f9f7 1845 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1846 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1847 }
<> 144:ef7eb2e8f9f7 1848 }
<> 144:ef7eb2e8f9f7 1849 }
<> 144:ef7eb2e8f9f7 1850
<> 156:95d6b41a828b 1851 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<> 156:95d6b41a828b 1852 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1853 {
<> 144:ef7eb2e8f9f7 1854 /* Set the SPI Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1855 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 156:95d6b41a828b 1856 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1857 }
<> 144:ef7eb2e8f9f7 1858 else
<> 144:ef7eb2e8f9f7 1859 {
<> 156:95d6b41a828b 1860 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1861 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<> 156:95d6b41a828b 1862 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1863 }
<> 144:ef7eb2e8f9f7 1864
<> 144:ef7eb2e8f9f7 1865 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1866 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1867
<> 156:95d6b41a828b 1868 /* Set the DMA AbortCpltCallback */
<> 156:95d6b41a828b 1869 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1870
<> 156:95d6b41a828b 1871 /* Enable the Rx DMA Stream/Channel */
<> 156:95d6b41a828b 1872 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 156:95d6b41a828b 1873
<> 144:ef7eb2e8f9f7 1874 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1875 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1876
<> 144:ef7eb2e8f9f7 1877 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<> 144:ef7eb2e8f9f7 1878 is performed in DMA reception complete callback */
<> 144:ef7eb2e8f9f7 1879 hspi->hdmatx->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 1880 hspi->hdmatx->XferCpltCallback = NULL;
<> 156:95d6b41a828b 1881 hspi->hdmatx->XferErrorCallback = NULL;
<> 156:95d6b41a828b 1882 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1883
<> 156:95d6b41a828b 1884 /* Enable the Tx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1885 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1886
<> 144:ef7eb2e8f9f7 1887 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1888 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1889 {
<> 144:ef7eb2e8f9f7 1890 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1891 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1892 }
<> 156:95d6b41a828b 1893 /* Enable the SPI Error Interrupt Bit */
<> 156:95d6b41a828b 1894 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1897 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1898
<> 144:ef7eb2e8f9f7 1899 error :
<> 144:ef7eb2e8f9f7 1900 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1901 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1902 return errorcode;
<> 144:ef7eb2e8f9f7 1903 }
<> 144:ef7eb2e8f9f7 1904
<> 144:ef7eb2e8f9f7 1905 /**
<> 156:95d6b41a828b 1906 * @brief Abort ongoing transfer (blocking mode).
<> 156:95d6b41a828b 1907 * @param hspi SPI handle.
<> 156:95d6b41a828b 1908 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
<> 156:95d6b41a828b 1909 * started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1910 * This procedure performs following operations :
<> 156:95d6b41a828b 1911 * - Disable SPI Interrupts (depending of transfer direction)
<> 156:95d6b41a828b 1912 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1913 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1914 * - Set handle State to READY
<> 156:95d6b41a828b 1915 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1916 * @retval HAL status
<> 156:95d6b41a828b 1917 */
<> 156:95d6b41a828b 1918 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 1919 {
<> 156:95d6b41a828b 1920 HAL_StatusTypeDef errorcode;
<> 156:95d6b41a828b 1921
<> 156:95d6b41a828b 1922 /* Initialized local variable */
<> 156:95d6b41a828b 1923 errorcode = HAL_OK;
<> 156:95d6b41a828b 1924
<> 156:95d6b41a828b 1925 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 156:95d6b41a828b 1926 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
<> 156:95d6b41a828b 1927 {
<> 156:95d6b41a828b 1928 hspi->TxISR = SPI_AbortTx_ISR;
<> 156:95d6b41a828b 1929 while (hspi->State != HAL_SPI_STATE_ABORT)
<> 156:95d6b41a828b 1930 {
<> 156:95d6b41a828b 1931 }
<> 156:95d6b41a828b 1932 }
<> 156:95d6b41a828b 1933
<> 156:95d6b41a828b 1934 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
<> 156:95d6b41a828b 1935 {
<> 156:95d6b41a828b 1936 hspi->RxISR = SPI_AbortRx_ISR;
<> 156:95d6b41a828b 1937 while (hspi->State != HAL_SPI_STATE_ABORT)
<> 156:95d6b41a828b 1938 {
<> 156:95d6b41a828b 1939 }
<> 156:95d6b41a828b 1940 }
<> 156:95d6b41a828b 1941
<> 156:95d6b41a828b 1942 /* Clear ERRIE interrupts in case of DMA Mode */
<> 156:95d6b41a828b 1943 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
<> 156:95d6b41a828b 1944
<> 156:95d6b41a828b 1945 /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
<> 156:95d6b41a828b 1946 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
<> 156:95d6b41a828b 1947 {
<> 156:95d6b41a828b 1948 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1949 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 1950 {
<> 156:95d6b41a828b 1951 /* Set the SPI DMA Abort callback :
<> 156:95d6b41a828b 1952 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1953 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1954
<> 156:95d6b41a828b 1955 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 1956 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 1957 {
<> 156:95d6b41a828b 1958 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 1959 }
<> 156:95d6b41a828b 1960
<> 156:95d6b41a828b 1961 /* Disable Tx DMA Request */
<> 156:95d6b41a828b 1962 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
<> 156:95d6b41a828b 1963
<> 156:95d6b41a828b 1964 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 1965 {
<> 156:95d6b41a828b 1966 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 1967 }
<> 156:95d6b41a828b 1968
<> 156:95d6b41a828b 1969 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 1970 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 1971
<> 156:95d6b41a828b 1972 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 1973 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 1974 {
<> 156:95d6b41a828b 1975 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 1976 }
<> 156:95d6b41a828b 1977 }
<> 156:95d6b41a828b 1978 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1979 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 1980 {
<> 156:95d6b41a828b 1981 /* Set the SPI DMA Abort callback :
<> 156:95d6b41a828b 1982 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1983 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1984
<> 156:95d6b41a828b 1985 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 1986 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1987 {
<> 156:95d6b41a828b 1988 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 1989 }
<> 156:95d6b41a828b 1990
<> 156:95d6b41a828b 1991 /* Disable peripheral */
<> 156:95d6b41a828b 1992 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 1993
<> 156:95d6b41a828b 1994 /* Control the BSY flag */
<> 156:95d6b41a828b 1995 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 1996 {
<> 156:95d6b41a828b 1997 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 1998 }
<> 156:95d6b41a828b 1999
<> 156:95d6b41a828b 2000 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 2001 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2002 {
<> 156:95d6b41a828b 2003 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2004 }
<> 156:95d6b41a828b 2005
<> 156:95d6b41a828b 2006 /* Disable Rx DMA Request */
<> 156:95d6b41a828b 2007 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
<> 156:95d6b41a828b 2008 }
<> 156:95d6b41a828b 2009 }
<> 156:95d6b41a828b 2010 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 2011 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 2012 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2013
<> 156:95d6b41a828b 2014 /* Check error during Abort procedure */
<> 156:95d6b41a828b 2015 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
<> 156:95d6b41a828b 2016 {
<> 156:95d6b41a828b 2017 /* return HAL_Error in case of error during Abort procedure */
<> 156:95d6b41a828b 2018 errorcode = HAL_ERROR;
<> 156:95d6b41a828b 2019 }
<> 156:95d6b41a828b 2020 else
<> 156:95d6b41a828b 2021 {
<> 156:95d6b41a828b 2022 /* Reset errorCode */
<> 156:95d6b41a828b 2023 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 2024 }
<> 156:95d6b41a828b 2025
<> 156:95d6b41a828b 2026 /* Clear the Error flags in the SR register */
<> 156:95d6b41a828b 2027 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 156:95d6b41a828b 2028 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 156:95d6b41a828b 2029
<> 156:95d6b41a828b 2030 /* Restore hspi->state to ready */
<> 156:95d6b41a828b 2031 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 2032
<> 156:95d6b41a828b 2033 return errorcode;
<> 156:95d6b41a828b 2034 }
<> 156:95d6b41a828b 2035
<> 156:95d6b41a828b 2036 /**
<> 156:95d6b41a828b 2037 * @brief Abort ongoing transfer (Interrupt mode).
<> 156:95d6b41a828b 2038 * @param hspi SPI handle.
<> 156:95d6b41a828b 2039 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
<> 156:95d6b41a828b 2040 * started in Interrupt or DMA mode.
<> 156:95d6b41a828b 2041 * This procedure performs following operations :
<> 156:95d6b41a828b 2042 * - Disable SPI Interrupts (depending of transfer direction)
<> 156:95d6b41a828b 2043 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 2044 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 2045 * - Set handle State to READY
<> 156:95d6b41a828b 2046 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 2047 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 2048 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 2049 * @retval HAL status
<> 156:95d6b41a828b 2050 */
<> 156:95d6b41a828b 2051 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 2052 {
<> 156:95d6b41a828b 2053 HAL_StatusTypeDef errorcode;
<> 156:95d6b41a828b 2054 uint32_t abortcplt ;
<> 156:95d6b41a828b 2055
<> 156:95d6b41a828b 2056 /* Initialized local variable */
<> 156:95d6b41a828b 2057 errorcode = HAL_OK;
<> 156:95d6b41a828b 2058 abortcplt = 1U;
<> 156:95d6b41a828b 2059
<> 156:95d6b41a828b 2060 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
<> 156:95d6b41a828b 2061 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
<> 156:95d6b41a828b 2062 {
<> 156:95d6b41a828b 2063 hspi->TxISR = SPI_AbortTx_ISR;
<> 156:95d6b41a828b 2064 while (hspi->State != HAL_SPI_STATE_ABORT)
<> 156:95d6b41a828b 2065 {
<> 156:95d6b41a828b 2066 }
<> 156:95d6b41a828b 2067 }
<> 156:95d6b41a828b 2068
<> 156:95d6b41a828b 2069 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
<> 156:95d6b41a828b 2070 {
<> 156:95d6b41a828b 2071 hspi->RxISR = SPI_AbortRx_ISR;
<> 156:95d6b41a828b 2072 while (hspi->State != HAL_SPI_STATE_ABORT)
<> 156:95d6b41a828b 2073 {
<> 156:95d6b41a828b 2074 }
<> 156:95d6b41a828b 2075 }
<> 156:95d6b41a828b 2076
<> 156:95d6b41a828b 2077 /* Clear ERRIE interrupts in case of DMA Mode */
<> 156:95d6b41a828b 2078 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
<> 156:95d6b41a828b 2079
<> 156:95d6b41a828b 2080 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
<> 156:95d6b41a828b 2081 before any call to DMA Abort functions */
<> 156:95d6b41a828b 2082 /* DMA Tx Handle is valid */
<> 156:95d6b41a828b 2083 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2084 {
<> 156:95d6b41a828b 2085 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
<> 156:95d6b41a828b 2086 Otherwise, set it to NULL */
<> 156:95d6b41a828b 2087 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
<> 156:95d6b41a828b 2088 {
<> 156:95d6b41a828b 2089 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
<> 156:95d6b41a828b 2090 }
<> 156:95d6b41a828b 2091 else
<> 156:95d6b41a828b 2092 {
<> 156:95d6b41a828b 2093 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2094 }
<> 156:95d6b41a828b 2095 }
<> 156:95d6b41a828b 2096 /* DMA Rx Handle is valid */
<> 156:95d6b41a828b 2097 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2098 {
<> 156:95d6b41a828b 2099 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
<> 156:95d6b41a828b 2100 Otherwise, set it to NULL */
<> 156:95d6b41a828b 2101 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
<> 156:95d6b41a828b 2102 {
<> 156:95d6b41a828b 2103 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
<> 156:95d6b41a828b 2104 }
<> 156:95d6b41a828b 2105 else
<> 156:95d6b41a828b 2106 {
<> 156:95d6b41a828b 2107 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2108 }
<> 156:95d6b41a828b 2109 }
<> 156:95d6b41a828b 2110
<> 156:95d6b41a828b 2111 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 156:95d6b41a828b 2112 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
<> 156:95d6b41a828b 2113 {
<> 156:95d6b41a828b 2114 /* Abort the SPI DMA Tx Stream/Channel */
<> 156:95d6b41a828b 2115 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2116 {
<> 156:95d6b41a828b 2117 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2118 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 2119 {
<> 156:95d6b41a828b 2120 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2121 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2122 }
<> 156:95d6b41a828b 2123 else
<> 156:95d6b41a828b 2124 {
<> 156:95d6b41a828b 2125 abortcplt = 0U;
<> 156:95d6b41a828b 2126 }
<> 156:95d6b41a828b 2127 }
<> 156:95d6b41a828b 2128 /* Abort the SPI DMA Rx Stream/Channel */
<> 156:95d6b41a828b 2129 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2130 {
<> 156:95d6b41a828b 2131 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2132 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 2133 {
<> 156:95d6b41a828b 2134 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2135 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2136 abortcplt = 1U;
<> 156:95d6b41a828b 2137 }
<> 156:95d6b41a828b 2138 else
<> 156:95d6b41a828b 2139 {
<> 156:95d6b41a828b 2140 abortcplt = 0U;
<> 156:95d6b41a828b 2141 }
<> 156:95d6b41a828b 2142 }
<> 156:95d6b41a828b 2143 }
<> 156:95d6b41a828b 2144
<> 156:95d6b41a828b 2145 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 156:95d6b41a828b 2146 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
<> 156:95d6b41a828b 2147 {
<> 156:95d6b41a828b 2148 /* Abort the SPI DMA Tx Stream/Channel */
<> 156:95d6b41a828b 2149 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2150 {
<> 156:95d6b41a828b 2151 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2152 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 2153 {
<> 156:95d6b41a828b 2154 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2155 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2156 }
<> 156:95d6b41a828b 2157 else
<> 156:95d6b41a828b 2158 {
<> 156:95d6b41a828b 2159 abortcplt = 0U;
<> 156:95d6b41a828b 2160 }
<> 156:95d6b41a828b 2161 }
<> 156:95d6b41a828b 2162 }
<> 156:95d6b41a828b 2163 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 156:95d6b41a828b 2164 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
<> 156:95d6b41a828b 2165 {
<> 156:95d6b41a828b 2166 /* Abort the SPI DMA Rx Stream/Channel */
<> 156:95d6b41a828b 2167 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2168 {
<> 156:95d6b41a828b 2169 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2170 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 2171 {
<> 156:95d6b41a828b 2172 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2173 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2174 }
<> 156:95d6b41a828b 2175 else
<> 156:95d6b41a828b 2176 {
<> 156:95d6b41a828b 2177 abortcplt = 0U;
<> 156:95d6b41a828b 2178 }
<> 156:95d6b41a828b 2179 }
<> 156:95d6b41a828b 2180 }
<> 156:95d6b41a828b 2181
<> 156:95d6b41a828b 2182 if (abortcplt == 1U)
<> 156:95d6b41a828b 2183 {
<> 156:95d6b41a828b 2184 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 2185 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 2186 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2187
<> 156:95d6b41a828b 2188 /* Check error during Abort procedure */
<> 156:95d6b41a828b 2189 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
<> 156:95d6b41a828b 2190 {
<> 156:95d6b41a828b 2191 /* return HAL_Error in case of error during Abort procedure */
<> 156:95d6b41a828b 2192 errorcode = HAL_ERROR;
<> 156:95d6b41a828b 2193 }
<> 156:95d6b41a828b 2194 else
<> 156:95d6b41a828b 2195 {
<> 156:95d6b41a828b 2196 /* Reset errorCode */
<> 156:95d6b41a828b 2197 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 2198 }
<> 156:95d6b41a828b 2199
<> 156:95d6b41a828b 2200 /* Clear the Error flags in the SR register */
<> 156:95d6b41a828b 2201 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 156:95d6b41a828b 2202 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 156:95d6b41a828b 2203
<> 156:95d6b41a828b 2204 /* Restore hspi->State to Ready */
<> 156:95d6b41a828b 2205 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 2206
<> 156:95d6b41a828b 2207 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 2208 HAL_SPI_AbortCpltCallback(hspi);
<> 156:95d6b41a828b 2209 }
<> 156:95d6b41a828b 2210
<> 156:95d6b41a828b 2211 return errorcode;
<> 156:95d6b41a828b 2212 }
<> 156:95d6b41a828b 2213
<> 156:95d6b41a828b 2214 /**
<> 144:ef7eb2e8f9f7 2215 * @brief Pause the DMA Transfer.
<> 144:ef7eb2e8f9f7 2216 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2217 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2218 * @retval HAL status
<> 144:ef7eb2e8f9f7 2219 */
<> 144:ef7eb2e8f9f7 2220 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2221 {
<> 144:ef7eb2e8f9f7 2222 /* Process Locked */
<> 144:ef7eb2e8f9f7 2223 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 2224
<> 144:ef7eb2e8f9f7 2225 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2226 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2227
<> 144:ef7eb2e8f9f7 2228 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2229 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2230
<> 144:ef7eb2e8f9f7 2231 return HAL_OK;
<> 144:ef7eb2e8f9f7 2232 }
<> 144:ef7eb2e8f9f7 2233
<> 144:ef7eb2e8f9f7 2234 /**
<> 144:ef7eb2e8f9f7 2235 * @brief Resume the DMA Transfer.
<> 144:ef7eb2e8f9f7 2236 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2237 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2238 * @retval HAL status
<> 144:ef7eb2e8f9f7 2239 */
<> 144:ef7eb2e8f9f7 2240 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2241 {
<> 144:ef7eb2e8f9f7 2242 /* Process Locked */
<> 144:ef7eb2e8f9f7 2243 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 2244
<> 144:ef7eb2e8f9f7 2245 /* Enable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2246 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2247
<> 144:ef7eb2e8f9f7 2248 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2249 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2250
<> 144:ef7eb2e8f9f7 2251 return HAL_OK;
<> 144:ef7eb2e8f9f7 2252 }
<> 144:ef7eb2e8f9f7 2253
<> 144:ef7eb2e8f9f7 2254 /**
<> 144:ef7eb2e8f9f7 2255 * @brief Stop the DMA Transfer.
<> 144:ef7eb2e8f9f7 2256 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2257 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2258 * @retval HAL status
<> 144:ef7eb2e8f9f7 2259 */
<> 144:ef7eb2e8f9f7 2260 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2261 {
<> 144:ef7eb2e8f9f7 2262 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 2263 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<> 144:ef7eb2e8f9f7 2264 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 2265 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 2266 */
<> 144:ef7eb2e8f9f7 2267
<> 156:95d6b41a828b 2268 /* Abort the SPI DMA tx Stream/Channel */
<> 156:95d6b41a828b 2269 if (hspi->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 2270 {
<> 144:ef7eb2e8f9f7 2271 HAL_DMA_Abort(hspi->hdmatx);
<> 144:ef7eb2e8f9f7 2272 }
<> 156:95d6b41a828b 2273 /* Abort the SPI DMA rx Stream/Channel */
<> 156:95d6b41a828b 2274 if (hspi->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 2275 {
<> 144:ef7eb2e8f9f7 2276 HAL_DMA_Abort(hspi->hdmarx);
<> 144:ef7eb2e8f9f7 2277 }
<> 144:ef7eb2e8f9f7 2278
<> 144:ef7eb2e8f9f7 2279 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2280 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2281 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2282 return HAL_OK;
<> 144:ef7eb2e8f9f7 2283 }
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 /**
<> 144:ef7eb2e8f9f7 2286 * @brief Handle SPI interrupt request.
<> 144:ef7eb2e8f9f7 2287 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2288 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2289 * @retval None
<> 144:ef7eb2e8f9f7 2290 */
<> 144:ef7eb2e8f9f7 2291 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2292 {
<> 144:ef7eb2e8f9f7 2293 uint32_t itsource = hspi->Instance->CR2;
<> 144:ef7eb2e8f9f7 2294 uint32_t itflag = hspi->Instance->SR;
<> 144:ef7eb2e8f9f7 2295
<> 144:ef7eb2e8f9f7 2296 /* SPI in mode Receiver ----------------------------------------------------*/
<> 156:95d6b41a828b 2297 if (((itflag & SPI_FLAG_OVR) == RESET) &&
<> 156:95d6b41a828b 2298 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 2299 {
<> 144:ef7eb2e8f9f7 2300 hspi->RxISR(hspi);
<> 144:ef7eb2e8f9f7 2301 return;
<> 144:ef7eb2e8f9f7 2302 }
<> 144:ef7eb2e8f9f7 2303
<> 156:95d6b41a828b 2304 /* SPI in mode Transmitter -------------------------------------------------*/
<> 156:95d6b41a828b 2305 if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 2306 {
<> 144:ef7eb2e8f9f7 2307 hspi->TxISR(hspi);
<> 144:ef7eb2e8f9f7 2308 return;
<> 144:ef7eb2e8f9f7 2309 }
<> 144:ef7eb2e8f9f7 2310
<> 156:95d6b41a828b 2311 /* SPI in Error Treatment --------------------------------------------------*/
<> 156:95d6b41a828b 2312 if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 2313 {
<> 156:95d6b41a828b 2314 /* SPI Overrun error interrupt occurred ----------------------------------*/
<> 156:95d6b41a828b 2315 if ((itflag & SPI_FLAG_OVR) != RESET)
<> 144:ef7eb2e8f9f7 2316 {
<> 156:95d6b41a828b 2317 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2318 {
<> 156:95d6b41a828b 2319 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<> 144:ef7eb2e8f9f7 2320 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2321 }
<> 144:ef7eb2e8f9f7 2322 else
<> 144:ef7eb2e8f9f7 2323 {
<> 156:95d6b41a828b 2324 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2325 return;
<> 144:ef7eb2e8f9f7 2326 }
<> 144:ef7eb2e8f9f7 2327 }
<> 144:ef7eb2e8f9f7 2328
<> 156:95d6b41a828b 2329 /* SPI Mode Fault error interrupt occurred -------------------------------*/
<> 156:95d6b41a828b 2330 if ((itflag & SPI_FLAG_MODF) != RESET)
<> 144:ef7eb2e8f9f7 2331 {
<> 156:95d6b41a828b 2332 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<> 144:ef7eb2e8f9f7 2333 __HAL_SPI_CLEAR_MODFFLAG(hspi);
<> 144:ef7eb2e8f9f7 2334 }
<> 144:ef7eb2e8f9f7 2335
<> 156:95d6b41a828b 2336 /* SPI Frame error interrupt occurred ------------------------------------*/
<> 156:95d6b41a828b 2337 if ((itflag & SPI_FLAG_FRE) != RESET)
<> 144:ef7eb2e8f9f7 2338 {
<> 156:95d6b41a828b 2339 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<> 144:ef7eb2e8f9f7 2340 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 144:ef7eb2e8f9f7 2341 }
<> 144:ef7eb2e8f9f7 2342
<> 156:95d6b41a828b 2343 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 156:95d6b41a828b 2344 {
<> 156:95d6b41a828b 2345 /* Disable all interrupts */
<> 156:95d6b41a828b 2346 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
<> 156:95d6b41a828b 2347
<> 156:95d6b41a828b 2348 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 2349 /* Disable the SPI DMA requests if enabled */
<> 156:95d6b41a828b 2350 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
<> 156:95d6b41a828b 2351 {
<> 156:95d6b41a828b 2352 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
<> 156:95d6b41a828b 2353
<> 156:95d6b41a828b 2354 /* Abort the SPI DMA Rx channel */
<> 156:95d6b41a828b 2355 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2356 {
<> 156:95d6b41a828b 2357 /* Set the SPI DMA Abort callback :
<> 156:95d6b41a828b 2358 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 2359 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
<> 156:95d6b41a828b 2360 HAL_DMA_Abort_IT(hspi->hdmarx);
<> 156:95d6b41a828b 2361 }
<> 156:95d6b41a828b 2362 /* Abort the SPI DMA Tx channel */
<> 156:95d6b41a828b 2363 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2364 {
<> 156:95d6b41a828b 2365 /* Set the SPI DMA Abort callback :
<> 156:95d6b41a828b 2366 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 2367 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
<> 156:95d6b41a828b 2368 HAL_DMA_Abort_IT(hspi->hdmatx);
<> 156:95d6b41a828b 2369 }
<> 156:95d6b41a828b 2370 }
<> 156:95d6b41a828b 2371 else
<> 156:95d6b41a828b 2372 {
<> 156:95d6b41a828b 2373 /* Call user error callback */
<> 156:95d6b41a828b 2374 HAL_SPI_ErrorCallback(hspi);
<> 156:95d6b41a828b 2375 }
<> 156:95d6b41a828b 2376 }
<> 144:ef7eb2e8f9f7 2377 return;
<> 144:ef7eb2e8f9f7 2378 }
<> 144:ef7eb2e8f9f7 2379 }
<> 144:ef7eb2e8f9f7 2380
<> 144:ef7eb2e8f9f7 2381 /**
<> 144:ef7eb2e8f9f7 2382 * @brief Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2383 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2384 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2385 * @retval None
<> 144:ef7eb2e8f9f7 2386 */
<> 144:ef7eb2e8f9f7 2387 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2388 {
<> 144:ef7eb2e8f9f7 2389 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2390 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2391
<> 144:ef7eb2e8f9f7 2392 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2393 the HAL_SPI_TxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2394 */
<> 144:ef7eb2e8f9f7 2395 }
<> 144:ef7eb2e8f9f7 2396
<> 144:ef7eb2e8f9f7 2397 /**
<> 144:ef7eb2e8f9f7 2398 * @brief Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2399 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2400 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2401 * @retval None
<> 144:ef7eb2e8f9f7 2402 */
<> 144:ef7eb2e8f9f7 2403 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2404 {
<> 144:ef7eb2e8f9f7 2405 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2406 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2407
<> 144:ef7eb2e8f9f7 2408 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2409 the HAL_SPI_RxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2410 */
<> 144:ef7eb2e8f9f7 2411 }
<> 144:ef7eb2e8f9f7 2412
<> 144:ef7eb2e8f9f7 2413 /**
<> 144:ef7eb2e8f9f7 2414 * @brief Tx and Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2415 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2416 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2417 * @retval None
<> 144:ef7eb2e8f9f7 2418 */
<> 144:ef7eb2e8f9f7 2419 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2420 {
<> 144:ef7eb2e8f9f7 2421 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2422 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2423
<> 144:ef7eb2e8f9f7 2424 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2425 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2426 */
<> 144:ef7eb2e8f9f7 2427 }
<> 144:ef7eb2e8f9f7 2428
<> 144:ef7eb2e8f9f7 2429 /**
<> 144:ef7eb2e8f9f7 2430 * @brief Tx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 2431 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2432 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2433 * @retval None
<> 144:ef7eb2e8f9f7 2434 */
<> 144:ef7eb2e8f9f7 2435 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2436 {
<> 144:ef7eb2e8f9f7 2437 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2438 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2439
<> 144:ef7eb2e8f9f7 2440 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2441 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2442 */
<> 144:ef7eb2e8f9f7 2443 }
<> 144:ef7eb2e8f9f7 2444
<> 144:ef7eb2e8f9f7 2445 /**
<> 144:ef7eb2e8f9f7 2446 * @brief Rx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 2447 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2448 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2449 * @retval None
<> 144:ef7eb2e8f9f7 2450 */
<> 144:ef7eb2e8f9f7 2451 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2452 {
<> 144:ef7eb2e8f9f7 2453 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2454 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2455
<> 144:ef7eb2e8f9f7 2456 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2457 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
<> 144:ef7eb2e8f9f7 2458 */
<> 144:ef7eb2e8f9f7 2459 }
<> 144:ef7eb2e8f9f7 2460
<> 144:ef7eb2e8f9f7 2461 /**
<> 144:ef7eb2e8f9f7 2462 * @brief Tx and Rx Half Transfer callback.
<> 144:ef7eb2e8f9f7 2463 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2464 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2465 * @retval None
<> 144:ef7eb2e8f9f7 2466 */
<> 144:ef7eb2e8f9f7 2467 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2468 {
<> 144:ef7eb2e8f9f7 2469 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2470 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2471
<> 144:ef7eb2e8f9f7 2472 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2473 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
<> 144:ef7eb2e8f9f7 2474 */
<> 144:ef7eb2e8f9f7 2475 }
<> 144:ef7eb2e8f9f7 2476
<> 144:ef7eb2e8f9f7 2477 /**
<> 144:ef7eb2e8f9f7 2478 * @brief SPI error callback.
<> 144:ef7eb2e8f9f7 2479 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2480 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2481 * @retval None
<> 144:ef7eb2e8f9f7 2482 */
<> 156:95d6b41a828b 2483 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2484 {
<> 144:ef7eb2e8f9f7 2485 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2486 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2487
<> 144:ef7eb2e8f9f7 2488 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2489 the HAL_SPI_ErrorCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2490 */
<> 144:ef7eb2e8f9f7 2491 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
<> 144:ef7eb2e8f9f7 2492 and user can use HAL_SPI_GetError() API to check the latest error occurred
<> 144:ef7eb2e8f9f7 2493 */
<> 144:ef7eb2e8f9f7 2494 }
<> 144:ef7eb2e8f9f7 2495
<> 144:ef7eb2e8f9f7 2496 /**
<> 156:95d6b41a828b 2497 * @brief SPI Abort Complete callback.
<> 156:95d6b41a828b 2498 * @param hspi SPI handle.
<> 156:95d6b41a828b 2499 * @retval None
<> 156:95d6b41a828b 2500 */
<> 156:95d6b41a828b 2501 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 2502 {
<> 156:95d6b41a828b 2503 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 2504 UNUSED(hspi);
<> 156:95d6b41a828b 2505
<> 156:95d6b41a828b 2506 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 2507 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 2508 */
<> 156:95d6b41a828b 2509 }
<> 156:95d6b41a828b 2510
<> 156:95d6b41a828b 2511 /**
<> 144:ef7eb2e8f9f7 2512 * @}
<> 144:ef7eb2e8f9f7 2513 */
<> 144:ef7eb2e8f9f7 2514
<> 144:ef7eb2e8f9f7 2515 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 2516 * @brief SPI control functions
<> 144:ef7eb2e8f9f7 2517 *
<> 144:ef7eb2e8f9f7 2518 @verbatim
<> 144:ef7eb2e8f9f7 2519 ===============================================================================
<> 144:ef7eb2e8f9f7 2520 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 2521 ===============================================================================
<> 144:ef7eb2e8f9f7 2522 [..]
<> 144:ef7eb2e8f9f7 2523 This subsection provides a set of functions allowing to control the SPI.
<> 144:ef7eb2e8f9f7 2524 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<> 144:ef7eb2e8f9f7 2525 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<> 144:ef7eb2e8f9f7 2526 @endverbatim
<> 144:ef7eb2e8f9f7 2527 * @{
<> 144:ef7eb2e8f9f7 2528 */
<> 144:ef7eb2e8f9f7 2529
<> 144:ef7eb2e8f9f7 2530 /**
<> 144:ef7eb2e8f9f7 2531 * @brief Return the SPI handle state.
<> 144:ef7eb2e8f9f7 2532 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2533 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2534 * @retval SPI state
<> 144:ef7eb2e8f9f7 2535 */
<> 144:ef7eb2e8f9f7 2536 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2537 {
<> 144:ef7eb2e8f9f7 2538 /* Return SPI handle state */
<> 144:ef7eb2e8f9f7 2539 return hspi->State;
<> 144:ef7eb2e8f9f7 2540 }
<> 144:ef7eb2e8f9f7 2541
<> 144:ef7eb2e8f9f7 2542 /**
<> 144:ef7eb2e8f9f7 2543 * @brief Return the SPI error code.
<> 144:ef7eb2e8f9f7 2544 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2545 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2546 * @retval SPI error code in bitmap format
<> 144:ef7eb2e8f9f7 2547 */
<> 144:ef7eb2e8f9f7 2548 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2549 {
<> 156:95d6b41a828b 2550 /* Return SPI ErrorCode */
<> 144:ef7eb2e8f9f7 2551 return hspi->ErrorCode;
<> 144:ef7eb2e8f9f7 2552 }
<> 144:ef7eb2e8f9f7 2553
<> 144:ef7eb2e8f9f7 2554 /**
<> 144:ef7eb2e8f9f7 2555 * @}
<> 144:ef7eb2e8f9f7 2556 */
<> 144:ef7eb2e8f9f7 2557
<> 144:ef7eb2e8f9f7 2558 /**
<> 144:ef7eb2e8f9f7 2559 * @}
<> 144:ef7eb2e8f9f7 2560 */
<> 144:ef7eb2e8f9f7 2561
<> 144:ef7eb2e8f9f7 2562 /** @addtogroup SPI_Private_Functions
<> 156:95d6b41a828b 2563 * @brief Private functions
<> 144:ef7eb2e8f9f7 2564 * @{
<> 144:ef7eb2e8f9f7 2565 */
<> 144:ef7eb2e8f9f7 2566
<> 144:ef7eb2e8f9f7 2567 /**
<> 144:ef7eb2e8f9f7 2568 * @brief DMA SPI transmit process complete callback.
<> 144:ef7eb2e8f9f7 2569 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2570 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2571 * @retval None
<> 144:ef7eb2e8f9f7 2572 */
<> 144:ef7eb2e8f9f7 2573 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2574 {
<> 156:95d6b41a828b 2575 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2576 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2577
<> 156:95d6b41a828b 2578 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 2579 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2580
<> 156:95d6b41a828b 2581 /* DMA Normal Mode */
<> 156:95d6b41a828b 2582 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2583 {
<> 156:95d6b41a828b 2584 /* Disable ERR interrupt */
<> 156:95d6b41a828b 2585 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 156:95d6b41a828b 2586
<> 144:ef7eb2e8f9f7 2587 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 2588 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 2589
<> 144:ef7eb2e8f9f7 2590 /* Check the end of the transaction */
<> 156:95d6b41a828b 2591 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2592 {
<> 156:95d6b41a828b 2593 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2594 }
<> 144:ef7eb2e8f9f7 2595
<> 144:ef7eb2e8f9f7 2596 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
<> 156:95d6b41a828b 2597 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 2598 {
<> 144:ef7eb2e8f9f7 2599 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2600 }
<> 144:ef7eb2e8f9f7 2601
<> 156:95d6b41a828b 2602 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2603 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2604
<> 156:95d6b41a828b 2605 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2606 {
<> 144:ef7eb2e8f9f7 2607 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2608 return;
<> 144:ef7eb2e8f9f7 2609 }
<> 144:ef7eb2e8f9f7 2610 }
<> 144:ef7eb2e8f9f7 2611 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2612 }
<> 144:ef7eb2e8f9f7 2613
<> 144:ef7eb2e8f9f7 2614 /**
<> 144:ef7eb2e8f9f7 2615 * @brief DMA SPI receive process complete callback.
<> 144:ef7eb2e8f9f7 2616 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2617 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2618 * @retval None
<> 144:ef7eb2e8f9f7 2619 */
<> 144:ef7eb2e8f9f7 2620 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2621 {
<> 156:95d6b41a828b 2622 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2623 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2624 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 2625 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 2626 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 2627
<> 156:95d6b41a828b 2628 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 2629 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2630
<> 156:95d6b41a828b 2631 /* DMA Normal Mode */
<> 156:95d6b41a828b 2632 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2633 {
<> 156:95d6b41a828b 2634 /* Disable ERR interrupt */
<> 156:95d6b41a828b 2635 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 156:95d6b41a828b 2636
<> 156:95d6b41a828b 2637 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2638 /* CRC handling */
<> 156:95d6b41a828b 2639 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2640 {
<> 156:95d6b41a828b 2641 /* Wait until RXNE flag */
<> 156:95d6b41a828b 2642 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2643 {
<> 144:ef7eb2e8f9f7 2644 /* Error on the CRC reception */
<> 156:95d6b41a828b 2645 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2646 }
<> 156:95d6b41a828b 2647 /* Read CRC */
<> 156:95d6b41a828b 2648 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 2649 {
<> 144:ef7eb2e8f9f7 2650 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2651 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2652 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2653 }
<> 144:ef7eb2e8f9f7 2654 else
<> 144:ef7eb2e8f9f7 2655 {
<> 144:ef7eb2e8f9f7 2656 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2657 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2658 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2659
<> 156:95d6b41a828b 2660 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 2661 {
<> 156:95d6b41a828b 2662 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2663 {
<> 144:ef7eb2e8f9f7 2664 /* Error on the CRC reception */
<> 156:95d6b41a828b 2665 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2666 }
<> 144:ef7eb2e8f9f7 2667 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2668 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2669 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2670 }
<> 144:ef7eb2e8f9f7 2671 }
<> 144:ef7eb2e8f9f7 2672 }
<> 156:95d6b41a828b 2673 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 2674
<> 144:ef7eb2e8f9f7 2675 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
<> 144:ef7eb2e8f9f7 2676 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2677
<> 144:ef7eb2e8f9f7 2678 /* Check the end of the transaction */
<> 156:95d6b41a828b 2679 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2680 {
<> 156:95d6b41a828b 2681 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2682 }
<> 144:ef7eb2e8f9f7 2683
<> 156:95d6b41a828b 2684 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2685 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2686
<> 156:95d6b41a828b 2687 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2688 /* Check if CRC error occurred */
<> 156:95d6b41a828b 2689 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 2690 {
<> 156:95d6b41a828b 2691 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2692 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2693 }
<> 156:95d6b41a828b 2694 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 2695
<> 156:95d6b41a828b 2696 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2697 {
<> 144:ef7eb2e8f9f7 2698 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2699 return;
<> 144:ef7eb2e8f9f7 2700 }
<> 144:ef7eb2e8f9f7 2701 }
<> 144:ef7eb2e8f9f7 2702 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2703 }
<> 144:ef7eb2e8f9f7 2704
<> 144:ef7eb2e8f9f7 2705 /**
<> 144:ef7eb2e8f9f7 2706 * @brief DMA SPI transmit receive process complete callback.
<> 156:95d6b41a828b 2707 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2708 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2709 * @retval None
<> 144:ef7eb2e8f9f7 2710 */
<> 144:ef7eb2e8f9f7 2711 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2712 {
<> 156:95d6b41a828b 2713 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2714 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2715 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 2716 __IO int16_t tmpreg = 0U;
<> 156:95d6b41a828b 2717 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 2718 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 2719 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2720
<> 156:95d6b41a828b 2721 /* DMA Normal Mode */
<> 156:95d6b41a828b 2722 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2723 {
<> 156:95d6b41a828b 2724 /* Disable ERR interrupt */
<> 156:95d6b41a828b 2725 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 156:95d6b41a828b 2726
<> 156:95d6b41a828b 2727 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2728 /* CRC handling */
<> 156:95d6b41a828b 2729 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2730 {
<> 156:95d6b41a828b 2731 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
<> 144:ef7eb2e8f9f7 2732 {
<> 156:95d6b41a828b 2733 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
<> 156:95d6b41a828b 2734 tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2735 {
<> 144:ef7eb2e8f9f7 2736 /* Error on the CRC reception */
<> 156:95d6b41a828b 2737 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2738 }
<> 156:95d6b41a828b 2739 /* Read CRC to Flush DR and RXNE flag */
<> 144:ef7eb2e8f9f7 2740 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2741 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2742 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2743 }
<> 144:ef7eb2e8f9f7 2744 else
<> 144:ef7eb2e8f9f7 2745 {
<> 156:95d6b41a828b 2746 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2747 {
<> 144:ef7eb2e8f9f7 2748 /* Error on the CRC reception */
<> 156:95d6b41a828b 2749 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2750 }
<> 156:95d6b41a828b 2751 /* Read CRC to Flush DR and RXNE flag */
<> 144:ef7eb2e8f9f7 2752 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2753 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2754 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2755 }
<> 144:ef7eb2e8f9f7 2756 }
<> 156:95d6b41a828b 2757 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 2758
<> 144:ef7eb2e8f9f7 2759 /* Check the end of the transaction */
<> 156:95d6b41a828b 2760 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2761 {
<> 156:95d6b41a828b 2762 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2763 }
<> 156:95d6b41a828b 2764
<> 144:ef7eb2e8f9f7 2765 /* Disable Rx/Tx DMA Request */
<> 144:ef7eb2e8f9f7 2766 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2767
<> 156:95d6b41a828b 2768 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2769 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2770 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2771
<> 156:95d6b41a828b 2772 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2773 /* Check if CRC error occurred */
<> 156:95d6b41a828b 2774 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 2775 {
<> 156:95d6b41a828b 2776 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2777 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2778 }
<> 156:95d6b41a828b 2779 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 2780
<> 156:95d6b41a828b 2781 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2782 {
<> 144:ef7eb2e8f9f7 2783 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2784 return;
<> 144:ef7eb2e8f9f7 2785 }
<> 144:ef7eb2e8f9f7 2786 }
<> 144:ef7eb2e8f9f7 2787 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2788 }
<> 144:ef7eb2e8f9f7 2789
<> 144:ef7eb2e8f9f7 2790 /**
<> 144:ef7eb2e8f9f7 2791 * @brief DMA SPI half transmit process complete callback.
<> 156:95d6b41a828b 2792 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2793 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2794 * @retval None
<> 144:ef7eb2e8f9f7 2795 */
<> 144:ef7eb2e8f9f7 2796 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2797 {
<> 156:95d6b41a828b 2798 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2799
<> 144:ef7eb2e8f9f7 2800 HAL_SPI_TxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2801 }
<> 144:ef7eb2e8f9f7 2802
<> 144:ef7eb2e8f9f7 2803 /**
<> 144:ef7eb2e8f9f7 2804 * @brief DMA SPI half receive process complete callback
<> 144:ef7eb2e8f9f7 2805 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2806 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2807 * @retval None
<> 144:ef7eb2e8f9f7 2808 */
<> 144:ef7eb2e8f9f7 2809 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2810 {
<> 156:95d6b41a828b 2811 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2812
<> 144:ef7eb2e8f9f7 2813 HAL_SPI_RxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2814 }
<> 144:ef7eb2e8f9f7 2815
<> 144:ef7eb2e8f9f7 2816 /**
<> 144:ef7eb2e8f9f7 2817 * @brief DMA SPI half transmit receive process complete callback.
<> 156:95d6b41a828b 2818 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2819 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2820 * @retval None
<> 144:ef7eb2e8f9f7 2821 */
<> 144:ef7eb2e8f9f7 2822 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2823 {
<> 156:95d6b41a828b 2824 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2825
<> 144:ef7eb2e8f9f7 2826 HAL_SPI_TxRxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2827 }
<> 144:ef7eb2e8f9f7 2828
<> 144:ef7eb2e8f9f7 2829 /**
<> 144:ef7eb2e8f9f7 2830 * @brief DMA SPI communication error callback.
<> 156:95d6b41a828b 2831 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2832 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2833 * @retval None
<> 144:ef7eb2e8f9f7 2834 */
<> 144:ef7eb2e8f9f7 2835 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2836 {
<> 156:95d6b41a828b 2837 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2838
<> 144:ef7eb2e8f9f7 2839 /* Stop the disable DMA transfer on SPI side */
<> 144:ef7eb2e8f9f7 2840 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2841
<> 156:95d6b41a828b 2842 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2843 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2844 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2845 }
<> 144:ef7eb2e8f9f7 2846
<> 144:ef7eb2e8f9f7 2847 /**
<> 156:95d6b41a828b 2848 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
<> 156:95d6b41a828b 2849 * (To be called at end of DMA Abort procedure following error occurrence).
<> 156:95d6b41a828b 2850 * @param hdma DMA handle.
<> 156:95d6b41a828b 2851 * @retval None
<> 156:95d6b41a828b 2852 */
<> 156:95d6b41a828b 2853 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2854 {
<> 156:95d6b41a828b 2855 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2856 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 2857 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2858
<> 156:95d6b41a828b 2859 HAL_SPI_ErrorCallback(hspi);
<> 156:95d6b41a828b 2860 }
<> 156:95d6b41a828b 2861
<> 156:95d6b41a828b 2862 /**
<> 156:95d6b41a828b 2863 * @brief DMA SPI Tx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2864 * (To be called at end of DMA Tx Abort procedure following user abort request).
<> 156:95d6b41a828b 2865 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2866 * Abort still ongoing for Rx DMA Handle.
<> 156:95d6b41a828b 2867 * @param hdma DMA handle.
<> 156:95d6b41a828b 2868 * @retval None
<> 156:95d6b41a828b 2869 */
<> 156:95d6b41a828b 2870 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2871 {
<> 156:95d6b41a828b 2872 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2873
<> 156:95d6b41a828b 2874 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2875
<> 156:95d6b41a828b 2876 /* Disable Tx DMA Request */
<> 156:95d6b41a828b 2877 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 156:95d6b41a828b 2878
<> 156:95d6b41a828b 2879 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2880 {
<> 156:95d6b41a828b 2881 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2882 }
<> 156:95d6b41a828b 2883
<> 156:95d6b41a828b 2884 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 2885 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 2886
<> 156:95d6b41a828b 2887 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 2888 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2889 {
<> 156:95d6b41a828b 2890 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2891 }
<> 156:95d6b41a828b 2892
<> 156:95d6b41a828b 2893 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2894 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2895 {
<> 156:95d6b41a828b 2896 if (hspi->hdmarx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2897 {
<> 156:95d6b41a828b 2898 return;
<> 156:95d6b41a828b 2899 }
<> 156:95d6b41a828b 2900 }
<> 156:95d6b41a828b 2901
<> 156:95d6b41a828b 2902 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2903 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 2904 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2905
<> 156:95d6b41a828b 2906 /* Check no error during Abort procedure */
<> 156:95d6b41a828b 2907 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
<> 156:95d6b41a828b 2908 {
<> 156:95d6b41a828b 2909 /* Reset errorCode */
<> 156:95d6b41a828b 2910 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 2911 }
<> 156:95d6b41a828b 2912
<> 156:95d6b41a828b 2913 /* Clear the Error flags in the SR register */
<> 156:95d6b41a828b 2914 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 156:95d6b41a828b 2915 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 156:95d6b41a828b 2916
<> 156:95d6b41a828b 2917 /* Restore hspi->State to Ready */
<> 156:95d6b41a828b 2918 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 2919
<> 156:95d6b41a828b 2920 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2921 HAL_SPI_AbortCpltCallback(hspi);
<> 156:95d6b41a828b 2922 }
<> 156:95d6b41a828b 2923
<> 156:95d6b41a828b 2924 /**
<> 156:95d6b41a828b 2925 * @brief DMA SPI Rx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2926 * (To be called at end of DMA Rx Abort procedure following user abort request).
<> 156:95d6b41a828b 2927 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2928 * Abort still ongoing for Tx DMA Handle.
<> 156:95d6b41a828b 2929 * @param hdma DMA handle.
<> 156:95d6b41a828b 2930 * @retval None
<> 156:95d6b41a828b 2931 */
<> 156:95d6b41a828b 2932 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2933 {
<> 156:95d6b41a828b 2934 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2935
<> 156:95d6b41a828b 2936 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 2937 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 2938
<> 156:95d6b41a828b 2939 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2940
<> 156:95d6b41a828b 2941 /* Disable Rx DMA Request */
<> 156:95d6b41a828b 2942 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 156:95d6b41a828b 2943
<> 156:95d6b41a828b 2944 /* Control the BSY flag */
<> 156:95d6b41a828b 2945 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2946 {
<> 156:95d6b41a828b 2947 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2948 }
<> 156:95d6b41a828b 2949
<> 156:95d6b41a828b 2950 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 2951 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2952 {
<> 156:95d6b41a828b 2953 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2954 }
<> 156:95d6b41a828b 2955
<> 156:95d6b41a828b 2956 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2957 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2958 {
<> 156:95d6b41a828b 2959 if (hspi->hdmatx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2960 {
<> 156:95d6b41a828b 2961 return;
<> 156:95d6b41a828b 2962 }
<> 156:95d6b41a828b 2963 }
<> 156:95d6b41a828b 2964
<> 156:95d6b41a828b 2965 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2966 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 2967 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2968
<> 156:95d6b41a828b 2969 /* Check no error during Abort procedure */
<> 156:95d6b41a828b 2970 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
<> 156:95d6b41a828b 2971 {
<> 156:95d6b41a828b 2972 /* Reset errorCode */
<> 156:95d6b41a828b 2973 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 2974 }
<> 156:95d6b41a828b 2975
<> 156:95d6b41a828b 2976 /* Clear the Error flags in the SR register */
<> 156:95d6b41a828b 2977 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 156:95d6b41a828b 2978 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 156:95d6b41a828b 2979
<> 156:95d6b41a828b 2980 /* Restore hspi->State to Ready */
<> 156:95d6b41a828b 2981 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 2982
<> 156:95d6b41a828b 2983 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2984 HAL_SPI_AbortCpltCallback(hspi);
<> 156:95d6b41a828b 2985 }
<> 156:95d6b41a828b 2986
<> 156:95d6b41a828b 2987 /**
<> 144:ef7eb2e8f9f7 2988 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2989 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2990 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2991 * @retval None
<> 144:ef7eb2e8f9f7 2992 */
<> 144:ef7eb2e8f9f7 2993 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2994 {
<> 144:ef7eb2e8f9f7 2995 /* Receive data in packing mode */
<> 156:95d6b41a828b 2996 if (hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 2997 {
<> 156:95d6b41a828b 2998 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2999 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 156:95d6b41a828b 3000 hspi->RxXferCount -= 2U;
<> 156:95d6b41a828b 3001 if (hspi->RxXferCount == 1U)
<> 144:ef7eb2e8f9f7 3002 {
<> 144:ef7eb2e8f9f7 3003 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 3004 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 3005 }
<> 144:ef7eb2e8f9f7 3006 }
<> 144:ef7eb2e8f9f7 3007 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 3008 else
<> 144:ef7eb2e8f9f7 3009 {
<> 144:ef7eb2e8f9f7 3010 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3011 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3012 }
<> 144:ef7eb2e8f9f7 3013
<> 144:ef7eb2e8f9f7 3014 /* check end of the reception */
<> 156:95d6b41a828b 3015 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3016 {
<> 156:95d6b41a828b 3017 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3018 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3019 {
<> 144:ef7eb2e8f9f7 3020 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 3021 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 3022 return;
<> 144:ef7eb2e8f9f7 3023 }
<> 156:95d6b41a828b 3024 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3025
<> 156:95d6b41a828b 3026 /* Disable RXNE and ERR interrupt */
<> 156:95d6b41a828b 3027 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 156:95d6b41a828b 3028
<> 156:95d6b41a828b 3029 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3030 {
<> 144:ef7eb2e8f9f7 3031 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3032 }
<> 144:ef7eb2e8f9f7 3033 }
<> 144:ef7eb2e8f9f7 3034 }
<> 144:ef7eb2e8f9f7 3035
<> 156:95d6b41a828b 3036 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3037 /**
<> 144:ef7eb2e8f9f7 3038 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3039 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3040 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3041 * @retval None
<> 144:ef7eb2e8f9f7 3042 */
<> 144:ef7eb2e8f9f7 3043 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3044 {
<> 156:95d6b41a828b 3045 __IO uint8_t tmpreg = 0U;
<> 156:95d6b41a828b 3046
<> 156:95d6b41a828b 3047 /* Read data register to flush CRC */
<> 156:95d6b41a828b 3048 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 156:95d6b41a828b 3049
<> 144:ef7eb2e8f9f7 3050 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3051 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3052
<> 144:ef7eb2e8f9f7 3053 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 3054
<> 144:ef7eb2e8f9f7 3055 /* check end of the reception */
<> 156:95d6b41a828b 3056 if (hspi->CRCSize == 0U)
<> 144:ef7eb2e8f9f7 3057 {
<> 156:95d6b41a828b 3058 /* Disable RXNE and ERR interrupt */
<> 156:95d6b41a828b 3059 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 156:95d6b41a828b 3060
<> 156:95d6b41a828b 3061 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3062 {
<> 144:ef7eb2e8f9f7 3063 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3064 }
<> 144:ef7eb2e8f9f7 3065 }
<> 144:ef7eb2e8f9f7 3066 }
<> 156:95d6b41a828b 3067 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3068
<> 144:ef7eb2e8f9f7 3069 /**
<> 144:ef7eb2e8f9f7 3070 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3071 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3072 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3073 * @retval None
<> 144:ef7eb2e8f9f7 3074 */
<> 144:ef7eb2e8f9f7 3075 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3076 {
<> 144:ef7eb2e8f9f7 3077 /* Transmit data in packing Bit mode */
<> 156:95d6b41a828b 3078 if (hspi->TxXferCount >= 2U)
<> 144:ef7eb2e8f9f7 3079 {
<> 144:ef7eb2e8f9f7 3080 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3081 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 156:95d6b41a828b 3082 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 3083 }
<> 144:ef7eb2e8f9f7 3084 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 3085 else
<> 144:ef7eb2e8f9f7 3086 {
<> 144:ef7eb2e8f9f7 3087 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 3088 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3089 }
<> 144:ef7eb2e8f9f7 3090
<> 144:ef7eb2e8f9f7 3091 /* check the end of the transmission */
<> 156:95d6b41a828b 3092 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3093 {
<> 156:95d6b41a828b 3094 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3095 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3096 {
<> 156:95d6b41a828b 3097 /* Set CRC Next Bit to send CRC */
<> 144:ef7eb2e8f9f7 3098 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 156:95d6b41a828b 3099 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3100 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3101 return;
<> 144:ef7eb2e8f9f7 3102 }
<> 156:95d6b41a828b 3103 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3104
<> 144:ef7eb2e8f9f7 3105 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3106 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3107
<> 156:95d6b41a828b 3108 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3109 {
<> 144:ef7eb2e8f9f7 3110 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3111 }
<> 144:ef7eb2e8f9f7 3112 }
<> 144:ef7eb2e8f9f7 3113 }
<> 144:ef7eb2e8f9f7 3114
<> 144:ef7eb2e8f9f7 3115 /**
<> 144:ef7eb2e8f9f7 3116 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3117 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3118 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3119 * @retval None
<> 144:ef7eb2e8f9f7 3120 */
<> 144:ef7eb2e8f9f7 3121 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3122 {
<> 144:ef7eb2e8f9f7 3123 /* Receive data in 16 Bit mode */
<> 156:95d6b41a828b 3124 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3125 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3126 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3127
<> 156:95d6b41a828b 3128 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3129 {
<> 156:95d6b41a828b 3130 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3131 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3132 {
<> 144:ef7eb2e8f9f7 3133 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 3134 return;
<> 144:ef7eb2e8f9f7 3135 }
<> 156:95d6b41a828b 3136 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3137
<> 144:ef7eb2e8f9f7 3138 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 3139 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 3140
<> 156:95d6b41a828b 3141 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3142 {
<> 144:ef7eb2e8f9f7 3143 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3144 }
<> 144:ef7eb2e8f9f7 3145 }
<> 144:ef7eb2e8f9f7 3146 }
<> 144:ef7eb2e8f9f7 3147
<> 156:95d6b41a828b 3148 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3149 /**
<> 144:ef7eb2e8f9f7 3150 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3151 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3152 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3153 * @retval None
<> 144:ef7eb2e8f9f7 3154 */
<> 144:ef7eb2e8f9f7 3155 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3156 {
<> 144:ef7eb2e8f9f7 3157 /* Receive data in 16 Bit mode */
<> 156:95d6b41a828b 3158 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 3159
<> 156:95d6b41a828b 3160 /* Read data register to flush CRC */
<> 156:95d6b41a828b 3161 tmpreg = hspi->Instance->DR;
<> 156:95d6b41a828b 3162
<> 144:ef7eb2e8f9f7 3163 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3164 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3165
<> 144:ef7eb2e8f9f7 3166 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 3167 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 3168
<> 144:ef7eb2e8f9f7 3169 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3170 }
<> 156:95d6b41a828b 3171 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3172
<> 144:ef7eb2e8f9f7 3173 /**
<> 144:ef7eb2e8f9f7 3174 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3175 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3176 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3177 * @retval None
<> 144:ef7eb2e8f9f7 3178 */
<> 144:ef7eb2e8f9f7 3179 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3180 {
<> 144:ef7eb2e8f9f7 3181 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 3182 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3183 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3184 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3185
<> 144:ef7eb2e8f9f7 3186 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3187 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3188 {
<> 156:95d6b41a828b 3189 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3190 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3191 {
<> 156:95d6b41a828b 3192 /* Set CRC Next Bit to send CRC */
<> 144:ef7eb2e8f9f7 3193 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 156:95d6b41a828b 3194 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3195 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3196 return;
<> 144:ef7eb2e8f9f7 3197 }
<> 156:95d6b41a828b 3198 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3199
<> 144:ef7eb2e8f9f7 3200 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3201 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3202
<> 156:95d6b41a828b 3203 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3204 {
<> 144:ef7eb2e8f9f7 3205 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3206 }
<> 144:ef7eb2e8f9f7 3207 }
<> 144:ef7eb2e8f9f7 3208 }
<> 144:ef7eb2e8f9f7 3209
<> 156:95d6b41a828b 3210 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3211 /**
<> 144:ef7eb2e8f9f7 3212 * @brief Manage the CRC 8-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3213 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3214 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3215 * @retval None
<> 144:ef7eb2e8f9f7 3216 */
<> 144:ef7eb2e8f9f7 3217 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3218 {
<> 156:95d6b41a828b 3219 __IO uint8_t tmpreg = 0U;
<> 156:95d6b41a828b 3220
<> 156:95d6b41a828b 3221 /* Read data register to flush CRC */
<> 156:95d6b41a828b 3222 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 156:95d6b41a828b 3223
<> 144:ef7eb2e8f9f7 3224 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3225 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3226
<> 144:ef7eb2e8f9f7 3227 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 3228
<> 156:95d6b41a828b 3229 if (hspi->CRCSize == 0U)
<> 144:ef7eb2e8f9f7 3230 {
<> 144:ef7eb2e8f9f7 3231 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3232 }
<> 144:ef7eb2e8f9f7 3233 }
<> 156:95d6b41a828b 3234 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3235
<> 144:ef7eb2e8f9f7 3236 /**
<> 144:ef7eb2e8f9f7 3237 * @brief Manage the receive 8-bit in Interrupt context.
<> 144:ef7eb2e8f9f7 3238 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3239 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3240 * @retval None
<> 144:ef7eb2e8f9f7 3241 */
<> 144:ef7eb2e8f9f7 3242 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3243 {
<> 144:ef7eb2e8f9f7 3244 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3245 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3246
<> 156:95d6b41a828b 3247 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3248 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3249 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 3250 {
<> 156:95d6b41a828b 3251 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3252 }
<> 156:95d6b41a828b 3253 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3254
<> 156:95d6b41a828b 3255 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3256 {
<> 156:95d6b41a828b 3257 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3258 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3259 {
<> 144:ef7eb2e8f9f7 3260 hspi->RxISR = SPI_RxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 3261 return;
<> 144:ef7eb2e8f9f7 3262 }
<> 156:95d6b41a828b 3263 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3264 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3265 }
<> 144:ef7eb2e8f9f7 3266 }
<> 144:ef7eb2e8f9f7 3267
<> 156:95d6b41a828b 3268 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3269 /**
<> 144:ef7eb2e8f9f7 3270 * @brief Manage the CRC 16-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3271 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3272 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3273 * @retval None
<> 144:ef7eb2e8f9f7 3274 */
<> 144:ef7eb2e8f9f7 3275 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3276 {
<> 156:95d6b41a828b 3277 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 3278
<> 156:95d6b41a828b 3279 /* Read data register to flush CRC */
<> 144:ef7eb2e8f9f7 3280 tmpreg = hspi->Instance->DR;
<> 156:95d6b41a828b 3281
<> 144:ef7eb2e8f9f7 3282 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3283 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3284
<> 144:ef7eb2e8f9f7 3285 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3286 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3287
<> 144:ef7eb2e8f9f7 3288 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3289 }
<> 156:95d6b41a828b 3290 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3291
<> 144:ef7eb2e8f9f7 3292 /**
<> 144:ef7eb2e8f9f7 3293 * @brief Manage the 16-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3294 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3295 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3296 * @retval None
<> 144:ef7eb2e8f9f7 3297 */
<> 144:ef7eb2e8f9f7 3298 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3299 {
<> 144:ef7eb2e8f9f7 3300 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3301 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3302 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3303
<> 156:95d6b41a828b 3304 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3305 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3306 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 3307 {
<> 156:95d6b41a828b 3308 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3309 }
<> 156:95d6b41a828b 3310 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3311
<> 156:95d6b41a828b 3312 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3313 {
<> 156:95d6b41a828b 3314 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3315 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3316 {
<> 144:ef7eb2e8f9f7 3317 hspi->RxISR = SPI_RxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 3318 return;
<> 144:ef7eb2e8f9f7 3319 }
<> 156:95d6b41a828b 3320 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3321 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3322 }
<> 144:ef7eb2e8f9f7 3323 }
<> 144:ef7eb2e8f9f7 3324
<> 144:ef7eb2e8f9f7 3325 /**
<> 144:ef7eb2e8f9f7 3326 * @brief Handle the data 8-bit transmit in Interrupt mode.
<> 144:ef7eb2e8f9f7 3327 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3328 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3329 * @retval None
<> 144:ef7eb2e8f9f7 3330 */
<> 144:ef7eb2e8f9f7 3331 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3332 {
<> 144:ef7eb2e8f9f7 3333 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 3334 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3335
<> 156:95d6b41a828b 3336 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3337 {
<> 156:95d6b41a828b 3338 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3339 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3340 {
<> 144:ef7eb2e8f9f7 3341 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3342 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3343 }
<> 156:95d6b41a828b 3344 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3345 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3346 }
<> 144:ef7eb2e8f9f7 3347 }
<> 144:ef7eb2e8f9f7 3348
<> 144:ef7eb2e8f9f7 3349 /**
<> 144:ef7eb2e8f9f7 3350 * @brief Handle the data 16-bit transmit in Interrupt mode.
<> 144:ef7eb2e8f9f7 3351 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3352 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3353 * @retval None
<> 144:ef7eb2e8f9f7 3354 */
<> 144:ef7eb2e8f9f7 3355 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3356 {
<> 144:ef7eb2e8f9f7 3357 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 3358 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3359 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3360 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3361
<> 156:95d6b41a828b 3362 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3363 {
<> 156:95d6b41a828b 3364 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3365 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3366 {
<> 144:ef7eb2e8f9f7 3367 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3368 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3369 }
<> 156:95d6b41a828b 3370 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3371 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3372 }
<> 144:ef7eb2e8f9f7 3373 }
<> 144:ef7eb2e8f9f7 3374
<> 144:ef7eb2e8f9f7 3375 /**
<> 144:ef7eb2e8f9f7 3376 * @brief Handle SPI Communication Timeout.
<> 144:ef7eb2e8f9f7 3377 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 156:95d6b41a828b 3378 * the configuration information for SPI module.
<> 156:95d6b41a828b 3379 * @param Flag: SPI flag to check
<> 156:95d6b41a828b 3380 * @param State: flag state to check
<> 156:95d6b41a828b 3381 * @param Timeout: Timeout duration
<> 156:95d6b41a828b 3382 * @param Tickstart: tick start value
<> 144:ef7eb2e8f9f7 3383 * @retval HAL status
<> 144:ef7eb2e8f9f7 3384 */
<> 156:95d6b41a828b 3385 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
<> 156:95d6b41a828b 3386 uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3387 {
<> 156:95d6b41a828b 3388 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
<> 144:ef7eb2e8f9f7 3389 {
<> 156:95d6b41a828b 3390 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 3391 {
<> 156:95d6b41a828b 3392 if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 3393 {
<> 144:ef7eb2e8f9f7 3394 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 3395 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 3396 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 3397
<> 144:ef7eb2e8f9f7 3398 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 3399 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3400
<> 156:95d6b41a828b 3401 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 156:95d6b41a828b 3402 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3403 {
<> 144:ef7eb2e8f9f7 3404 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3405 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3406 }
<> 144:ef7eb2e8f9f7 3407
<> 144:ef7eb2e8f9f7 3408 /* Reset CRC Calculation */
<> 156:95d6b41a828b 3409 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3410 {
<> 144:ef7eb2e8f9f7 3411 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 3412 }
<> 144:ef7eb2e8f9f7 3413
<> 156:95d6b41a828b 3414 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3415
<> 144:ef7eb2e8f9f7 3416 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3417 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 3418
<> 144:ef7eb2e8f9f7 3419 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3420 }
<> 144:ef7eb2e8f9f7 3421 }
<> 144:ef7eb2e8f9f7 3422 }
<> 144:ef7eb2e8f9f7 3423
<> 144:ef7eb2e8f9f7 3424 return HAL_OK;
<> 144:ef7eb2e8f9f7 3425 }
<> 144:ef7eb2e8f9f7 3426
<> 144:ef7eb2e8f9f7 3427 /**
<> 144:ef7eb2e8f9f7 3428 * @brief Handle SPI FIFO Communication Timeout.
<> 144:ef7eb2e8f9f7 3429 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 156:95d6b41a828b 3430 * the configuration information for SPI module.
<> 156:95d6b41a828b 3431 * @param Fifo: Fifo to check
<> 156:95d6b41a828b 3432 * @param State: Fifo state to check
<> 156:95d6b41a828b 3433 * @param Timeout: Timeout duration
<> 156:95d6b41a828b 3434 * @param Tickstart: tick start value
<> 144:ef7eb2e8f9f7 3435 * @retval HAL status
<> 144:ef7eb2e8f9f7 3436 */
<> 156:95d6b41a828b 3437 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
<> 156:95d6b41a828b 3438 uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3439 {
<> 144:ef7eb2e8f9f7 3440 __IO uint8_t tmpreg;
<> 156:95d6b41a828b 3441
<> 156:95d6b41a828b 3442 while ((hspi->Instance->SR & Fifo) != State)
<> 144:ef7eb2e8f9f7 3443 {
<> 156:95d6b41a828b 3444 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
<> 144:ef7eb2e8f9f7 3445 {
<> 156:95d6b41a828b 3446 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3447 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3448 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3449 }
<> 144:ef7eb2e8f9f7 3450
<> 156:95d6b41a828b 3451 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 3452 {
<> 156:95d6b41a828b 3453 if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 3454 {
<> 144:ef7eb2e8f9f7 3455 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 3456 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 3457 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 3458
<> 144:ef7eb2e8f9f7 3459 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 3460 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3461
<> 156:95d6b41a828b 3462 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 156:95d6b41a828b 3463 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3464 {
<> 144:ef7eb2e8f9f7 3465 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3466 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3467 }
<> 144:ef7eb2e8f9f7 3468
<> 144:ef7eb2e8f9f7 3469 /* Reset CRC Calculation */
<> 156:95d6b41a828b 3470 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3471 {
<> 144:ef7eb2e8f9f7 3472 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 3473 }
<> 144:ef7eb2e8f9f7 3474
<> 144:ef7eb2e8f9f7 3475 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3476
<> 144:ef7eb2e8f9f7 3477 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3478 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 3479
<> 144:ef7eb2e8f9f7 3480 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3481 }
<> 144:ef7eb2e8f9f7 3482 }
<> 144:ef7eb2e8f9f7 3483 }
<> 144:ef7eb2e8f9f7 3484
<> 144:ef7eb2e8f9f7 3485 return HAL_OK;
<> 144:ef7eb2e8f9f7 3486 }
<> 144:ef7eb2e8f9f7 3487
<> 144:ef7eb2e8f9f7 3488 /**
<> 144:ef7eb2e8f9f7 3489 * @brief Handle the check of the RX transaction complete.
<> 144:ef7eb2e8f9f7 3490 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3491 * the configuration information for SPI module.
<> 156:95d6b41a828b 3492 * @param Timeout: Timeout duration
<> 156:95d6b41a828b 3493 * @param Tickstart: tick start value
<> 156:95d6b41a828b 3494 * @retval HAL status
<> 144:ef7eb2e8f9f7 3495 */
<> 156:95d6b41a828b 3496 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3497 {
<> 156:95d6b41a828b 3498 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 156:95d6b41a828b 3499 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3500 {
<> 144:ef7eb2e8f9f7 3501 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3502 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3503 }
<> 156:95d6b41a828b 3504
<> 144:ef7eb2e8f9f7 3505 /* Control the BSY flag */
<> 156:95d6b41a828b 3506 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3507 {
<> 156:95d6b41a828b 3508 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3509 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3510 }
<> 144:ef7eb2e8f9f7 3511
<> 156:95d6b41a828b 3512 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 156:95d6b41a828b 3513 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3514 {
<> 144:ef7eb2e8f9f7 3515 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 3516 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3517 {
<> 156:95d6b41a828b 3518 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3519 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3520 }
<> 144:ef7eb2e8f9f7 3521 }
<> 144:ef7eb2e8f9f7 3522 return HAL_OK;
<> 144:ef7eb2e8f9f7 3523 }
<> 144:ef7eb2e8f9f7 3524
<> 144:ef7eb2e8f9f7 3525 /**
<> 156:95d6b41a828b 3526 * @brief Handle the check of the RXTX or TX transaction complete.
<> 156:95d6b41a828b 3527 * @param hspi: SPI handle
<> 156:95d6b41a828b 3528 * @param Timeout: Timeout duration
<> 156:95d6b41a828b 3529 * @param Tickstart: tick start value
<> 156:95d6b41a828b 3530 * @retval HAL status
<> 144:ef7eb2e8f9f7 3531 */
<> 156:95d6b41a828b 3532 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3533 {
<> 144:ef7eb2e8f9f7 3534 /* Control if the TX fifo is empty */
<> 156:95d6b41a828b 3535 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3536 {
<> 156:95d6b41a828b 3537 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3538 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3539 }
<> 144:ef7eb2e8f9f7 3540 /* Control the BSY flag */
<> 156:95d6b41a828b 3541 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3542 {
<> 156:95d6b41a828b 3543 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3544 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3545 }
<> 144:ef7eb2e8f9f7 3546 return HAL_OK;
<> 144:ef7eb2e8f9f7 3547 }
<> 144:ef7eb2e8f9f7 3548
<> 144:ef7eb2e8f9f7 3549 /**
<> 144:ef7eb2e8f9f7 3550 * @brief Handle the end of the RXTX transaction.
<> 144:ef7eb2e8f9f7 3551 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3552 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3553 * @retval None
<> 144:ef7eb2e8f9f7 3554 */
<> 144:ef7eb2e8f9f7 3555 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3556 {
<> 156:95d6b41a828b 3557 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 3558
<> 156:95d6b41a828b 3559 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 3560 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 3561
<> 144:ef7eb2e8f9f7 3562 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 3563 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 3564
<> 144:ef7eb2e8f9f7 3565 /* Check the end of the transaction */
<> 156:95d6b41a828b 3566 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3567 {
<> 156:95d6b41a828b 3568 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3569 }
<> 144:ef7eb2e8f9f7 3570
<> 156:95d6b41a828b 3571 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3572 /* Check if CRC error occurred */
<> 156:95d6b41a828b 3573 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 3574 {
<> 144:ef7eb2e8f9f7 3575 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 3576 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 3577 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3578 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3579 }
<> 144:ef7eb2e8f9f7 3580 else
<> 144:ef7eb2e8f9f7 3581 {
<> 156:95d6b41a828b 3582 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3583 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3584 {
<> 156:95d6b41a828b 3585 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 3586 {
<> 144:ef7eb2e8f9f7 3587 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3588 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3589 }
<> 144:ef7eb2e8f9f7 3590 else
<> 144:ef7eb2e8f9f7 3591 {
<> 144:ef7eb2e8f9f7 3592 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3593 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3594 }
<> 144:ef7eb2e8f9f7 3595 }
<> 144:ef7eb2e8f9f7 3596 else
<> 144:ef7eb2e8f9f7 3597 {
<> 144:ef7eb2e8f9f7 3598 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3599 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3600 }
<> 156:95d6b41a828b 3601 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3602 }
<> 156:95d6b41a828b 3603 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3604 }
<> 144:ef7eb2e8f9f7 3605
<> 144:ef7eb2e8f9f7 3606 /**
<> 144:ef7eb2e8f9f7 3607 * @brief Handle the end of the RX transaction.
<> 144:ef7eb2e8f9f7 3608 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3609 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3610 * @retval None
<> 144:ef7eb2e8f9f7 3611 */
<> 144:ef7eb2e8f9f7 3612 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3613 {
<> 156:95d6b41a828b 3614 /* Disable RXNE and ERR interrupt */
<> 156:95d6b41a828b 3615 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 156:95d6b41a828b 3616
<> 156:95d6b41a828b 3617 /* Check the end of the transaction */
<> 156:95d6b41a828b 3618 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3619 {
<> 156:95d6b41a828b 3620 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 156:95d6b41a828b 3621 }
<> 156:95d6b41a828b 3622 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 3623
<> 156:95d6b41a828b 3624 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3625 /* Check if CRC error occurred */
<> 156:95d6b41a828b 3626 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 156:95d6b41a828b 3627 {
<> 156:95d6b41a828b 3628 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 156:95d6b41a828b 3629 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 156:95d6b41a828b 3630 HAL_SPI_ErrorCallback(hspi);
<> 156:95d6b41a828b 3631 }
<> 156:95d6b41a828b 3632 else
<> 156:95d6b41a828b 3633 {
<> 156:95d6b41a828b 3634 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3635 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3636 {
<> 156:95d6b41a828b 3637 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3638 }
<> 144:ef7eb2e8f9f7 3639 else
<> 144:ef7eb2e8f9f7 3640 {
<> 156:95d6b41a828b 3641 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3642 }
<> 156:95d6b41a828b 3643 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3644 }
<> 156:95d6b41a828b 3645 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3646 }
<> 144:ef7eb2e8f9f7 3647
<> 144:ef7eb2e8f9f7 3648 /**
<> 144:ef7eb2e8f9f7 3649 * @brief Handle the end of the TX transaction.
<> 144:ef7eb2e8f9f7 3650 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3651 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3652 * @retval None
<> 144:ef7eb2e8f9f7 3653 */
<> 144:ef7eb2e8f9f7 3654 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3655 {
<> 156:95d6b41a828b 3656 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 3657
<> 156:95d6b41a828b 3658 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 3659 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 3660
<> 144:ef7eb2e8f9f7 3661 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3662 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3663
<> 144:ef7eb2e8f9f7 3664 /* Check the end of the transaction */
<> 156:95d6b41a828b 3665 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3666 {
<> 156:95d6b41a828b 3667 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3668 }
<> 144:ef7eb2e8f9f7 3669
<> 144:ef7eb2e8f9f7 3670 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 156:95d6b41a828b 3671 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 3672 {
<> 144:ef7eb2e8f9f7 3673 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3674 }
<> 144:ef7eb2e8f9f7 3675
<> 144:ef7eb2e8f9f7 3676 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 3677 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3678 {
<> 144:ef7eb2e8f9f7 3679 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3680 }
<> 144:ef7eb2e8f9f7 3681 else
<> 144:ef7eb2e8f9f7 3682 {
<> 144:ef7eb2e8f9f7 3683 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3684 }
<> 144:ef7eb2e8f9f7 3685 }
<> 144:ef7eb2e8f9f7 3686
<> 144:ef7eb2e8f9f7 3687 /**
<> 156:95d6b41a828b 3688 * @brief Handle abort a Rx transaction.
<> 156:95d6b41a828b 3689 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 156:95d6b41a828b 3690 * the configuration information for SPI module.
<> 156:95d6b41a828b 3691 * @retval None
<> 156:95d6b41a828b 3692 */
<> 156:95d6b41a828b 3693 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 3694 {
<> 156:95d6b41a828b 3695 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 3696 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 3697
<> 156:95d6b41a828b 3698 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 156:95d6b41a828b 3699 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
<> 156:95d6b41a828b 3700
<> 156:95d6b41a828b 3701 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
<> 156:95d6b41a828b 3702 {
<> 156:95d6b41a828b 3703 }
<> 156:95d6b41a828b 3704
<> 156:95d6b41a828b 3705 /* Control the BSY flag */
<> 156:95d6b41a828b 3706 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3707 {
<> 156:95d6b41a828b 3708 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3709 }
<> 156:95d6b41a828b 3710
<> 156:95d6b41a828b 3711 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 3712 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3713 {
<> 156:95d6b41a828b 3714 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3715 }
<> 156:95d6b41a828b 3716
<> 156:95d6b41a828b 3717 hspi->State = HAL_SPI_STATE_ABORT;
<> 156:95d6b41a828b 3718 }
<> 156:95d6b41a828b 3719
<> 156:95d6b41a828b 3720 /**
<> 156:95d6b41a828b 3721 * @brief Handle abort a Tx or Rx/Tx transaction.
<> 156:95d6b41a828b 3722 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 156:95d6b41a828b 3723 * the configuration information for SPI module.
<> 156:95d6b41a828b 3724 * @retval None
<> 156:95d6b41a828b 3725 */
<> 156:95d6b41a828b 3726 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 3727 {
<> 156:95d6b41a828b 3728 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 156:95d6b41a828b 3729 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
<> 156:95d6b41a828b 3730
<> 156:95d6b41a828b 3731 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
<> 156:95d6b41a828b 3732 {
<> 156:95d6b41a828b 3733 }
<> 156:95d6b41a828b 3734
<> 156:95d6b41a828b 3735 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3736 {
<> 156:95d6b41a828b 3737 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3738 }
<> 156:95d6b41a828b 3739
<> 156:95d6b41a828b 3740 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 3741 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 3742
<> 156:95d6b41a828b 3743 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 3744 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3745 {
<> 156:95d6b41a828b 3746 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3747 }
<> 156:95d6b41a828b 3748
<> 156:95d6b41a828b 3749 hspi->State = HAL_SPI_STATE_ABORT;
<> 156:95d6b41a828b 3750 }
<> 156:95d6b41a828b 3751
<> 156:95d6b41a828b 3752 /**
<> 144:ef7eb2e8f9f7 3753 * @}
<> 144:ef7eb2e8f9f7 3754 */
<> 144:ef7eb2e8f9f7 3755
<> 144:ef7eb2e8f9f7 3756 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 3757
<> 144:ef7eb2e8f9f7 3758 /**
<> 144:ef7eb2e8f9f7 3759 * @}
<> 144:ef7eb2e8f9f7 3760 */
<> 144:ef7eb2e8f9f7 3761
<> 144:ef7eb2e8f9f7 3762 /**
<> 144:ef7eb2e8f9f7 3763 * @}
<> 144:ef7eb2e8f9f7 3764 */
<> 144:ef7eb2e8f9f7 3765
<> 144:ef7eb2e8f9f7 3766 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/