mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c@144:ef7eb2e8f9f7
Child:
156:95d6b41a828b
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_spi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief SPI HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The SPI HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SPI_HandleTypeDef hspi;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
<> 144:ef7eb2e8f9f7 26 (##) Enable the SPIx interface clock
<> 144:ef7eb2e8f9f7 27 (##) SPI pins configuration
<> 144:ef7eb2e8f9f7 28 (+++) Enable the clock for the SPI GPIOs
<> 144:ef7eb2e8f9f7 29 (+++) Configure these SPI pins as alternate function push-pull
<> 144:ef7eb2e8f9f7 30 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 31 (+++) Configure the SPIx interrupt priority
<> 144:ef7eb2e8f9f7 32 (+++) Enable the NVIC SPI IRQ handle
<> 144:ef7eb2e8f9f7 33 (##) DMA Configuration if you need to use DMA process
<> 144:ef7eb2e8f9f7 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
<> 144:ef7eb2e8f9f7 35 (+++) Enable the DMAx clock
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA handle parameters
<> 144:ef7eb2e8f9f7 37 (+++) Configure the DMA Tx or Rx channel
<> 144:ef7eb2e8f9f7 38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
<> 144:ef7eb2e8f9f7 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
<> 144:ef7eb2e8f9f7 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<> 144:ef7eb2e8f9f7 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 46 by calling the customized HAL_SPI_MspInit() API.
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 Circular mode restriction:
<> 144:ef7eb2e8f9f7 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<> 144:ef7eb2e8f9f7 50 (##) Master 2Lines RxOnly
<> 144:ef7eb2e8f9f7 51 (##) Master 1Line Rx
<> 144:ef7eb2e8f9f7 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
<> 144:ef7eb2e8f9f7 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<> 144:ef7eb2e8f9f7 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 @note
<> 144:ef7eb2e8f9f7 57 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
<> 144:ef7eb2e8f9f7 58 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
<> 144:ef7eb2e8f9f7 59 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 @endverbatim
<> 144:ef7eb2e8f9f7 62 ******************************************************************************
<> 144:ef7eb2e8f9f7 63 * @attention
<> 144:ef7eb2e8f9f7 64 *
<> 144:ef7eb2e8f9f7 65 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 68 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 69 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 70 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 71 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 72 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 73 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 74 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 75 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 76 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 79 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 80 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 81 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 82 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 83 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 84 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 85 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 86 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 ******************************************************************************
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /*
<> 144:ef7eb2e8f9f7 93 Additional Table:
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 Using the HAL it is not possible to reach all supported SPI frequency with the differents
<> 144:ef7eb2e8f9f7 96 the following table resume the max SPI frequency reached with data size 8bits/16bits,
<> 144:ef7eb2e8f9f7 97 according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
<> 144:ef7eb2e8f9f7 98 +-----------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 99 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line
<> 144:ef7eb2e8f9f7 100 | Process | Tranfert mode |---------------------|---------------------|------------------
<> 144:ef7eb2e8f9f7 101 | | | Master | Slave | Master | Slave | Master | Slave
<> 144:ef7eb2e8f9f7 102 |=========================================================================================
<> 144:ef7eb2e8f9f7 103 | T | Polling | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
<> 144:ef7eb2e8f9f7 104 | X |----------------|----------|----------|----------|----------|----------|-------
<> 144:ef7eb2e8f9f7 105 | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
<> 144:ef7eb2e8f9f7 106 | R |----------------|----------|----------|----------|----------|----------|-------
<> 144:ef7eb2e8f9f7 107 | X | DMA | fPCLK/32 | fPCLK/16 | NA | NA | NA | NA
<> 144:ef7eb2e8f9f7 108 |=========|================|==========|==========|==========|==========|==========|=======
<> 144:ef7eb2e8f9f7 109 | | Polling | fPCLK/32 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
<> 144:ef7eb2e8f9f7 110 | |----------------|----------|----------|----------|----------|----------|-------
<> 144:ef7eb2e8f9f7 111 | R | Interrupt | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
<> 144:ef7eb2e8f9f7 112 | X |----------------|----------|----------|----------|----------|----------|-------
<> 144:ef7eb2e8f9f7 113 | | DMA | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/4 | fPCLK/8 | fPCLK/
<> 144:ef7eb2e8f9f7 114 |=========|================|==========|==========|==========|==========|==========|=======
<> 144:ef7eb2e8f9f7 115 | | Polling | fPCLK/16 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
<> 144:ef7eb2e8f9f7 116 | |----------------|----------|----------|----------|----------|----------|-------
<> 144:ef7eb2e8f9f7 117 | T | Interrupt | fPCLK/32 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
<> 144:ef7eb2e8f9f7 118 | X |----------------|----------|----------|----------|----------|----------|-------
<> 144:ef7eb2e8f9f7 119 | | DMA | fPCLK/2 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/
<> 144:ef7eb2e8f9f7 120 +-----------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 121 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16
<> 144:ef7eb2e8f9f7 122 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 126 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 129 * @{
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** @defgroup SPI SPI
<> 144:ef7eb2e8f9f7 133 * @brief SPI HAL module driver
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /* Private defines -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /** @defgroup SPI_Private_Constants SPI Private Constants
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 #define SPI_DEFAULT_TIMEOUT 50
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @}
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 150 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 151 /** @defgroup SPI_Private_Functions SPI Private Functions
<> 144:ef7eb2e8f9f7 152 * @{
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 155 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 156 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 157 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 158 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 159 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 160 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 161 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 162 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 163 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 164 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 165 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 166 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 167 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 168 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 169 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 170 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 171 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 172 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 173 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 174 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 175 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 176 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 177 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 178 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 179 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @}
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /** @defgroup SPI_Exported_Functions SPI Exported Functions
<> 144:ef7eb2e8f9f7 187 * @{
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 191 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 192 *
<> 144:ef7eb2e8f9f7 193 @verbatim
<> 144:ef7eb2e8f9f7 194 ===============================================================================
<> 144:ef7eb2e8f9f7 195 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 196 ===============================================================================
<> 144:ef7eb2e8f9f7 197 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 198 de-initialize the SPIx peripheral:
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 (+) User must implement HAL_SPI_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 201 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 (+) Call the function HAL_SPI_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 204 the selected configuration:
<> 144:ef7eb2e8f9f7 205 (++) Mode
<> 144:ef7eb2e8f9f7 206 (++) Direction
<> 144:ef7eb2e8f9f7 207 (++) Data Size
<> 144:ef7eb2e8f9f7 208 (++) Clock Polarity and Phase
<> 144:ef7eb2e8f9f7 209 (++) NSS Management
<> 144:ef7eb2e8f9f7 210 (++) BaudRate Prescaler
<> 144:ef7eb2e8f9f7 211 (++) FirstBit
<> 144:ef7eb2e8f9f7 212 (++) TIMode
<> 144:ef7eb2e8f9f7 213 (++) CRC Calculation
<> 144:ef7eb2e8f9f7 214 (++) CRC Polynomial if CRC enabled
<> 144:ef7eb2e8f9f7 215 (++) CRC Length, used only with Data8 and Data16
<> 144:ef7eb2e8f9f7 216 (++) FIFO reception threshold
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 219 of the selected SPIx peripheral.
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 @endverbatim
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * @brief Initialize the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 227 * in the SPI_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 228 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 229 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 230 * @retval HAL status
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 uint32_t frxth;
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Check the SPI handle allocation */
<> 144:ef7eb2e8f9f7 237 if(hspi == NULL)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Check the parameters */
<> 144:ef7eb2e8f9f7 243 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 244 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 144:ef7eb2e8f9f7 245 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 246 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 247 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 144:ef7eb2e8f9f7 248 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 144:ef7eb2e8f9f7 249 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 250 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
<> 144:ef7eb2e8f9f7 251 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 252 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 144:ef7eb2e8f9f7 253 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<> 144:ef7eb2e8f9f7 254 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<> 144:ef7eb2e8f9f7 255 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<> 144:ef7eb2e8f9f7 256 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 if(hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 261 hspi->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 264 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Disable the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 270 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* Align by default the rs fifo threshold on the data size */
<> 144:ef7eb2e8f9f7 273 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 frxth = SPI_RXFIFO_THRESHOLD_HF;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277 else
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 frxth = SPI_RXFIFO_THRESHOLD_QF;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* CRC calculation is valid only for 16Bit and 8 Bit */
<> 144:ef7eb2e8f9f7 283 if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 /* CRC must be disabled */
<> 144:ef7eb2e8f9f7 286 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Align the CRC Length on the data size */
<> 144:ef7eb2e8f9f7 290 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 /* CRC Length aligned on the data size : value set by default */
<> 144:ef7eb2e8f9f7 293 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297 else
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 304 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
<> 144:ef7eb2e8f9f7 305 Communication speed, First bit, CRC calculation state, CRC Length */
<> 144:ef7eb2e8f9f7 306 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
<> 144:ef7eb2e8f9f7 307 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 144:ef7eb2e8f9f7 308 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 hspi->Instance->CR1|= SPI_CR1_CRCL;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Configure : NSS management */
<> 144:ef7eb2e8f9f7 316 /* Configure : Rx Fifo Threshold */
<> 144:ef7eb2e8f9f7 317 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
<> 144:ef7eb2e8f9f7 318 hspi->Init.DataSize ) | frxth;
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
<> 144:ef7eb2e8f9f7 321 /* Configure : CRC Polynomial */
<> 144:ef7eb2e8f9f7 322 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 144:ef7eb2e8f9f7 325 hspi->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SMOD);
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 328 hspi->State= HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 return HAL_OK;
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /**
<> 144:ef7eb2e8f9f7 334 * @brief DeInitialize the SPI peripheral.
<> 144:ef7eb2e8f9f7 335 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 336 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 337 * @retval HAL status
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 /* Check the SPI handle allocation */
<> 144:ef7eb2e8f9f7 342 if(hspi == NULL)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Check the parameters */
<> 144:ef7eb2e8f9f7 348 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 349 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Disable the SPI Peripheral Clock */
<> 144:ef7eb2e8f9f7 352 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 355 HAL_SPI_MspDeInit(hspi);
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 358 hspi->State = HAL_SPI_STATE_RESET;
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 return HAL_OK;
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @brief Initialize the SPI MSP.
<> 144:ef7eb2e8f9f7 367 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 368 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 369 * @retval None
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 374 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 377 the HAL_SPI_MspInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @brief DeInitialize the SPI MSP.
<> 144:ef7eb2e8f9f7 383 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 384 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 385 * @retval None
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 390 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 393 the HAL_SPI_MspDeInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /**
<> 144:ef7eb2e8f9f7 398 * @}
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 402 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 403 *
<> 144:ef7eb2e8f9f7 404 @verbatim
<> 144:ef7eb2e8f9f7 405 ==============================================================================
<> 144:ef7eb2e8f9f7 406 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 407 ===============================================================================
<> 144:ef7eb2e8f9f7 408 [..]
<> 144:ef7eb2e8f9f7 409 This subsection provides a set of functions allowing to manage the SPI
<> 144:ef7eb2e8f9f7 410 data transfers.
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 [..] The SPI supports master and slave mode :
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 415 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 416 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 417 after finishing transfer.
<> 144:ef7eb2e8f9f7 418 (++) No-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 419 or DMA, These APIs return the HAL status.
<> 144:ef7eb2e8f9f7 420 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 421 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 422 using DMA mode.
<> 144:ef7eb2e8f9f7 423 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 424 will be executed respectively at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 425 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<> 144:ef7eb2e8f9f7 428 exist for 1Line (simplex) and 2Lines (full duplex) modes.
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 @endverbatim
<> 144:ef7eb2e8f9f7 431 * @{
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /**
<> 144:ef7eb2e8f9f7 435 * @brief Transmit an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 436 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 437 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 438 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 439 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 440 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 441 * @retval HAL status
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 446 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Process Locked */
<> 144:ef7eb2e8f9f7 451 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 if(hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 456 goto error;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 462 goto error;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 466 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 467 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 468 hspi->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 469 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 470 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 471 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 144:ef7eb2e8f9f7 472 hspi->RxXferSize = 0;
<> 144:ef7eb2e8f9f7 473 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 476 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 477 {
<> 144:ef7eb2e8f9f7 478 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 482 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 488 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 491 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 492 }
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 495 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 498 while (hspi->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 501 if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 504 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 505 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507 else
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 /* Timeout management */
<> 144:ef7eb2e8f9f7 510 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 513 goto error;
<> 144:ef7eb2e8f9f7 514 }
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 519 else
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 while (hspi->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* Wait until TXE flag is set to send data */
<> 144:ef7eb2e8f9f7 524 if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 if(hspi->TxXferCount > 1)
<> 144:ef7eb2e8f9f7 527 {
<> 144:ef7eb2e8f9f7 528 /* write on the data register in packing mode */
<> 144:ef7eb2e8f9f7 529 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 530 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 531 hspi->TxXferCount -= 2;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533 else
<> 144:ef7eb2e8f9f7 534 {
<> 144:ef7eb2e8f9f7 535 *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 536 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539 else
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 /* Timeout management */
<> 144:ef7eb2e8f9f7 542 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 545 goto error;
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 552 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 558 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 144:ef7eb2e8f9f7 564 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 error:
<> 144:ef7eb2e8f9f7 575 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 576 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 577 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 578 return errorcode;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 583 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 584 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 585 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 586 * @param Size: amount of data to be received
<> 144:ef7eb2e8f9f7 587 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 588 * @retval HAL status
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 __IO uint16_t tmpreg;
<> 144:ef7eb2e8f9f7 593 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 594 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 /* the receive process is not supported in 2Lines direction master mode */
<> 144:ef7eb2e8f9f7 599 /* in this case we call the TransmitReceive process */
<> 144:ef7eb2e8f9f7 600 /* Process Locked */
<> 144:ef7eb2e8f9f7 601 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Process Locked */
<> 144:ef7eb2e8f9f7 605 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 if(hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 610 goto error;
<> 144:ef7eb2e8f9f7 611 }
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 616 goto error;
<> 144:ef7eb2e8f9f7 617 }
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 620 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 621 hspi->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 622 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 623 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 624 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 144:ef7eb2e8f9f7 625 hspi->TxXferSize = 0;
<> 144:ef7eb2e8f9f7 626 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 629 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 630 {
<> 144:ef7eb2e8f9f7 631 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 632 /* this is done to handle the CRCNEXT before the latest data */
<> 144:ef7eb2e8f9f7 633 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Set the Rx Fido threshold */
<> 144:ef7eb2e8f9f7 637 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 /* set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 640 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642 else
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 645 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Configure communication direction 1Line and enabled SPI if needed */
<> 144:ef7eb2e8f9f7 649 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 655 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 658 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 /* Transfer loop */
<> 144:ef7eb2e8f9f7 664 while(hspi->RxXferCount > 0)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 /* Check the RXNE flag */
<> 144:ef7eb2e8f9f7 667 if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 /* read the received data */
<> 144:ef7eb2e8f9f7 670 (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 671 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673 else
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 /* Timeout management */
<> 144:ef7eb2e8f9f7 676 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 677 {
<> 144:ef7eb2e8f9f7 678 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 679 goto error;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684 else
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 /* Transfer loop */
<> 144:ef7eb2e8f9f7 687 while(hspi->RxXferCount > 0)
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 /* Check the RXNE flag */
<> 144:ef7eb2e8f9f7 690 if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 693 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 694 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696 else
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 /* Timeout management */
<> 144:ef7eb2e8f9f7 699 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 702 goto error;
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Handle the CRC Transmission */
<> 144:ef7eb2e8f9f7 709 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 /* freeze the CRC before the latest data */
<> 144:ef7eb2e8f9f7 712 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Read the latest data */
<> 144:ef7eb2e8f9f7 715 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 /* the latest data has not been received */
<> 144:ef7eb2e8f9f7 718 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 719 goto error;
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* Receive last data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 723 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727 /* Receive last data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 728 else
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* Wait until TXE flag */
<> 144:ef7eb2e8f9f7 734 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 735 {
<> 144:ef7eb2e8f9f7 736 /* Flag Error*/
<> 144:ef7eb2e8f9f7 737 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 738 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 739 goto error;
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 743 {
<> 144:ef7eb2e8f9f7 744 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 745 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 746 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748 else
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 751 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 752 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 757 {
<> 144:ef7eb2e8f9f7 758 /* Error on the CRC reception */
<> 144:ef7eb2e8f9f7 759 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 760 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 761 goto error;
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 764 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 765 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 766 }
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 771 if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 777 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 780 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 784 {
<> 144:ef7eb2e8f9f7 785 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 error :
<> 144:ef7eb2e8f9f7 789 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 790 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 791 return errorcode;
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /**
<> 144:ef7eb2e8f9f7 795 * @brief Transmit and Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 796 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 797 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 798 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 799 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 800 * @param Size: amount of data to be sent and received
<> 144:ef7eb2e8f9f7 801 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 802 * @retval HAL status
<> 144:ef7eb2e8f9f7 803 */
<> 144:ef7eb2e8f9f7 804 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 __IO uint16_t tmpreg;
<> 144:ef7eb2e8f9f7 807 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 808 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Process Locked */
<> 144:ef7eb2e8f9f7 813 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 if(hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 818 goto error;
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 824 goto error;
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 828 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 829 hspi->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 830 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 831 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 832 hspi->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 833 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 834 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 837 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 840 }
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Set the Rx Fido threshold */
<> 144:ef7eb2e8f9f7 843 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 846 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848 else
<> 144:ef7eb2e8f9f7 849 {
<> 144:ef7eb2e8f9f7 850 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 851 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 855 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 858 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Transmit and Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 862 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 /* Check TXE flag */
<> 144:ef7eb2e8f9f7 867 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 868 {
<> 144:ef7eb2e8f9f7 869 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 870 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 871 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 874 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
<> 144:ef7eb2e8f9f7 877 if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 }
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /* Check RXNE flag */
<> 144:ef7eb2e8f9f7 886 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 889 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 890 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 895 goto error;
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897 }
<> 144:ef7eb2e8f9f7 898 }
<> 144:ef7eb2e8f9f7 899 /* Transmit and Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 900 else
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 /* check TXE flag */
<> 144:ef7eb2e8f9f7 905 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 if(hspi->TxXferCount > 1)
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 910 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 911 hspi->TxXferCount -= 2;
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913 else
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 916 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 920 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
<> 144:ef7eb2e8f9f7 923 if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929 }
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /* Wait until RXNE flag is reset */
<> 144:ef7eb2e8f9f7 932 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 933 {
<> 144:ef7eb2e8f9f7 934 if(hspi->RxXferCount > 1)
<> 144:ef7eb2e8f9f7 935 {
<> 144:ef7eb2e8f9f7 936 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 937 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 938 hspi->RxXferCount -= 2;
<> 144:ef7eb2e8f9f7 939 if(hspi->RxXferCount <= 1)
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 /* set fiforxthresold before to switch on 8 bit data size */
<> 144:ef7eb2e8f9f7 942 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944 }
<> 144:ef7eb2e8f9f7 945 else
<> 144:ef7eb2e8f9f7 946 {
<> 144:ef7eb2e8f9f7 947 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 948 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 949 }
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 952 {
<> 144:ef7eb2e8f9f7 953 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 954 goto error;
<> 144:ef7eb2e8f9f7 955 }
<> 144:ef7eb2e8f9f7 956 }
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Read CRC from DR to close CRC calculation process */
<> 144:ef7eb2e8f9f7 960 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 /* Wait until TXE flag */
<> 144:ef7eb2e8f9f7 963 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 964 {
<> 144:ef7eb2e8f9f7 965 /* Error on the CRC reception */
<> 144:ef7eb2e8f9f7 966 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 967 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 968 goto error;
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 974 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 975 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 976 }
<> 144:ef7eb2e8f9f7 977 else
<> 144:ef7eb2e8f9f7 978 {
<> 144:ef7eb2e8f9f7 979 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 980 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 981 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Error on the CRC reception */
<> 144:ef7eb2e8f9f7 988 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 989 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 990 goto error;
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 993 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 994 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 1000 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 1001 {
<> 144:ef7eb2e8f9f7 1002 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 1003 /* Clear CRC Flag */
<> 144:ef7eb2e8f9f7 1004 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1007 }
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 1010 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1016 {
<> 144:ef7eb2e8f9f7 1017 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 error :
<> 144:ef7eb2e8f9f7 1021 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1022 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1023 return errorcode;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /**
<> 144:ef7eb2e8f9f7 1027 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1028 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1029 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1030 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1031 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1032 * @retval HAL status
<> 144:ef7eb2e8f9f7 1033 */
<> 144:ef7eb2e8f9f7 1034 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1037 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /* Process Locked */
<> 144:ef7eb2e8f9f7 1040 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1045 goto error;
<> 144:ef7eb2e8f9f7 1046 }
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 if(hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1049 {
<> 144:ef7eb2e8f9f7 1050 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1051 goto error;
<> 144:ef7eb2e8f9f7 1052 }
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /* prepare the transfer */
<> 144:ef7eb2e8f9f7 1055 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1056 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1057 hspi->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1058 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1059 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1060 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 144:ef7eb2e8f9f7 1061 hspi->RxXferSize = 0;
<> 144:ef7eb2e8f9f7 1062 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1063 hspi->RxISR = NULL;
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 /* Set the function for IT treatment */
<> 144:ef7eb2e8f9f7 1066 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<> 144:ef7eb2e8f9f7 1067 {
<> 144:ef7eb2e8f9f7 1068 hspi->TxISR = SPI_TxISR_16BIT;
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070 else
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 hspi->TxISR = SPI_TxISR_8BIT;
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1076 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1082 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1085 }
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1088 __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1092 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1095 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1096 }
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 error :
<> 144:ef7eb2e8f9f7 1099 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1100 return errorcode;
<> 144:ef7eb2e8f9f7 1101 }
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /**
<> 144:ef7eb2e8f9f7 1104 * @brief Receive an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1105 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1106 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1107 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1108 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1109 * @retval HAL status
<> 144:ef7eb2e8f9f7 1110 */
<> 144:ef7eb2e8f9f7 1111 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1112 {
<> 144:ef7eb2e8f9f7 1113 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* Process Locked */
<> 144:ef7eb2e8f9f7 1116 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 if(hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1119 {
<> 144:ef7eb2e8f9f7 1120 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1121 goto error;
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1124 {
<> 144:ef7eb2e8f9f7 1125 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1126 goto error;
<> 144:ef7eb2e8f9f7 1127 }
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /* Configure communication */
<> 144:ef7eb2e8f9f7 1130 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1131 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1132 hspi->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1133 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1134 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1135 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 144:ef7eb2e8f9f7 1136 hspi->TxXferSize = 0;
<> 144:ef7eb2e8f9f7 1137 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1142 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1143 /* the receive process is not supported in 2Lines direction master mode */
<> 144:ef7eb2e8f9f7 1144 /* in this we call the TransmitReceive process */
<> 144:ef7eb2e8f9f7 1145 return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1149 {
<> 144:ef7eb2e8f9f7 1150 hspi->CRCSize = 1;
<> 144:ef7eb2e8f9f7 1151 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 1152 {
<> 144:ef7eb2e8f9f7 1153 hspi->CRCSize = 2;
<> 144:ef7eb2e8f9f7 1154 }
<> 144:ef7eb2e8f9f7 1155 }
<> 144:ef7eb2e8f9f7 1156 else
<> 144:ef7eb2e8f9f7 1157 {
<> 144:ef7eb2e8f9f7 1158 hspi->CRCSize = 0;
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 hspi->TxISR = NULL;
<> 144:ef7eb2e8f9f7 1162 /* check the data size to adapt Rx threshold and the set the function for IT treatment */
<> 144:ef7eb2e8f9f7 1163 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<> 144:ef7eb2e8f9f7 1164 {
<> 144:ef7eb2e8f9f7 1165 /* set fiforxthresold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1166 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1167 hspi->RxISR = SPI_RxISR_16BIT;
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169 else
<> 144:ef7eb2e8f9f7 1170 {
<> 144:ef7eb2e8f9f7 1171 /* set fiforxthresold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1172 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1173 hspi->RxISR = SPI_RxISR_8BIT;
<> 144:ef7eb2e8f9f7 1174 }
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1177 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1178 {
<> 144:ef7eb2e8f9f7 1179 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1180 }
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1183 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1184 {
<> 144:ef7eb2e8f9f7 1185 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1189 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1192 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1193 {
<> 144:ef7eb2e8f9f7 1194 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1195 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1196 }
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 error :
<> 144:ef7eb2e8f9f7 1199 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1200 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1201 return errorcode;
<> 144:ef7eb2e8f9f7 1202 }
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /**
<> 144:ef7eb2e8f9f7 1205 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1206 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1207 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1208 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1209 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1210 * @param Size: amount of data to be sent and received
<> 144:ef7eb2e8f9f7 1211 * @retval HAL status
<> 144:ef7eb2e8f9f7 1212 */
<> 144:ef7eb2e8f9f7 1213 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1214 {
<> 144:ef7eb2e8f9f7 1215 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1216 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* Process locked */
<> 144:ef7eb2e8f9f7 1219 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 if(!((hspi->State == HAL_SPI_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1222 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1223 {
<> 144:ef7eb2e8f9f7 1224 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1225 goto error;
<> 144:ef7eb2e8f9f7 1226 }
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1231 goto error;
<> 144:ef7eb2e8f9f7 1232 }
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 hspi->CRCSize = 0;
<> 144:ef7eb2e8f9f7 1235 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1236 {
<> 144:ef7eb2e8f9f7 1237 hspi->CRCSize = 1;
<> 144:ef7eb2e8f9f7 1238 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 1239 {
<> 144:ef7eb2e8f9f7 1240 hspi->CRCSize = 2;
<> 144:ef7eb2e8f9f7 1241 }
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1245 {
<> 144:ef7eb2e8f9f7 1246 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1247 }
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1250 hspi->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 1251 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1252 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1253 hspi->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 1254 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1255 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /* Set the function for IT treatment */
<> 144:ef7eb2e8f9f7 1258 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 hspi->RxISR = SPI_2linesRxISR_16BIT;
<> 144:ef7eb2e8f9f7 1261 hspi->TxISR = SPI_2linesTxISR_16BIT;
<> 144:ef7eb2e8f9f7 1262 }
<> 144:ef7eb2e8f9f7 1263 else
<> 144:ef7eb2e8f9f7 1264 {
<> 144:ef7eb2e8f9f7 1265 hspi->RxISR = SPI_2linesRxISR_8BIT;
<> 144:ef7eb2e8f9f7 1266 hspi->TxISR = SPI_2linesTxISR_8BIT;
<> 144:ef7eb2e8f9f7 1267 }
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1270 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1271 {
<> 144:ef7eb2e8f9f7 1272 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1273 }
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* check if packing mode is enabled and if there is more than 2 data to receive */
<> 144:ef7eb2e8f9f7 1276 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
<> 144:ef7eb2e8f9f7 1277 {
<> 144:ef7eb2e8f9f7 1278 /* set fiforxthresold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1279 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1280 }
<> 144:ef7eb2e8f9f7 1281 else
<> 144:ef7eb2e8f9f7 1282 {
<> 144:ef7eb2e8f9f7 1283 /* set fiforxthresold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1284 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1285 }
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Enable TXE, RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1288 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1291 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1292 {
<> 144:ef7eb2e8f9f7 1293 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1294 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1295 }
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 error :
<> 144:ef7eb2e8f9f7 1298 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1299 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1300 return errorcode;
<> 144:ef7eb2e8f9f7 1301 }
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 /**
<> 144:ef7eb2e8f9f7 1304 * @brief Transmit an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1305 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1306 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1307 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1308 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1309 * @retval HAL status
<> 144:ef7eb2e8f9f7 1310 */
<> 144:ef7eb2e8f9f7 1311 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1312 {
<> 144:ef7eb2e8f9f7 1313 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1314 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /* Process Locked */
<> 144:ef7eb2e8f9f7 1317 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 if(hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1322 goto error;
<> 144:ef7eb2e8f9f7 1323 }
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1326 {
<> 144:ef7eb2e8f9f7 1327 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1328 goto error;
<> 144:ef7eb2e8f9f7 1329 }
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1332 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1333 hspi->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1334 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1335 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1336 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 144:ef7eb2e8f9f7 1337 hspi->RxXferSize = 0;
<> 144:ef7eb2e8f9f7 1338 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1341 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1342 {
<> 144:ef7eb2e8f9f7 1343 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1344 }
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1347 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1348 {
<> 144:ef7eb2e8f9f7 1349 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1350 }
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /* Set the SPI TxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1353 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /* Set the SPI TxDMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1356 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1359 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1360
<> 144:ef7eb2e8f9f7 1361 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 144:ef7eb2e8f9f7 1362 /* packing mode is enabled only if the DMA setting is HALWORD */
<> 144:ef7eb2e8f9f7 1363 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1364 {
<> 144:ef7eb2e8f9f7 1365 /* Check the even/odd of the data size + crc if enabled */
<> 144:ef7eb2e8f9f7 1366 if((hspi->TxXferCount & 0x1) == 0)
<> 144:ef7eb2e8f9f7 1367 {
<> 144:ef7eb2e8f9f7 1368 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 144:ef7eb2e8f9f7 1369 hspi->TxXferCount = (hspi->TxXferCount >> 1);
<> 144:ef7eb2e8f9f7 1370 }
<> 144:ef7eb2e8f9f7 1371 else
<> 144:ef7eb2e8f9f7 1372 {
<> 144:ef7eb2e8f9f7 1373 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 144:ef7eb2e8f9f7 1374 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
<> 144:ef7eb2e8f9f7 1375 }
<> 144:ef7eb2e8f9f7 1376 }
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /* Enable the Tx DMA channel */
<> 144:ef7eb2e8f9f7 1379 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1382 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1383 {
<> 144:ef7eb2e8f9f7 1384 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1385 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1386 }
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1389 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 error :
<> 144:ef7eb2e8f9f7 1392 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1393 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1394 return errorcode;
<> 144:ef7eb2e8f9f7 1395 }
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 /**
<> 144:ef7eb2e8f9f7 1398 * @brief Receive an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1399 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1400 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1401 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1402 * @note When the CRC feature is enabled the pData Length must be Size + 1.
<> 144:ef7eb2e8f9f7 1403 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1404 * @retval HAL status
<> 144:ef7eb2e8f9f7 1405 */
<> 144:ef7eb2e8f9f7 1406 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1407 {
<> 144:ef7eb2e8f9f7 1408 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 /* Process Locked */
<> 144:ef7eb2e8f9f7 1411 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 if(hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1414 {
<> 144:ef7eb2e8f9f7 1415 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1416 goto error;
<> 144:ef7eb2e8f9f7 1417 }
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1420 {
<> 144:ef7eb2e8f9f7 1421 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1422 goto error;
<> 144:ef7eb2e8f9f7 1423 }
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1426 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1427 hspi->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1428 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1429 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1430 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 144:ef7eb2e8f9f7 1431 hspi->TxXferSize = 0;
<> 144:ef7eb2e8f9f7 1432 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 1435 {
<> 144:ef7eb2e8f9f7 1436 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1437 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1438 /* the receive process is not supported in 2Lines direction master mode */
<> 144:ef7eb2e8f9f7 1439 /* in this case we call the TransmitReceive process */
<> 144:ef7eb2e8f9f7 1440 return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
<> 144:ef7eb2e8f9f7 1441 }
<> 144:ef7eb2e8f9f7 1442
<> 144:ef7eb2e8f9f7 1443 /* Configure communication direction : 1Line */
<> 144:ef7eb2e8f9f7 1444 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1445 {
<> 144:ef7eb2e8f9f7 1446 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1447 }
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 1450 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1451 {
<> 144:ef7eb2e8f9f7 1452 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1453 }
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 /* packing mode management is enabled by the DMA settings */
<> 144:ef7eb2e8f9f7 1456 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1457 {
<> 144:ef7eb2e8f9f7 1458 /* Restriction the DMA data received is not allowed in this mode */
<> 144:ef7eb2e8f9f7 1459 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1460 goto error;
<> 144:ef7eb2e8f9f7 1461 }
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 144:ef7eb2e8f9f7 1464 if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1465 {
<> 144:ef7eb2e8f9f7 1466 /* set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1467 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1468 }
<> 144:ef7eb2e8f9f7 1469 else
<> 144:ef7eb2e8f9f7 1470 {
<> 144:ef7eb2e8f9f7 1471 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1472 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1473 }
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475 /* Set the SPI RxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1476 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 /* Set the SPI Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1479 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1482 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1485 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /* Enable the Rx DMA channel */
<> 144:ef7eb2e8f9f7 1488 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1489
<> 144:ef7eb2e8f9f7 1490 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1491 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1492 {
<> 144:ef7eb2e8f9f7 1493 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1494 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1495 }
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 error:
<> 144:ef7eb2e8f9f7 1498 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1499 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1500 return errorcode;
<> 144:ef7eb2e8f9f7 1501 }
<> 144:ef7eb2e8f9f7 1502
<> 144:ef7eb2e8f9f7 1503 /**
<> 144:ef7eb2e8f9f7 1504 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1505 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1506 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1507 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1508 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1509 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
<> 144:ef7eb2e8f9f7 1510 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1511 * @retval HAL status
<> 144:ef7eb2e8f9f7 1512 */
<> 144:ef7eb2e8f9f7 1513 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1514 {
<> 144:ef7eb2e8f9f7 1515 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1516 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1517
<> 144:ef7eb2e8f9f7 1518 /* Process locked */
<> 144:ef7eb2e8f9f7 1519 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1520
<> 144:ef7eb2e8f9f7 1521 if(!((hspi->State == HAL_SPI_STATE_READY) ||
<> 144:ef7eb2e8f9f7 1522 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1523 {
<> 144:ef7eb2e8f9f7 1524 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1525 goto error;
<> 144:ef7eb2e8f9f7 1526 }
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 1529 {
<> 144:ef7eb2e8f9f7 1530 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1531 goto error;
<> 144:ef7eb2e8f9f7 1532 }
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 /* check if the transmit Receive function is not called by a receive master */
<> 144:ef7eb2e8f9f7 1535 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1536 {
<> 144:ef7eb2e8f9f7 1537 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1538 }
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1541 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1542 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1543 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1544 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1545 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1546 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /* Reset CRC Calculation + increase the rxsize */
<> 144:ef7eb2e8f9f7 1549 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1550 {
<> 144:ef7eb2e8f9f7 1551 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1552 }
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 /* Reset the threshold bit */
<> 144:ef7eb2e8f9f7 1555 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
<> 144:ef7eb2e8f9f7 1556
<> 144:ef7eb2e8f9f7 1557 /* the packing mode management is enabled by the DMA settings according the spi data size */
<> 144:ef7eb2e8f9f7 1558 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1559 {
<> 144:ef7eb2e8f9f7 1560 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1561 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1562 }
<> 144:ef7eb2e8f9f7 1563 else
<> 144:ef7eb2e8f9f7 1564 {
<> 144:ef7eb2e8f9f7 1565 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1566 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1567
<> 144:ef7eb2e8f9f7 1568 if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1569 {
<> 144:ef7eb2e8f9f7 1570 if((hspi->TxXferSize & 0x1) == 0x0)
<> 144:ef7eb2e8f9f7 1571 {
<> 144:ef7eb2e8f9f7 1572 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 144:ef7eb2e8f9f7 1573 hspi->TxXferCount = hspi->TxXferCount >> 1;
<> 144:ef7eb2e8f9f7 1574 }
<> 144:ef7eb2e8f9f7 1575 else
<> 144:ef7eb2e8f9f7 1576 {
<> 144:ef7eb2e8f9f7 1577 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 144:ef7eb2e8f9f7 1578 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
<> 144:ef7eb2e8f9f7 1579 }
<> 144:ef7eb2e8f9f7 1580 }
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1583 {
<> 144:ef7eb2e8f9f7 1584 /* set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1585 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 if((hspi->RxXferCount & 0x1) == 0x0 )
<> 144:ef7eb2e8f9f7 1588 {
<> 144:ef7eb2e8f9f7 1589 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 144:ef7eb2e8f9f7 1590 hspi->RxXferCount = hspi->RxXferCount >> 1;
<> 144:ef7eb2e8f9f7 1591 }
<> 144:ef7eb2e8f9f7 1592 else
<> 144:ef7eb2e8f9f7 1593 {
<> 144:ef7eb2e8f9f7 1594 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 144:ef7eb2e8f9f7 1595 hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
<> 144:ef7eb2e8f9f7 1596 }
<> 144:ef7eb2e8f9f7 1597 }
<> 144:ef7eb2e8f9f7 1598 }
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
<> 144:ef7eb2e8f9f7 1601 reception request (RXNE) */
<> 144:ef7eb2e8f9f7 1602 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1603 {
<> 144:ef7eb2e8f9f7 1604 /* Set the SPI Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1605 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1606 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1607 }
<> 144:ef7eb2e8f9f7 1608 else
<> 144:ef7eb2e8f9f7 1609 {
<> 144:ef7eb2e8f9f7 1610 /* Set the SPI Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1611 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1612 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1613 }
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1616 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1619 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /* Enable the Rx DMA channel */
<> 144:ef7eb2e8f9f7 1622 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<> 144:ef7eb2e8f9f7 1625 is performed in DMA reception complete callback */
<> 144:ef7eb2e8f9f7 1626 hspi->hdmatx->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1627 hspi->hdmatx->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1630 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 /* Enable the Tx DMA channel */
<> 144:ef7eb2e8f9f7 1633 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1634
<> 144:ef7eb2e8f9f7 1635 /* Check if the SPI is already enabled */
<> 144:ef7eb2e8f9f7 1636 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1637 {
<> 144:ef7eb2e8f9f7 1638 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1639 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1640 }
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1643 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1644
<> 144:ef7eb2e8f9f7 1645 error :
<> 144:ef7eb2e8f9f7 1646 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1647 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1648 return errorcode;
<> 144:ef7eb2e8f9f7 1649 }
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 /**
<> 144:ef7eb2e8f9f7 1652 * @brief Pause the DMA Transfer.
<> 144:ef7eb2e8f9f7 1653 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1654 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1655 * @retval HAL status
<> 144:ef7eb2e8f9f7 1656 */
<> 144:ef7eb2e8f9f7 1657 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1658 {
<> 144:ef7eb2e8f9f7 1659 /* Process Locked */
<> 144:ef7eb2e8f9f7 1660 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1663 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1664
<> 144:ef7eb2e8f9f7 1665 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1666 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1667
<> 144:ef7eb2e8f9f7 1668 return HAL_OK;
<> 144:ef7eb2e8f9f7 1669 }
<> 144:ef7eb2e8f9f7 1670
<> 144:ef7eb2e8f9f7 1671 /**
<> 144:ef7eb2e8f9f7 1672 * @brief Resume the DMA Transfer.
<> 144:ef7eb2e8f9f7 1673 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1674 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1675 * @retval HAL status
<> 144:ef7eb2e8f9f7 1676 */
<> 144:ef7eb2e8f9f7 1677 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1678 {
<> 144:ef7eb2e8f9f7 1679 /* Process Locked */
<> 144:ef7eb2e8f9f7 1680 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1681
<> 144:ef7eb2e8f9f7 1682 /* Enable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1683 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1684
<> 144:ef7eb2e8f9f7 1685 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1686 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1687
<> 144:ef7eb2e8f9f7 1688 return HAL_OK;
<> 144:ef7eb2e8f9f7 1689 }
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 /**
<> 144:ef7eb2e8f9f7 1692 * @brief Stop the DMA Transfer.
<> 144:ef7eb2e8f9f7 1693 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1694 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1695 * @retval HAL status
<> 144:ef7eb2e8f9f7 1696 */
<> 144:ef7eb2e8f9f7 1697 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1698 {
<> 144:ef7eb2e8f9f7 1699 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 1700 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<> 144:ef7eb2e8f9f7 1701 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 1702 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 1703 */
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 /* Abort the SPI DMA tx channel */
<> 144:ef7eb2e8f9f7 1706 if(hspi->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 1707 {
<> 144:ef7eb2e8f9f7 1708 HAL_DMA_Abort(hspi->hdmatx);
<> 144:ef7eb2e8f9f7 1709 }
<> 144:ef7eb2e8f9f7 1710 /* Abort the SPI DMA rx channel */
<> 144:ef7eb2e8f9f7 1711 if(hspi->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1712 {
<> 144:ef7eb2e8f9f7 1713 HAL_DMA_Abort(hspi->hdmarx);
<> 144:ef7eb2e8f9f7 1714 }
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 1717 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1718 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1719 return HAL_OK;
<> 144:ef7eb2e8f9f7 1720 }
<> 144:ef7eb2e8f9f7 1721
<> 144:ef7eb2e8f9f7 1722 /**
<> 144:ef7eb2e8f9f7 1723 * @brief Handle SPI interrupt request.
<> 144:ef7eb2e8f9f7 1724 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1725 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 1726 * @retval None
<> 144:ef7eb2e8f9f7 1727 */
<> 144:ef7eb2e8f9f7 1728 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1729 {
<> 144:ef7eb2e8f9f7 1730 uint32_t itsource = hspi->Instance->CR2;
<> 144:ef7eb2e8f9f7 1731 uint32_t itflag = hspi->Instance->SR;
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 /* SPI in mode Receiver ----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1734 if(((itflag & SPI_FLAG_OVR) == RESET) &&
<> 144:ef7eb2e8f9f7 1735 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 1736 {
<> 144:ef7eb2e8f9f7 1737 hspi->RxISR(hspi);
<> 144:ef7eb2e8f9f7 1738 return;
<> 144:ef7eb2e8f9f7 1739 }
<> 144:ef7eb2e8f9f7 1740
<> 144:ef7eb2e8f9f7 1741 /* SPI in mode Transmitter ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1742 if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 1743 {
<> 144:ef7eb2e8f9f7 1744 hspi->TxISR(hspi);
<> 144:ef7eb2e8f9f7 1745 return;
<> 144:ef7eb2e8f9f7 1746 }
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /* SPI in Error Treatment ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1749 if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
<> 144:ef7eb2e8f9f7 1750 {
<> 144:ef7eb2e8f9f7 1751 /* SPI Overrun error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 1752 if((itflag & SPI_FLAG_OVR) != RESET)
<> 144:ef7eb2e8f9f7 1753 {
<> 144:ef7eb2e8f9f7 1754 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1755 {
<> 144:ef7eb2e8f9f7 1756 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
<> 144:ef7eb2e8f9f7 1757 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1758 }
<> 144:ef7eb2e8f9f7 1759 else
<> 144:ef7eb2e8f9f7 1760 {
<> 144:ef7eb2e8f9f7 1761 return;
<> 144:ef7eb2e8f9f7 1762 }
<> 144:ef7eb2e8f9f7 1763 }
<> 144:ef7eb2e8f9f7 1764
<> 144:ef7eb2e8f9f7 1765 /* SPI Mode Fault error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 1766 if((itflag & SPI_FLAG_MODF) != RESET)
<> 144:ef7eb2e8f9f7 1767 {
<> 144:ef7eb2e8f9f7 1768 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
<> 144:ef7eb2e8f9f7 1769 __HAL_SPI_CLEAR_MODFFLAG(hspi);
<> 144:ef7eb2e8f9f7 1770 }
<> 144:ef7eb2e8f9f7 1771
<> 144:ef7eb2e8f9f7 1772 /* SPI Frame error interrupt occurred ----------------------------------------*/
<> 144:ef7eb2e8f9f7 1773 if((itflag & SPI_FLAG_FRE) != RESET)
<> 144:ef7eb2e8f9f7 1774 {
<> 144:ef7eb2e8f9f7 1775 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
<> 144:ef7eb2e8f9f7 1776 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 144:ef7eb2e8f9f7 1777 }
<> 144:ef7eb2e8f9f7 1778
<> 144:ef7eb2e8f9f7 1779 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 1780 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1781 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 1782 return;
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784 }
<> 144:ef7eb2e8f9f7 1785
<> 144:ef7eb2e8f9f7 1786 /**
<> 144:ef7eb2e8f9f7 1787 * @brief Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1788 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1789 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1790 * @retval None
<> 144:ef7eb2e8f9f7 1791 */
<> 144:ef7eb2e8f9f7 1792 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1793 {
<> 144:ef7eb2e8f9f7 1794 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1795 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1796
<> 144:ef7eb2e8f9f7 1797 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1798 the HAL_SPI_TxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 1799 */
<> 144:ef7eb2e8f9f7 1800 }
<> 144:ef7eb2e8f9f7 1801
<> 144:ef7eb2e8f9f7 1802 /**
<> 144:ef7eb2e8f9f7 1803 * @brief Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1804 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1805 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1806 * @retval None
<> 144:ef7eb2e8f9f7 1807 */
<> 144:ef7eb2e8f9f7 1808 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1809 {
<> 144:ef7eb2e8f9f7 1810 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1811 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1814 the HAL_SPI_RxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 1815 */
<> 144:ef7eb2e8f9f7 1816 }
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /**
<> 144:ef7eb2e8f9f7 1819 * @brief Tx and Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1820 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1821 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1822 * @retval None
<> 144:ef7eb2e8f9f7 1823 */
<> 144:ef7eb2e8f9f7 1824 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1825 {
<> 144:ef7eb2e8f9f7 1826 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1827 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1828
<> 144:ef7eb2e8f9f7 1829 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1830 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 1831 */
<> 144:ef7eb2e8f9f7 1832 }
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 /**
<> 144:ef7eb2e8f9f7 1835 * @brief Tx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 1836 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1837 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1838 * @retval None
<> 144:ef7eb2e8f9f7 1839 */
<> 144:ef7eb2e8f9f7 1840 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1841 {
<> 144:ef7eb2e8f9f7 1842 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1843 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1844
<> 144:ef7eb2e8f9f7 1845 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1846 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 1847 */
<> 144:ef7eb2e8f9f7 1848 }
<> 144:ef7eb2e8f9f7 1849
<> 144:ef7eb2e8f9f7 1850 /**
<> 144:ef7eb2e8f9f7 1851 * @brief Rx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 1852 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1853 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1854 * @retval None
<> 144:ef7eb2e8f9f7 1855 */
<> 144:ef7eb2e8f9f7 1856 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1857 {
<> 144:ef7eb2e8f9f7 1858 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1859 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1862 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
<> 144:ef7eb2e8f9f7 1863 */
<> 144:ef7eb2e8f9f7 1864 }
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /**
<> 144:ef7eb2e8f9f7 1867 * @brief Tx and Rx Half Transfer callback.
<> 144:ef7eb2e8f9f7 1868 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1869 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1870 * @retval None
<> 144:ef7eb2e8f9f7 1871 */
<> 144:ef7eb2e8f9f7 1872 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1873 {
<> 144:ef7eb2e8f9f7 1874 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1875 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1876
<> 144:ef7eb2e8f9f7 1877 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1878 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
<> 144:ef7eb2e8f9f7 1879 */
<> 144:ef7eb2e8f9f7 1880 }
<> 144:ef7eb2e8f9f7 1881
<> 144:ef7eb2e8f9f7 1882 /**
<> 144:ef7eb2e8f9f7 1883 * @brief SPI error callback.
<> 144:ef7eb2e8f9f7 1884 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1885 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1886 * @retval None
<> 144:ef7eb2e8f9f7 1887 */
<> 144:ef7eb2e8f9f7 1888 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1889 {
<> 144:ef7eb2e8f9f7 1890 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1891 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 1892
<> 144:ef7eb2e8f9f7 1893 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1894 the HAL_SPI_ErrorCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 1895 */
<> 144:ef7eb2e8f9f7 1896 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
<> 144:ef7eb2e8f9f7 1897 and user can use HAL_SPI_GetError() API to check the latest error occurred
<> 144:ef7eb2e8f9f7 1898 */
<> 144:ef7eb2e8f9f7 1899 }
<> 144:ef7eb2e8f9f7 1900
<> 144:ef7eb2e8f9f7 1901 /**
<> 144:ef7eb2e8f9f7 1902 * @}
<> 144:ef7eb2e8f9f7 1903 */
<> 144:ef7eb2e8f9f7 1904
<> 144:ef7eb2e8f9f7 1905 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1906 * @brief SPI control functions
<> 144:ef7eb2e8f9f7 1907 *
<> 144:ef7eb2e8f9f7 1908 @verbatim
<> 144:ef7eb2e8f9f7 1909 ===============================================================================
<> 144:ef7eb2e8f9f7 1910 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1911 ===============================================================================
<> 144:ef7eb2e8f9f7 1912 [..]
<> 144:ef7eb2e8f9f7 1913 This subsection provides a set of functions allowing to control the SPI.
<> 144:ef7eb2e8f9f7 1914 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<> 144:ef7eb2e8f9f7 1915 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<> 144:ef7eb2e8f9f7 1916 @endverbatim
<> 144:ef7eb2e8f9f7 1917 * @{
<> 144:ef7eb2e8f9f7 1918 */
<> 144:ef7eb2e8f9f7 1919
<> 144:ef7eb2e8f9f7 1920 /**
<> 144:ef7eb2e8f9f7 1921 * @brief Return the SPI handle state.
<> 144:ef7eb2e8f9f7 1922 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1923 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1924 * @retval SPI state
<> 144:ef7eb2e8f9f7 1925 */
<> 144:ef7eb2e8f9f7 1926 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1927 {
<> 144:ef7eb2e8f9f7 1928 /* Return SPI handle state */
<> 144:ef7eb2e8f9f7 1929 return hspi->State;
<> 144:ef7eb2e8f9f7 1930 }
<> 144:ef7eb2e8f9f7 1931
<> 144:ef7eb2e8f9f7 1932 /**
<> 144:ef7eb2e8f9f7 1933 * @brief Return the SPI error code.
<> 144:ef7eb2e8f9f7 1934 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1935 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1936 * @retval SPI error code in bitmap format
<> 144:ef7eb2e8f9f7 1937 */
<> 144:ef7eb2e8f9f7 1938 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 1939 {
<> 144:ef7eb2e8f9f7 1940 return hspi->ErrorCode;
<> 144:ef7eb2e8f9f7 1941 }
<> 144:ef7eb2e8f9f7 1942
<> 144:ef7eb2e8f9f7 1943 /**
<> 144:ef7eb2e8f9f7 1944 * @}
<> 144:ef7eb2e8f9f7 1945 */
<> 144:ef7eb2e8f9f7 1946
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /**
<> 144:ef7eb2e8f9f7 1949 * @}
<> 144:ef7eb2e8f9f7 1950 */
<> 144:ef7eb2e8f9f7 1951
<> 144:ef7eb2e8f9f7 1952 /** @addtogroup SPI_Private_Functions
<> 144:ef7eb2e8f9f7 1953 * @brief Private functions
<> 144:ef7eb2e8f9f7 1954 * @{
<> 144:ef7eb2e8f9f7 1955 */
<> 144:ef7eb2e8f9f7 1956
<> 144:ef7eb2e8f9f7 1957 /**
<> 144:ef7eb2e8f9f7 1958 * @brief DMA SPI transmit process complete callback.
<> 144:ef7eb2e8f9f7 1959 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1960 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1961 * @retval None
<> 144:ef7eb2e8f9f7 1962 */
<> 144:ef7eb2e8f9f7 1963 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1964 {
<> 144:ef7eb2e8f9f7 1965 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 1968 {
<> 144:ef7eb2e8f9f7 1969 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1970 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1971
<> 144:ef7eb2e8f9f7 1972 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 1973 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1974 {
<> 144:ef7eb2e8f9f7 1975 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 1976 }
<> 144:ef7eb2e8f9f7 1977
<> 144:ef7eb2e8f9f7 1978 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
<> 144:ef7eb2e8f9f7 1979 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 1980 {
<> 144:ef7eb2e8f9f7 1981 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1982 }
<> 144:ef7eb2e8f9f7 1983
<> 144:ef7eb2e8f9f7 1984 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1985 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1986
<> 144:ef7eb2e8f9f7 1987 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1988 {
<> 144:ef7eb2e8f9f7 1989 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 1990 return;
<> 144:ef7eb2e8f9f7 1991 }
<> 144:ef7eb2e8f9f7 1992 }
<> 144:ef7eb2e8f9f7 1993 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 1994 }
<> 144:ef7eb2e8f9f7 1995
<> 144:ef7eb2e8f9f7 1996 /**
<> 144:ef7eb2e8f9f7 1997 * @brief DMA SPI receive process complete callback.
<> 144:ef7eb2e8f9f7 1998 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1999 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2000 * @retval None
<> 144:ef7eb2e8f9f7 2001 */
<> 144:ef7eb2e8f9f7 2002 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2003 {
<> 144:ef7eb2e8f9f7 2004 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2005
<> 144:ef7eb2e8f9f7 2006 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2007 {
<> 144:ef7eb2e8f9f7 2008 __IO uint16_t tmpreg;
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /* CRC handling */
<> 144:ef7eb2e8f9f7 2011 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2012 {
<> 144:ef7eb2e8f9f7 2013 /* Wait until TXE flag */
<> 144:ef7eb2e8f9f7 2014 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 2015 {
<> 144:ef7eb2e8f9f7 2016 /* Error on the CRC reception */
<> 144:ef7eb2e8f9f7 2017 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 2018 }
<> 144:ef7eb2e8f9f7 2019 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 2020 {
<> 144:ef7eb2e8f9f7 2021 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2022 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2023 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2024 }
<> 144:ef7eb2e8f9f7 2025 else
<> 144:ef7eb2e8f9f7 2026 {
<> 144:ef7eb2e8f9f7 2027 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2028 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2029 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2030
<> 144:ef7eb2e8f9f7 2031 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 2032 {
<> 144:ef7eb2e8f9f7 2033 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 2034 {
<> 144:ef7eb2e8f9f7 2035 /* Error on the CRC reception */
<> 144:ef7eb2e8f9f7 2036 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 2037 }
<> 144:ef7eb2e8f9f7 2038 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2039 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2040 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2041 }
<> 144:ef7eb2e8f9f7 2042 }
<> 144:ef7eb2e8f9f7 2043 }
<> 144:ef7eb2e8f9f7 2044
<> 144:ef7eb2e8f9f7 2045 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
<> 144:ef7eb2e8f9f7 2046 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2047
<> 144:ef7eb2e8f9f7 2048 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 2049 if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
<> 144:ef7eb2e8f9f7 2050 {
<> 144:ef7eb2e8f9f7 2051 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2052 }
<> 144:ef7eb2e8f9f7 2053
<> 144:ef7eb2e8f9f7 2054 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 2055 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2056
<> 144:ef7eb2e8f9f7 2057 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 2058 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 2059 {
<> 144:ef7eb2e8f9f7 2060 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 2061 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2062 }
<> 144:ef7eb2e8f9f7 2063
<> 144:ef7eb2e8f9f7 2064 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2065 {
<> 144:ef7eb2e8f9f7 2066 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2067 return;
<> 144:ef7eb2e8f9f7 2068 }
<> 144:ef7eb2e8f9f7 2069 }
<> 144:ef7eb2e8f9f7 2070 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2071 }
<> 144:ef7eb2e8f9f7 2072
<> 144:ef7eb2e8f9f7 2073 /**
<> 144:ef7eb2e8f9f7 2074 * @brief DMA SPI transmit receive process complete callback.
<> 144:ef7eb2e8f9f7 2075 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2076 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2077 * @retval None
<> 144:ef7eb2e8f9f7 2078 */
<> 144:ef7eb2e8f9f7 2079 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2080 {
<> 144:ef7eb2e8f9f7 2081 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2082
<> 144:ef7eb2e8f9f7 2083 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2084 {
<> 144:ef7eb2e8f9f7 2085 __IO int16_t tmpreg;
<> 144:ef7eb2e8f9f7 2086 /* CRC handling */
<> 144:ef7eb2e8f9f7 2087 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2088 {
<> 144:ef7eb2e8f9f7 2089 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
<> 144:ef7eb2e8f9f7 2090 {
<> 144:ef7eb2e8f9f7 2091 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 2092 {
<> 144:ef7eb2e8f9f7 2093 /* Error on the CRC reception */
<> 144:ef7eb2e8f9f7 2094 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 2095 }
<> 144:ef7eb2e8f9f7 2096 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2097 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2098 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2099 }
<> 144:ef7eb2e8f9f7 2100 else
<> 144:ef7eb2e8f9f7 2101 {
<> 144:ef7eb2e8f9f7 2102 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 2103 {
<> 144:ef7eb2e8f9f7 2104 /* Error on the CRC reception */
<> 144:ef7eb2e8f9f7 2105 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 2106 }
<> 144:ef7eb2e8f9f7 2107 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2108 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2109 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2110 }
<> 144:ef7eb2e8f9f7 2111 }
<> 144:ef7eb2e8f9f7 2112
<> 144:ef7eb2e8f9f7 2113 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 2114 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 2115 {
<> 144:ef7eb2e8f9f7 2116 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2117 }
<> 144:ef7eb2e8f9f7 2118
<> 144:ef7eb2e8f9f7 2119 /* Disable Rx/Tx DMA Request */
<> 144:ef7eb2e8f9f7 2120 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2121
<> 144:ef7eb2e8f9f7 2122 hspi->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 2123 hspi->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 2124 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2125
<> 144:ef7eb2e8f9f7 2126 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 2127 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 2128 {
<> 144:ef7eb2e8f9f7 2129 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 2130 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2131 }
<> 144:ef7eb2e8f9f7 2132
<> 144:ef7eb2e8f9f7 2133 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2134 {
<> 144:ef7eb2e8f9f7 2135 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2136 return;
<> 144:ef7eb2e8f9f7 2137 }
<> 144:ef7eb2e8f9f7 2138 }
<> 144:ef7eb2e8f9f7 2139 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2140 }
<> 144:ef7eb2e8f9f7 2141
<> 144:ef7eb2e8f9f7 2142 /**
<> 144:ef7eb2e8f9f7 2143 * @brief DMA SPI half transmit process complete callback.
<> 144:ef7eb2e8f9f7 2144 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2145 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2146 * @retval None
<> 144:ef7eb2e8f9f7 2147 */
<> 144:ef7eb2e8f9f7 2148 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2149 {
<> 144:ef7eb2e8f9f7 2150 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2151
<> 144:ef7eb2e8f9f7 2152 HAL_SPI_TxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2153 }
<> 144:ef7eb2e8f9f7 2154
<> 144:ef7eb2e8f9f7 2155 /**
<> 144:ef7eb2e8f9f7 2156 * @brief DMA SPI half receive process complete callback
<> 144:ef7eb2e8f9f7 2157 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2158 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2159 * @retval None
<> 144:ef7eb2e8f9f7 2160 */
<> 144:ef7eb2e8f9f7 2161 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2162 {
<> 144:ef7eb2e8f9f7 2163 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 HAL_SPI_RxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2166 }
<> 144:ef7eb2e8f9f7 2167
<> 144:ef7eb2e8f9f7 2168 /**
<> 144:ef7eb2e8f9f7 2169 * @brief DMA SPI half transmit receive process complete callback.
<> 144:ef7eb2e8f9f7 2170 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2171 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2172 * @retval None
<> 144:ef7eb2e8f9f7 2173 */
<> 144:ef7eb2e8f9f7 2174 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2175 {
<> 144:ef7eb2e8f9f7 2176 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2177
<> 144:ef7eb2e8f9f7 2178 HAL_SPI_TxRxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2179 }
<> 144:ef7eb2e8f9f7 2180
<> 144:ef7eb2e8f9f7 2181 /**
<> 144:ef7eb2e8f9f7 2182 * @brief DMA SPI communication error callback.
<> 144:ef7eb2e8f9f7 2183 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2184 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2185 * @retval None
<> 144:ef7eb2e8f9f7 2186 */
<> 144:ef7eb2e8f9f7 2187 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2188 {
<> 144:ef7eb2e8f9f7 2189 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2190
<> 144:ef7eb2e8f9f7 2191 /* Stop the disable DMA transfer on SPI side */
<> 144:ef7eb2e8f9f7 2192 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2193
<> 144:ef7eb2e8f9f7 2194 hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
<> 144:ef7eb2e8f9f7 2195 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2196 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2197 }
<> 144:ef7eb2e8f9f7 2198
<> 144:ef7eb2e8f9f7 2199 /**
<> 144:ef7eb2e8f9f7 2200 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2201 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2202 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2203 * @retval None
<> 144:ef7eb2e8f9f7 2204 */
<> 144:ef7eb2e8f9f7 2205 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2206 {
<> 144:ef7eb2e8f9f7 2207 /* Receive data in packing mode */
<> 144:ef7eb2e8f9f7 2208 if(hspi->RxXferCount > 1)
<> 144:ef7eb2e8f9f7 2209 {
<> 144:ef7eb2e8f9f7 2210 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2211 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 2212 hspi->RxXferCount -= 2;
<> 144:ef7eb2e8f9f7 2213 if(hspi->RxXferCount == 1)
<> 144:ef7eb2e8f9f7 2214 {
<> 144:ef7eb2e8f9f7 2215 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 2216 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 2217 }
<> 144:ef7eb2e8f9f7 2218 }
<> 144:ef7eb2e8f9f7 2219 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 2220 else
<> 144:ef7eb2e8f9f7 2221 {
<> 144:ef7eb2e8f9f7 2222 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 2223 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 2224 }
<> 144:ef7eb2e8f9f7 2225
<> 144:ef7eb2e8f9f7 2226 /* check end of the reception */
<> 144:ef7eb2e8f9f7 2227 if(hspi->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 2228 {
<> 144:ef7eb2e8f9f7 2229 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2230 {
<> 144:ef7eb2e8f9f7 2231 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 2232 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 2233 return;
<> 144:ef7eb2e8f9f7 2234 }
<> 144:ef7eb2e8f9f7 2235
<> 144:ef7eb2e8f9f7 2236 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 2237 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 2238
<> 144:ef7eb2e8f9f7 2239 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 2240 {
<> 144:ef7eb2e8f9f7 2241 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2242 }
<> 144:ef7eb2e8f9f7 2243 }
<> 144:ef7eb2e8f9f7 2244 }
<> 144:ef7eb2e8f9f7 2245
<> 144:ef7eb2e8f9f7 2246 /**
<> 144:ef7eb2e8f9f7 2247 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2248 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2249 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2250 * @retval None
<> 144:ef7eb2e8f9f7 2251 */
<> 144:ef7eb2e8f9f7 2252 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2253 {
<> 144:ef7eb2e8f9f7 2254 __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 2255 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2256 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2257
<> 144:ef7eb2e8f9f7 2258 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 2259
<> 144:ef7eb2e8f9f7 2260 /* check end of the reception */
<> 144:ef7eb2e8f9f7 2261 if(hspi->CRCSize == 0)
<> 144:ef7eb2e8f9f7 2262 {
<> 144:ef7eb2e8f9f7 2263 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 2264 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 2265
<> 144:ef7eb2e8f9f7 2266 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 2267 {
<> 144:ef7eb2e8f9f7 2268 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2269 }
<> 144:ef7eb2e8f9f7 2270 }
<> 144:ef7eb2e8f9f7 2271 }
<> 144:ef7eb2e8f9f7 2272
<> 144:ef7eb2e8f9f7 2273 /**
<> 144:ef7eb2e8f9f7 2274 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2275 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2276 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2277 * @retval None
<> 144:ef7eb2e8f9f7 2278 */
<> 144:ef7eb2e8f9f7 2279 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2280 {
<> 144:ef7eb2e8f9f7 2281 /* Transmit data in packing Bit mode */
<> 144:ef7eb2e8f9f7 2282 if(hspi->TxXferCount >= 2)
<> 144:ef7eb2e8f9f7 2283 {
<> 144:ef7eb2e8f9f7 2284 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 2285 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 2286 hspi->TxXferCount -= 2;
<> 144:ef7eb2e8f9f7 2287 }
<> 144:ef7eb2e8f9f7 2288 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 2289 else
<> 144:ef7eb2e8f9f7 2290 {
<> 144:ef7eb2e8f9f7 2291 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 2292 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 2293 }
<> 144:ef7eb2e8f9f7 2294
<> 144:ef7eb2e8f9f7 2295 /* check the end of the transmission */
<> 144:ef7eb2e8f9f7 2296 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 2297 {
<> 144:ef7eb2e8f9f7 2298 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2299 {
<> 144:ef7eb2e8f9f7 2300 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 2301 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 2302 return;
<> 144:ef7eb2e8f9f7 2303 }
<> 144:ef7eb2e8f9f7 2304 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 2305 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 2306
<> 144:ef7eb2e8f9f7 2307 if(hspi->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 2308 {
<> 144:ef7eb2e8f9f7 2309 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2310 }
<> 144:ef7eb2e8f9f7 2311 }
<> 144:ef7eb2e8f9f7 2312 }
<> 144:ef7eb2e8f9f7 2313
<> 144:ef7eb2e8f9f7 2314 /**
<> 144:ef7eb2e8f9f7 2315 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2316 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2317 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2318 * @retval None
<> 144:ef7eb2e8f9f7 2319 */
<> 144:ef7eb2e8f9f7 2320 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2321 {
<> 144:ef7eb2e8f9f7 2322 /* Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 2323 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2324 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 2325 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327 if(hspi->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 2328 {
<> 144:ef7eb2e8f9f7 2329 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2330 {
<> 144:ef7eb2e8f9f7 2331 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 2332 return;
<> 144:ef7eb2e8f9f7 2333 }
<> 144:ef7eb2e8f9f7 2334
<> 144:ef7eb2e8f9f7 2335 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 2336 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 2337
<> 144:ef7eb2e8f9f7 2338 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 2339 {
<> 144:ef7eb2e8f9f7 2340 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2341 }
<> 144:ef7eb2e8f9f7 2342 }
<> 144:ef7eb2e8f9f7 2343 }
<> 144:ef7eb2e8f9f7 2344
<> 144:ef7eb2e8f9f7 2345 /**
<> 144:ef7eb2e8f9f7 2346 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2347 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2348 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2349 * @retval None
<> 144:ef7eb2e8f9f7 2350 */
<> 144:ef7eb2e8f9f7 2351 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2352 {
<> 144:ef7eb2e8f9f7 2353 /* Receive data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 2354 __IO uint16_t tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2355 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2356 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 2359 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 2360
<> 144:ef7eb2e8f9f7 2361 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2362 }
<> 144:ef7eb2e8f9f7 2363
<> 144:ef7eb2e8f9f7 2364 /**
<> 144:ef7eb2e8f9f7 2365 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 2366 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2367 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2368 * @retval None
<> 144:ef7eb2e8f9f7 2369 */
<> 144:ef7eb2e8f9f7 2370 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2371 {
<> 144:ef7eb2e8f9f7 2372 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 2373 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 2374 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 2375 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 2376
<> 144:ef7eb2e8f9f7 2377 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 2378 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 2379 {
<> 144:ef7eb2e8f9f7 2380 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2381 {
<> 144:ef7eb2e8f9f7 2382 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 2383 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 2384 return;
<> 144:ef7eb2e8f9f7 2385 }
<> 144:ef7eb2e8f9f7 2386 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 2387 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 2388
<> 144:ef7eb2e8f9f7 2389 if(hspi->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 2390 {
<> 144:ef7eb2e8f9f7 2391 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2392 }
<> 144:ef7eb2e8f9f7 2393 }
<> 144:ef7eb2e8f9f7 2394 }
<> 144:ef7eb2e8f9f7 2395
<> 144:ef7eb2e8f9f7 2396 /**
<> 144:ef7eb2e8f9f7 2397 * @brief Manage the CRC 8-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 2398 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2399 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2400 * @retval None
<> 144:ef7eb2e8f9f7 2401 */
<> 144:ef7eb2e8f9f7 2402 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2403 {
<> 144:ef7eb2e8f9f7 2404 __IO uint8_t tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 2405 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2406 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2407
<> 144:ef7eb2e8f9f7 2408 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 2409
<> 144:ef7eb2e8f9f7 2410 if(hspi->CRCSize == 0)
<> 144:ef7eb2e8f9f7 2411 {
<> 144:ef7eb2e8f9f7 2412 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2413 }
<> 144:ef7eb2e8f9f7 2414 }
<> 144:ef7eb2e8f9f7 2415
<> 144:ef7eb2e8f9f7 2416 /**
<> 144:ef7eb2e8f9f7 2417 * @brief Manage the receive 8-bit in Interrupt context.
<> 144:ef7eb2e8f9f7 2418 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2419 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2420 * @retval None
<> 144:ef7eb2e8f9f7 2421 */
<> 144:ef7eb2e8f9f7 2422 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2423 {
<> 144:ef7eb2e8f9f7 2424 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 2425 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 2426
<> 144:ef7eb2e8f9f7 2427 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 2428 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 2429 {
<> 144:ef7eb2e8f9f7 2430 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
<> 144:ef7eb2e8f9f7 2431 }
<> 144:ef7eb2e8f9f7 2432
<> 144:ef7eb2e8f9f7 2433 if(hspi->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 2434 {
<> 144:ef7eb2e8f9f7 2435 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2436 {
<> 144:ef7eb2e8f9f7 2437 hspi->RxISR = SPI_RxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 2438 return;
<> 144:ef7eb2e8f9f7 2439 }
<> 144:ef7eb2e8f9f7 2440 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2441 }
<> 144:ef7eb2e8f9f7 2442 }
<> 144:ef7eb2e8f9f7 2443
<> 144:ef7eb2e8f9f7 2444 /**
<> 144:ef7eb2e8f9f7 2445 * @brief Manage the CRC 16-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 2446 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2447 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2448 * @retval None
<> 144:ef7eb2e8f9f7 2449 */
<> 144:ef7eb2e8f9f7 2450 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2451 {
<> 144:ef7eb2e8f9f7 2452 __IO uint16_t tmpreg;
<> 144:ef7eb2e8f9f7 2453
<> 144:ef7eb2e8f9f7 2454 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2455 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2456 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2457
<> 144:ef7eb2e8f9f7 2458 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 2459 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2460
<> 144:ef7eb2e8f9f7 2461 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2462 }
<> 144:ef7eb2e8f9f7 2463
<> 144:ef7eb2e8f9f7 2464 /**
<> 144:ef7eb2e8f9f7 2465 * @brief Manage the 16-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 2466 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2467 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2468 * @retval None
<> 144:ef7eb2e8f9f7 2469 */
<> 144:ef7eb2e8f9f7 2470 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2471 {
<> 144:ef7eb2e8f9f7 2472 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2473 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 2474 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 2475
<> 144:ef7eb2e8f9f7 2476 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 2477 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 2478 {
<> 144:ef7eb2e8f9f7 2479 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
<> 144:ef7eb2e8f9f7 2480 }
<> 144:ef7eb2e8f9f7 2481
<> 144:ef7eb2e8f9f7 2482 if(hspi->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 2483 {
<> 144:ef7eb2e8f9f7 2484 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2485 {
<> 144:ef7eb2e8f9f7 2486 hspi->RxISR = SPI_RxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 2487 return;
<> 144:ef7eb2e8f9f7 2488 }
<> 144:ef7eb2e8f9f7 2489 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2490 }
<> 144:ef7eb2e8f9f7 2491 }
<> 144:ef7eb2e8f9f7 2492
<> 144:ef7eb2e8f9f7 2493 /**
<> 144:ef7eb2e8f9f7 2494 * @brief Handle the data 8-bit transmit in Interrupt mode.
<> 144:ef7eb2e8f9f7 2495 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2496 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2497 * @retval None
<> 144:ef7eb2e8f9f7 2498 */
<> 144:ef7eb2e8f9f7 2499 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2500 {
<> 144:ef7eb2e8f9f7 2501 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 2502 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 2503
<> 144:ef7eb2e8f9f7 2504 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 2505 {
<> 144:ef7eb2e8f9f7 2506 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2507 {
<> 144:ef7eb2e8f9f7 2508 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 2509 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
<> 144:ef7eb2e8f9f7 2510 }
<> 144:ef7eb2e8f9f7 2511 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2512 }
<> 144:ef7eb2e8f9f7 2513 }
<> 144:ef7eb2e8f9f7 2514
<> 144:ef7eb2e8f9f7 2515 /**
<> 144:ef7eb2e8f9f7 2516 * @brief Handle the data 16-bit transmit in Interrupt mode.
<> 144:ef7eb2e8f9f7 2517 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2518 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2519 * @retval None
<> 144:ef7eb2e8f9f7 2520 */
<> 144:ef7eb2e8f9f7 2521 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2522 {
<> 144:ef7eb2e8f9f7 2523 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 2524 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 2525 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 2526 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 2527
<> 144:ef7eb2e8f9f7 2528 if(hspi->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 2529 {
<> 144:ef7eb2e8f9f7 2530 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2531 {
<> 144:ef7eb2e8f9f7 2532 /* Enable CRC Transmission */
<> 144:ef7eb2e8f9f7 2533 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
<> 144:ef7eb2e8f9f7 2534 }
<> 144:ef7eb2e8f9f7 2535 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 2536 }
<> 144:ef7eb2e8f9f7 2537 }
<> 144:ef7eb2e8f9f7 2538
<> 144:ef7eb2e8f9f7 2539 /**
<> 144:ef7eb2e8f9f7 2540 * @brief Handle SPI Communication Timeout.
<> 144:ef7eb2e8f9f7 2541 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2542 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2543 * @param Flag : SPI flag to check
<> 144:ef7eb2e8f9f7 2544 * @param State : flag state to check
<> 144:ef7eb2e8f9f7 2545 * @param Timeout : Timeout duration
<> 144:ef7eb2e8f9f7 2546 * @retval HAL status
<> 144:ef7eb2e8f9f7 2547 */
<> 144:ef7eb2e8f9f7 2548 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2549 {
<> 144:ef7eb2e8f9f7 2550 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2551
<> 144:ef7eb2e8f9f7 2552 while((hspi->Instance->SR & Flag) != State)
<> 144:ef7eb2e8f9f7 2553 {
<> 144:ef7eb2e8f9f7 2554 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2555 {
<> 144:ef7eb2e8f9f7 2556 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 2557 {
<> 144:ef7eb2e8f9f7 2558 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 2559 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 2560 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 2561
<> 144:ef7eb2e8f9f7 2562 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 2563 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2564
<> 144:ef7eb2e8f9f7 2565 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 2566 {
<> 144:ef7eb2e8f9f7 2567 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 2568 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 2569 }
<> 144:ef7eb2e8f9f7 2570
<> 144:ef7eb2e8f9f7 2571 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 2572 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2573 {
<> 144:ef7eb2e8f9f7 2574 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 2575 }
<> 144:ef7eb2e8f9f7 2576
<> 144:ef7eb2e8f9f7 2577 hspi->State= HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2578
<> 144:ef7eb2e8f9f7 2579 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2580 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2581
<> 144:ef7eb2e8f9f7 2582 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2583 }
<> 144:ef7eb2e8f9f7 2584 }
<> 144:ef7eb2e8f9f7 2585 }
<> 144:ef7eb2e8f9f7 2586
<> 144:ef7eb2e8f9f7 2587 return HAL_OK;
<> 144:ef7eb2e8f9f7 2588 }
<> 144:ef7eb2e8f9f7 2589
<> 144:ef7eb2e8f9f7 2590 /**
<> 144:ef7eb2e8f9f7 2591 * @brief Handle SPI FIFO Communication Timeout.
<> 144:ef7eb2e8f9f7 2592 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2593 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2594 * @param Fifo : Fifo to check
<> 144:ef7eb2e8f9f7 2595 * @param State : Fifo state to check
<> 144:ef7eb2e8f9f7 2596 * @param Timeout : Timeout duration
<> 144:ef7eb2e8f9f7 2597 * @retval HAL status
<> 144:ef7eb2e8f9f7 2598 */
<> 144:ef7eb2e8f9f7 2599 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2600 {
<> 144:ef7eb2e8f9f7 2601 __IO uint8_t tmpreg;
<> 144:ef7eb2e8f9f7 2602 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2603
<> 144:ef7eb2e8f9f7 2604 while((hspi->Instance->SR & Fifo) != State)
<> 144:ef7eb2e8f9f7 2605 {
<> 144:ef7eb2e8f9f7 2606 if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
<> 144:ef7eb2e8f9f7 2607 {
<> 144:ef7eb2e8f9f7 2608 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 2609 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2610 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2611 }
<> 144:ef7eb2e8f9f7 2612
<> 144:ef7eb2e8f9f7 2613 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2614 {
<> 144:ef7eb2e8f9f7 2615 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 2616 {
<> 144:ef7eb2e8f9f7 2617 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 2618 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 2619 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 2620
<> 144:ef7eb2e8f9f7 2621 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 2622 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2623
<> 144:ef7eb2e8f9f7 2624 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 2625 {
<> 144:ef7eb2e8f9f7 2626 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 2627 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 2628 }
<> 144:ef7eb2e8f9f7 2629
<> 144:ef7eb2e8f9f7 2630 /* Reset CRC Calculation */
<> 144:ef7eb2e8f9f7 2631 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2632 {
<> 144:ef7eb2e8f9f7 2633 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 2634 }
<> 144:ef7eb2e8f9f7 2635
<> 144:ef7eb2e8f9f7 2636 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2637
<> 144:ef7eb2e8f9f7 2638 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2639 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2640
<> 144:ef7eb2e8f9f7 2641 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2642 }
<> 144:ef7eb2e8f9f7 2643 }
<> 144:ef7eb2e8f9f7 2644 }
<> 144:ef7eb2e8f9f7 2645
<> 144:ef7eb2e8f9f7 2646 return HAL_OK;
<> 144:ef7eb2e8f9f7 2647 }
<> 144:ef7eb2e8f9f7 2648
<> 144:ef7eb2e8f9f7 2649 /**
<> 144:ef7eb2e8f9f7 2650 * @brief Handle the check of the RX transaction complete.
<> 144:ef7eb2e8f9f7 2651 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2652 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2653 * @param Timeout : Timeout duration
<> 144:ef7eb2e8f9f7 2654 * @retval None.
<> 144:ef7eb2e8f9f7 2655 */
<> 144:ef7eb2e8f9f7 2656 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2657 {
<> 144:ef7eb2e8f9f7 2658 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 2659 {
<> 144:ef7eb2e8f9f7 2660 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 2661 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 2662 }
<> 144:ef7eb2e8f9f7 2663
<> 144:ef7eb2e8f9f7 2664 /* Control the BSY flag */
<> 144:ef7eb2e8f9f7 2665 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 2666 {
<> 144:ef7eb2e8f9f7 2667 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2668 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2669 }
<> 144:ef7eb2e8f9f7 2670
<> 144:ef7eb2e8f9f7 2671 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 2672 {
<> 144:ef7eb2e8f9f7 2673 /* Empty the FRLVL fifo */
<> 144:ef7eb2e8f9f7 2674 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 2675 {
<> 144:ef7eb2e8f9f7 2676 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2677 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2678 }
<> 144:ef7eb2e8f9f7 2679 }
<> 144:ef7eb2e8f9f7 2680 return HAL_OK;
<> 144:ef7eb2e8f9f7 2681 }
<> 144:ef7eb2e8f9f7 2682
<> 144:ef7eb2e8f9f7 2683 /**
<> 144:ef7eb2e8f9f7 2684 * @brief Handle the check of the RXTX or TX transaction complete.
<> 144:ef7eb2e8f9f7 2685 * @param hspi: SPI handle
<> 144:ef7eb2e8f9f7 2686 * @param Timeout : Timeout duration
<> 144:ef7eb2e8f9f7 2687 */
<> 144:ef7eb2e8f9f7 2688 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2689 {
<> 144:ef7eb2e8f9f7 2690 /* Control if the TX fifo is empty */
<> 144:ef7eb2e8f9f7 2691 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 2692 {
<> 144:ef7eb2e8f9f7 2693 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2694 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2695 }
<> 144:ef7eb2e8f9f7 2696 /* Control the BSY flag */
<> 144:ef7eb2e8f9f7 2697 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 2698 {
<> 144:ef7eb2e8f9f7 2699 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2700 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2701 }
<> 144:ef7eb2e8f9f7 2702 return HAL_OK;
<> 144:ef7eb2e8f9f7 2703 }
<> 144:ef7eb2e8f9f7 2704
<> 144:ef7eb2e8f9f7 2705 /**
<> 144:ef7eb2e8f9f7 2706 * @brief Handle the end of the RXTX transaction.
<> 144:ef7eb2e8f9f7 2707 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2708 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2709 * @retval None
<> 144:ef7eb2e8f9f7 2710 */
<> 144:ef7eb2e8f9f7 2711 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2712 {
<> 144:ef7eb2e8f9f7 2713 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 2714 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 2715
<> 144:ef7eb2e8f9f7 2716 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 2717 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
<> 144:ef7eb2e8f9f7 2718 {
<> 144:ef7eb2e8f9f7 2719 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2720 }
<> 144:ef7eb2e8f9f7 2721
<> 144:ef7eb2e8f9f7 2722 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 2723 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 2724 {
<> 144:ef7eb2e8f9f7 2725 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2726 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 2727 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2728 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2729 }
<> 144:ef7eb2e8f9f7 2730 else
<> 144:ef7eb2e8f9f7 2731 {
<> 144:ef7eb2e8f9f7 2732 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2733 {
<> 144:ef7eb2e8f9f7 2734 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 2735 {
<> 144:ef7eb2e8f9f7 2736 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2737 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2738 }
<> 144:ef7eb2e8f9f7 2739 else
<> 144:ef7eb2e8f9f7 2740 {
<> 144:ef7eb2e8f9f7 2741 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2742 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2743 }
<> 144:ef7eb2e8f9f7 2744 }
<> 144:ef7eb2e8f9f7 2745 else
<> 144:ef7eb2e8f9f7 2746 {
<> 144:ef7eb2e8f9f7 2747 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2748 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2749 }
<> 144:ef7eb2e8f9f7 2750 }
<> 144:ef7eb2e8f9f7 2751 }
<> 144:ef7eb2e8f9f7 2752
<> 144:ef7eb2e8f9f7 2753 /**
<> 144:ef7eb2e8f9f7 2754 * @brief Handle the end of the RX transaction.
<> 144:ef7eb2e8f9f7 2755 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2756 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2757 * @retval None
<> 144:ef7eb2e8f9f7 2758 */
<> 144:ef7eb2e8f9f7 2759 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2760 {
<> 144:ef7eb2e8f9f7 2761 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 2762 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2763
<> 144:ef7eb2e8f9f7 2764 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 2765 if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
<> 144:ef7eb2e8f9f7 2766 {
<> 144:ef7eb2e8f9f7 2767 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2768 }
<> 144:ef7eb2e8f9f7 2769 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2770
<> 144:ef7eb2e8f9f7 2771 /* Check if CRC error occurred */
<> 144:ef7eb2e8f9f7 2772 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 2773 {
<> 144:ef7eb2e8f9f7 2774 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
<> 144:ef7eb2e8f9f7 2775 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2776 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2777 }
<> 144:ef7eb2e8f9f7 2778 else
<> 144:ef7eb2e8f9f7 2779 {
<> 144:ef7eb2e8f9f7 2780 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2781 {
<> 144:ef7eb2e8f9f7 2782 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2783 }
<> 144:ef7eb2e8f9f7 2784 else
<> 144:ef7eb2e8f9f7 2785 {
<> 144:ef7eb2e8f9f7 2786 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2787 }
<> 144:ef7eb2e8f9f7 2788 }
<> 144:ef7eb2e8f9f7 2789 }
<> 144:ef7eb2e8f9f7 2790
<> 144:ef7eb2e8f9f7 2791 /**
<> 144:ef7eb2e8f9f7 2792 * @brief Handle the end of the TX transaction.
<> 144:ef7eb2e8f9f7 2793 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2794 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2795 * @retval None
<> 144:ef7eb2e8f9f7 2796 */
<> 144:ef7eb2e8f9f7 2797 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2798 {
<> 144:ef7eb2e8f9f7 2799 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 2800 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 2801
<> 144:ef7eb2e8f9f7 2802 /* Check the end of the transaction */
<> 144:ef7eb2e8f9f7 2803 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
<> 144:ef7eb2e8f9f7 2804 {
<> 144:ef7eb2e8f9f7 2805 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2806 }
<> 144:ef7eb2e8f9f7 2807
<> 144:ef7eb2e8f9f7 2808 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 144:ef7eb2e8f9f7 2809 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 2810 {
<> 144:ef7eb2e8f9f7 2811 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2812 }
<> 144:ef7eb2e8f9f7 2813
<> 144:ef7eb2e8f9f7 2814 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2815 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2816 {
<> 144:ef7eb2e8f9f7 2817 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2818 }
<> 144:ef7eb2e8f9f7 2819 else
<> 144:ef7eb2e8f9f7 2820 {
<> 144:ef7eb2e8f9f7 2821 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2822 }
<> 144:ef7eb2e8f9f7 2823 }
<> 144:ef7eb2e8f9f7 2824
<> 144:ef7eb2e8f9f7 2825 /**
<> 144:ef7eb2e8f9f7 2826 * @}
<> 144:ef7eb2e8f9f7 2827 */
<> 144:ef7eb2e8f9f7 2828
<> 144:ef7eb2e8f9f7 2829 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2830
<> 144:ef7eb2e8f9f7 2831 /**
<> 144:ef7eb2e8f9f7 2832 * @}
<> 144:ef7eb2e8f9f7 2833 */
<> 144:ef7eb2e8f9f7 2834
<> 144:ef7eb2e8f9f7 2835 /**
<> 144:ef7eb2e8f9f7 2836 * @}
<> 144:ef7eb2e8f9f7 2837 */
<> 144:ef7eb2e8f9f7 2838
<> 144:ef7eb2e8f9f7 2839 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/