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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_irda.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief IRDA HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the IrDA (Infrared Data Association) Peripheral
<> 144:ef7eb2e8f9f7 10 * (IRDA)
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 The IRDA HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
<> 144:ef7eb2e8f9f7 24 (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
<> 144:ef7eb2e8f9f7 25 in setting the associated USART or UART in IRDA mode:
<> 144:ef7eb2e8f9f7 26 (++) Enable the USARTx/UARTx interface clock.
<> 144:ef7eb2e8f9f7 27 (++) USARTx/UARTx pins configuration:
<> 144:ef7eb2e8f9f7 28 (+++) Enable the clock for the USARTx/UARTx GPIOs.
<> 144:ef7eb2e8f9f7 29 (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
<> 144:ef7eb2e8f9f7 30 (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 31 and HAL_IRDA_Receive_IT() APIs):
<> 144:ef7eb2e8f9f7 32 (+++) Configure the USARTx/UARTx interrupt priority.
<> 144:ef7eb2e8f9f7 33 (+++) Enable the NVIC USARTx/UARTx IRQ handle.
<> 144:ef7eb2e8f9f7 34 (+++) The specific IRDA interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 35 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 36 __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 39 and HAL_IRDA_Receive_DMA() APIs):
<> 144:ef7eb2e8f9f7 40 (+++) Declare a DMA handle structure for the Tx/Rx channel.
<> 144:ef7eb2e8f9f7 41 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 42 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 43 (+++) Configure the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 44 (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 45 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
<> 144:ef7eb2e8f9f7 48 the normal or low power mode and the clock prescaler in the hirda handle Init structure.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
<> 144:ef7eb2e8f9f7 51 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 52 by calling the customized HAL_IRDA_MspInit() API.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 -@@- The specific IRDA interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 55 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 56 __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 61 =================================
<> 144:ef7eb2e8f9f7 62 [..]
<> 144:ef7eb2e8f9f7 63 (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 64 (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 67 ===================================
<> 144:ef7eb2e8f9f7 68 [..]
<> 144:ef7eb2e8f9f7 69 (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 70 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 72 (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 73 (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 74 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 75 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 76 add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 79 ==============================
<> 144:ef7eb2e8f9f7 80 [..]
<> 144:ef7eb2e8f9f7 81 (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 82 (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 83 add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 84 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 85 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 86 (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 87 (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 88 add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 89 (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 90 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 91 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 92 add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 *** IRDA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 95 ====================================
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 Below the list of most used macros in IRDA HAL driver.
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
<> 144:ef7eb2e8f9f7 100 (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
<> 144:ef7eb2e8f9f7 101 (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
<> 144:ef7eb2e8f9f7 102 (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
<> 144:ef7eb2e8f9f7 103 (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 104 (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 105 (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 [..]
<> 144:ef7eb2e8f9f7 108 (@) You can refer to the IRDA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 @endverbatim
<> 144:ef7eb2e8f9f7 111 ******************************************************************************
<> 144:ef7eb2e8f9f7 112 * @attention
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 115 *
<> 144:ef7eb2e8f9f7 116 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 117 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 118 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 119 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 120 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 121 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 122 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 123 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 124 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 125 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 126 *
<> 144:ef7eb2e8f9f7 127 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 128 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 129 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 130 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 131 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 132 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 133 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 134 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 135 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 136 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 137 *
<> 144:ef7eb2e8f9f7 138 ******************************************************************************
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @defgroup IRDA IRDA
<> 144:ef7eb2e8f9f7 151 * @brief HAL IRDA module driver
<> 144:ef7eb2e8f9f7 152 * @{
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 156:95d6b41a828b 155 #ifdef HAL_IRDA_MODULE_ENABLED
<> 156:95d6b41a828b 156
<> 144:ef7eb2e8f9f7 157 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /** @defgroup IRDA_Private_Constants IRDA Private Constants
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 156:95d6b41a828b 162 #define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
<> 144:ef7eb2e8f9f7 163 #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
<> 144:ef7eb2e8f9f7 164 | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
<> 144:ef7eb2e8f9f7 165 /**
<> 144:ef7eb2e8f9f7 166 * @}
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 170 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 171 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 172 /** @addtogroup IRDA_Private_Functions
<> 144:ef7eb2e8f9f7 173 * @{
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 176 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 177 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<> 156:95d6b41a828b 178 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 179 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 180 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 181 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 182 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 183 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 184 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 185 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 186 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 187 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 188 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 189 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 190 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 191 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 192 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @}
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 204 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 205 *
<> 144:ef7eb2e8f9f7 206 @verbatim
<> 144:ef7eb2e8f9f7 207 ==============================================================================
<> 144:ef7eb2e8f9f7 208 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 209 ==============================================================================
<> 144:ef7eb2e8f9f7 210 [..]
<> 144:ef7eb2e8f9f7 211 This subsection provides a set of functions allowing to initialize the USARTx
<> 144:ef7eb2e8f9f7 212 in asynchronous IRDA mode.
<> 144:ef7eb2e8f9f7 213 (+) For the asynchronous mode only these parameters can be configured:
<> 144:ef7eb2e8f9f7 214 (++) Baud Rate
<> 144:ef7eb2e8f9f7 215 (++) Word Length
<> 144:ef7eb2e8f9f7 216 (++) Parity
<> 144:ef7eb2e8f9f7 217 (++) Power mode
<> 144:ef7eb2e8f9f7 218 (++) Prescaler setting
<> 144:ef7eb2e8f9f7 219 (++) Receiver/transmitter modes
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 [..]
<> 144:ef7eb2e8f9f7 222 The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
<> 144:ef7eb2e8f9f7 223 (details for the procedures are available in reference manual).
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 @endverbatim
<> 144:ef7eb2e8f9f7 226 * @{
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /*
<> 144:ef7eb2e8f9f7 230 Additional Table: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 231 in the data register is transmitted but is changed by the parity bit.
<> 144:ef7eb2e8f9f7 232 According to device capability (support or not of 7-bit word length),
<> 144:ef7eb2e8f9f7 233 frame length is either defined by the M bit (8-bits or 9-bits)
<> 144:ef7eb2e8f9f7 234 or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
<> 144:ef7eb2e8f9f7 235 Possible IRDA frame formats are as listed in the following table:
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 Table 1. IRDA frame format.
<> 144:ef7eb2e8f9f7 238 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 239 | M bit | PCE bit | IRDA frame |
<> 144:ef7eb2e8f9f7 240 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 241 | 0 | 0 | | SB | 8-bit data | STB | |
<> 144:ef7eb2e8f9f7 242 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 243 | 0 | 1 | | SB | 7-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 244 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 245 | 1 | 0 | | SB | 9-bit data | STB | |
<> 144:ef7eb2e8f9f7 246 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 247 | 1 | 1 | | SB | 8-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 248 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 249 | M1 bit | M0 bit | PCE bit | IRDA frame |
<> 144:ef7eb2e8f9f7 250 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 251 | 0 | 0 | 0 | | SB | 8 bit data | STB | |
<> 144:ef7eb2e8f9f7 252 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 253 | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 254 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 255 | 0 | 1 | 0 | | SB | 9 bit data | STB | |
<> 144:ef7eb2e8f9f7 256 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 257 | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 258 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 259 | 1 | 0 | 0 | | SB | 7 bit data | STB | |
<> 144:ef7eb2e8f9f7 260 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 261 | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 262 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @brief Initialize the IRDA mode according to the specified
<> 144:ef7eb2e8f9f7 268 * parameters in the IRDA_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 269 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 270 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 271 * @retval HAL status
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 276 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* Check the USART/UART associated to the IRDA handle */
<> 144:ef7eb2e8f9f7 282 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 if(hirda->gState == HAL_IRDA_STATE_RESET)
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 287 hirda->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 290 HAL_IRDA_MspInit(hirda);
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Disable the Peripheral to update the configuration registers */
<> 144:ef7eb2e8f9f7 296 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Set the IRDA Communication parameters */
<> 144:ef7eb2e8f9f7 299 if (IRDA_SetConfig(hirda) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* In IRDA mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 305 - LINEN, STOP and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 306 - SCEN and HDSEL bits in the USART_CR3 register.*/
<> 156:95d6b41a828b 307 CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
<> 156:95d6b41a828b 308 CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* set the UART/USART in IRDA mode */
<> 144:ef7eb2e8f9f7 311 hirda->Instance->CR3 |= USART_CR3_IREN;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 314 __HAL_IRDA_ENABLE(hirda);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 317 return (IRDA_CheckIdleState(hirda));
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @brief DeInitialize the IRDA peripheral.
<> 144:ef7eb2e8f9f7 322 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 323 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 324 * @retval HAL status
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 329 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Check the USART/UART associated to the IRDA handle */
<> 144:ef7eb2e8f9f7 335 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 340 HAL_IRDA_MspDeInit(hirda);
<> 144:ef7eb2e8f9f7 341 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 342 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 343
<> 156:95d6b41a828b 344 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 156:95d6b41a828b 345 hirda->gState = HAL_IRDA_STATE_RESET;
<> 156:95d6b41a828b 346 hirda->RxState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Process Unlock */
<> 144:ef7eb2e8f9f7 349 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 return HAL_OK;
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @brief Initialize the IRDA MSP.
<> 144:ef7eb2e8f9f7 356 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 357 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 358 * @retval None
<> 144:ef7eb2e8f9f7 359 */
<> 156:95d6b41a828b 360 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 363 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 366 the HAL_IRDA_MspInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @brief DeInitialize the IRDA MSP.
<> 144:ef7eb2e8f9f7 372 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 373 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 374 * @retval None
<> 144:ef7eb2e8f9f7 375 */
<> 156:95d6b41a828b 376 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 379 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 382 the HAL_IRDA_MspDeInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @}
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 391 * @brief IRDA Transmit and Receive functions
<> 144:ef7eb2e8f9f7 392 *
<> 144:ef7eb2e8f9f7 393 @verbatim
<> 156:95d6b41a828b 394 ===============================================================================
<> 156:95d6b41a828b 395 ##### IO operation functions #####
<> 156:95d6b41a828b 396 ===============================================================================
<> 144:ef7eb2e8f9f7 397 [..]
<> 144:ef7eb2e8f9f7 398 This subsection provides a set of functions allowing to manage the IRDA data transfers.
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 [..]
<> 144:ef7eb2e8f9f7 401 IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
<> 144:ef7eb2e8f9f7 402 on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
<> 144:ef7eb2e8f9f7 403 is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
<> 144:ef7eb2e8f9f7 404 While receiving data, transmission should be avoided as the data to be transmitted
<> 144:ef7eb2e8f9f7 405 could be corrupted.
<> 144:ef7eb2e8f9f7 406
<> 156:95d6b41a828b 407 (#) There are two mode of transfer:
<> 144:ef7eb2e8f9f7 408 (++) Blocking mode: the communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 409 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 410 after finishing transfer.
<> 156:95d6b41a828b 411 (++) Non-Blocking mode: the communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 412 or DMA, these API's return the HAL status.
<> 144:ef7eb2e8f9f7 413 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 414 dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 415 using DMA mode.
<> 144:ef7eb2e8f9f7 416 The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 417 will be executed respectively at the end of the Transmit or Receive process
<> 144:ef7eb2e8f9f7 418 The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 (#) Blocking mode APIs are :
<> 144:ef7eb2e8f9f7 421 (++) HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 422 (++) HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 (#) Non Blocking mode APIs with Interrupt are :
<> 144:ef7eb2e8f9f7 425 (++) HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 426 (++) HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 427 (++) HAL_IRDA_IRQHandler()
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 (#) Non Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 430 (++) HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 431 (++) HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 432 (++) HAL_IRDA_DMAPause()
<> 144:ef7eb2e8f9f7 433 (++) HAL_IRDA_DMAResume()
<> 144:ef7eb2e8f9f7 434 (++) HAL_IRDA_DMAStop()
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
<> 144:ef7eb2e8f9f7 437 (++) HAL_IRDA_TxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 438 (++) HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 439 (++) HAL_IRDA_RxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 440 (++) HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 441 (++) HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 442
<> 156:95d6b41a828b 443 (#) Non-Blocking mode transfers could be aborted using Abort API's :
<> 156:95d6b41a828b 444 (++) HAL_IRDA_Abort()
<> 156:95d6b41a828b 445 (++) HAL_IRDA_AbortTransmit()
<> 156:95d6b41a828b 446 (++) HAL_IRDA_AbortReceive()
<> 156:95d6b41a828b 447 (++) HAL_IRDA_Abort_IT()
<> 156:95d6b41a828b 448 (++) HAL_IRDA_AbortTransmit_IT()
<> 156:95d6b41a828b 449 (++) HAL_IRDA_AbortReceive_IT()
<> 156:95d6b41a828b 450
<> 156:95d6b41a828b 451 (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
<> 156:95d6b41a828b 452 (++) HAL_IRDA_AbortCpltCallback()
<> 156:95d6b41a828b 453 (++) HAL_IRDA_AbortTransmitCpltCallback()
<> 156:95d6b41a828b 454 (++) HAL_IRDA_AbortReceiveCpltCallback()
<> 156:95d6b41a828b 455
<> 156:95d6b41a828b 456 (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
<> 156:95d6b41a828b 457 Errors are handled as follows :
<> 156:95d6b41a828b 458 (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
<> 156:95d6b41a828b 459 to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
<> 156:95d6b41a828b 460 Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
<> 156:95d6b41a828b 461 and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
<> 156:95d6b41a828b 462 If user wants to abort it, Abort services should be called by user.
<> 156:95d6b41a828b 463 (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
<> 156:95d6b41a828b 464 This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
<> 156:95d6b41a828b 465 Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
<> 156:95d6b41a828b 466
<> 144:ef7eb2e8f9f7 467 @endverbatim
<> 144:ef7eb2e8f9f7 468 * @{
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /**
<> 156:95d6b41a828b 472 * @brief Send an amount of data in blocking mode.
<> 156:95d6b41a828b 473 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 474 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 475 * @param pData Pointer to data buffer.
<> 156:95d6b41a828b 476 * @param Size Amount of data to be sent.
<> 156:95d6b41a828b 477 * @param Timeout Specify timeout value.
<> 144:ef7eb2e8f9f7 478 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 479 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 480 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 481 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 482 * @retval HAL status
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 uint16_t* tmp;
<> 156:95d6b41a828b 487 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 490 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 491 {
<> 156:95d6b41a828b 492 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 498 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 499 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 500 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 501 {
<> 156:95d6b41a828b 502 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Process Locked */
<> 144:ef7eb2e8f9f7 509 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 156:95d6b41a828b 512 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 513
<> 156:95d6b41a828b 514 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 515 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 518 hirda->TxXferCount = Size;
<> 156:95d6b41a828b 519 while(hirda->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 522
<> 156:95d6b41a828b 523 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 tmp = (uint16_t*) pData;
<> 156:95d6b41a828b 530 hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 156:95d6b41a828b 531 pData += 2;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533 else
<> 144:ef7eb2e8f9f7 534 {
<> 156:95d6b41a828b 535 hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538
<> 156:95d6b41a828b 539 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* At end of Tx process, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 545 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 548 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 return HAL_OK;
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552 else
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /**
<> 156:95d6b41a828b 559 * @brief Receive an amount of data in blocking mode.
<> 156:95d6b41a828b 560 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 561 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 562 * @param pData Pointer to data buffer.
<> 156:95d6b41a828b 563 * @param Size Amount of data to be received.
<> 156:95d6b41a828b 564 * @param Timeout Specify timeout value.
<> 144:ef7eb2e8f9f7 565 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 566 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 567 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 568 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 569 * @retval HAL status
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 574 uint16_t uhMask;
<> 156:95d6b41a828b 575 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 578 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 579 {
<> 156:95d6b41a828b 580 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 586 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 587 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 588 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 589 {
<> 156:95d6b41a828b 590 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Process Locked */
<> 144:ef7eb2e8f9f7 597 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 156:95d6b41a828b 600 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 601
<> 156:95d6b41a828b 602 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 603 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 606 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 607
<> 156:95d6b41a828b 608 /* Computation of the mask to apply to RDR register
<> 144:ef7eb2e8f9f7 609 of the UART associated to the IRDA */
<> 144:ef7eb2e8f9f7 610 IRDA_MASK_COMPUTATION(hirda);
<> 144:ef7eb2e8f9f7 611 uhMask = hirda->Mask;
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /* Check data remaining to be received */
<> 156:95d6b41a828b 614 while(hirda->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 hirda->RxXferCount--;
<> 144:ef7eb2e8f9f7 617
<> 156:95d6b41a828b 618 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 tmp = (uint16_t*) pData ;
<> 144:ef7eb2e8f9f7 625 *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
<> 144:ef7eb2e8f9f7 626 pData +=2;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628 else
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 635 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 638 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 return HAL_OK;
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642 else
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /**
<> 156:95d6b41a828b 649 * @brief Send an amount of data in interrupt mode.
<> 156:95d6b41a828b 650 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 651 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 652 * @param pData Pointer to data buffer.
<> 156:95d6b41a828b 653 * @param Size Amount of data to be sent.
<> 144:ef7eb2e8f9f7 654 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 655 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 656 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 657 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 658 * @retval HAL status
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 663 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 664 {
<> 156:95d6b41a828b 665 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 671 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 672 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 673 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 674 {
<> 156:95d6b41a828b 675 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 676 {
<> 144:ef7eb2e8f9f7 677 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 678 }
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Process Locked */
<> 144:ef7eb2e8f9f7 682 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 685 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 686 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 689 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 692 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Enable the IRDA Transmit Data Register Empty Interrupt */
<> 156:95d6b41a828b 695 SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 return HAL_OK;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699 else
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 156:95d6b41a828b 706 * @brief Receive an amount of data in interrupt mode.
<> 156:95d6b41a828b 707 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 708 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 709 * @param pData Pointer to data buffer.
<> 156:95d6b41a828b 710 * @param Size Amount of data to be received.
<> 144:ef7eb2e8f9f7 711 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 712 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 713 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 714 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 715 * @retval HAL status
<> 144:ef7eb2e8f9f7 716 */
<> 144:ef7eb2e8f9f7 717 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 720 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 721 {
<> 156:95d6b41a828b 722 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 723 {
<> 144:ef7eb2e8f9f7 724 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 728 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 729 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 730 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 731 {
<> 156:95d6b41a828b 732 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Process Locked */
<> 156:95d6b41a828b 739 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 742 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 743 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Computation of the mask to apply to the RDR register
<> 144:ef7eb2e8f9f7 746 of the UART associated to the IRDA */
<> 144:ef7eb2e8f9f7 747 IRDA_MASK_COMPUTATION(hirda);
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 750 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 753 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 754
<> 156:95d6b41a828b 755 /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
<> 156:95d6b41a828b 756 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 759 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 return HAL_OK;
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763 else
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 766 }
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 156:95d6b41a828b 770 * @brief Send an amount of data in DMA mode.
<> 156:95d6b41a828b 771 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 772 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 773 * @param pData pointer to data buffer.
<> 156:95d6b41a828b 774 * @param Size amount of data to be sent.
<> 144:ef7eb2e8f9f7 775 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 776 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 777 * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 778 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 779 * @retval HAL status
<> 144:ef7eb2e8f9f7 780 */
<> 144:ef7eb2e8f9f7 781 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 784 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 785 {
<> 156:95d6b41a828b 786 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 792 should be aligned on a u16 frontier, as data copy into TDR will be
<> 144:ef7eb2e8f9f7 793 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 794 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 795 {
<> 156:95d6b41a828b 796 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Process Locked */
<> 144:ef7eb2e8f9f7 803 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 806 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 807 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 810 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 813 hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 816 hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 819 hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 820
<> 156:95d6b41a828b 821 /* Set the DMA abort callback */
<> 156:95d6b41a828b 822 hirda->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 823
<> 144:ef7eb2e8f9f7 824 /* Enable the IRDA transmit DMA channel */
<> 156:95d6b41a828b 825 HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /* Clear the TC flag in the ICR register */
<> 144:ef7eb2e8f9f7 828 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
<> 144:ef7eb2e8f9f7 829
<> 156:95d6b41a828b 830 /* Process Unlocked */
<> 156:95d6b41a828b 831 __HAL_UNLOCK(hirda);
<> 156:95d6b41a828b 832
<> 144:ef7eb2e8f9f7 833 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 834 in the USART CR3 register */
<> 156:95d6b41a828b 835 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 return HAL_OK;
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 else
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /**
<> 156:95d6b41a828b 846 * @brief Receive an amount of data in DMA mode.
<> 156:95d6b41a828b 847 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 848 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 849 * @param pData Pointer to data buffer.
<> 156:95d6b41a828b 850 * @param Size Amount of data to be received.
<> 144:ef7eb2e8f9f7 851 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 852 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 853 * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 854 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 855 * @retval HAL status
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 858 {
<> 144:ef7eb2e8f9f7 859 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 860 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 861 {
<> 156:95d6b41a828b 862 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 865 }
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 868 should be aligned on a u16 frontier, as data copy from RDR will be
<> 144:ef7eb2e8f9f7 869 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 870 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 871 {
<> 156:95d6b41a828b 872 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /* Process Locked */
<> 144:ef7eb2e8f9f7 879 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 882 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 885 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 888 hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 891 hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 894 hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 895
<> 156:95d6b41a828b 896 /* Set the DMA abort callback */
<> 156:95d6b41a828b 897 hirda->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 898
<> 144:ef7eb2e8f9f7 899 /* Enable the DMA channel */
<> 156:95d6b41a828b 900 HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
<> 156:95d6b41a828b 901
<> 156:95d6b41a828b 902 /* Process Unlocked */
<> 156:95d6b41a828b 903 __HAL_UNLOCK(hirda);
<> 156:95d6b41a828b 904
<> 156:95d6b41a828b 905 /* Enable the UART Parity Error Interrupt */
<> 156:95d6b41a828b 906 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 907
<> 156:95d6b41a828b 908 /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 909 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 912 in the USART CR3 register */
<> 156:95d6b41a828b 913 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 return HAL_OK;
<> 144:ef7eb2e8f9f7 916 }
<> 144:ef7eb2e8f9f7 917 else
<> 144:ef7eb2e8f9f7 918 {
<> 144:ef7eb2e8f9f7 919 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921 }
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /**
<> 156:95d6b41a828b 925 * @brief Pause the DMA Transfer.
<> 156:95d6b41a828b 926 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 927 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 928 * @retval HAL status
<> 144:ef7eb2e8f9f7 929 */
<> 144:ef7eb2e8f9f7 930 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 /* Process Locked */
<> 144:ef7eb2e8f9f7 933 __HAL_LOCK(hirda);
<> 156:95d6b41a828b 934
<> 156:95d6b41a828b 935 if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
<> 156:95d6b41a828b 936 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
<> 144:ef7eb2e8f9f7 937 {
<> 144:ef7eb2e8f9f7 938 /* Disable the IRDA DMA Tx request */
<> 144:ef7eb2e8f9f7 939 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 940 }
<> 156:95d6b41a828b 941 if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
<> 156:95d6b41a828b 942 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<> 144:ef7eb2e8f9f7 943 {
<> 156:95d6b41a828b 944 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 945 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 946 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 947
<> 144:ef7eb2e8f9f7 948 /* Disable the IRDA DMA Rx request */
<> 144:ef7eb2e8f9f7 949 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 953 __HAL_UNLOCK(hirda);
<> 156:95d6b41a828b 954
<> 156:95d6b41a828b 955 return HAL_OK;
<> 144:ef7eb2e8f9f7 956 }
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /**
<> 156:95d6b41a828b 959 * @brief Resume the DMA Transfer.
<> 156:95d6b41a828b 960 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 961 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 962 * @retval HAL status
<> 144:ef7eb2e8f9f7 963 */
<> 144:ef7eb2e8f9f7 964 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 /* Process Locked */
<> 144:ef7eb2e8f9f7 967 __HAL_LOCK(hirda);
<> 156:95d6b41a828b 968
<> 144:ef7eb2e8f9f7 969 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 /* Enable the IRDA DMA Tx request */
<> 144:ef7eb2e8f9f7 972 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 /* Clear the Overrun flag before resuming the Rx transfer*/
<> 144:ef7eb2e8f9f7 977 __HAL_IRDA_CLEAR_OREFLAG(hirda);
<> 156:95d6b41a828b 978
<> 156:95d6b41a828b 979 /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 980 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 981 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 982
<> 144:ef7eb2e8f9f7 983 /* Enable the IRDA DMA Rx request */
<> 144:ef7eb2e8f9f7 984 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 985 }
<> 156:95d6b41a828b 986
<> 144:ef7eb2e8f9f7 987 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 988 __HAL_UNLOCK(hirda);
<> 156:95d6b41a828b 989
<> 144:ef7eb2e8f9f7 990 return HAL_OK;
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /**
<> 156:95d6b41a828b 994 * @brief Stop the DMA Transfer.
<> 156:95d6b41a828b 995 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 996 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 997 * @retval HAL status
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 1002 to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
<> 156:95d6b41a828b 1003 HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
<> 156:95d6b41a828b 1004 indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
<> 156:95d6b41a828b 1005 interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
<> 156:95d6b41a828b 1006 the stream and the corresponding call back is executed. */
<> 156:95d6b41a828b 1007
<> 156:95d6b41a828b 1008 /* Stop IRDA DMA Tx request if ongoing */
<> 156:95d6b41a828b 1009 if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
<> 156:95d6b41a828b 1010 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
<> 156:95d6b41a828b 1011 {
<> 156:95d6b41a828b 1012 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1013
<> 156:95d6b41a828b 1014 /* Abort the IRDA DMA Tx channel */
<> 156:95d6b41a828b 1015 if(hirda->hdmatx != NULL)
<> 156:95d6b41a828b 1016 {
<> 156:95d6b41a828b 1017 HAL_DMA_Abort(hirda->hdmatx);
<> 156:95d6b41a828b 1018 }
<> 156:95d6b41a828b 1019
<> 156:95d6b41a828b 1020 IRDA_EndTxTransfer(hirda);
<> 156:95d6b41a828b 1021 }
<> 156:95d6b41a828b 1022
<> 156:95d6b41a828b 1023 /* Stop IRDA DMA Rx request if ongoing */
<> 156:95d6b41a828b 1024 if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
<> 156:95d6b41a828b 1025 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<> 156:95d6b41a828b 1026 {
<> 156:95d6b41a828b 1027 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1028
<> 156:95d6b41a828b 1029 /* Abort the IRDA DMA Rx channel */
<> 156:95d6b41a828b 1030 if(hirda->hdmarx != NULL)
<> 156:95d6b41a828b 1031 {
<> 156:95d6b41a828b 1032 HAL_DMA_Abort(hirda->hdmarx);
<> 156:95d6b41a828b 1033 }
<> 156:95d6b41a828b 1034
<> 156:95d6b41a828b 1035 IRDA_EndRxTransfer(hirda);
<> 156:95d6b41a828b 1036 }
<> 156:95d6b41a828b 1037
<> 156:95d6b41a828b 1038 return HAL_OK;
<> 156:95d6b41a828b 1039 }
<> 156:95d6b41a828b 1040
<> 156:95d6b41a828b 1041 /**
<> 156:95d6b41a828b 1042 * @brief Abort ongoing transfers (blocking mode).
<> 156:95d6b41a828b 1043 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1044 * the configuration information for the specified UART module.
<> 156:95d6b41a828b 1045 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1046 * This procedure performs following operations :
<> 156:95d6b41a828b 1047 * - Disable IRDA Interrupts (Tx and Rx)
<> 156:95d6b41a828b 1048 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1049 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1050 * - Set handle State to READY
<> 156:95d6b41a828b 1051 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1052 * @retval HAL status
<> 156:95d6b41a828b 1053 */
<> 156:95d6b41a828b 1054 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1055 {
<> 156:95d6b41a828b 1056 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1057 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1058 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1059
<> 156:95d6b41a828b 1060 /* Disable the IRDA DMA Tx request if enabled */
<> 156:95d6b41a828b 1061 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1062 {
<> 156:95d6b41a828b 1063 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1064
<> 156:95d6b41a828b 1065 /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1066 if(hirda->hdmatx != NULL)
<> 156:95d6b41a828b 1067 {
<> 156:95d6b41a828b 1068 /* Set the IRDA DMA Abort callback to Null.
<> 156:95d6b41a828b 1069 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1070 hirda->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1071
<> 156:95d6b41a828b 1072 HAL_DMA_Abort(hirda->hdmatx);
<> 156:95d6b41a828b 1073 }
<> 156:95d6b41a828b 1074 }
<> 156:95d6b41a828b 1075
<> 156:95d6b41a828b 1076 /* Disable the IRDA DMA Rx request if enabled */
<> 156:95d6b41a828b 1077 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1078 {
<> 156:95d6b41a828b 1079 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1080
<> 156:95d6b41a828b 1081 /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1082 if(hirda->hdmarx != NULL)
<> 156:95d6b41a828b 1083 {
<> 156:95d6b41a828b 1084 /* Set the IRDA DMA Abort callback to Null.
<> 156:95d6b41a828b 1085 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1086 hirda->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1087
<> 156:95d6b41a828b 1088 HAL_DMA_Abort(hirda->hdmarx);
<> 156:95d6b41a828b 1089 }
<> 156:95d6b41a828b 1090 }
<> 156:95d6b41a828b 1091
<> 156:95d6b41a828b 1092 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 1093 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 1094 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 1095
<> 156:95d6b41a828b 1096 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1097 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
<> 144:ef7eb2e8f9f7 1098
<> 156:95d6b41a828b 1099 /* Restore hirda->gState and hirda->RxState to Ready */
<> 156:95d6b41a828b 1100 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1101 hirda->RxState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1102
<> 156:95d6b41a828b 1103 /* Reset Handle ErrorCode to No Error */
<> 156:95d6b41a828b 1104 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 156:95d6b41a828b 1105
<> 156:95d6b41a828b 1106 return HAL_OK;
<> 156:95d6b41a828b 1107 }
<> 156:95d6b41a828b 1108
<> 156:95d6b41a828b 1109 /**
<> 156:95d6b41a828b 1110 * @brief Abort ongoing Transmit transfer (blocking mode).
<> 156:95d6b41a828b 1111 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1112 * the configuration information for the specified UART module.
<> 156:95d6b41a828b 1113 * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1114 * This procedure performs following operations :
<> 156:95d6b41a828b 1115 * - Disable IRDA Interrupts (Tx)
<> 156:95d6b41a828b 1116 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1117 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1118 * - Set handle State to READY
<> 156:95d6b41a828b 1119 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1120 * @retval HAL status
<> 156:95d6b41a828b 1121 */
<> 156:95d6b41a828b 1122 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1123 {
<> 156:95d6b41a828b 1124 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 1125 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1126
<> 156:95d6b41a828b 1127 /* Disable the IRDA DMA Tx request if enabled */
<> 156:95d6b41a828b 1128 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<> 144:ef7eb2e8f9f7 1129 {
<> 156:95d6b41a828b 1130 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1131
<> 156:95d6b41a828b 1132 /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1133 if(hirda->hdmatx != NULL)
<> 156:95d6b41a828b 1134 {
<> 156:95d6b41a828b 1135 /* Set the IRDA DMA Abort callback to Null.
<> 156:95d6b41a828b 1136 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1137 hirda->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1138
<> 156:95d6b41a828b 1139 HAL_DMA_Abort(hirda->hdmatx);
<> 156:95d6b41a828b 1140 }
<> 144:ef7eb2e8f9f7 1141 }
<> 156:95d6b41a828b 1142
<> 156:95d6b41a828b 1143 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1144 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 1145
<> 156:95d6b41a828b 1146 /* Restore hirda->gState to Ready */
<> 156:95d6b41a828b 1147 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1148
<> 156:95d6b41a828b 1149 return HAL_OK;
<> 156:95d6b41a828b 1150 }
<> 156:95d6b41a828b 1151
<> 156:95d6b41a828b 1152 /**
<> 156:95d6b41a828b 1153 * @brief Abort ongoing Receive transfer (blocking mode).
<> 156:95d6b41a828b 1154 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1155 * the configuration information for the specified UART module.
<> 156:95d6b41a828b 1156 * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1157 * This procedure performs following operations :
<> 156:95d6b41a828b 1158 * - Disable IRDA Interrupts (Rx)
<> 156:95d6b41a828b 1159 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1160 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1161 * - Set handle State to READY
<> 156:95d6b41a828b 1162 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1163 * @retval HAL status
<> 156:95d6b41a828b 1164 */
<> 156:95d6b41a828b 1165 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1166 {
<> 156:95d6b41a828b 1167 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1168 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 1169 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1170
<> 156:95d6b41a828b 1171 /* Disable the IRDA DMA Rx request if enabled */
<> 156:95d6b41a828b 1172 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 144:ef7eb2e8f9f7 1173 {
<> 156:95d6b41a828b 1174 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1175
<> 156:95d6b41a828b 1176 /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1177 if(hirda->hdmarx != NULL)
<> 156:95d6b41a828b 1178 {
<> 156:95d6b41a828b 1179 /* Set the IRDA DMA Abort callback to Null.
<> 156:95d6b41a828b 1180 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1181 hirda->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1182
<> 156:95d6b41a828b 1183 HAL_DMA_Abort(hirda->hdmarx);
<> 156:95d6b41a828b 1184 }
<> 144:ef7eb2e8f9f7 1185 }
<> 156:95d6b41a828b 1186
<> 156:95d6b41a828b 1187 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1188 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 1189
<> 156:95d6b41a828b 1190 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1191 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
<> 156:95d6b41a828b 1192
<> 156:95d6b41a828b 1193 /* Restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1194 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 return HAL_OK;
<> 144:ef7eb2e8f9f7 1197 }
<> 144:ef7eb2e8f9f7 1198
<> 156:95d6b41a828b 1199 /**
<> 156:95d6b41a828b 1200 * @brief Abort ongoing transfers (Interrupt mode).
<> 156:95d6b41a828b 1201 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1202 * the configuration information for the specified UART module.
<> 156:95d6b41a828b 1203 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1204 * This procedure performs following operations :
<> 156:95d6b41a828b 1205 * - Disable IRDA Interrupts (Tx and Rx)
<> 156:95d6b41a828b 1206 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1207 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1208 * - Set handle State to READY
<> 156:95d6b41a828b 1209 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1210 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1211 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1212 * @retval HAL status
<> 156:95d6b41a828b 1213 */
<> 156:95d6b41a828b 1214 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1215 {
<> 156:95d6b41a828b 1216 uint32_t abortcplt = 1U;
<> 156:95d6b41a828b 1217
<> 156:95d6b41a828b 1218 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1219 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1220 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1221
<> 156:95d6b41a828b 1222 /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
<> 156:95d6b41a828b 1223 before any call to DMA Abort functions */
<> 156:95d6b41a828b 1224 /* DMA Tx Handle is valid */
<> 156:95d6b41a828b 1225 if(hirda->hdmatx != NULL)
<> 156:95d6b41a828b 1226 {
<> 156:95d6b41a828b 1227 /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
<> 156:95d6b41a828b 1228 Otherwise, set it to NULL */
<> 156:95d6b41a828b 1229 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1230 {
<> 156:95d6b41a828b 1231 hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
<> 156:95d6b41a828b 1232 }
<> 156:95d6b41a828b 1233 else
<> 156:95d6b41a828b 1234 {
<> 156:95d6b41a828b 1235 hirda->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1236 }
<> 156:95d6b41a828b 1237 }
<> 156:95d6b41a828b 1238 /* DMA Rx Handle is valid */
<> 156:95d6b41a828b 1239 if(hirda->hdmarx != NULL)
<> 156:95d6b41a828b 1240 {
<> 156:95d6b41a828b 1241 /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
<> 156:95d6b41a828b 1242 Otherwise, set it to NULL */
<> 156:95d6b41a828b 1243 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1244 {
<> 156:95d6b41a828b 1245 hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
<> 156:95d6b41a828b 1246 }
<> 156:95d6b41a828b 1247 else
<> 156:95d6b41a828b 1248 {
<> 156:95d6b41a828b 1249 hirda->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1250 }
<> 156:95d6b41a828b 1251 }
<> 156:95d6b41a828b 1252
<> 156:95d6b41a828b 1253 /* Disable the IRDA DMA Tx request if enabled */
<> 156:95d6b41a828b 1254 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1255 {
<> 156:95d6b41a828b 1256 /* Disable DMA Tx at UART level */
<> 156:95d6b41a828b 1257 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1258
<> 156:95d6b41a828b 1259 /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1260 if(hirda->hdmatx != NULL)
<> 156:95d6b41a828b 1261 {
<> 156:95d6b41a828b 1262 /* IRDA Tx DMA Abort callback has already been initialised :
<> 156:95d6b41a828b 1263 will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1264
<> 156:95d6b41a828b 1265 /* Abort DMA TX */
<> 156:95d6b41a828b 1266 if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 1267 {
<> 156:95d6b41a828b 1268 hirda->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1269 }
<> 156:95d6b41a828b 1270 else
<> 156:95d6b41a828b 1271 {
<> 156:95d6b41a828b 1272 abortcplt = 0U;
<> 156:95d6b41a828b 1273 }
<> 156:95d6b41a828b 1274 }
<> 156:95d6b41a828b 1275 }
<> 156:95d6b41a828b 1276
<> 156:95d6b41a828b 1277 /* Disable the IRDA DMA Rx request if enabled */
<> 156:95d6b41a828b 1278 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1279 {
<> 156:95d6b41a828b 1280 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1281
<> 156:95d6b41a828b 1282 /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1283 if(hirda->hdmarx != NULL)
<> 156:95d6b41a828b 1284 {
<> 156:95d6b41a828b 1285 /* IRDA Rx DMA Abort callback has already been initialised :
<> 156:95d6b41a828b 1286 will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1287
<> 156:95d6b41a828b 1288 /* Abort DMA RX */
<> 156:95d6b41a828b 1289 if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1290 {
<> 156:95d6b41a828b 1291 hirda->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1292 abortcplt = 1;
<> 156:95d6b41a828b 1293 }
<> 156:95d6b41a828b 1294 else
<> 156:95d6b41a828b 1295 {
<> 156:95d6b41a828b 1296 abortcplt = 0;
<> 156:95d6b41a828b 1297 }
<> 156:95d6b41a828b 1298 }
<> 156:95d6b41a828b 1299 }
<> 156:95d6b41a828b 1300
<> 156:95d6b41a828b 1301 /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
<> 156:95d6b41a828b 1302 if (abortcplt == 1U)
<> 156:95d6b41a828b 1303 {
<> 156:95d6b41a828b 1304 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 1305 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 1306 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 1307
<> 156:95d6b41a828b 1308 /* Reset errorCode */
<> 156:95d6b41a828b 1309 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 156:95d6b41a828b 1310
<> 156:95d6b41a828b 1311 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1312 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
<> 156:95d6b41a828b 1313
<> 156:95d6b41a828b 1314 /* Restore hirda->gState and hirda->RxState to Ready */
<> 156:95d6b41a828b 1315 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1316 hirda->RxState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1317
<> 156:95d6b41a828b 1318 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1319 HAL_IRDA_AbortCpltCallback(hirda);
<> 156:95d6b41a828b 1320 }
<> 156:95d6b41a828b 1321
<> 156:95d6b41a828b 1322 return HAL_OK;
<> 156:95d6b41a828b 1323 }
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /**
<> 156:95d6b41a828b 1326 * @brief Abort ongoing Transmit transfer (Interrupt mode).
<> 156:95d6b41a828b 1327 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1328 * the configuration information for the specified UART module.
<> 156:95d6b41a828b 1329 * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1330 * This procedure performs following operations :
<> 156:95d6b41a828b 1331 * - Disable IRDA Interrupts (Tx)
<> 156:95d6b41a828b 1332 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1333 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1334 * - Set handle State to READY
<> 156:95d6b41a828b 1335 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1336 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1337 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1338 * @retval HAL status
<> 156:95d6b41a828b 1339 */
<> 156:95d6b41a828b 1340 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1341 {
<> 156:95d6b41a828b 1342 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 1343 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1344
<> 156:95d6b41a828b 1345 /* Disable the IRDA DMA Tx request if enabled */
<> 156:95d6b41a828b 1346 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1347 {
<> 156:95d6b41a828b 1348 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1349
<> 156:95d6b41a828b 1350 /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1351 if(hirda->hdmatx != NULL)
<> 156:95d6b41a828b 1352 {
<> 156:95d6b41a828b 1353 /* Set the IRDA DMA Abort callback :
<> 156:95d6b41a828b 1354 will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1355 hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
<> 156:95d6b41a828b 1356
<> 156:95d6b41a828b 1357 /* Abort DMA TX */
<> 156:95d6b41a828b 1358 if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 1359 {
<> 156:95d6b41a828b 1360 /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1361 hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
<> 156:95d6b41a828b 1362 }
<> 156:95d6b41a828b 1363 }
<> 156:95d6b41a828b 1364 else
<> 156:95d6b41a828b 1365 {
<> 156:95d6b41a828b 1366 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1367 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 1368
<> 156:95d6b41a828b 1369 /* Restore hirda->gState to Ready */
<> 156:95d6b41a828b 1370 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1371
<> 156:95d6b41a828b 1372 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1373 HAL_IRDA_AbortTransmitCpltCallback(hirda);
<> 156:95d6b41a828b 1374 }
<> 156:95d6b41a828b 1375 }
<> 156:95d6b41a828b 1376 else
<> 156:95d6b41a828b 1377 {
<> 156:95d6b41a828b 1378 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1379 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 1380
<> 156:95d6b41a828b 1381 /* Restore hirda->gState to Ready */
<> 156:95d6b41a828b 1382 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1383
<> 156:95d6b41a828b 1384 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1385 HAL_IRDA_AbortTransmitCpltCallback(hirda);
<> 156:95d6b41a828b 1386 }
<> 156:95d6b41a828b 1387
<> 156:95d6b41a828b 1388 return HAL_OK;
<> 156:95d6b41a828b 1389 }
<> 156:95d6b41a828b 1390
<> 156:95d6b41a828b 1391 /**
<> 156:95d6b41a828b 1392 * @brief Abort ongoing Receive transfer (Interrupt mode).
<> 156:95d6b41a828b 1393 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1394 * the configuration information for the specified UART module.
<> 156:95d6b41a828b 1395 * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1396 * This procedure performs following operations :
<> 156:95d6b41a828b 1397 * - Disable IRDA Interrupts (Rx)
<> 156:95d6b41a828b 1398 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1399 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1400 * - Set handle State to READY
<> 156:95d6b41a828b 1401 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1402 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1403 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1404 * @retval HAL status
<> 156:95d6b41a828b 1405 */
<> 156:95d6b41a828b 1406 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1407 {
<> 156:95d6b41a828b 1408 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1409 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 1410 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1411
<> 156:95d6b41a828b 1412 /* Disable the IRDA DMA Rx request if enabled */
<> 156:95d6b41a828b 1413 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1414 {
<> 156:95d6b41a828b 1415 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1416
<> 156:95d6b41a828b 1417 /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1418 if(hirda->hdmarx != NULL)
<> 156:95d6b41a828b 1419 {
<> 156:95d6b41a828b 1420 /* Set the IRDA DMA Abort callback :
<> 156:95d6b41a828b 1421 will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1422 hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
<> 156:95d6b41a828b 1423
<> 156:95d6b41a828b 1424 /* Abort DMA RX */
<> 156:95d6b41a828b 1425 if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1426 {
<> 156:95d6b41a828b 1427 /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1428 hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
<> 156:95d6b41a828b 1429 }
<> 156:95d6b41a828b 1430 }
<> 156:95d6b41a828b 1431 else
<> 156:95d6b41a828b 1432 {
<> 156:95d6b41a828b 1433 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1434 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 1435
<> 156:95d6b41a828b 1436 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1437 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
<> 156:95d6b41a828b 1438
<> 156:95d6b41a828b 1439 /* Restore hirda->RxState to Ready */
<> 156:95d6b41a828b 1440 hirda->RxState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1441
<> 156:95d6b41a828b 1442 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1443 HAL_IRDA_AbortReceiveCpltCallback(hirda);
<> 156:95d6b41a828b 1444 }
<> 156:95d6b41a828b 1445 }
<> 156:95d6b41a828b 1446 else
<> 156:95d6b41a828b 1447 {
<> 156:95d6b41a828b 1448 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1449 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 1450
<> 156:95d6b41a828b 1451 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1452 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
<> 156:95d6b41a828b 1453
<> 156:95d6b41a828b 1454 /* Restore hirda->RxState to Ready */
<> 156:95d6b41a828b 1455 hirda->RxState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1456
<> 156:95d6b41a828b 1457 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1458 HAL_IRDA_AbortReceiveCpltCallback(hirda);
<> 156:95d6b41a828b 1459 }
<> 156:95d6b41a828b 1460
<> 156:95d6b41a828b 1461 return HAL_OK;
<> 156:95d6b41a828b 1462 }
<> 156:95d6b41a828b 1463
<> 156:95d6b41a828b 1464 /**
<> 156:95d6b41a828b 1465 * @brief Handle IRDA interrupt request.
<> 156:95d6b41a828b 1466 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1467 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1468 * @retval None
<> 144:ef7eb2e8f9f7 1469 */
<> 144:ef7eb2e8f9f7 1470 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1471 {
<> 156:95d6b41a828b 1472 uint32_t isrflags = READ_REG(hirda->Instance->ISR);
<> 156:95d6b41a828b 1473 uint32_t cr1its = READ_REG(hirda->Instance->CR1);
<> 156:95d6b41a828b 1474 uint32_t cr3its;
<> 156:95d6b41a828b 1475 uint32_t errorflags;
<> 144:ef7eb2e8f9f7 1476
<> 156:95d6b41a828b 1477 /* If no error occurs */
<> 156:95d6b41a828b 1478 errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
<> 156:95d6b41a828b 1479 if (errorflags == RESET)
<> 156:95d6b41a828b 1480 {
<> 156:95d6b41a828b 1481 /* IRDA in mode Receiver ---------------------------------------------------*/
<> 156:95d6b41a828b 1482 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 156:95d6b41a828b 1483 {
<> 156:95d6b41a828b 1484 IRDA_Receive_IT(hirda);
<> 156:95d6b41a828b 1485 return;
<> 156:95d6b41a828b 1486 }
<> 156:95d6b41a828b 1487 }
<> 156:95d6b41a828b 1488
<> 156:95d6b41a828b 1489 /* If some errors occur */
<> 156:95d6b41a828b 1490 cr3its = READ_REG(hirda->Instance->CR3);
<> 156:95d6b41a828b 1491 if( (errorflags != RESET)
<> 156:95d6b41a828b 1492 && ( ((cr3its & USART_CR3_EIE) != RESET)
<> 156:95d6b41a828b 1493 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
<> 156:95d6b41a828b 1494 {
<> 156:95d6b41a828b 1495 /* IRDA parity error interrupt occurred -------------------------------------*/
<> 156:95d6b41a828b 1496 if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<> 156:95d6b41a828b 1497 {
<> 156:95d6b41a828b 1498 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
<> 144:ef7eb2e8f9f7 1499
<> 156:95d6b41a828b 1500 hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
<> 156:95d6b41a828b 1501 }
<> 156:95d6b41a828b 1502
<> 156:95d6b41a828b 1503 /* IRDA frame error interrupt occurred --------------------------------------*/
<> 156:95d6b41a828b 1504 if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 156:95d6b41a828b 1505 {
<> 156:95d6b41a828b 1506 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
<> 156:95d6b41a828b 1507
<> 156:95d6b41a828b 1508 hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
<> 156:95d6b41a828b 1509 }
<> 144:ef7eb2e8f9f7 1510
<> 156:95d6b41a828b 1511 /* IRDA noise error interrupt occurred --------------------------------------*/
<> 156:95d6b41a828b 1512 if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 156:95d6b41a828b 1513 {
<> 156:95d6b41a828b 1514 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
<> 156:95d6b41a828b 1515
<> 156:95d6b41a828b 1516 hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
<> 156:95d6b41a828b 1517 }
<> 144:ef7eb2e8f9f7 1518
<> 156:95d6b41a828b 1519 /* IRDA Over-Run interrupt occurred -----------------------------------------*/
<> 156:95d6b41a828b 1520 if(((isrflags & USART_ISR_ORE) != RESET) &&
<> 156:95d6b41a828b 1521 (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
<> 156:95d6b41a828b 1522 {
<> 156:95d6b41a828b 1523 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
<> 156:95d6b41a828b 1524
<> 156:95d6b41a828b 1525 hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
<> 156:95d6b41a828b 1526 }
<> 144:ef7eb2e8f9f7 1527
<> 156:95d6b41a828b 1528 /* Call IRDA Error Call back function if need be --------------------------*/
<> 156:95d6b41a828b 1529 if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
<> 156:95d6b41a828b 1530 {
<> 156:95d6b41a828b 1531 /* IRDA in mode Receiver ---------------------------------------------------*/
<> 156:95d6b41a828b 1532 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 156:95d6b41a828b 1533 {
<> 156:95d6b41a828b 1534 IRDA_Receive_IT(hirda);
<> 156:95d6b41a828b 1535 }
<> 144:ef7eb2e8f9f7 1536
<> 156:95d6b41a828b 1537 /* If Overrun error occurs, or if any error occurs in DMA mode reception,
<> 156:95d6b41a828b 1538 consider error as blocking */
<> 156:95d6b41a828b 1539 if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
<> 156:95d6b41a828b 1540 (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
<> 156:95d6b41a828b 1541 {
<> 156:95d6b41a828b 1542 /* Blocking error : transfer is aborted
<> 156:95d6b41a828b 1543 Set the IRDA state ready to be able to start again the process,
<> 156:95d6b41a828b 1544 Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<> 156:95d6b41a828b 1545 IRDA_EndRxTransfer(hirda);
<> 156:95d6b41a828b 1546
<> 156:95d6b41a828b 1547 /* Disable the IRDA DMA Rx request if enabled */
<> 156:95d6b41a828b 1548 if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1549 {
<> 156:95d6b41a828b 1550 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1551
<> 156:95d6b41a828b 1552 /* Abort the IRDA DMA Rx channel */
<> 156:95d6b41a828b 1553 if(hirda->hdmarx != NULL)
<> 156:95d6b41a828b 1554 {
<> 156:95d6b41a828b 1555 /* Set the IRDA DMA Abort callback :
<> 156:95d6b41a828b 1556 will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1557 hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
<> 144:ef7eb2e8f9f7 1558
<> 156:95d6b41a828b 1559 /* Abort DMA RX */
<> 156:95d6b41a828b 1560 if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1561 {
<> 156:95d6b41a828b 1562 /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1563 hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
<> 156:95d6b41a828b 1564 }
<> 156:95d6b41a828b 1565 }
<> 156:95d6b41a828b 1566 else
<> 156:95d6b41a828b 1567 {
<> 156:95d6b41a828b 1568 /* Call user error callback */
<> 156:95d6b41a828b 1569 HAL_IRDA_ErrorCallback(hirda);
<> 156:95d6b41a828b 1570 }
<> 156:95d6b41a828b 1571 }
<> 156:95d6b41a828b 1572 else
<> 156:95d6b41a828b 1573 {
<> 156:95d6b41a828b 1574 /* Call user error callback */
<> 156:95d6b41a828b 1575 HAL_IRDA_ErrorCallback(hirda);
<> 156:95d6b41a828b 1576 }
<> 156:95d6b41a828b 1577 }
<> 156:95d6b41a828b 1578 else
<> 156:95d6b41a828b 1579 {
<> 156:95d6b41a828b 1580 /* Non Blocking error : transfer could go on.
<> 156:95d6b41a828b 1581 Error is notified to user through user error callback */
<> 156:95d6b41a828b 1582 HAL_IRDA_ErrorCallback(hirda);
<> 156:95d6b41a828b 1583 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 156:95d6b41a828b 1584 }
<> 156:95d6b41a828b 1585 }
<> 156:95d6b41a828b 1586 return;
<> 144:ef7eb2e8f9f7 1587
<> 156:95d6b41a828b 1588 } /* End if some error occurs */
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /* IRDA in mode Transmitter ------------------------------------------------*/
<> 156:95d6b41a828b 1591 if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<> 144:ef7eb2e8f9f7 1592 {
<> 144:ef7eb2e8f9f7 1593 IRDA_Transmit_IT(hirda);
<> 156:95d6b41a828b 1594 return;
<> 144:ef7eb2e8f9f7 1595 }
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 /* IRDA in mode Transmitter (transmission end) -----------------------------*/
<> 156:95d6b41a828b 1598 if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<> 144:ef7eb2e8f9f7 1599 {
<> 144:ef7eb2e8f9f7 1600 IRDA_EndTransmit_IT(hirda);
<> 156:95d6b41a828b 1601 return;
<> 144:ef7eb2e8f9f7 1602 }
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 }
<> 144:ef7eb2e8f9f7 1605
<> 144:ef7eb2e8f9f7 1606 /**
<> 144:ef7eb2e8f9f7 1607 * @brief Tx Transfer completed callback.
<> 156:95d6b41a828b 1608 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1609 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1610 * @retval None
<> 144:ef7eb2e8f9f7 1611 */
<> 156:95d6b41a828b 1612 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1613 {
<> 144:ef7eb2e8f9f7 1614 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1615 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1616
<> 156:95d6b41a828b 1617 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1618 the HAL_IRDA_TxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1619 */
<> 144:ef7eb2e8f9f7 1620 }
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 /**
<> 144:ef7eb2e8f9f7 1623 * @brief Tx Half Transfer completed callback.
<> 156:95d6b41a828b 1624 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1625 * the configuration information for the specified USART module.
<> 144:ef7eb2e8f9f7 1626 * @retval None
<> 144:ef7eb2e8f9f7 1627 */
<> 156:95d6b41a828b 1628 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1629 {
<> 144:ef7eb2e8f9f7 1630 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1631 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1632
<> 156:95d6b41a828b 1633 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1634 the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1635 */
<> 144:ef7eb2e8f9f7 1636 }
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 /**
<> 144:ef7eb2e8f9f7 1639 * @brief Rx Transfer completed callback.
<> 156:95d6b41a828b 1640 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1641 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1642 * @retval None
<> 144:ef7eb2e8f9f7 1643 */
<> 144:ef7eb2e8f9f7 1644 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1645 {
<> 144:ef7eb2e8f9f7 1646 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1647 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1648
<> 156:95d6b41a828b 1649 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1650 the HAL_IRDA_RxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1651 */
<> 144:ef7eb2e8f9f7 1652 }
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 /**
<> 144:ef7eb2e8f9f7 1655 * @brief Rx Half Transfer complete callback.
<> 144:ef7eb2e8f9f7 1656 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1657 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1658 * @retval None
<> 144:ef7eb2e8f9f7 1659 */
<> 144:ef7eb2e8f9f7 1660 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1661 {
<> 144:ef7eb2e8f9f7 1662 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1663 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1664
<> 144:ef7eb2e8f9f7 1665 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1666 the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1667 */
<> 144:ef7eb2e8f9f7 1668 }
<> 144:ef7eb2e8f9f7 1669
<> 144:ef7eb2e8f9f7 1670 /**
<> 144:ef7eb2e8f9f7 1671 * @brief IRDA error callback.
<> 156:95d6b41a828b 1672 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1673 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1674 * @retval None
<> 144:ef7eb2e8f9f7 1675 */
<> 156:95d6b41a828b 1676 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1677 {
<> 156:95d6b41a828b 1678 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1679 UNUSED(hirda);
<> 156:95d6b41a828b 1680
<> 156:95d6b41a828b 1681 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1682 the HAL_IRDA_ErrorCallback can be implemented in the user file.
<> 156:95d6b41a828b 1683 */
<> 156:95d6b41a828b 1684 }
<> 156:95d6b41a828b 1685
<> 156:95d6b41a828b 1686 /**
<> 156:95d6b41a828b 1687 * @brief IRDA Abort Complete callback.
<> 156:95d6b41a828b 1688 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1689 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 1690 * @retval None
<> 156:95d6b41a828b 1691 */
<> 156:95d6b41a828b 1692 __weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1693 {
<> 144:ef7eb2e8f9f7 1694 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1695 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1696
<> 156:95d6b41a828b 1697 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1698 the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1699 */
<> 156:95d6b41a828b 1700 }
<> 156:95d6b41a828b 1701
<> 156:95d6b41a828b 1702 /**
<> 156:95d6b41a828b 1703 * @brief IRDA Abort Complete callback.
<> 156:95d6b41a828b 1704 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1705 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 1706 * @retval None
<> 156:95d6b41a828b 1707 */
<> 156:95d6b41a828b 1708 __weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1709 {
<> 156:95d6b41a828b 1710 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1711 UNUSED(hirda);
<> 156:95d6b41a828b 1712
<> 156:95d6b41a828b 1713 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1714 the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1715 */
<> 156:95d6b41a828b 1716 }
<> 156:95d6b41a828b 1717
<> 156:95d6b41a828b 1718 /**
<> 156:95d6b41a828b 1719 * @brief IRDA Abort Receive Complete callback.
<> 156:95d6b41a828b 1720 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1721 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 1722 * @retval None
<> 156:95d6b41a828b 1723 */
<> 156:95d6b41a828b 1724 __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1725 {
<> 156:95d6b41a828b 1726 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1727 UNUSED(hirda);
<> 156:95d6b41a828b 1728
<> 156:95d6b41a828b 1729 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1730 the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1731 */
<> 144:ef7eb2e8f9f7 1732 }
<> 144:ef7eb2e8f9f7 1733
<> 144:ef7eb2e8f9f7 1734 /**
<> 144:ef7eb2e8f9f7 1735 * @}
<> 144:ef7eb2e8f9f7 1736 */
<> 144:ef7eb2e8f9f7 1737
<> 144:ef7eb2e8f9f7 1738 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1739 * @brief IRDA State and Errors functions
<> 144:ef7eb2e8f9f7 1740 *
<> 144:ef7eb2e8f9f7 1741 @verbatim
<> 144:ef7eb2e8f9f7 1742 ==============================================================================
<> 156:95d6b41a828b 1743 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 1744 ==============================================================================
<> 144:ef7eb2e8f9f7 1745 [..]
<> 144:ef7eb2e8f9f7 1746 This subsection provides a set of functions allowing to return the State of IrDA
<> 144:ef7eb2e8f9f7 1747 communication process and also return Peripheral Errors occurred during communication process
<> 144:ef7eb2e8f9f7 1748 (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
<> 144:ef7eb2e8f9f7 1749 of the IRDA peripheral handle.
<> 144:ef7eb2e8f9f7 1750 (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
<> 144:ef7eb2e8f9f7 1751 communication.
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 @endverbatim
<> 144:ef7eb2e8f9f7 1754 * @{
<> 144:ef7eb2e8f9f7 1755 */
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 /**
<> 144:ef7eb2e8f9f7 1758 * @brief Return the IRDA handle state.
<> 144:ef7eb2e8f9f7 1759 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1760 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1761 * @retval HAL state
<> 144:ef7eb2e8f9f7 1762 */
<> 144:ef7eb2e8f9f7 1763 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1764 {
<> 144:ef7eb2e8f9f7 1765 /* Return IRDA handle state */
<> 156:95d6b41a828b 1766 uint32_t temp1= 0x00U, temp2 = 0x00U;
<> 144:ef7eb2e8f9f7 1767 temp1 = hirda->gState;
<> 144:ef7eb2e8f9f7 1768 temp2 = hirda->RxState;
<> 156:95d6b41a828b 1769
<> 144:ef7eb2e8f9f7 1770 return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
<> 144:ef7eb2e8f9f7 1771 }
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 /**
<> 144:ef7eb2e8f9f7 1774 * @brief Return the IRDA handle error code.
<> 144:ef7eb2e8f9f7 1775 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1776 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1777 * @retval IRDA Error Code
<> 144:ef7eb2e8f9f7 1778 */
<> 144:ef7eb2e8f9f7 1779 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1780 {
<> 144:ef7eb2e8f9f7 1781 return hirda->ErrorCode;
<> 144:ef7eb2e8f9f7 1782 }
<> 144:ef7eb2e8f9f7 1783
<> 144:ef7eb2e8f9f7 1784 /**
<> 144:ef7eb2e8f9f7 1785 * @}
<> 144:ef7eb2e8f9f7 1786 */
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 /**
<> 144:ef7eb2e8f9f7 1789 * @}
<> 144:ef7eb2e8f9f7 1790 */
<> 144:ef7eb2e8f9f7 1791
<> 156:95d6b41a828b 1792 /** @defgroup IRDA_Private_Functions IRDA Private Functions
<> 144:ef7eb2e8f9f7 1793 * @{
<> 144:ef7eb2e8f9f7 1794 */
<> 144:ef7eb2e8f9f7 1795
<> 144:ef7eb2e8f9f7 1796 /**
<> 156:95d6b41a828b 1797 * @brief Configure the IRDA peripheral.
<> 156:95d6b41a828b 1798 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1799 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1800 * @retval None
<> 144:ef7eb2e8f9f7 1801 */
<> 144:ef7eb2e8f9f7 1802 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1803 {
<> 156:95d6b41a828b 1804 uint32_t tmpreg = 0x00000000U;
<> 144:ef7eb2e8f9f7 1805 IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
<> 144:ef7eb2e8f9f7 1806 HAL_StatusTypeDef ret = HAL_OK;
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /* Check the communication parameters */
<> 144:ef7eb2e8f9f7 1809 assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 1810 assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
<> 144:ef7eb2e8f9f7 1811 assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
<> 144:ef7eb2e8f9f7 1812 assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
<> 144:ef7eb2e8f9f7 1813 assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
<> 144:ef7eb2e8f9f7 1814 assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
<> 144:ef7eb2e8f9f7 1815
<> 144:ef7eb2e8f9f7 1816 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1817 /* Configure the IRDA Word Length, Parity and transfer Mode:
<> 144:ef7eb2e8f9f7 1818 Set the M bits according to hirda->Init.WordLength value
<> 144:ef7eb2e8f9f7 1819 Set PCE and PS bits according to hirda->Init.Parity value
<> 144:ef7eb2e8f9f7 1820 Set TE and RE bits according to hirda->Init.Mode value */
<> 144:ef7eb2e8f9f7 1821 tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
<> 144:ef7eb2e8f9f7 1822
<> 144:ef7eb2e8f9f7 1823 MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
<> 144:ef7eb2e8f9f7 1824
<> 144:ef7eb2e8f9f7 1825 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1826 MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
<> 144:ef7eb2e8f9f7 1827
<> 144:ef7eb2e8f9f7 1828 /*-------------------------- USART GTPR Configuration ----------------------*/
<> 144:ef7eb2e8f9f7 1829 MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1832 IRDA_GETCLOCKSOURCE(hirda, clocksource);
<> 144:ef7eb2e8f9f7 1833 switch (clocksource)
<> 144:ef7eb2e8f9f7 1834 {
<> 144:ef7eb2e8f9f7 1835 case IRDA_CLOCKSOURCE_PCLK1:
<> 144:ef7eb2e8f9f7 1836 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1837 break;
<> 144:ef7eb2e8f9f7 1838 case IRDA_CLOCKSOURCE_HSI:
<> 144:ef7eb2e8f9f7 1839 hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1840 break;
<> 144:ef7eb2e8f9f7 1841 case IRDA_CLOCKSOURCE_SYSCLK:
<> 144:ef7eb2e8f9f7 1842 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1843 break;
<> 144:ef7eb2e8f9f7 1844 case IRDA_CLOCKSOURCE_LSE:
<> 144:ef7eb2e8f9f7 1845 hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1846 break;
<> 144:ef7eb2e8f9f7 1847 case IRDA_CLOCKSOURCE_UNDEFINED:
<> 144:ef7eb2e8f9f7 1848 default:
<> 144:ef7eb2e8f9f7 1849 ret = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1850 break;
<> 144:ef7eb2e8f9f7 1851 }
<> 144:ef7eb2e8f9f7 1852
<> 144:ef7eb2e8f9f7 1853 return ret;
<> 144:ef7eb2e8f9f7 1854 }
<> 144:ef7eb2e8f9f7 1855
<> 144:ef7eb2e8f9f7 1856 /**
<> 156:95d6b41a828b 1857 * @brief Check the IRDA Idle State.
<> 156:95d6b41a828b 1858 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1859 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1860 * @retval HAL status
<> 144:ef7eb2e8f9f7 1861 */
<> 144:ef7eb2e8f9f7 1862 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1863 {
<> 156:95d6b41a828b 1864 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /* Initialize the IRDA ErrorCode */
<> 144:ef7eb2e8f9f7 1867 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1868
<> 156:95d6b41a828b 1869 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 1870 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 1871
<> 144:ef7eb2e8f9f7 1872 /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
<> 144:ef7eb2e8f9f7 1873 Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
<> 144:ef7eb2e8f9f7 1874 */
<> 144:ef7eb2e8f9f7 1875 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1876 if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance))
<> 144:ef7eb2e8f9f7 1877 {
<> 144:ef7eb2e8f9f7 1878 /* Check if the Transmitter is enabled */
<> 144:ef7eb2e8f9f7 1879 if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<> 144:ef7eb2e8f9f7 1880 {
<> 144:ef7eb2e8f9f7 1881 /* Wait until TEACK flag is set */
<> 156:95d6b41a828b 1882 if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1883 {
<> 144:ef7eb2e8f9f7 1884 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 1885 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1886 }
<> 144:ef7eb2e8f9f7 1887 }
<> 144:ef7eb2e8f9f7 1888
<> 144:ef7eb2e8f9f7 1889 /* Check if the Receiver is enabled */
<> 144:ef7eb2e8f9f7 1890 if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<> 144:ef7eb2e8f9f7 1891 {
<> 144:ef7eb2e8f9f7 1892 /* Wait until REACK flag is set */
<> 156:95d6b41a828b 1893 if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1894 {
<> 144:ef7eb2e8f9f7 1895 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 1896 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1897 }
<> 144:ef7eb2e8f9f7 1898 }
<> 144:ef7eb2e8f9f7 1899 }
<> 144:ef7eb2e8f9f7 1900 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 1901
<> 144:ef7eb2e8f9f7 1902 /* Initialize the IRDA state*/
<> 156:95d6b41a828b 1903 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1904 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1905
<> 144:ef7eb2e8f9f7 1906 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1907 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1908
<> 144:ef7eb2e8f9f7 1909 return HAL_OK;
<> 144:ef7eb2e8f9f7 1910 }
<> 144:ef7eb2e8f9f7 1911
<> 144:ef7eb2e8f9f7 1912 /**
<> 144:ef7eb2e8f9f7 1913 * @brief Handle IRDA Communication Timeout.
<> 156:95d6b41a828b 1914 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1915 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 1916 * @param Flag Specifies the IRDA flag to check.
<> 156:95d6b41a828b 1917 * @param Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
<> 156:95d6b41a828b 1918 * @param Tickstart Tick start value
<> 156:95d6b41a828b 1919 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 1920 * @retval HAL status
<> 144:ef7eb2e8f9f7 1921 */
<> 156:95d6b41a828b 1922 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1923 {
<> 144:ef7eb2e8f9f7 1924 /* Wait until flag is set */
<> 156:95d6b41a828b 1925 while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
<> 144:ef7eb2e8f9f7 1926 {
<> 156:95d6b41a828b 1927 /* Check for the Timeout */
<> 156:95d6b41a828b 1928 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1929 {
<> 156:95d6b41a828b 1930 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1931 {
<> 156:95d6b41a828b 1932 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 156:95d6b41a828b 1933 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
<> 156:95d6b41a828b 1934 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1935
<> 156:95d6b41a828b 1936 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1937 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1938
<> 156:95d6b41a828b 1939 /* Process Unlocked */
<> 156:95d6b41a828b 1940 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1941
<> 156:95d6b41a828b 1942 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1943 }
<> 144:ef7eb2e8f9f7 1944 }
<> 144:ef7eb2e8f9f7 1945 }
<> 144:ef7eb2e8f9f7 1946 return HAL_OK;
<> 144:ef7eb2e8f9f7 1947 }
<> 144:ef7eb2e8f9f7 1948
<> 156:95d6b41a828b 1949
<> 156:95d6b41a828b 1950 /**
<> 156:95d6b41a828b 1951 * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
<> 156:95d6b41a828b 1952 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1953 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 1954 * @retval None
<> 156:95d6b41a828b 1955 */
<> 156:95d6b41a828b 1956 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1957 {
<> 156:95d6b41a828b 1958 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 1959 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1960
<> 156:95d6b41a828b 1961 /* At end of Tx process, restore hirda->gState to Ready */
<> 156:95d6b41a828b 1962 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1963 }
<> 156:95d6b41a828b 1964
<> 156:95d6b41a828b 1965
<> 156:95d6b41a828b 1966 /**
<> 156:95d6b41a828b 1967 * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
<> 156:95d6b41a828b 1968 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1969 * the configuration information for the specified IRDA module.
<> 156:95d6b41a828b 1970 * @retval None
<> 156:95d6b41a828b 1971 */
<> 156:95d6b41a828b 1972 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
<> 156:95d6b41a828b 1973 {
<> 156:95d6b41a828b 1974 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1975 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 1976 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1977
<> 156:95d6b41a828b 1978 /* At end of Rx process, restore hirda->RxState to Ready */
<> 156:95d6b41a828b 1979 hirda->RxState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 1980 }
<> 156:95d6b41a828b 1981
<> 156:95d6b41a828b 1982
<> 144:ef7eb2e8f9f7 1983 /**
<> 144:ef7eb2e8f9f7 1984 * @brief DMA IRDA transmit process complete callback.
<> 156:95d6b41a828b 1985 * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 1986 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1987 * @retval None
<> 144:ef7eb2e8f9f7 1988 */
<> 144:ef7eb2e8f9f7 1989 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1990 {
<> 156:95d6b41a828b 1991 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 1992
<> 144:ef7eb2e8f9f7 1993 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1994 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 144:ef7eb2e8f9f7 1995 {
<> 156:95d6b41a828b 1996 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1997
<> 144:ef7eb2e8f9f7 1998 /* Disable the DMA transfer for transmit request by resetting the DMAT bit
<> 144:ef7eb2e8f9f7 1999 in the IRDA CR3 register */
<> 156:95d6b41a828b 2000 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 2001
<> 144:ef7eb2e8f9f7 2002 /* Enable the IRDA Transmit Complete Interrupt */
<> 156:95d6b41a828b 2003 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2004 }
<> 144:ef7eb2e8f9f7 2005 /* DMA Circular mode */
<> 144:ef7eb2e8f9f7 2006 else
<> 144:ef7eb2e8f9f7 2007 {
<> 144:ef7eb2e8f9f7 2008 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 2009 }
<> 156:95d6b41a828b 2010
<> 144:ef7eb2e8f9f7 2011 }
<> 144:ef7eb2e8f9f7 2012
<> 144:ef7eb2e8f9f7 2013 /**
<> 156:95d6b41a828b 2014 * @brief DMA IRDA transmit process half complete callback.
<> 156:95d6b41a828b 2015 * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 2016 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2017 * @retval None
<> 144:ef7eb2e8f9f7 2018 */
<> 144:ef7eb2e8f9f7 2019 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2020 {
<> 156:95d6b41a828b 2021 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2022
<> 144:ef7eb2e8f9f7 2023 HAL_IRDA_TxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 2024 }
<> 144:ef7eb2e8f9f7 2025
<> 144:ef7eb2e8f9f7 2026 /**
<> 144:ef7eb2e8f9f7 2027 * @brief DMA IRDA receive process complete callback.
<> 144:ef7eb2e8f9f7 2028 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2029 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2030 * @retval None
<> 144:ef7eb2e8f9f7 2031 */
<> 144:ef7eb2e8f9f7 2032 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2033 {
<> 156:95d6b41a828b 2034 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 2037 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 144:ef7eb2e8f9f7 2038 {
<> 156:95d6b41a828b 2039 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 2040
<> 156:95d6b41a828b 2041 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 2042 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 2043 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2044
<> 144:ef7eb2e8f9f7 2045 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
<> 144:ef7eb2e8f9f7 2046 in the IRDA CR3 register */
<> 156:95d6b41a828b 2047 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 2048
<> 144:ef7eb2e8f9f7 2049 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 2050 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 2051 }
<> 144:ef7eb2e8f9f7 2052
<> 144:ef7eb2e8f9f7 2053 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 2054 }
<> 144:ef7eb2e8f9f7 2055
<> 144:ef7eb2e8f9f7 2056 /**
<> 144:ef7eb2e8f9f7 2057 * @brief DMA IRDA receive process half complete callback.
<> 144:ef7eb2e8f9f7 2058 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2059 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2060 * @retval None
<> 144:ef7eb2e8f9f7 2061 */
<> 144:ef7eb2e8f9f7 2062 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2063 {
<> 156:95d6b41a828b 2064 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2065
<> 144:ef7eb2e8f9f7 2066 HAL_IRDA_RxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 2067 }
<> 144:ef7eb2e8f9f7 2068
<> 144:ef7eb2e8f9f7 2069 /**
<> 156:95d6b41a828b 2070 * @brief DMA IRDA communication error callback.
<> 156:95d6b41a828b 2071 * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2072 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2073 * @retval None
<> 144:ef7eb2e8f9f7 2074 */
<> 144:ef7eb2e8f9f7 2075 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2076 {
<> 156:95d6b41a828b 2077 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2078
<> 156:95d6b41a828b 2079 /* Stop IRDA DMA Tx request if ongoing */
<> 156:95d6b41a828b 2080 if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 156:95d6b41a828b 2081 &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
<> 156:95d6b41a828b 2082 {
<> 156:95d6b41a828b 2083 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 2084 IRDA_EndTxTransfer(hirda);
<> 156:95d6b41a828b 2085 }
<> 144:ef7eb2e8f9f7 2086
<> 156:95d6b41a828b 2087 /* Stop IRDA DMA Rx request if ongoing */
<> 156:95d6b41a828b 2088 if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 156:95d6b41a828b 2089 &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
<> 156:95d6b41a828b 2090 {
<> 156:95d6b41a828b 2091 hirda->RxXferCount = 0;
<> 156:95d6b41a828b 2092 IRDA_EndRxTransfer(hirda);
<> 156:95d6b41a828b 2093 }
<> 156:95d6b41a828b 2094
<> 144:ef7eb2e8f9f7 2095 hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
<> 156:95d6b41a828b 2096 HAL_IRDA_ErrorCallback(hirda);
<> 156:95d6b41a828b 2097 }
<> 156:95d6b41a828b 2098
<> 156:95d6b41a828b 2099 /**
<> 156:95d6b41a828b 2100 * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
<> 156:95d6b41a828b 2101 * (To be called at end of DMA Abort procedure following error occurrence).
<> 156:95d6b41a828b 2102 * @param hdma DMA handle.
<> 156:95d6b41a828b 2103 * @retval None
<> 156:95d6b41a828b 2104 */
<> 156:95d6b41a828b 2105 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2106 {
<> 156:95d6b41a828b 2107 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2108 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 2109 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2110
<> 144:ef7eb2e8f9f7 2111 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 2112 }
<> 144:ef7eb2e8f9f7 2113
<> 156:95d6b41a828b 2114 /**
<> 156:95d6b41a828b 2115 * @brief DMA IRDA Tx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2116 * (To be called at end of DMA Tx Abort procedure following user abort request).
<> 156:95d6b41a828b 2117 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2118 * Abort still ongoing for Rx DMA Handle.
<> 156:95d6b41a828b 2119 * @param hdma DMA handle.
<> 156:95d6b41a828b 2120 * @retval None
<> 156:95d6b41a828b 2121 */
<> 156:95d6b41a828b 2122 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2123 {
<> 156:95d6b41a828b 2124 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
<> 156:95d6b41a828b 2125
<> 156:95d6b41a828b 2126 hirda->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2127
<> 156:95d6b41a828b 2128 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2129 if(hirda->hdmarx != NULL)
<> 156:95d6b41a828b 2130 {
<> 156:95d6b41a828b 2131 if(hirda->hdmarx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2132 {
<> 156:95d6b41a828b 2133 return;
<> 156:95d6b41a828b 2134 }
<> 156:95d6b41a828b 2135 }
<> 156:95d6b41a828b 2136
<> 156:95d6b41a828b 2137 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2138 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 2139 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 2140
<> 156:95d6b41a828b 2141 /* Reset errorCode */
<> 156:95d6b41a828b 2142 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 156:95d6b41a828b 2143
<> 156:95d6b41a828b 2144 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2145 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
<> 156:95d6b41a828b 2146
<> 156:95d6b41a828b 2147 /* Restore hirda->gState and hirda->RxState to Ready */
<> 156:95d6b41a828b 2148 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 2149 hirda->RxState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 2150
<> 156:95d6b41a828b 2151 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2152 HAL_IRDA_AbortCpltCallback(hirda);
<> 156:95d6b41a828b 2153 }
<> 156:95d6b41a828b 2154
<> 144:ef7eb2e8f9f7 2155
<> 144:ef7eb2e8f9f7 2156 /**
<> 156:95d6b41a828b 2157 * @brief DMA IRDA Rx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2158 * (To be called at end of DMA Rx Abort procedure following user abort request).
<> 156:95d6b41a828b 2159 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2160 * Abort still ongoing for Tx DMA Handle.
<> 156:95d6b41a828b 2161 * @param hdma DMA handle.
<> 156:95d6b41a828b 2162 * @retval None
<> 156:95d6b41a828b 2163 */
<> 156:95d6b41a828b 2164 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2165 {
<> 156:95d6b41a828b 2166 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
<> 156:95d6b41a828b 2167
<> 156:95d6b41a828b 2168 hirda->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2169
<> 156:95d6b41a828b 2170 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2171 if(hirda->hdmatx != NULL)
<> 156:95d6b41a828b 2172 {
<> 156:95d6b41a828b 2173 if(hirda->hdmatx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2174 {
<> 156:95d6b41a828b 2175 return;
<> 156:95d6b41a828b 2176 }
<> 156:95d6b41a828b 2177 }
<> 156:95d6b41a828b 2178
<> 156:95d6b41a828b 2179 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2180 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 2181 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 2182
<> 156:95d6b41a828b 2183 /* Reset errorCode */
<> 156:95d6b41a828b 2184 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 156:95d6b41a828b 2185
<> 156:95d6b41a828b 2186 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2187 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
<> 156:95d6b41a828b 2188
<> 156:95d6b41a828b 2189 /* Restore hirda->gState and hirda->RxState to Ready */
<> 156:95d6b41a828b 2190 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 2191 hirda->RxState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 2192
<> 156:95d6b41a828b 2193 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2194 HAL_IRDA_AbortCpltCallback(hirda);
<> 156:95d6b41a828b 2195 }
<> 156:95d6b41a828b 2196
<> 156:95d6b41a828b 2197
<> 156:95d6b41a828b 2198 /**
<> 156:95d6b41a828b 2199 * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
<> 156:95d6b41a828b 2200 * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
<> 156:95d6b41a828b 2201 * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
<> 156:95d6b41a828b 2202 * and leads to user Tx Abort Complete callback execution).
<> 156:95d6b41a828b 2203 * @param hdma DMA handle.
<> 156:95d6b41a828b 2204 * @retval None
<> 156:95d6b41a828b 2205 */
<> 156:95d6b41a828b 2206 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2207 {
<> 156:95d6b41a828b 2208 IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2209
<> 156:95d6b41a828b 2210 hirda->TxXferCount = 0U;
<> 156:95d6b41a828b 2211
<> 156:95d6b41a828b 2212 /* Restore hirda->gState to Ready */
<> 156:95d6b41a828b 2213 hirda->gState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 2214
<> 156:95d6b41a828b 2215 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2216 HAL_IRDA_AbortTransmitCpltCallback(hirda);
<> 156:95d6b41a828b 2217 }
<> 156:95d6b41a828b 2218
<> 156:95d6b41a828b 2219 /**
<> 156:95d6b41a828b 2220 * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
<> 156:95d6b41a828b 2221 * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
<> 156:95d6b41a828b 2222 * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
<> 156:95d6b41a828b 2223 * and leads to user Rx Abort Complete callback execution).
<> 156:95d6b41a828b 2224 * @param hdma DMA handle.
<> 156:95d6b41a828b 2225 * @retval None
<> 156:95d6b41a828b 2226 */
<> 156:95d6b41a828b 2227 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2228 {
<> 156:95d6b41a828b 2229 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 156:95d6b41a828b 2230
<> 156:95d6b41a828b 2231 hirda->RxXferCount = 0U;
<> 156:95d6b41a828b 2232
<> 156:95d6b41a828b 2233 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2234 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
<> 156:95d6b41a828b 2235
<> 156:95d6b41a828b 2236 /* Restore hirda->RxState to Ready */
<> 156:95d6b41a828b 2237 hirda->RxState = HAL_IRDA_STATE_READY;
<> 156:95d6b41a828b 2238
<> 156:95d6b41a828b 2239 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2240 HAL_IRDA_AbortReceiveCpltCallback(hirda);
<> 156:95d6b41a828b 2241 }
<> 156:95d6b41a828b 2242
<> 156:95d6b41a828b 2243 /**
<> 156:95d6b41a828b 2244 * @brief Send an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 2245 * @note Function is called under interruption only, once
<> 144:ef7eb2e8f9f7 2246 * interruptions have been enabled by HAL_IRDA_Transmit_IT().
<> 156:95d6b41a828b 2247 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 2248 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 2249 * @retval HAL status
<> 144:ef7eb2e8f9f7 2250 */
<> 144:ef7eb2e8f9f7 2251 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 2252 {
<> 144:ef7eb2e8f9f7 2253 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 2254
<> 144:ef7eb2e8f9f7 2255 /* Check that a Tx process is ongoing */
<> 144:ef7eb2e8f9f7 2256 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2257 {
<> 156:95d6b41a828b 2258 if(hirda->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2259 {
<> 144:ef7eb2e8f9f7 2260 /* Disable the IRDA Transmit Data Register Empty Interrupt */
<> 156:95d6b41a828b 2261 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 2262
<> 144:ef7eb2e8f9f7 2263 /* Enable the IRDA Transmit Complete Interrupt */
<> 156:95d6b41a828b 2264 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2265
<> 144:ef7eb2e8f9f7 2266 return HAL_OK;
<> 144:ef7eb2e8f9f7 2267 }
<> 144:ef7eb2e8f9f7 2268 else
<> 144:ef7eb2e8f9f7 2269 {
<> 144:ef7eb2e8f9f7 2270 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2271 {
<> 144:ef7eb2e8f9f7 2272 tmp = (uint16_t*) hirda->pTxBuffPtr;
<> 156:95d6b41a828b 2273 hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 156:95d6b41a828b 2274 hirda->pTxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 2275 }
<> 144:ef7eb2e8f9f7 2276 else
<> 144:ef7eb2e8f9f7 2277 {
<> 156:95d6b41a828b 2278 hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 2279 }
<> 144:ef7eb2e8f9f7 2280 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 2281
<> 144:ef7eb2e8f9f7 2282 return HAL_OK;
<> 144:ef7eb2e8f9f7 2283 }
<> 144:ef7eb2e8f9f7 2284 }
<> 144:ef7eb2e8f9f7 2285 else
<> 144:ef7eb2e8f9f7 2286 {
<> 144:ef7eb2e8f9f7 2287 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2288 }
<> 144:ef7eb2e8f9f7 2289 }
<> 144:ef7eb2e8f9f7 2290
<> 144:ef7eb2e8f9f7 2291 /**
<> 144:ef7eb2e8f9f7 2292 * @brief Wrap up transmission in non-blocking mode.
<> 156:95d6b41a828b 2293 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2294 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 2295 * @retval HAL status
<> 144:ef7eb2e8f9f7 2296 */
<> 144:ef7eb2e8f9f7 2297 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 2298 {
<> 144:ef7eb2e8f9f7 2299 /* Disable the IRDA Transmit Complete Interrupt */
<> 156:95d6b41a828b 2300 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2301
<> 144:ef7eb2e8f9f7 2302 /* Tx process is ended, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 2303 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 2304
<> 144:ef7eb2e8f9f7 2305 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 2306
<> 144:ef7eb2e8f9f7 2307 return HAL_OK;
<> 144:ef7eb2e8f9f7 2308 }
<> 144:ef7eb2e8f9f7 2309
<> 144:ef7eb2e8f9f7 2310 /**
<> 156:95d6b41a828b 2311 * @brief Receive an amount of data in interrupt mode.
<> 156:95d6b41a828b 2312 * @note Function is called under interruption only, once
<> 156:95d6b41a828b 2313 * interruptions have been enabled by HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 2314 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 2315 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 2316 * @retval HAL status
<> 144:ef7eb2e8f9f7 2317 */
<> 144:ef7eb2e8f9f7 2318 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 2319 {
<> 144:ef7eb2e8f9f7 2320 uint16_t* tmp;
<> 156:95d6b41a828b 2321 uint16_t uhMask = hirda->Mask;
<> 156:95d6b41a828b 2322 uint16_t uhdata;
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 /* Check that a Rx process is ongoing */
<> 144:ef7eb2e8f9f7 2325 if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 2326 {
<> 156:95d6b41a828b 2327 uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
<> 144:ef7eb2e8f9f7 2328 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2329 {
<> 144:ef7eb2e8f9f7 2330 tmp = (uint16_t*) hirda->pRxBuffPtr ;
<> 156:95d6b41a828b 2331 *tmp = (uint16_t)(uhdata & uhMask);
<> 156:95d6b41a828b 2332 hirda->pRxBuffPtr +=2U;
<> 144:ef7eb2e8f9f7 2333 }
<> 144:ef7eb2e8f9f7 2334 else
<> 144:ef7eb2e8f9f7 2335 {
<> 156:95d6b41a828b 2336 *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 2337 }
<> 144:ef7eb2e8f9f7 2338
<> 156:95d6b41a828b 2339 if(--hirda->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2340 {
<> 156:95d6b41a828b 2341 /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
<> 156:95d6b41a828b 2342 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 144:ef7eb2e8f9f7 2343
<> 144:ef7eb2e8f9f7 2344 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 2345 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2346
<> 144:ef7eb2e8f9f7 2347 /* Rx process is completed, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 2348 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 2349
<> 144:ef7eb2e8f9f7 2350 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 2351
<> 144:ef7eb2e8f9f7 2352 return HAL_OK;
<> 144:ef7eb2e8f9f7 2353 }
<> 144:ef7eb2e8f9f7 2354
<> 144:ef7eb2e8f9f7 2355 return HAL_OK;
<> 144:ef7eb2e8f9f7 2356 }
<> 144:ef7eb2e8f9f7 2357 else
<> 144:ef7eb2e8f9f7 2358 {
<> 144:ef7eb2e8f9f7 2359 /* Clear RXNE interrupt flag */
<> 144:ef7eb2e8f9f7 2360 __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
<> 144:ef7eb2e8f9f7 2361
<> 144:ef7eb2e8f9f7 2362 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2363 }
<> 144:ef7eb2e8f9f7 2364 }
<> 144:ef7eb2e8f9f7 2365
<> 144:ef7eb2e8f9f7 2366 /**
<> 144:ef7eb2e8f9f7 2367 * @}
<> 144:ef7eb2e8f9f7 2368 */
<> 144:ef7eb2e8f9f7 2369
<> 156:95d6b41a828b 2370 #endif /* HAL_IRDA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2371 /**
<> 144:ef7eb2e8f9f7 2372 * @}
<> 144:ef7eb2e8f9f7 2373 */
<> 144:ef7eb2e8f9f7 2374
<> 144:ef7eb2e8f9f7 2375 /**
<> 144:ef7eb2e8f9f7 2376 * @}
<> 144:ef7eb2e8f9f7 2377 */
<> 144:ef7eb2e8f9f7 2378
<> 144:ef7eb2e8f9f7 2379 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 2380
<> 144:ef7eb2e8f9f7 2381 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/