mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c@144:ef7eb2e8f9f7
Child:
156:95d6b41a828b
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_irda.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief IRDA HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the IrDA (Infrared Data Association) Peripheral
<> 144:ef7eb2e8f9f7 10 * (IRDA)
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 The IRDA HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
<> 144:ef7eb2e8f9f7 24 (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
<> 144:ef7eb2e8f9f7 25 in setting the associated USART or UART in IRDA mode:
<> 144:ef7eb2e8f9f7 26 (++) Enable the USARTx/UARTx interface clock.
<> 144:ef7eb2e8f9f7 27 (++) USARTx/UARTx pins configuration:
<> 144:ef7eb2e8f9f7 28 (+++) Enable the clock for the USARTx/UARTx GPIOs.
<> 144:ef7eb2e8f9f7 29 (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
<> 144:ef7eb2e8f9f7 30 (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 31 and HAL_IRDA_Receive_IT() APIs):
<> 144:ef7eb2e8f9f7 32 (+++) Configure the USARTx/UARTx interrupt priority.
<> 144:ef7eb2e8f9f7 33 (+++) Enable the NVIC USARTx/UARTx IRQ handle.
<> 144:ef7eb2e8f9f7 34 (+++) The specific IRDA interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 35 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 36 __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 39 and HAL_IRDA_Receive_DMA() APIs):
<> 144:ef7eb2e8f9f7 40 (+++) Declare a DMA handle structure for the Tx/Rx channel.
<> 144:ef7eb2e8f9f7 41 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 42 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 43 (+++) Configure the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 44 (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 45 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
<> 144:ef7eb2e8f9f7 48 the normal or low power mode and the clock prescaler in the hirda handle Init structure.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
<> 144:ef7eb2e8f9f7 51 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 52 by calling the customized HAL_IRDA_MspInit() API.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 -@@- The specific IRDA interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 55 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 56 __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 61 =================================
<> 144:ef7eb2e8f9f7 62 [..]
<> 144:ef7eb2e8f9f7 63 (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 64 (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 67 ===================================
<> 144:ef7eb2e8f9f7 68 [..]
<> 144:ef7eb2e8f9f7 69 (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 70 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 72 (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 73 (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 74 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 75 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 76 add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 79 ==============================
<> 144:ef7eb2e8f9f7 80 [..]
<> 144:ef7eb2e8f9f7 81 (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 82 (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 83 add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 84 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 85 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 86 (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 87 (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 88 add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 89 (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 90 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 91 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 92 add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 *** IRDA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 95 ====================================
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 Below the list of most used macros in IRDA HAL driver.
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
<> 144:ef7eb2e8f9f7 100 (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
<> 144:ef7eb2e8f9f7 101 (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
<> 144:ef7eb2e8f9f7 102 (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
<> 144:ef7eb2e8f9f7 103 (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 104 (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 105 (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 [..]
<> 144:ef7eb2e8f9f7 108 (@) You can refer to the IRDA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 @endverbatim
<> 144:ef7eb2e8f9f7 111 ******************************************************************************
<> 144:ef7eb2e8f9f7 112 * @attention
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 115 *
<> 144:ef7eb2e8f9f7 116 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 117 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 118 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 119 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 120 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 121 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 122 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 123 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 124 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 125 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 126 *
<> 144:ef7eb2e8f9f7 127 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 128 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 129 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 130 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 131 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 132 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 133 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 134 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 135 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 136 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 137 *
<> 144:ef7eb2e8f9f7 138 ******************************************************************************
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #ifdef HAL_IRDA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** @defgroup IRDA IRDA
<> 144:ef7eb2e8f9f7 153 * @brief HAL IRDA module driver
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /** @defgroup IRDA_Private_Constants IRDA Private Constants
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162 #define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */
<> 144:ef7eb2e8f9f7 163 #define IRDA_TXDMA_TIMEOUTVALUE 22000
<> 144:ef7eb2e8f9f7 164 #define IRDA_TIMEOUT_VALUE 22000
<> 144:ef7eb2e8f9f7 165 #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
<> 144:ef7eb2e8f9f7 166 | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 172 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 173 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 174 /** @addtogroup IRDA_Private_Functions IRDA Private Functions
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 178 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 179 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 180 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 181 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 182 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 183 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 184 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 185 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 186 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 187 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @}
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 199 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 200 *
<> 144:ef7eb2e8f9f7 201 @verbatim
<> 144:ef7eb2e8f9f7 202 ==============================================================================
<> 144:ef7eb2e8f9f7 203 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 204 ==============================================================================
<> 144:ef7eb2e8f9f7 205 [..]
<> 144:ef7eb2e8f9f7 206 This subsection provides a set of functions allowing to initialize the USARTx
<> 144:ef7eb2e8f9f7 207 in asynchronous IRDA mode.
<> 144:ef7eb2e8f9f7 208 (+) For the asynchronous mode only these parameters can be configured:
<> 144:ef7eb2e8f9f7 209 (++) Baud Rate
<> 144:ef7eb2e8f9f7 210 (++) Word Length
<> 144:ef7eb2e8f9f7 211 (++) Parity
<> 144:ef7eb2e8f9f7 212 (++) Power mode
<> 144:ef7eb2e8f9f7 213 (++) Prescaler setting
<> 144:ef7eb2e8f9f7 214 (++) Receiver/transmitter modes
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 [..]
<> 144:ef7eb2e8f9f7 217 The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
<> 144:ef7eb2e8f9f7 218 (details for the procedures are available in reference manual).
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 @endverbatim
<> 144:ef7eb2e8f9f7 221 * @{
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /*
<> 144:ef7eb2e8f9f7 225 Additional Table: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 226 in the data register is transmitted but is changed by the parity bit.
<> 144:ef7eb2e8f9f7 227 According to device capability (support or not of 7-bit word length),
<> 144:ef7eb2e8f9f7 228 frame length is either defined by the M bit (8-bits or 9-bits)
<> 144:ef7eb2e8f9f7 229 or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
<> 144:ef7eb2e8f9f7 230 Possible IRDA frame formats are as listed in the following table:
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 Table 1. IRDA frame format.
<> 144:ef7eb2e8f9f7 233 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 234 | M bit | PCE bit | IRDA frame |
<> 144:ef7eb2e8f9f7 235 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 236 | 0 | 0 | | SB | 8-bit data | STB | |
<> 144:ef7eb2e8f9f7 237 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 238 | 0 | 1 | | SB | 7-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 239 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 240 | 1 | 0 | | SB | 9-bit data | STB | |
<> 144:ef7eb2e8f9f7 241 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 242 | 1 | 1 | | SB | 8-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 243 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 244 | M1 bit | M0 bit | PCE bit | IRDA frame |
<> 144:ef7eb2e8f9f7 245 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 246 | 0 | 0 | 0 | | SB | 8 bit data | STB | |
<> 144:ef7eb2e8f9f7 247 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 248 | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 249 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 250 | 0 | 1 | 0 | | SB | 9 bit data | STB | |
<> 144:ef7eb2e8f9f7 251 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 252 | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 253 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 254 | 1 | 0 | 0 | | SB | 7 bit data | STB | |
<> 144:ef7eb2e8f9f7 255 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 256 | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 257 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @brief Initialize the IRDA mode according to the specified
<> 144:ef7eb2e8f9f7 263 * parameters in the IRDA_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 264 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 265 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 266 * @retval HAL status
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 271 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Check the USART/UART associated to the IRDA handle */
<> 144:ef7eb2e8f9f7 277 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 if(hirda->gState == HAL_IRDA_STATE_RESET)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 282 hirda->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 285 HAL_IRDA_MspInit(hirda);
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Disable the Peripheral to update the configuration registers */
<> 144:ef7eb2e8f9f7 291 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /* Set the IRDA Communication parameters */
<> 144:ef7eb2e8f9f7 294 if (IRDA_SetConfig(hirda) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* In IRDA mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 300 - LINEN, STOP and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 301 - SCEN and HDSEL bits in the USART_CR3 register.*/
<> 144:ef7eb2e8f9f7 302 hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
<> 144:ef7eb2e8f9f7 303 hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* set the UART/USART in IRDA mode */
<> 144:ef7eb2e8f9f7 306 hirda->Instance->CR3 |= USART_CR3_IREN;
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 309 __HAL_IRDA_ENABLE(hirda);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 312 return (IRDA_CheckIdleState(hirda));
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @brief DeInitialize the IRDA peripheral.
<> 144:ef7eb2e8f9f7 317 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 318 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 319 * @retval HAL status
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 324 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Check the USART/UART associated to the IRDA handle */
<> 144:ef7eb2e8f9f7 330 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 335 HAL_IRDA_MspDeInit(hirda);
<> 144:ef7eb2e8f9f7 336 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 337 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 hirda->gState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 340 hirda->RxState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Process Unlock */
<> 144:ef7eb2e8f9f7 343 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 return HAL_OK;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @brief Initialize the IRDA MSP.
<> 144:ef7eb2e8f9f7 350 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 351 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 352 * @retval None
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 357 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 360 the HAL_IRDA_MspInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @brief DeInitialize the IRDA MSP.
<> 144:ef7eb2e8f9f7 366 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 367 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 373 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 376 the HAL_IRDA_MspDeInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @}
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 385 * @brief IRDA Transmit and Receive functions
<> 144:ef7eb2e8f9f7 386 *
<> 144:ef7eb2e8f9f7 387 @verbatim
<> 144:ef7eb2e8f9f7 388 ==============================================================================
<> 144:ef7eb2e8f9f7 389 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 390 ==============================================================================
<> 144:ef7eb2e8f9f7 391 [..]
<> 144:ef7eb2e8f9f7 392 This subsection provides a set of functions allowing to manage the IRDA data transfers.
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 [..]
<> 144:ef7eb2e8f9f7 395 IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
<> 144:ef7eb2e8f9f7 396 on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
<> 144:ef7eb2e8f9f7 397 is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
<> 144:ef7eb2e8f9f7 398 While receiving data, transmission should be avoided as the data to be transmitted
<> 144:ef7eb2e8f9f7 399 could be corrupted.
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 402 (++) Blocking mode: the communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 403 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 404 after finishing transfer.
<> 144:ef7eb2e8f9f7 405 (++) No-Blocking mode: the communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 406 or DMA, these API's return the HAL status.
<> 144:ef7eb2e8f9f7 407 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 408 dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 409 using DMA mode.
<> 144:ef7eb2e8f9f7 410 The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 411 will be executed respectively at the end of the Transmit or Receive process
<> 144:ef7eb2e8f9f7 412 The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 (#) Blocking mode APIs are :
<> 144:ef7eb2e8f9f7 415 (++) HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 416 (++) HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 (#) Non Blocking mode APIs with Interrupt are :
<> 144:ef7eb2e8f9f7 419 (++) HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 420 (++) HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 421 (++) HAL_IRDA_IRQHandler()
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 (#) Non Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 424 (++) HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 425 (++) HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 426 (++) HAL_IRDA_DMAPause()
<> 144:ef7eb2e8f9f7 427 (++) HAL_IRDA_DMAResume()
<> 144:ef7eb2e8f9f7 428 (++) HAL_IRDA_DMAStop()
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
<> 144:ef7eb2e8f9f7 431 (++) HAL_IRDA_TxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 432 (++) HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 433 (++) HAL_IRDA_RxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 434 (++) HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 435 (++) HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 @endverbatim
<> 144:ef7eb2e8f9f7 438 * @{
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @brief Send an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 443 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 444 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 445 * @param pData: Pointer to data buffer.
<> 144:ef7eb2e8f9f7 446 * @param Size: Amount of data to be sent.
<> 144:ef7eb2e8f9f7 447 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 448 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 449 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 450 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 451 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 452 * @retval HAL status
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 459 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 467 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 468 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 469 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 if((((uint32_t)pData)&1) != 0)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Process Locked */
<> 144:ef7eb2e8f9f7 478 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 485 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 486 while(hirda->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 tmp = (uint16_t*) pData;
<> 144:ef7eb2e8f9f7 497 hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
<> 144:ef7eb2e8f9f7 498 pData +=2;
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500 else
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* At end of Tx process, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 512 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 515 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 return HAL_OK;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 else
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /**
<> 144:ef7eb2e8f9f7 526 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 527 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 528 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 529 * @param pData: Pointer to data buffer.
<> 144:ef7eb2e8f9f7 530 * @param Size: Amount of data to be received.
<> 144:ef7eb2e8f9f7 531 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 532 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 533 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 534 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 535 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 536 * @retval HAL status
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 541 uint16_t uhMask;
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 544 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 547 {
<> 144:ef7eb2e8f9f7 548 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 552 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 553 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 554 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 if((((uint32_t)pData)&1) != 0)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Process Locked */
<> 144:ef7eb2e8f9f7 563 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 570 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Computation of the mask to apply to the RDR register
<> 144:ef7eb2e8f9f7 573 of the UART associated to the IRDA */
<> 144:ef7eb2e8f9f7 574 IRDA_MASK_COMPUTATION(hirda);
<> 144:ef7eb2e8f9f7 575 uhMask = hirda->Mask;
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Check data remaining to be received */
<> 144:ef7eb2e8f9f7 578 while(hirda->RxXferCount > 0)
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 hirda->RxXferCount--;
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 tmp = (uint16_t*) pData ;
<> 144:ef7eb2e8f9f7 589 *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
<> 144:ef7eb2e8f9f7 590 pData +=2;
<> 144:ef7eb2e8f9f7 591 }
<> 144:ef7eb2e8f9f7 592 else
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 599 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 602 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 return HAL_OK;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606 else
<> 144:ef7eb2e8f9f7 607 {
<> 144:ef7eb2e8f9f7 608 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /**
<> 144:ef7eb2e8f9f7 613 * @brief Send an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 614 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 615 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 616 * @param pData: Pointer to data buffer.
<> 144:ef7eb2e8f9f7 617 * @param Size: Amount of data to be sent.
<> 144:ef7eb2e8f9f7 618 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 619 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 620 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 621 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 622 * @retval HAL status
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 625 {
<> 144:ef7eb2e8f9f7 626 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 627 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 630 {
<> 144:ef7eb2e8f9f7 631 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 635 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 636 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 637 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 if((((uint32_t)pData)&1) != 0)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Process Locked */
<> 144:ef7eb2e8f9f7 646 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 649 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 650 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 657 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Enable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 660 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 return HAL_OK;
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664 else
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Receive an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 672 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 673 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 674 * @param pData: Pointer to data buffer.
<> 144:ef7eb2e8f9f7 675 * @param Size: Amount of data to be received.
<> 144:ef7eb2e8f9f7 676 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 677 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 678 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 679 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 680 * @retval HAL status
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 685 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 693 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 694 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 695 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 if((((uint32_t)pData)&1) != 0)
<> 144:ef7eb2e8f9f7 698 {
<> 144:ef7eb2e8f9f7 699 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 700 }
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Process Locked */
<> 144:ef7eb2e8f9f7 704 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 707 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 708 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /* Computation of the mask to apply to the RDR register
<> 144:ef7eb2e8f9f7 711 of the UART associated to the IRDA */
<> 144:ef7eb2e8f9f7 712 IRDA_MASK_COMPUTATION(hirda);
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 719 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Enable the IRDA Data Register not empty Interrupt */
<> 144:ef7eb2e8f9f7 722 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Enable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 725 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 728 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 return HAL_OK;
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732 else
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /**
<> 144:ef7eb2e8f9f7 739 * @brief Send an amount of data in DMA mode.
<> 144:ef7eb2e8f9f7 740 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 741 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 742 * @param pData: pointer to data buffer.
<> 144:ef7eb2e8f9f7 743 * @param Size: amount of data to be sent.
<> 144:ef7eb2e8f9f7 744 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 745 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 746 * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 747 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 748 * @retval HAL status
<> 144:ef7eb2e8f9f7 749 */
<> 144:ef7eb2e8f9f7 750 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 755 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 758 {
<> 144:ef7eb2e8f9f7 759 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 763 should be aligned on a u16 frontier, as data copy into TDR will be
<> 144:ef7eb2e8f9f7 764 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 765 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 if((((uint32_t)pData)&1) != 0)
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771 }
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Process Locked */
<> 144:ef7eb2e8f9f7 774 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 777 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 778 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 785 hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 788 hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 791 hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* Enable the IRDA transmit DMA channel */
<> 144:ef7eb2e8f9f7 794 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 795 HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Clear the TC flag in the ICR register */
<> 144:ef7eb2e8f9f7 798 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 801 in the USART CR3 register */
<> 144:ef7eb2e8f9f7 802 hirda->Instance->CR3 |= USART_CR3_DMAT;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 805 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 return HAL_OK;
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809 else
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /**
<> 144:ef7eb2e8f9f7 816 * @brief Receive an amount of data in DMA mode.
<> 144:ef7eb2e8f9f7 817 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 818 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 819 * @param pData: Pointer to data buffer.
<> 144:ef7eb2e8f9f7 820 * @param Size: Amount of data to be received.
<> 144:ef7eb2e8f9f7 821 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 822 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 823 * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 824 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 825 * @retval HAL status
<> 144:ef7eb2e8f9f7 826 */
<> 144:ef7eb2e8f9f7 827 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 832 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 840 should be aligned on a u16 frontier, as data copy from RDR will be
<> 144:ef7eb2e8f9f7 841 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 842 if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 843 {
<> 144:ef7eb2e8f9f7 844 if((((uint32_t)pData)&1) != 0)
<> 144:ef7eb2e8f9f7 845 {
<> 144:ef7eb2e8f9f7 846 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Process Locked */
<> 144:ef7eb2e8f9f7 851 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 854 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 861 hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 864 hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 867 hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 870 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 871 HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 874 in the USART CR3 register */
<> 144:ef7eb2e8f9f7 875 hirda->Instance->CR3 |= USART_CR3_DMAR;
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 878 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 return HAL_OK;
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882 else
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /**
<> 144:ef7eb2e8f9f7 890 * @brief Pause the DMA Transfer.
<> 144:ef7eb2e8f9f7 891 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 892 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 893 * @retval HAL status
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 896 {
<> 144:ef7eb2e8f9f7 897 /* Process Locked */
<> 144:ef7eb2e8f9f7 898 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 /* Disable the IRDA DMA Tx request */
<> 144:ef7eb2e8f9f7 903 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 /* Disable the IRDA DMA Rx request */
<> 144:ef7eb2e8f9f7 908 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 912 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 return HAL_OK;
<> 144:ef7eb2e8f9f7 915 }
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /**
<> 144:ef7eb2e8f9f7 918 * @brief Resume the DMA Transfer.
<> 144:ef7eb2e8f9f7 919 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 920 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 921 * @retval HAL status
<> 144:ef7eb2e8f9f7 922 */
<> 144:ef7eb2e8f9f7 923 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 /* Process Locked */
<> 144:ef7eb2e8f9f7 926 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 929 {
<> 144:ef7eb2e8f9f7 930 /* Enable the IRDA DMA Tx request */
<> 144:ef7eb2e8f9f7 931 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 /* Clear the Overrun flag before resuming the Rx transfer*/
<> 144:ef7eb2e8f9f7 936 __HAL_IRDA_CLEAR_OREFLAG(hirda);
<> 144:ef7eb2e8f9f7 937 /* Enable the IRDA DMA Rx request */
<> 144:ef7eb2e8f9f7 938 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 942 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 return HAL_OK;
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /**
<> 144:ef7eb2e8f9f7 948 * @brief Stop the DMA Transfer.
<> 144:ef7eb2e8f9f7 949 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 950 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 951 * @retval HAL status
<> 144:ef7eb2e8f9f7 952 */
<> 144:ef7eb2e8f9f7 953 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 954 {
<> 144:ef7eb2e8f9f7 955 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 956 to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
<> 144:ef7eb2e8f9f7 957 HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
<> 144:ef7eb2e8f9f7 958 indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
<> 144:ef7eb2e8f9f7 959 generated if the DMA transfer interruption occurs at the middle or at the end of the stream
<> 144:ef7eb2e8f9f7 960 and the corresponding call back is executed.
<> 144:ef7eb2e8f9f7 961 */
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /* Disable the IRDA Tx/Rx DMA requests */
<> 144:ef7eb2e8f9f7 964 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 965 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /* Abort the IRDA DMA tx channel */
<> 144:ef7eb2e8f9f7 968 if(hirda->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 969 {
<> 144:ef7eb2e8f9f7 970 HAL_DMA_Abort(hirda->hdmatx);
<> 144:ef7eb2e8f9f7 971 }
<> 144:ef7eb2e8f9f7 972 /* Abort the IRDA DMA rx channel */
<> 144:ef7eb2e8f9f7 973 if(hirda->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 974 {
<> 144:ef7eb2e8f9f7 975 HAL_DMA_Abort(hirda->hdmarx);
<> 144:ef7eb2e8f9f7 976 }
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 979 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 return HAL_OK;
<> 144:ef7eb2e8f9f7 982 }
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /**
<> 144:ef7eb2e8f9f7 986 * @brief Handle IRDA interrupt request.
<> 144:ef7eb2e8f9f7 987 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 988 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 989 * @retval None
<> 144:ef7eb2e8f9f7 990 */
<> 144:ef7eb2e8f9f7 991 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 /* IRDA parity error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 994 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
<> 144:ef7eb2e8f9f7 999 /* Set the IRDA Rx state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1000 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1001 }
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* IRDA frame error interrupt occurred --------------------------------------*/
<> 144:ef7eb2e8f9f7 1004 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 1005 {
<> 144:ef7eb2e8f9f7 1006 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
<> 144:ef7eb2e8f9f7 1009 /* Set the IRDA Rx state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1010 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* IRDA noise error interrupt occurred --------------------------------------*/
<> 144:ef7eb2e8f9f7 1014 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
<> 144:ef7eb2e8f9f7 1019 /* Set the IRDA Rx state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1020 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* IRDA Over-Run interrupt occurred -----------------------------------------*/
<> 144:ef7eb2e8f9f7 1024 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
<> 144:ef7eb2e8f9f7 1029 /* Set the IRDA Rx state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1030 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1031 }
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /* Call IRDA Error Call back function if need be --------------------------*/
<> 144:ef7eb2e8f9f7 1034 if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /* IRDA in mode Receiver ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1040 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 IRDA_Receive_IT(hirda);
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* IRDA in mode Transmitter ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1047 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 1048 {
<> 144:ef7eb2e8f9f7 1049 IRDA_Transmit_IT(hirda);
<> 144:ef7eb2e8f9f7 1050 }
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* IRDA in mode Transmitter (transmission end) -----------------------------*/
<> 144:ef7eb2e8f9f7 1053 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 IRDA_EndTransmit_IT(hirda);
<> 144:ef7eb2e8f9f7 1056 }
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 }
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /**
<> 144:ef7eb2e8f9f7 1061 * @brief Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1062 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1063 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1064 * @retval None
<> 144:ef7eb2e8f9f7 1065 */
<> 144:ef7eb2e8f9f7 1066 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1067 {
<> 144:ef7eb2e8f9f7 1068 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1069 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1072 the HAL_IRDA_TxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1073 */
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /**
<> 144:ef7eb2e8f9f7 1077 * @brief Tx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 1078 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1079 * the configuration information for the specified USART module.
<> 144:ef7eb2e8f9f7 1080 * @retval None
<> 144:ef7eb2e8f9f7 1081 */
<> 144:ef7eb2e8f9f7 1082 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1085 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1088 the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1089 */
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /**
<> 144:ef7eb2e8f9f7 1093 * @brief Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 1094 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1095 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1096 * @retval None
<> 144:ef7eb2e8f9f7 1097 */
<> 144:ef7eb2e8f9f7 1098 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1099 {
<> 144:ef7eb2e8f9f7 1100 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1101 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1104 the HAL_IRDA_RxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1105 */
<> 144:ef7eb2e8f9f7 1106 }
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /**
<> 144:ef7eb2e8f9f7 1109 * @brief Rx Half Transfer complete callback.
<> 144:ef7eb2e8f9f7 1110 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1111 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1112 * @retval None
<> 144:ef7eb2e8f9f7 1113 */
<> 144:ef7eb2e8f9f7 1114 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1115 {
<> 144:ef7eb2e8f9f7 1116 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1117 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1120 the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1121 */
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /**
<> 144:ef7eb2e8f9f7 1125 * @brief IRDA error callback.
<> 144:ef7eb2e8f9f7 1126 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1127 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1128 * @retval None
<> 144:ef7eb2e8f9f7 1129 */
<> 144:ef7eb2e8f9f7 1130 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1131 {
<> 144:ef7eb2e8f9f7 1132 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1133 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1136 the HAL_IRDA_ErrorCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1137 */
<> 144:ef7eb2e8f9f7 1138 }
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 /**
<> 144:ef7eb2e8f9f7 1141 * @}
<> 144:ef7eb2e8f9f7 1142 */
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1145 * @brief IRDA State and Errors functions
<> 144:ef7eb2e8f9f7 1146 *
<> 144:ef7eb2e8f9f7 1147 @verbatim
<> 144:ef7eb2e8f9f7 1148 ==============================================================================
<> 144:ef7eb2e8f9f7 1149 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1150 ==============================================================================
<> 144:ef7eb2e8f9f7 1151 [..]
<> 144:ef7eb2e8f9f7 1152 This subsection provides a set of functions allowing to return the State of IrDA
<> 144:ef7eb2e8f9f7 1153 communication process and also return Peripheral Errors occurred during communication process
<> 144:ef7eb2e8f9f7 1154 (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
<> 144:ef7eb2e8f9f7 1155 of the IRDA peripheral handle.
<> 144:ef7eb2e8f9f7 1156 (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
<> 144:ef7eb2e8f9f7 1157 communication.
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 @endverbatim
<> 144:ef7eb2e8f9f7 1160 * @{
<> 144:ef7eb2e8f9f7 1161 */
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /**
<> 144:ef7eb2e8f9f7 1164 * @brief Return the IRDA handle state.
<> 144:ef7eb2e8f9f7 1165 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1166 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1167 * @retval HAL state
<> 144:ef7eb2e8f9f7 1168 */
<> 144:ef7eb2e8f9f7 1169 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1170 {
<> 144:ef7eb2e8f9f7 1171 /* Return IRDA handle state */
<> 144:ef7eb2e8f9f7 1172 uint32_t temp1= 0x00, temp2 = 0x00;
<> 144:ef7eb2e8f9f7 1173 temp1 = hirda->gState;
<> 144:ef7eb2e8f9f7 1174 temp2 = hirda->RxState;
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
<> 144:ef7eb2e8f9f7 1177 }
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /**
<> 144:ef7eb2e8f9f7 1180 * @brief Return the IRDA handle error code.
<> 144:ef7eb2e8f9f7 1181 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1182 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1183 * @retval IRDA Error Code
<> 144:ef7eb2e8f9f7 1184 */
<> 144:ef7eb2e8f9f7 1185 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1186 {
<> 144:ef7eb2e8f9f7 1187 return hirda->ErrorCode;
<> 144:ef7eb2e8f9f7 1188 }
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /**
<> 144:ef7eb2e8f9f7 1191 * @}
<> 144:ef7eb2e8f9f7 1192 */
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 /**
<> 144:ef7eb2e8f9f7 1195 * @}
<> 144:ef7eb2e8f9f7 1196 */
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /** @addtogroup IRDA_Private_Functions IRDA Private Functions
<> 144:ef7eb2e8f9f7 1199 * @{
<> 144:ef7eb2e8f9f7 1200 */
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /**
<> 144:ef7eb2e8f9f7 1204 * @brief Configure the IRDA peripheral.
<> 144:ef7eb2e8f9f7 1205 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1206 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1207 * @retval None
<> 144:ef7eb2e8f9f7 1208 */
<> 144:ef7eb2e8f9f7 1209 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1210 {
<> 144:ef7eb2e8f9f7 1211 uint32_t tmpreg = 0x00000000;
<> 144:ef7eb2e8f9f7 1212 IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
<> 144:ef7eb2e8f9f7 1213 HAL_StatusTypeDef ret = HAL_OK;
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /* Check the communication parameters */
<> 144:ef7eb2e8f9f7 1216 assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 1217 assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
<> 144:ef7eb2e8f9f7 1218 assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
<> 144:ef7eb2e8f9f7 1219 assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
<> 144:ef7eb2e8f9f7 1220 assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
<> 144:ef7eb2e8f9f7 1221 assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1224 /* Configure the IRDA Word Length, Parity and transfer Mode:
<> 144:ef7eb2e8f9f7 1225 Set the M bits according to hirda->Init.WordLength value
<> 144:ef7eb2e8f9f7 1226 Set PCE and PS bits according to hirda->Init.Parity value
<> 144:ef7eb2e8f9f7 1227 Set TE and RE bits according to hirda->Init.Mode value */
<> 144:ef7eb2e8f9f7 1228 tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1233 MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /*-------------------------- USART GTPR Configuration ----------------------*/
<> 144:ef7eb2e8f9f7 1236 MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1239 IRDA_GETCLOCKSOURCE(hirda, clocksource);
<> 144:ef7eb2e8f9f7 1240 switch (clocksource)
<> 144:ef7eb2e8f9f7 1241 {
<> 144:ef7eb2e8f9f7 1242 case IRDA_CLOCKSOURCE_PCLK1:
<> 144:ef7eb2e8f9f7 1243 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1244 break;
<> 144:ef7eb2e8f9f7 1245 case IRDA_CLOCKSOURCE_HSI:
<> 144:ef7eb2e8f9f7 1246 hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1247 break;
<> 144:ef7eb2e8f9f7 1248 case IRDA_CLOCKSOURCE_SYSCLK:
<> 144:ef7eb2e8f9f7 1249 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1250 break;
<> 144:ef7eb2e8f9f7 1251 case IRDA_CLOCKSOURCE_LSE:
<> 144:ef7eb2e8f9f7 1252 hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1253 break;
<> 144:ef7eb2e8f9f7 1254 case IRDA_CLOCKSOURCE_UNDEFINED:
<> 144:ef7eb2e8f9f7 1255 default:
<> 144:ef7eb2e8f9f7 1256 ret = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1257 break;
<> 144:ef7eb2e8f9f7 1258 }
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 return ret;
<> 144:ef7eb2e8f9f7 1261 }
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /**
<> 144:ef7eb2e8f9f7 1264 * @brief Check the IRDA Idle State.
<> 144:ef7eb2e8f9f7 1265 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1266 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1267 * @retval HAL status
<> 144:ef7eb2e8f9f7 1268 */
<> 144:ef7eb2e8f9f7 1269 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1270 {
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Initialize the IRDA ErrorCode */
<> 144:ef7eb2e8f9f7 1273 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
<> 144:ef7eb2e8f9f7 1276 Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
<> 144:ef7eb2e8f9f7 1277 */
<> 144:ef7eb2e8f9f7 1278 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1279 if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance))
<> 144:ef7eb2e8f9f7 1280 {
<> 144:ef7eb2e8f9f7 1281 /* Check if the Transmitter is enabled */
<> 144:ef7eb2e8f9f7 1282 if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<> 144:ef7eb2e8f9f7 1283 {
<> 144:ef7eb2e8f9f7 1284 /* Wait until TEACK flag is set */
<> 144:ef7eb2e8f9f7 1285 if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1286 {
<> 144:ef7eb2e8f9f7 1287 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 1288 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1289 }
<> 144:ef7eb2e8f9f7 1290 }
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /* Check if the Receiver is enabled */
<> 144:ef7eb2e8f9f7 1293 if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<> 144:ef7eb2e8f9f7 1294 {
<> 144:ef7eb2e8f9f7 1295 /* Wait until REACK flag is set */
<> 144:ef7eb2e8f9f7 1296 if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1297 {
<> 144:ef7eb2e8f9f7 1298 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 1299 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301 }
<> 144:ef7eb2e8f9f7 1302 }
<> 144:ef7eb2e8f9f7 1303 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /* Initialize the IRDA state*/
<> 144:ef7eb2e8f9f7 1306 hirda->gState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1307 hirda->RxState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1310 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 return HAL_OK;
<> 144:ef7eb2e8f9f7 1313 }
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /**
<> 144:ef7eb2e8f9f7 1316 * @brief Handle IRDA Communication Timeout.
<> 144:ef7eb2e8f9f7 1317 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1318 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1319 * @param Flag: specifies the IRDA flag to check.
<> 144:ef7eb2e8f9f7 1320 * @param Status: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
<> 144:ef7eb2e8f9f7 1321 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 1322 * @retval HAL status
<> 144:ef7eb2e8f9f7 1323 */
<> 144:ef7eb2e8f9f7 1324 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1325 {
<> 144:ef7eb2e8f9f7 1326 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1329 if(Status == RESET)
<> 144:ef7eb2e8f9f7 1330 {
<> 144:ef7eb2e8f9f7 1331 while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1332 {
<> 144:ef7eb2e8f9f7 1333 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1334 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1335 {
<> 144:ef7eb2e8f9f7 1336 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1337 {
<> 144:ef7eb2e8f9f7 1338 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 1339 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
<> 144:ef7eb2e8f9f7 1340 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
<> 144:ef7eb2e8f9f7 1341 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
<> 144:ef7eb2e8f9f7 1342 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 hirda->gState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1345 hirda->RxState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1348 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1351 }
<> 144:ef7eb2e8f9f7 1352 }
<> 144:ef7eb2e8f9f7 1353 }
<> 144:ef7eb2e8f9f7 1354 }
<> 144:ef7eb2e8f9f7 1355 else
<> 144:ef7eb2e8f9f7 1356 {
<> 144:ef7eb2e8f9f7 1357 while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1358 {
<> 144:ef7eb2e8f9f7 1359 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1360 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1361 {
<> 144:ef7eb2e8f9f7 1362 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1363 {
<> 144:ef7eb2e8f9f7 1364 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 1365 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
<> 144:ef7eb2e8f9f7 1366 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
<> 144:ef7eb2e8f9f7 1367 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
<> 144:ef7eb2e8f9f7 1368 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 hirda->gState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1371 hirda->RxState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1374 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378 }
<> 144:ef7eb2e8f9f7 1379 }
<> 144:ef7eb2e8f9f7 1380 }
<> 144:ef7eb2e8f9f7 1381 return HAL_OK;
<> 144:ef7eb2e8f9f7 1382 }
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /**
<> 144:ef7eb2e8f9f7 1385 * @brief DMA IRDA transmit process complete callback.
<> 144:ef7eb2e8f9f7 1386 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1387 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1388 * @retval None
<> 144:ef7eb2e8f9f7 1389 */
<> 144:ef7eb2e8f9f7 1390 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1391 {
<> 144:ef7eb2e8f9f7 1392 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1395 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 144:ef7eb2e8f9f7 1396 {
<> 144:ef7eb2e8f9f7 1397 hirda->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /* Disable the DMA transfer for transmit request by resetting the DMAT bit
<> 144:ef7eb2e8f9f7 1400 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1401 hirda->Instance->CR3 &= ~(USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1404 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406 /* DMA Circular mode */
<> 144:ef7eb2e8f9f7 1407 else
<> 144:ef7eb2e8f9f7 1408 {
<> 144:ef7eb2e8f9f7 1409 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1410 }
<> 144:ef7eb2e8f9f7 1411 }
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 /**
<> 144:ef7eb2e8f9f7 1414 * @brief DMA IRDA transmit process half complete callback.
<> 144:ef7eb2e8f9f7 1415 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1416 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1417 * @retval None
<> 144:ef7eb2e8f9f7 1418 */
<> 144:ef7eb2e8f9f7 1419 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1420 {
<> 144:ef7eb2e8f9f7 1421 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1422
<> 144:ef7eb2e8f9f7 1423 HAL_IRDA_TxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1424 }
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 /**
<> 144:ef7eb2e8f9f7 1427 * @brief DMA IRDA receive process complete callback.
<> 144:ef7eb2e8f9f7 1428 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1429 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1430 * @retval None
<> 144:ef7eb2e8f9f7 1431 */
<> 144:ef7eb2e8f9f7 1432 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1433 {
<> 144:ef7eb2e8f9f7 1434 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1437 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 144:ef7eb2e8f9f7 1438 {
<> 144:ef7eb2e8f9f7 1439 hirda->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
<> 144:ef7eb2e8f9f7 1442 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1443 hirda->Instance->CR3 &= ~(USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1446 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1447 }
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1450 }
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /**
<> 144:ef7eb2e8f9f7 1453 * @brief DMA IRDA receive process half complete callback.
<> 144:ef7eb2e8f9f7 1454 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1455 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1456 * @retval None
<> 144:ef7eb2e8f9f7 1457 */
<> 144:ef7eb2e8f9f7 1458 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1459 {
<> 144:ef7eb2e8f9f7 1460 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 HAL_IRDA_RxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1463 }
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 /**
<> 144:ef7eb2e8f9f7 1466 * @brief DMA IRDA communication error callback.
<> 144:ef7eb2e8f9f7 1467 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1468 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1469 * @retval None
<> 144:ef7eb2e8f9f7 1470 */
<> 144:ef7eb2e8f9f7 1471 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1472 {
<> 144:ef7eb2e8f9f7 1473 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475 hirda->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1476 hirda->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1477 hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1478 hirda->gState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1479 hirda->RxState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1482 }
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 /**
<> 144:ef7eb2e8f9f7 1486 * @brief Send an amount of data in non-blocking mode.
<> 144:ef7eb2e8f9f7 1487 * @note Function is called under interruption only, once
<> 144:ef7eb2e8f9f7 1488 * interruptions have been enabled by HAL_IRDA_Transmit_IT().
<> 144:ef7eb2e8f9f7 1489 * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1490 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1491 * @retval HAL status
<> 144:ef7eb2e8f9f7 1492 */
<> 144:ef7eb2e8f9f7 1493 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1494 {
<> 144:ef7eb2e8f9f7 1495 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 /* Check that a Tx process is ongoing */
<> 144:ef7eb2e8f9f7 1498 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1499 {
<> 144:ef7eb2e8f9f7 1500 if(hirda->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1501 {
<> 144:ef7eb2e8f9f7 1502 /* Disable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 1503 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
<> 144:ef7eb2e8f9f7 1504
<> 144:ef7eb2e8f9f7 1505 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1506 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 return HAL_OK;
<> 144:ef7eb2e8f9f7 1509 }
<> 144:ef7eb2e8f9f7 1510 else
<> 144:ef7eb2e8f9f7 1511 {
<> 144:ef7eb2e8f9f7 1512 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1513 {
<> 144:ef7eb2e8f9f7 1514 tmp = (uint16_t*) hirda->pTxBuffPtr;
<> 144:ef7eb2e8f9f7 1515 hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
<> 144:ef7eb2e8f9f7 1516 hirda->pTxBuffPtr += 2;
<> 144:ef7eb2e8f9f7 1517 }
<> 144:ef7eb2e8f9f7 1518 else
<> 144:ef7eb2e8f9f7 1519 {
<> 144:ef7eb2e8f9f7 1520 hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
<> 144:ef7eb2e8f9f7 1521 }
<> 144:ef7eb2e8f9f7 1522 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 1523
<> 144:ef7eb2e8f9f7 1524 return HAL_OK;
<> 144:ef7eb2e8f9f7 1525 }
<> 144:ef7eb2e8f9f7 1526 }
<> 144:ef7eb2e8f9f7 1527 else
<> 144:ef7eb2e8f9f7 1528 {
<> 144:ef7eb2e8f9f7 1529 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1530 }
<> 144:ef7eb2e8f9f7 1531 }
<> 144:ef7eb2e8f9f7 1532
<> 144:ef7eb2e8f9f7 1533 /**
<> 144:ef7eb2e8f9f7 1534 * @brief Wrap up transmission in non-blocking mode.
<> 144:ef7eb2e8f9f7 1535 * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1536 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1537 * @retval HAL status
<> 144:ef7eb2e8f9f7 1538 */
<> 144:ef7eb2e8f9f7 1539 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1540 {
<> 144:ef7eb2e8f9f7 1541 /* Disable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1542 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* Tx process is ended, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 1545 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 return HAL_OK;
<> 144:ef7eb2e8f9f7 1550 }
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /**
<> 144:ef7eb2e8f9f7 1554 * @brief Receive an amount of data in non-blocking mode.
<> 144:ef7eb2e8f9f7 1555 * Function is called under interruption only, once
<> 144:ef7eb2e8f9f7 1556 * interruptions have been enabled by HAL_IRDA_Receive_IT().
<> 144:ef7eb2e8f9f7 1557 * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1558 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1559 * @retval HAL status
<> 144:ef7eb2e8f9f7 1560 */
<> 144:ef7eb2e8f9f7 1561 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1562 {
<> 144:ef7eb2e8f9f7 1563 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1564 uint16_t uhMask = hirda->Mask;
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /* Check that a Rx process is ongoing */
<> 144:ef7eb2e8f9f7 1567 if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1568 {
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1571 {
<> 144:ef7eb2e8f9f7 1572 tmp = (uint16_t*) hirda->pRxBuffPtr ;
<> 144:ef7eb2e8f9f7 1573 *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
<> 144:ef7eb2e8f9f7 1574 hirda->pRxBuffPtr +=2;
<> 144:ef7eb2e8f9f7 1575 }
<> 144:ef7eb2e8f9f7 1576 else
<> 144:ef7eb2e8f9f7 1577 {
<> 144:ef7eb2e8f9f7 1578 *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 1579 }
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 if(--hirda->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 1582 {
<> 144:ef7eb2e8f9f7 1583 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 /* Disable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 1586 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 1589 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 /* Rx process is completed, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1592 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 return HAL_OK;
<> 144:ef7eb2e8f9f7 1597 }
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 return HAL_OK;
<> 144:ef7eb2e8f9f7 1600 }
<> 144:ef7eb2e8f9f7 1601 else
<> 144:ef7eb2e8f9f7 1602 {
<> 144:ef7eb2e8f9f7 1603 /* Clear RXNE interrupt flag */
<> 144:ef7eb2e8f9f7 1604 __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
<> 144:ef7eb2e8f9f7 1605
<> 144:ef7eb2e8f9f7 1606 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1607 }
<> 144:ef7eb2e8f9f7 1608 }
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 /**
<> 144:ef7eb2e8f9f7 1611 * @}
<> 144:ef7eb2e8f9f7 1612 */
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /**
<> 144:ef7eb2e8f9f7 1615 * @}
<> 144:ef7eb2e8f9f7 1616 */
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 /**
<> 144:ef7eb2e8f9f7 1619 * @}
<> 144:ef7eb2e8f9f7 1620 */
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 #endif /* HAL_IRDA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1625
<> 144:ef7eb2e8f9f7 1626 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/