mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/stm_spi_api.c@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 16:45:37 2018 +0100
Revision:
186:707f6e361f3e
Parent:
181:57724642e740
Child:
187:0387e8f68319
mbed-dev library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * Copyright (c) 2015, STMicroelectronics
<> 149:156823d33999 4 * All rights reserved.
<> 149:156823d33999 5 *
<> 149:156823d33999 6 * Redistribution and use in source and binary forms, with or without
<> 149:156823d33999 7 * modification, are permitted provided that the following conditions are met:
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 10 * this list of conditions and the following disclaimer.
<> 149:156823d33999 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 12 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 13 * and/or other materials provided with the distribution.
<> 149:156823d33999 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 15 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 16 * without specific prior written permission.
<> 149:156823d33999 17 *
<> 149:156823d33999 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 28 *******************************************************************************
<> 149:156823d33999 29 */
<> 149:156823d33999 30 #include "mbed_assert.h"
<> 149:156823d33999 31 #include "mbed_error.h"
AnnaBridge 179:b0033dcd6934 32 #include "mbed_debug.h"
<> 149:156823d33999 33 #include "spi_api.h"
<> 149:156823d33999 34
<> 149:156823d33999 35 #if DEVICE_SPI
<> 149:156823d33999 36 #include <stdbool.h>
<> 149:156823d33999 37 #include <math.h>
<> 149:156823d33999 38 #include <string.h>
<> 149:156823d33999 39 #include "cmsis.h"
<> 149:156823d33999 40 #include "pinmap.h"
<> 149:156823d33999 41 #include "PeripheralPins.h"
AnnaBridge 168:9672193075cf 42 #include "spi_device.h"
<> 149:156823d33999 43
<> 149:156823d33999 44 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 45 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
<> 149:156823d33999 46 #else
<> 149:156823d33999 47 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
<> 149:156823d33999 48 #endif
<> 149:156823d33999 49
<> 149:156823d33999 50 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 51 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
<> 149:156823d33999 52 #else
<> 149:156823d33999 53 #define SPI_S(obj) (( struct spi_s *)(obj))
<> 149:156823d33999 54 #endif
<> 149:156823d33999 55
<> 149:156823d33999 56 #ifndef DEBUG_STDIO
<> 149:156823d33999 57 # define DEBUG_STDIO 0
<> 149:156823d33999 58 #endif
<> 149:156823d33999 59
<> 149:156823d33999 60 #if DEBUG_STDIO
<> 149:156823d33999 61 # include <stdio.h>
<> 149:156823d33999 62 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
<> 149:156823d33999 63 #else
<> 149:156823d33999 64 # define DEBUG_PRINTF(...) {}
<> 149:156823d33999 65 #endif
<> 149:156823d33999 66
AnnaBridge 173:e131a1973e81 67 /* Consider 10ms as the default timeout for sending/receving 1 byte */
AnnaBridge 173:e131a1973e81 68 #define TIMEOUT_1_BYTE 10
AnnaBridge 173:e131a1973e81 69
Anna Bridge 186:707f6e361f3e 70 #if defined(SPI_FLAG_FRLVL) // STM32F0 STM32F3 STM32F7 STM32L4
Anna Bridge 186:707f6e361f3e 71 extern HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
Anna Bridge 186:707f6e361f3e 72 #endif
Anna Bridge 186:707f6e361f3e 73
<> 149:156823d33999 74 void init_spi(spi_t *obj)
<> 149:156823d33999 75 {
<> 149:156823d33999 76 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 77 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 78
<> 149:156823d33999 79 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 80
<> 149:156823d33999 81 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
<> 149:156823d33999 82 if (HAL_SPI_Init(handle) != HAL_OK) {
<> 149:156823d33999 83 error("Cannot initialize SPI");
<> 149:156823d33999 84 }
<> 149:156823d33999 85
AnnaBridge 173:e131a1973e81 86 /* In case of standard 4 wires SPI,PI can be kept enabled all time
AnnaBridge 173:e131a1973e81 87 * and SCK will only be generated during the write operations. But in case
AnnaBridge 173:e131a1973e81 88 * of 3 wires, it should be only enabled during rd/wr unitary operations,
AnnaBridge 173:e131a1973e81 89 * which is handled inside STM32 HAL layer.
AnnaBridge 173:e131a1973e81 90 */
AnnaBridge 173:e131a1973e81 91 if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
AnnaBridge 173:e131a1973e81 92 __HAL_SPI_ENABLE(handle);
AnnaBridge 173:e131a1973e81 93 }
<> 149:156823d33999 94 }
<> 149:156823d33999 95
<> 149:156823d33999 96 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 149:156823d33999 97 {
<> 149:156823d33999 98 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 99 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 100
<> 149:156823d33999 101 // Determine the SPI to use
<> 149:156823d33999 102 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 103 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 149:156823d33999 104 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 105 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 106
<> 149:156823d33999 107 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 149:156823d33999 108 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 149:156823d33999 109
<> 149:156823d33999 110 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
<> 149:156823d33999 111 MBED_ASSERT(spiobj->spi != (SPIName)NC);
<> 149:156823d33999 112
<> 149:156823d33999 113 #if defined SPI1_BASE
<> 149:156823d33999 114 // Enable SPI clock
<> 149:156823d33999 115 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 116 __HAL_RCC_SPI1_CLK_ENABLE();
<> 149:156823d33999 117 spiobj->spiIRQ = SPI1_IRQn;
<> 149:156823d33999 118 }
<> 149:156823d33999 119 #endif
<> 149:156823d33999 120
<> 149:156823d33999 121 #if defined SPI2_BASE
<> 149:156823d33999 122 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 123 __HAL_RCC_SPI2_CLK_ENABLE();
<> 149:156823d33999 124 spiobj->spiIRQ = SPI2_IRQn;
<> 149:156823d33999 125 }
<> 149:156823d33999 126 #endif
<> 149:156823d33999 127
<> 149:156823d33999 128 #if defined SPI3_BASE
<> 149:156823d33999 129 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 130 __HAL_RCC_SPI3_CLK_ENABLE();
<> 149:156823d33999 131 spiobj->spiIRQ = SPI3_IRQn;
<> 149:156823d33999 132 }
<> 149:156823d33999 133 #endif
<> 149:156823d33999 134
<> 149:156823d33999 135 #if defined SPI4_BASE
<> 149:156823d33999 136 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 137 __HAL_RCC_SPI4_CLK_ENABLE();
<> 149:156823d33999 138 spiobj->spiIRQ = SPI4_IRQn;
<> 149:156823d33999 139 }
<> 149:156823d33999 140 #endif
<> 149:156823d33999 141
<> 149:156823d33999 142 #if defined SPI5_BASE
<> 149:156823d33999 143 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 144 __HAL_RCC_SPI5_CLK_ENABLE();
<> 149:156823d33999 145 spiobj->spiIRQ = SPI5_IRQn;
<> 149:156823d33999 146 }
<> 149:156823d33999 147 #endif
<> 149:156823d33999 148
<> 149:156823d33999 149 #if defined SPI6_BASE
<> 149:156823d33999 150 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 151 __HAL_RCC_SPI6_CLK_ENABLE();
<> 149:156823d33999 152 spiobj->spiIRQ = SPI6_IRQn;
<> 149:156823d33999 153 }
<> 149:156823d33999 154 #endif
<> 149:156823d33999 155
<> 149:156823d33999 156 // Configure the SPI pins
<> 149:156823d33999 157 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 158 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 149:156823d33999 159 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 160 spiobj->pin_miso = miso;
<> 149:156823d33999 161 spiobj->pin_mosi = mosi;
<> 149:156823d33999 162 spiobj->pin_sclk = sclk;
<> 149:156823d33999 163 spiobj->pin_ssel = ssel;
<> 149:156823d33999 164 if (ssel != NC) {
<> 149:156823d33999 165 pinmap_pinout(ssel, PinMap_SPI_SSEL);
Anna Bridge 186:707f6e361f3e 166 handle->Init.NSS = SPI_NSS_HARD_OUTPUT;
<> 149:156823d33999 167 } else {
<> 149:156823d33999 168 handle->Init.NSS = SPI_NSS_SOFT;
<> 149:156823d33999 169 }
<> 149:156823d33999 170
<> 149:156823d33999 171 /* Fill default value */
<> 149:156823d33999 172 handle->Instance = SPI_INST(obj);
<> 149:156823d33999 173 handle->Init.Mode = SPI_MODE_MASTER;
<> 149:156823d33999 174 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
AnnaBridge 173:e131a1973e81 175
AnnaBridge 173:e131a1973e81 176 if (miso != NC) {
AnnaBridge 173:e131a1973e81 177 handle->Init.Direction = SPI_DIRECTION_2LINES;
AnnaBridge 173:e131a1973e81 178 } else {
AnnaBridge 173:e131a1973e81 179 handle->Init.Direction = SPI_DIRECTION_1LINE;
AnnaBridge 173:e131a1973e81 180 }
AnnaBridge 173:e131a1973e81 181
<> 149:156823d33999 182 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 183 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
AnnaBridge 165:e614a9f1c9e2 184 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 149:156823d33999 185 handle->Init.CRCPolynomial = 7;
<> 149:156823d33999 186 handle->Init.DataSize = SPI_DATASIZE_8BIT;
<> 149:156823d33999 187 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
AnnaBridge 165:e614a9f1c9e2 188 handle->Init.TIMode = SPI_TIMODE_DISABLE;
<> 149:156823d33999 189
<> 149:156823d33999 190 init_spi(obj);
<> 149:156823d33999 191 }
<> 149:156823d33999 192
<> 149:156823d33999 193 void spi_free(spi_t *obj)
<> 149:156823d33999 194 {
<> 149:156823d33999 195 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 196 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 197
<> 149:156823d33999 198 DEBUG_PRINTF("spi_free\r\n");
<> 149:156823d33999 199
<> 149:156823d33999 200 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 201 HAL_SPI_DeInit(handle);
<> 149:156823d33999 202
<> 149:156823d33999 203 #if defined SPI1_BASE
<> 149:156823d33999 204 // Reset SPI and disable clock
<> 149:156823d33999 205 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 206 __HAL_RCC_SPI1_FORCE_RESET();
<> 149:156823d33999 207 __HAL_RCC_SPI1_RELEASE_RESET();
<> 149:156823d33999 208 __HAL_RCC_SPI1_CLK_DISABLE();
<> 149:156823d33999 209 }
<> 149:156823d33999 210 #endif
<> 149:156823d33999 211 #if defined SPI2_BASE
<> 149:156823d33999 212 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 213 __HAL_RCC_SPI2_FORCE_RESET();
<> 149:156823d33999 214 __HAL_RCC_SPI2_RELEASE_RESET();
<> 149:156823d33999 215 __HAL_RCC_SPI2_CLK_DISABLE();
<> 149:156823d33999 216 }
<> 149:156823d33999 217 #endif
<> 149:156823d33999 218
<> 149:156823d33999 219 #if defined SPI3_BASE
<> 149:156823d33999 220 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 221 __HAL_RCC_SPI3_FORCE_RESET();
<> 149:156823d33999 222 __HAL_RCC_SPI3_RELEASE_RESET();
<> 149:156823d33999 223 __HAL_RCC_SPI3_CLK_DISABLE();
<> 149:156823d33999 224 }
<> 149:156823d33999 225 #endif
<> 149:156823d33999 226
<> 149:156823d33999 227 #if defined SPI4_BASE
<> 149:156823d33999 228 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 229 __HAL_RCC_SPI4_FORCE_RESET();
<> 149:156823d33999 230 __HAL_RCC_SPI4_RELEASE_RESET();
<> 149:156823d33999 231 __HAL_RCC_SPI4_CLK_DISABLE();
<> 149:156823d33999 232 }
<> 149:156823d33999 233 #endif
<> 149:156823d33999 234
<> 149:156823d33999 235 #if defined SPI5_BASE
<> 149:156823d33999 236 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 237 __HAL_RCC_SPI5_FORCE_RESET();
<> 149:156823d33999 238 __HAL_RCC_SPI5_RELEASE_RESET();
<> 149:156823d33999 239 __HAL_RCC_SPI5_CLK_DISABLE();
<> 149:156823d33999 240 }
<> 149:156823d33999 241 #endif
<> 149:156823d33999 242
<> 149:156823d33999 243 #if defined SPI6_BASE
<> 149:156823d33999 244 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 245 __HAL_RCC_SPI6_FORCE_RESET();
<> 149:156823d33999 246 __HAL_RCC_SPI6_RELEASE_RESET();
<> 149:156823d33999 247 __HAL_RCC_SPI6_CLK_DISABLE();
<> 149:156823d33999 248 }
<> 149:156823d33999 249 #endif
<> 149:156823d33999 250
<> 149:156823d33999 251 // Configure GPIOs
<> 149:156823d33999 252 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 253 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 254 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 255 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 256 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 257 }
<> 149:156823d33999 258 }
<> 149:156823d33999 259
<> 149:156823d33999 260 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 149:156823d33999 261 {
<> 149:156823d33999 262 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 263 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 264
<> 149:156823d33999 265 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
<> 149:156823d33999 266
<> 149:156823d33999 267 // Save new values
<> 149:156823d33999 268 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
<> 149:156823d33999 269
<> 149:156823d33999 270 switch (mode) {
<> 149:156823d33999 271 case 0:
<> 149:156823d33999 272 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 273 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 274 break;
<> 149:156823d33999 275 case 1:
<> 149:156823d33999 276 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 277 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 278 break;
<> 149:156823d33999 279 case 2:
<> 149:156823d33999 280 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 281 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 282 break;
<> 149:156823d33999 283 default:
<> 149:156823d33999 284 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 285 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 286 break;
<> 149:156823d33999 287 }
<> 149:156823d33999 288
<> 149:156823d33999 289 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 290 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
<> 149:156823d33999 291 }
<> 149:156823d33999 292
<> 149:156823d33999 293 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
<> 149:156823d33999 294
AnnaBridge 179:b0033dcd6934 295 if (slave && (handle->Init.Direction == SPI_DIRECTION_1LINE)) {
AnnaBridge 179:b0033dcd6934 296 /* SPI slave implemtation in MBED does not support the 3 wires SPI.
AnnaBridge 179:b0033dcd6934 297 * (e.g. when MISO is not connected). So we're forcing slave in
AnnaBridge 179:b0033dcd6934 298 * 2LINES mode. As MISO is not connected, slave will only read
AnnaBridge 179:b0033dcd6934 299 * from master, and cannot write to it. Inform user.
AnnaBridge 179:b0033dcd6934 300 */
AnnaBridge 179:b0033dcd6934 301 debug("3 wires SPI slave not supported - slave will only read\r\n");
AnnaBridge 179:b0033dcd6934 302 handle->Init.Direction = SPI_DIRECTION_2LINES;
AnnaBridge 179:b0033dcd6934 303 }
AnnaBridge 179:b0033dcd6934 304
<> 149:156823d33999 305 init_spi(obj);
<> 149:156823d33999 306 }
<> 149:156823d33999 307
<> 149:156823d33999 308 /*
<> 149:156823d33999 309 * Only the IP clock input is family dependant so it computed
<> 149:156823d33999 310 * separately in spi_get_clock_freq
<> 149:156823d33999 311 */
<> 149:156823d33999 312 extern int spi_get_clock_freq(spi_t *obj);
<> 149:156823d33999 313
<> 149:156823d33999 314 static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
<> 149:156823d33999 315 SPI_BAUDRATEPRESCALER_4,
<> 149:156823d33999 316 SPI_BAUDRATEPRESCALER_8,
<> 149:156823d33999 317 SPI_BAUDRATEPRESCALER_16,
<> 149:156823d33999 318 SPI_BAUDRATEPRESCALER_32,
<> 149:156823d33999 319 SPI_BAUDRATEPRESCALER_64,
<> 149:156823d33999 320 SPI_BAUDRATEPRESCALER_128,
<> 149:156823d33999 321 SPI_BAUDRATEPRESCALER_256};
<> 149:156823d33999 322
<> 149:156823d33999 323 void spi_frequency(spi_t *obj, int hz) {
<> 149:156823d33999 324 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 325 int spi_hz = 0;
<> 149:156823d33999 326 uint8_t prescaler_rank = 0;
<> 159:612c381a210f 327 uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1;
<> 149:156823d33999 328 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 329
<> 159:612c381a210f 330 /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */
<> 159:612c381a210f 331 spi_hz = spi_get_clock_freq(obj) / 2;
<> 149:156823d33999 332
<> 149:156823d33999 333 /* Define pre-scaler in order to get highest available frequency below requested frequency */
<> 159:612c381a210f 334 while ((spi_hz > hz) && (prescaler_rank < last_index)) {
<> 149:156823d33999 335 spi_hz = spi_hz / 2;
<> 149:156823d33999 336 prescaler_rank++;
<> 149:156823d33999 337 }
<> 149:156823d33999 338
<> 159:612c381a210f 339 /* Use the best fit pre-scaler */
<> 159:612c381a210f 340 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank];
<> 159:612c381a210f 341
<> 159:612c381a210f 342 /* In case maximum pre-scaler still gives too high freq, raise an error */
<> 159:612c381a210f 343 if (spi_hz > hz) {
<> 160:d5399cc887bb 344 DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz);
<> 149:156823d33999 345 }
<> 149:156823d33999 346
<> 159:612c381a210f 347 DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz);
<> 159:612c381a210f 348
<> 149:156823d33999 349 init_spi(obj);
<> 149:156823d33999 350 }
<> 149:156823d33999 351
<> 149:156823d33999 352 static inline int ssp_readable(spi_t *obj)
<> 149:156823d33999 353 {
<> 149:156823d33999 354 int status;
<> 149:156823d33999 355 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 356 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 357
<> 149:156823d33999 358 // Check if data is received
<> 149:156823d33999 359 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
<> 149:156823d33999 360 return status;
<> 149:156823d33999 361 }
<> 149:156823d33999 362
<> 149:156823d33999 363 static inline int ssp_writeable(spi_t *obj)
<> 149:156823d33999 364 {
<> 149:156823d33999 365 int status;
<> 149:156823d33999 366 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 367 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 368
<> 149:156823d33999 369 // Check if data is transmitted
<> 149:156823d33999 370 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
<> 149:156823d33999 371 return status;
<> 149:156823d33999 372 }
<> 149:156823d33999 373
<> 149:156823d33999 374 static inline int ssp_busy(spi_t *obj)
<> 149:156823d33999 375 {
<> 149:156823d33999 376 int status;
<> 149:156823d33999 377 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 378 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 379 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
<> 149:156823d33999 380 return status;
<> 149:156823d33999 381 }
<> 149:156823d33999 382
<> 149:156823d33999 383 int spi_master_write(spi_t *obj, int value)
<> 149:156823d33999 384 {
<> 149:156823d33999 385 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 386 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 387
AnnaBridge 173:e131a1973e81 388 if (handle->Init.Direction == SPI_DIRECTION_1LINE) {
AnnaBridge 173:e131a1973e81 389 return HAL_SPI_Transmit(handle, (uint8_t*)&value, 1, TIMEOUT_1_BYTE);
AnnaBridge 173:e131a1973e81 390 }
AnnaBridge 173:e131a1973e81 391
AnnaBridge 168:9672193075cf 392 #if defined(LL_SPI_RX_FIFO_TH_HALF)
AnnaBridge 168:9672193075cf 393 /* Configure the default data size */
AnnaBridge 168:9672193075cf 394 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 168:9672193075cf 395 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF);
AnnaBridge 168:9672193075cf 396 } else {
AnnaBridge 168:9672193075cf 397 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER);
AnnaBridge 168:9672193075cf 398 }
AnnaBridge 168:9672193075cf 399 #endif
<> 149:156823d33999 400
AnnaBridge 168:9672193075cf 401 /* Here we're using LL which means direct registers access
AnnaBridge 168:9672193075cf 402 * There is no error management, so we may end up looping
AnnaBridge 168:9672193075cf 403 * infinitely here in case of faulty device for insatnce,
AnnaBridge 168:9672193075cf 404 * but this will increase performances significantly
AnnaBridge 168:9672193075cf 405 */
<> 149:156823d33999 406
AnnaBridge 168:9672193075cf 407 /* Wait TXE flag to transmit data */
AnnaBridge 168:9672193075cf 408 while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj)));
AnnaBridge 168:9672193075cf 409
AnnaBridge 168:9672193075cf 410 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 168:9672193075cf 411 LL_SPI_TransmitData16(SPI_INST(obj), value);
<> 149:156823d33999 412 } else {
AnnaBridge 168:9672193075cf 413 LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t) value);
AnnaBridge 168:9672193075cf 414 }
AnnaBridge 168:9672193075cf 415
AnnaBridge 168:9672193075cf 416 /* Then wait RXE flag before reading */
AnnaBridge 168:9672193075cf 417 while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj)));
AnnaBridge 168:9672193075cf 418
AnnaBridge 168:9672193075cf 419 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 168:9672193075cf 420 return LL_SPI_ReceiveData16(SPI_INST(obj));
AnnaBridge 168:9672193075cf 421 } else {
AnnaBridge 168:9672193075cf 422 return LL_SPI_ReceiveData8(SPI_INST(obj));
<> 149:156823d33999 423 }
<> 149:156823d33999 424 }
<> 149:156823d33999 425
Kojto 170:19eb464bc2be 426 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 170:19eb464bc2be 427 char *rx_buffer, int rx_length, char write_fill)
AnnaBridge 167:e84263d55307 428 {
AnnaBridge 173:e131a1973e81 429 struct spi_s *spiobj = SPI_S(obj);
AnnaBridge 173:e131a1973e81 430 SPI_HandleTypeDef *handle = &(spiobj->handle);
AnnaBridge 167:e84263d55307 431 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 173:e131a1973e81 432 int i = 0;
AnnaBridge 173:e131a1973e81 433 if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
AnnaBridge 173:e131a1973e81 434 for (i = 0; i < total; i++) {
AnnaBridge 173:e131a1973e81 435 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 173:e131a1973e81 436 char in = spi_master_write(obj, out);
AnnaBridge 173:e131a1973e81 437 if (i < rx_length) {
AnnaBridge 173:e131a1973e81 438 rx_buffer[i] = in;
AnnaBridge 173:e131a1973e81 439 }
AnnaBridge 173:e131a1973e81 440 }
AnnaBridge 173:e131a1973e81 441 } else {
AnnaBridge 173:e131a1973e81 442 /* In case of 1 WIRE only, first handle TX, then Rx */
AnnaBridge 173:e131a1973e81 443 if (tx_length != 0) {
AnnaBridge 173:e131a1973e81 444 if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t*)tx_buffer, tx_length, tx_length*TIMEOUT_1_BYTE)) {
AnnaBridge 173:e131a1973e81 445 /* report an error */
AnnaBridge 173:e131a1973e81 446 total = 0;
AnnaBridge 173:e131a1973e81 447 }
AnnaBridge 173:e131a1973e81 448 }
AnnaBridge 173:e131a1973e81 449 if (rx_length != 0) {
AnnaBridge 173:e131a1973e81 450 if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t*)rx_buffer, rx_length, rx_length*TIMEOUT_1_BYTE)) {
AnnaBridge 173:e131a1973e81 451 /* report an error */
AnnaBridge 173:e131a1973e81 452 total = 0;
AnnaBridge 173:e131a1973e81 453 }
AnnaBridge 167:e84263d55307 454 }
AnnaBridge 167:e84263d55307 455 }
AnnaBridge 167:e84263d55307 456
AnnaBridge 167:e84263d55307 457 return total;
AnnaBridge 167:e84263d55307 458 }
AnnaBridge 167:e84263d55307 459
<> 149:156823d33999 460 int spi_slave_receive(spi_t *obj)
<> 149:156823d33999 461 {
<> 149:156823d33999 462 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
<> 149:156823d33999 463 };
<> 149:156823d33999 464
<> 149:156823d33999 465 int spi_slave_read(spi_t *obj)
<> 149:156823d33999 466 {
<> 149:156823d33999 467 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 468 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 469 while (!ssp_readable(obj));
AnnaBridge 173:e131a1973e81 470 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 173:e131a1973e81 471 return LL_SPI_ReceiveData16(SPI_INST(obj));
<> 149:156823d33999 472 } else {
AnnaBridge 173:e131a1973e81 473 return LL_SPI_ReceiveData8(SPI_INST(obj));
<> 149:156823d33999 474 }
<> 149:156823d33999 475 }
<> 149:156823d33999 476
<> 149:156823d33999 477 void spi_slave_write(spi_t *obj, int value)
<> 149:156823d33999 478 {
<> 149:156823d33999 479 SPI_TypeDef *spi = SPI_INST(obj);
<> 149:156823d33999 480 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 481 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 482 while (!ssp_writeable(obj));
<> 149:156823d33999 483 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 149:156823d33999 484 // Force 8-bit access to the data register
<> 149:156823d33999 485 uint8_t *p_spi_dr = 0;
<> 149:156823d33999 486 p_spi_dr = (uint8_t *) & (spi->DR);
<> 149:156823d33999 487 *p_spi_dr = (uint8_t)value;
<> 149:156823d33999 488 } else { // SPI_DATASIZE_16BIT
<> 149:156823d33999 489 spi->DR = (uint16_t)value;
<> 149:156823d33999 490 }
<> 149:156823d33999 491 }
<> 149:156823d33999 492
<> 149:156823d33999 493 int spi_busy(spi_t *obj)
<> 149:156823d33999 494 {
<> 149:156823d33999 495 return ssp_busy(obj);
<> 149:156823d33999 496 }
<> 149:156823d33999 497
<> 149:156823d33999 498 #ifdef DEVICE_SPI_ASYNCH
<> 149:156823d33999 499 typedef enum {
<> 149:156823d33999 500 SPI_TRANSFER_TYPE_NONE = 0,
<> 149:156823d33999 501 SPI_TRANSFER_TYPE_TX = 1,
<> 149:156823d33999 502 SPI_TRANSFER_TYPE_RX = 2,
<> 149:156823d33999 503 SPI_TRANSFER_TYPE_TXRX = 3,
<> 149:156823d33999 504 } transfer_type_t;
<> 149:156823d33999 505
<> 149:156823d33999 506
<> 149:156823d33999 507 /// @returns the number of bytes transferred, or `0` if nothing transferred
<> 149:156823d33999 508 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
<> 149:156823d33999 509 {
<> 149:156823d33999 510 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 511 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 512 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 513 // the HAL expects number of transfers instead of number of bytes
<> 149:156823d33999 514 // so for 16 bit transfer width the count needs to be halved
<> 149:156823d33999 515 size_t words;
<> 149:156823d33999 516
<> 149:156823d33999 517 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
<> 149:156823d33999 518
<> 149:156823d33999 519 obj->spi.transfer_type = transfer_type;
<> 149:156823d33999 520
<> 149:156823d33999 521 if (is16bit) {
<> 149:156823d33999 522 words = length / 2;
<> 149:156823d33999 523 } else {
<> 149:156823d33999 524 words = length;
<> 149:156823d33999 525 }
<> 149:156823d33999 526
<> 149:156823d33999 527 // enable the interrupt
<> 149:156823d33999 528 IRQn_Type irq_n = spiobj->spiIRQ;
<> 153:fa9ff456f731 529 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 530 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 531 NVIC_SetPriority(irq_n, 1);
<> 149:156823d33999 532 NVIC_EnableIRQ(irq_n);
<> 149:156823d33999 533
AnnaBridge 181:57724642e740 534 // flush FIFO
AnnaBridge 181:57724642e740 535 #if defined(SPI_FLAG_FRLVL) // STM32F0 STM32F3 STM32F7 STM32L4
AnnaBridge 181:57724642e740 536 HAL_SPIEx_FlushRxFifo(handle);
AnnaBridge 181:57724642e740 537 #endif
AnnaBridge 181:57724642e740 538
<> 149:156823d33999 539 // enable the right hal transfer
<> 149:156823d33999 540 int rc = 0;
<> 149:156823d33999 541 switch(transfer_type) {
<> 149:156823d33999 542 case SPI_TRANSFER_TYPE_TXRX:
<> 149:156823d33999 543 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
<> 149:156823d33999 544 break;
<> 149:156823d33999 545 case SPI_TRANSFER_TYPE_TX:
<> 149:156823d33999 546 rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
<> 149:156823d33999 547 break;
<> 149:156823d33999 548 case SPI_TRANSFER_TYPE_RX:
<> 149:156823d33999 549 // the receive function also "transmits" the receive buffer so in order
<> 149:156823d33999 550 // to guarantee that 0xff is on the line, we explicitly memset it here
<> 149:156823d33999 551 memset(rx, SPI_FILL_WORD, length);
<> 149:156823d33999 552 rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
<> 149:156823d33999 553 break;
<> 149:156823d33999 554 default:
<> 149:156823d33999 555 length = 0;
<> 149:156823d33999 556 }
<> 149:156823d33999 557
<> 149:156823d33999 558 if (rc) {
<> 149:156823d33999 559 DEBUG_PRINTF("SPI: RC=%u\n", rc);
<> 149:156823d33999 560 length = 0;
<> 149:156823d33999 561 }
<> 149:156823d33999 562
<> 149:156823d33999 563 return length;
<> 149:156823d33999 564 }
<> 149:156823d33999 565
<> 149:156823d33999 566 // asynchronous API
<> 149:156823d33999 567 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 568 {
<> 149:156823d33999 569 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 570 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 571
<> 149:156823d33999 572 // TODO: DMA usage is currently ignored
<> 149:156823d33999 573 (void) hint;
<> 149:156823d33999 574
<> 149:156823d33999 575 // check which use-case we have
<> 149:156823d33999 576 bool use_tx = (tx != NULL && tx_length > 0);
<> 149:156823d33999 577 bool use_rx = (rx != NULL && rx_length > 0);
<> 149:156823d33999 578 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 579
<> 149:156823d33999 580 // don't do anything, if the buffers aren't valid
<> 149:156823d33999 581 if (!use_tx && !use_rx)
<> 149:156823d33999 582 return;
<> 149:156823d33999 583
<> 149:156823d33999 584 // copy the buffers to the SPI object
<> 149:156823d33999 585 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 586 obj->tx_buff.length = tx_length;
<> 149:156823d33999 587 obj->tx_buff.pos = 0;
<> 149:156823d33999 588 obj->tx_buff.width = is16bit ? 16 : 8;
<> 149:156823d33999 589
<> 149:156823d33999 590 obj->rx_buff.buffer = rx;
<> 149:156823d33999 591 obj->rx_buff.length = rx_length;
<> 149:156823d33999 592 obj->rx_buff.pos = 0;
<> 149:156823d33999 593 obj->rx_buff.width = obj->tx_buff.width;
<> 149:156823d33999 594
<> 149:156823d33999 595 obj->spi.event = event;
<> 149:156823d33999 596
<> 149:156823d33999 597 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
<> 149:156823d33999 598
<> 149:156823d33999 599 // register the thunking handler
<> 149:156823d33999 600 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 601 NVIC_SetVector(irq_n, (uint32_t)handler);
<> 149:156823d33999 602
<> 149:156823d33999 603 // enable the right hal transfer
<> 149:156823d33999 604 if (use_tx && use_rx) {
<> 149:156823d33999 605 // we cannot manage different rx / tx sizes, let's use smaller one
<> 149:156823d33999 606 size_t size = (tx_length < rx_length)? tx_length : rx_length;
<> 149:156823d33999 607 if(tx_length != rx_length) {
<> 149:156823d33999 608 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
<> 149:156823d33999 609 obj->tx_buff.length = size;
<> 149:156823d33999 610 obj->rx_buff.length = size;
<> 149:156823d33999 611 }
<> 149:156823d33999 612 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
<> 149:156823d33999 613 } else if (use_tx) {
<> 149:156823d33999 614 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
<> 149:156823d33999 615 } else if (use_rx) {
<> 149:156823d33999 616 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
<> 149:156823d33999 617 }
<> 149:156823d33999 618 }
<> 149:156823d33999 619
<> 153:fa9ff456f731 620 inline uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 149:156823d33999 621 {
<> 149:156823d33999 622 int event = 0;
<> 149:156823d33999 623
<> 149:156823d33999 624 // call the CubeF4 handler, this will update the handle
<> 153:fa9ff456f731 625 HAL_SPI_IRQHandler(&obj->spi.handle);
<> 149:156823d33999 626
<> 153:fa9ff456f731 627 if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
<> 149:156823d33999 628 // When HAL SPI is back to READY state, check if there was an error
<> 153:fa9ff456f731 629 int error = obj->spi.handle.ErrorCode;
<> 149:156823d33999 630 if(error != HAL_SPI_ERROR_NONE) {
<> 149:156823d33999 631 // something went wrong and the transfer has definitely completed
<> 149:156823d33999 632 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 633
<> 149:156823d33999 634 if (error & HAL_SPI_ERROR_OVR) {
<> 149:156823d33999 635 // buffer overrun
<> 149:156823d33999 636 event |= SPI_EVENT_RX_OVERFLOW;
<> 149:156823d33999 637 }
<> 149:156823d33999 638 } else {
<> 149:156823d33999 639 // else we're done
<> 149:156823d33999 640 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 641 }
<> 153:fa9ff456f731 642 // enable the interrupt
<> 153:fa9ff456f731 643 NVIC_DisableIRQ(obj->spi.spiIRQ);
<> 153:fa9ff456f731 644 NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
<> 149:156823d33999 645 }
<> 149:156823d33999 646
<> 149:156823d33999 647
<> 149:156823d33999 648 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
<> 149:156823d33999 649 }
<> 149:156823d33999 650
<> 149:156823d33999 651 uint8_t spi_active(spi_t *obj)
<> 149:156823d33999 652 {
<> 149:156823d33999 653 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 654 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 655 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
<> 149:156823d33999 656
<> 149:156823d33999 657 switch(state) {
<> 149:156823d33999 658 case HAL_SPI_STATE_RESET:
<> 149:156823d33999 659 case HAL_SPI_STATE_READY:
<> 149:156823d33999 660 case HAL_SPI_STATE_ERROR:
<> 149:156823d33999 661 return 0;
<> 149:156823d33999 662 default:
<> 149:156823d33999 663 return 1;
<> 149:156823d33999 664 }
<> 149:156823d33999 665 }
<> 149:156823d33999 666
<> 149:156823d33999 667 void spi_abort_asynch(spi_t *obj)
<> 149:156823d33999 668 {
<> 149:156823d33999 669 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 670 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 671
<> 149:156823d33999 672 // disable interrupt
<> 149:156823d33999 673 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 674 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 675 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 676
<> 149:156823d33999 677 // clean-up
<> 149:156823d33999 678 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 679 HAL_SPI_DeInit(handle);
<> 149:156823d33999 680 HAL_SPI_Init(handle);
<> 149:156823d33999 681 __HAL_SPI_ENABLE(handle);
<> 149:156823d33999 682 }
<> 149:156823d33999 683
<> 149:156823d33999 684 #endif //DEVICE_SPI_ASYNCH
<> 149:156823d33999 685
<> 149:156823d33999 686 #endif