mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 16:45:37 2018 +0100
Revision:
186:707f6e361f3e
Parent:
174:b96e65c34a4d
Child:
189:f392fc9709a3
mbed-dev library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * @file rtc.c
<> 149:156823d33999 4 * @brief Implementation of a Rtc driver
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3525 $
<> 149:156823d33999 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
<> 149:156823d33999 9 ******************************************************************************
AnnaBridge 167:e84263d55307 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a �ON Semiconductor�).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 167:e84263d55307 14 * (�ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software�) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup rtc
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 * A real-time clock (RTC) is a computer clock ,that keeps track of the current time. The heart of the RTC is a series of
<> 149:156823d33999 31 * freely running counters one for each time unit, The series of counters is linked as follows: a roll over event of
<> 149:156823d33999 32 * the seconds counter produces a minutes enable pulse; a roll over event of the minutes counter produces an hours
<> 149:156823d33999 33 * enable pulse, etc.Note that all Counter registers are in an undefined state on power-up.
<> 149:156823d33999 34 * Use the Reset bit in the Control Register to reset the counters to their default values.
<> 149:156823d33999 35 * DIVISOR is the register containing the value to divide the clock frequency to produce 1Hz strobe ; 1Hz strobe is used
<> 149:156823d33999 36 * internally to time the incrementing of the Seconds Counter.
<> 149:156823d33999 37 * There is a set of register to set the values in the counter for each time unit.from where time is start to increment.
<> 149:156823d33999 38 * There is another set of register to set the ALARM ...Each of the Alarm Registers can be programmed with a value that
<> 149:156823d33999 39 * is used to compare to a Counter Register in order to produce an alarm (an interrupt) when the values match.
<> 149:156823d33999 40 * There is a programmable bit in each Alarm Register that determines if the alarm occurs upon a value match, or
<> 149:156823d33999 41 * if the alarm occurs upon a Counter increment condition.
<> 149:156823d33999 42 *
<> 149:156823d33999 43 */
Anna Bridge 186:707f6e361f3e 44
Anna Bridge 186:707f6e361f3e 45 #ifdef DEVICE_RTC
Anna Bridge 186:707f6e361f3e 46
<> 149:156823d33999 47 #include "rtc.h"
<> 149:156823d33999 48 #include "mbed_assert.h"
<> 150:02e0a0aed4ec 49 #include "lp_ticker_api.h"
<> 149:156823d33999 50
AnnaBridge 167:e84263d55307 51 static volatile uint64_t last_time_read;
AnnaBridge 167:e84263d55307 52
AnnaBridge 167:e84263d55307 53 /**
AnnaBridge 167:e84263d55307 54 * Convert sub seconds ticks to micro seconds.
AnnaBridge 167:e84263d55307 55 * The clock running at 32kHz, a tick is 1/32768 of a second.
AnnaBridge 167:e84263d55307 56 */
AnnaBridge 167:e84263d55307 57 static inline uint32_t ticks_to_us(uint16_t ticks) {
AnnaBridge 167:e84263d55307 58 return (((uint64_t)ticks * RTC_SEC_TO_US) / RTC_CLOCK_HZ);
AnnaBridge 167:e84263d55307 59 }
AnnaBridge 167:e84263d55307 60
AnnaBridge 167:e84263d55307 61 /**
AnnaBridge 167:e84263d55307 62 * Convert us into sub seconds ticks.
AnnaBridge 167:e84263d55307 63 * @note result might be troncated to be in the range [0 - RTC_SUB_SEC_MASK].
AnnaBridge 167:e84263d55307 64 */
AnnaBridge 167:e84263d55307 65 static inline uint16_t us_to_ticks(uint32_t us) {
AnnaBridge 167:e84263d55307 66 return (((uint64_t) us * RTC_CLOCK_HZ) / RTC_SEC_TO_US) & RTC_SUB_SEC_MASK;
AnnaBridge 167:e84263d55307 67 }
AnnaBridge 167:e84263d55307 68
AnnaBridge 167:e84263d55307 69 #define RTC_TICK_THRESHOLD 5
<> 149:156823d33999 70
<> 149:156823d33999 71 /* See rtc.h for details */
<> 149:156823d33999 72 void fRtcInit(void)
<> 149:156823d33999 73 {
<> 149:156823d33999 74 CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
<> 149:156823d33999 75 CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
<> 149:156823d33999 76
<> 149:156823d33999 77 /* Reset RTC control register */
AnnaBridge 167:e84263d55307 78 RTCREG->CONTROL.WORD = 0;
<> 149:156823d33999 79
<> 149:156823d33999 80 /* Initialize all counters */
AnnaBridge 167:e84263d55307 81 RTCREG->SECOND_COUNTER = 0;
AnnaBridge 167:e84263d55307 82 RTCREG->SUB_SECOND_COUNTER = 0;
AnnaBridge 167:e84263d55307 83 RTCREG->SECOND_ALARM = 0;
AnnaBridge 167:e84263d55307 84 RTCREG->SUB_SECOND_ALARM = 0;
AnnaBridge 167:e84263d55307 85 last_time_read = 0;
<> 149:156823d33999 86
<> 149:156823d33999 87 /* Reset RTC Status register */
AnnaBridge 167:e84263d55307 88 RTCREG->STATUS.WORD = 0;
<> 149:156823d33999 89
<> 149:156823d33999 90 /* Clear interrupt status */
AnnaBridge 167:e84263d55307 91 RTCREG->INT_CLEAR.WORD = (
AnnaBridge 167:e84263d55307 92 (1 << RTC_INT_CLR_SUB_SEC_BIT_POS) |
AnnaBridge 167:e84263d55307 93 (1 << RTC_INT_CLR_SEC_BIT_POS)
AnnaBridge 167:e84263d55307 94 );
<> 149:156823d33999 95
AnnaBridge 167:e84263d55307 96 /* Wait previous write to complete */
AnnaBridge 167:e84263d55307 97 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 149:156823d33999 98 /* Start sec & sub_sec counter */
AnnaBridge 167:e84263d55307 99 RTCREG->CONTROL.WORD |= (
AnnaBridge 167:e84263d55307 100 (True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
AnnaBridge 167:e84263d55307 101 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS)
AnnaBridge 167:e84263d55307 102 );
<> 149:156823d33999 103
<> 149:156823d33999 104 /* enable interruption associated with the rtc at NVIC level */
AnnaBridge 167:e84263d55307 105 NVIC_SetVector(Rtc_IRQn,(uint32_t) fRtcHandler); /* TODO define lp_ticker_isr */
<> 149:156823d33999 106 NVIC_ClearPendingIRQ(Rtc_IRQn);
<> 149:156823d33999 107 NVIC_EnableIRQ(Rtc_IRQn);
<> 149:156823d33999 108
AnnaBridge 167:e84263d55307 109 /* Wait for RTC to finish writing register */
AnnaBridge 167:e84263d55307 110 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 149:156823d33999 111 }
<> 149:156823d33999 112
<> 149:156823d33999 113 /* See rtc.h for details */
<> 149:156823d33999 114 void fRtcFree(void)
<> 149:156823d33999 115 {
AnnaBridge 167:e84263d55307 116 /* Disable interrupts and counter */
AnnaBridge 167:e84263d55307 117 RTCREG->CONTROL.WORD = 0;
<> 149:156823d33999 118
<> 149:156823d33999 119 /* disable interruption associated with the rtc */
<> 149:156823d33999 120 NVIC_DisableIRQ(Rtc_IRQn);
<> 149:156823d33999 121
AnnaBridge 167:e84263d55307 122 /* Wait for RTC to finish writing register */
AnnaBridge 167:e84263d55307 123 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 149:156823d33999 124 }
<> 149:156823d33999 125
<> 149:156823d33999 126 /* See rtc.h for details */
<> 149:156823d33999 127 void fRtcSetInterrupt(uint32_t timestamp)
<> 149:156823d33999 128 {
AnnaBridge 167:e84263d55307 129 uint64_t current_time = fRtcRead();
<> 149:156823d33999 130
AnnaBridge 167:e84263d55307 131 uint64_t full_timestamp = (current_time & ~UINT32_MAX) | timestamp;
AnnaBridge 167:e84263d55307 132 if ( (uint32_t)current_time > timestamp) {
AnnaBridge 167:e84263d55307 133 full_timestamp += ((uint64_t) UINT32_MAX) + 1;
AnnaBridge 167:e84263d55307 134 }
<> 149:156823d33999 135
AnnaBridge 167:e84263d55307 136 uint32_t target_seconds = full_timestamp / RTC_SEC_TO_US;
AnnaBridge 167:e84263d55307 137 uint16_t target_ticks = us_to_ticks(full_timestamp);
<> 149:156823d33999 138
AnnaBridge 167:e84263d55307 139 /*
AnnaBridge 167:e84263d55307 140 * If the interrupt is in more than one second from now then use the
AnnaBridge 167:e84263d55307 141 * second alarm, otherwise use the subsecond alarm.
AnnaBridge 167:e84263d55307 142 * In case of the second alarm is used, there is no need to preserve the
AnnaBridge 167:e84263d55307 143 * remaining subsecond because the irq handler should manage spurious
AnnaBridge 167:e84263d55307 144 * interrupts (like when the timestamp is in the past). In such case, irq
AnnaBridge 167:e84263d55307 145 * handler will schedule a new interrupt with the remaining us.
AnnaBridge 167:e84263d55307 146 */
AnnaBridge 167:e84263d55307 147 NVIC_DisableIRQ(Rtc_IRQn);
AnnaBridge 167:e84263d55307 148 if (target_seconds != RTCREG->SECOND_COUNTER) {
AnnaBridge 167:e84263d55307 149 RTCREG->SECOND_ALARM = target_seconds;
<> 149:156823d33999 150
AnnaBridge 167:e84263d55307 151 uint32_t rtc_control = RTCREG->CONTROL.WORD;
AnnaBridge 167:e84263d55307 152 rtc_control |= (1 << RTC_CONTROL_SEC_CNT_INT_BIT_POS); // enable seconds interrupt
AnnaBridge 167:e84263d55307 153 rtc_control &= ~(1 << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); // disable sub sec interrupt
AnnaBridge 167:e84263d55307 154 RTCREG->CONTROL.WORD = rtc_control;
AnnaBridge 167:e84263d55307 155 } else {
AnnaBridge 167:e84263d55307 156 uint16_t current_ticks = RTCREG->SUB_SECOND_COUNTER;
AnnaBridge 167:e84263d55307 157 if (current_ticks == target_ticks ||
AnnaBridge 167:e84263d55307 158 ((target_ticks > current_ticks) && ((target_ticks - current_ticks) < RTC_TICK_THRESHOLD)) ||
AnnaBridge 167:e84263d55307 159 ((target_ticks < current_ticks) && ((RTC_SUB_SEC_MASK - (current_ticks - target_ticks)) < RTC_TICK_THRESHOLD))) {
AnnaBridge 167:e84263d55307 160 // target ticks too close; schedule the interrupt immediately
AnnaBridge 167:e84263d55307 161 NVIC_SetPendingIRQ(Rtc_IRQn);
AnnaBridge 167:e84263d55307 162 } else {
AnnaBridge 167:e84263d55307 163 RTCREG->SUB_SECOND_ALARM = target_ticks;
AnnaBridge 167:e84263d55307 164
AnnaBridge 167:e84263d55307 165 uint32_t rtc_control = RTCREG->CONTROL.WORD;
AnnaBridge 167:e84263d55307 166 rtc_control &= ~(1 << RTC_CONTROL_SEC_CNT_INT_BIT_POS); // disable seconds interrupt
AnnaBridge 167:e84263d55307 167 rtc_control |= (1 << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); // enable sub sec interrupt
AnnaBridge 167:e84263d55307 168 RTCREG->CONTROL.WORD = rtc_control;
AnnaBridge 167:e84263d55307 169 }
AnnaBridge 167:e84263d55307 170 }
AnnaBridge 167:e84263d55307 171 NVIC_EnableIRQ(Rtc_IRQn);
AnnaBridge 167:e84263d55307 172
AnnaBridge 167:e84263d55307 173 /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
AnnaBridge 167:e84263d55307 174 while(RTCREG->STATUS.WORD &
AnnaBridge 167:e84263d55307 175 (
AnnaBridge 167:e84263d55307 176 (True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) |
AnnaBridge 167:e84263d55307 177 (True << RTC_STATUS_SEC_ALARM_WRT_BIT_POS) |
AnnaBridge 167:e84263d55307 178 (True << RTC_STATUS_CONTROL_WRT_BIT_POS)
AnnaBridge 167:e84263d55307 179 )
AnnaBridge 167:e84263d55307 180 );
<> 149:156823d33999 181 }
<> 149:156823d33999 182
<> 149:156823d33999 183 /* See rtc.h for details */
<> 149:156823d33999 184 void fRtcDisableInterrupt(void)
<> 149:156823d33999 185 {
<> 150:02e0a0aed4ec 186 NVIC_DisableIRQ(Rtc_IRQn);
<> 149:156823d33999 187 }
<> 149:156823d33999 188
<> 149:156823d33999 189 /* See rtc.h for details */
<> 149:156823d33999 190 void fRtcEnableInterrupt(void)
<> 149:156823d33999 191 {
<> 150:02e0a0aed4ec 192 NVIC_EnableIRQ(Rtc_IRQn);
<> 149:156823d33999 193 }
<> 149:156823d33999 194
<> 149:156823d33999 195 /* See rtc.h for details */
<> 149:156823d33999 196 void fRtcClearInterrupt(void)
<> 149:156823d33999 197 {
<> 149:156823d33999 198 /* Disable subsec/sec interrupt */
<> 149:156823d33999 199 /* Clear sec & sub_sec interrupts */
<> 149:156823d33999 200 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 149:156823d33999 201 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 150:02e0a0aed4ec 202
<> 150:02e0a0aed4ec 203 while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
AnnaBridge 167:e84263d55307 204 (True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS)))); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 205 }
<> 149:156823d33999 206
<> 149:156823d33999 207 /* See rtc.h for details */
<> 149:156823d33999 208 uint64_t fRtcRead(void)
<> 149:156823d33999 209 {
<> 149:156823d33999 210 /* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
<> 149:156823d33999 211 * That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
<> 149:156823d33999 212 * and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
<> 149:156823d33999 213 * If you read a zero in the sub-second counter then increment the second counter by 1.
<> 149:156823d33999 214 * Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
<> 149:156823d33999 215 */
AnnaBridge 167:e84263d55307 216 uint32_t seconds = RTCREG->SECOND_COUNTER;
AnnaBridge 167:e84263d55307 217 uint16_t ticks = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK;
<> 149:156823d33999 218
AnnaBridge 167:e84263d55307 219 /*
AnnaBridge 167:e84263d55307 220 * If seconds has changed while reading ticks, read them both again.
AnnaBridge 167:e84263d55307 221 */
AnnaBridge 167:e84263d55307 222 while (seconds != RTCREG->SECOND_COUNTER) {
AnnaBridge 167:e84263d55307 223 seconds = RTCREG->SECOND_COUNTER;
AnnaBridge 167:e84263d55307 224 ticks = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK;
AnnaBridge 167:e84263d55307 225 }
<> 149:156823d33999 226
AnnaBridge 167:e84263d55307 227 uint64_t current_time = ((uint64_t) seconds * RTC_SEC_TO_US) + ticks_to_us(ticks);
<> 149:156823d33999 228
<> 149:156823d33999 229 /*check that the time did not go backwards */
AnnaBridge 167:e84263d55307 230 MBED_ASSERT(current_time >= last_time_read);
AnnaBridge 167:e84263d55307 231 last_time_read = current_time;
<> 149:156823d33999 232
AnnaBridge 167:e84263d55307 233 return current_time;
<> 149:156823d33999 234 }
<> 149:156823d33999 235
<> 149:156823d33999 236 /* See rtc.h for details */
<> 149:156823d33999 237 void fRtcWrite(uint64_t RtcTimeus)
<> 149:156823d33999 238 {
<> 150:02e0a0aed4ec 239 uint32_t Second = False;
<> 150:02e0a0aed4ec 240 uint16_t SubSecond = False;
<> 149:156823d33999 241 /* Stop RTC */
<> 149:156823d33999 242 RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 149:156823d33999 243 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 149:156823d33999 244
<> 149:156823d33999 245 if(RtcTimeus > RTC_SEC_TO_US) {
<> 149:156823d33999 246 /* TimeStamp is big enough to set second counter */
<> 149:156823d33999 247 Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
<> 149:156823d33999 248 }
<> 149:156823d33999 249 RTCREG->SECOND_COUNTER = Second;
<> 149:156823d33999 250 RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
<> 149:156823d33999 251 if(RtcTimeus > False) {
<> 149:156823d33999 252 /* Convert TimeStamp to sub_seconds */
<> 149:156823d33999 253 SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
<> 149:156823d33999 254 }
<> 149:156823d33999 255 /* Set SUB_SEC_ALARM */
<> 149:156823d33999 256 RTCREG->SUB_SECOND_COUNTER = SubSecond;
<> 149:156823d33999 257
<> 149:156823d33999 258 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 259 /* Start RTC */
<> 149:156823d33999 260 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 149:156823d33999 261 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 149:156823d33999 262
<> 149:156823d33999 263 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 264 }
<> 149:156823d33999 265
<> 149:156823d33999 266 /* See rtc.h for details */
<> 149:156823d33999 267 void fRtcHandler(void)
<> 149:156823d33999 268 {
<> 149:156823d33999 269 /* Disable RTC interrupt */
<> 149:156823d33999 270 NVIC_DisableIRQ(Rtc_IRQn);
<> 149:156823d33999 271
<> 149:156823d33999 272 /* Clear sec & sub_sec interrupts */
AnnaBridge 167:e84263d55307 273 RTCREG->INT_CLEAR.WORD = (
AnnaBridge 167:e84263d55307 274 (True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
AnnaBridge 167:e84263d55307 275 (True << RTC_INT_CLR_SEC_BIT_POS)
AnnaBridge 167:e84263d55307 276 );
<> 149:156823d33999 277
AnnaBridge 167:e84263d55307 278 /* Disable sub seconds and seconds interrupts */
AnnaBridge 167:e84263d55307 279 RTCREG->CONTROL.WORD &= ~(
AnnaBridge 167:e84263d55307 280 (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
AnnaBridge 167:e84263d55307 281 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS)
AnnaBridge 167:e84263d55307 282 );
<> 149:156823d33999 283
<> 149:156823d33999 284 NVIC_EnableIRQ(Rtc_IRQn);
<> 149:156823d33999 285
AnnaBridge 167:e84263d55307 286 /* Wait for RTC to finish writing registers */
AnnaBridge 167:e84263d55307 287 while(RTCREG->STATUS.WORD &
AnnaBridge 167:e84263d55307 288 (
AnnaBridge 167:e84263d55307 289 (True << RTC_STATUS_CONTROL_WRT_BIT_POS) |
AnnaBridge 167:e84263d55307 290 (True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
AnnaBridge 167:e84263d55307 291 (True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS)
AnnaBridge 167:e84263d55307 292 )
AnnaBridge 167:e84263d55307 293 );
<> 149:156823d33999 294
<> 149:156823d33999 295 lp_ticker_irq_handler();
<> 149:156823d33999 296 }
<> 149:156823d33999 297
<> 149:156823d33999 298 boolean fIsRtcEnabled(void)
<> 149:156823d33999 299 {
<> 149:156823d33999 300 if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) {
<> 149:156823d33999 301 return True;
<> 149:156823d33999 302 } else {
<> 149:156823d33999 303 return False;
<> 149:156823d33999 304 }
<> 149:156823d33999 305 }
Anna Bridge 186:707f6e361f3e 306
Anna Bridge 186:707f6e361f3e 307 #endif