mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_M451/spi_api.c@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 16:45:37 2018 +0100
Revision:
186:707f6e361f3e
Parent:
176:447f873cad2f 
mbed-dev library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "spi_api.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_SPI
<> 149:156823d33999 20
<> 149:156823d33999 21 #include "cmsis.h"
<> 149:156823d33999 22 #include "pinmap.h"
<> 149:156823d33999 23 #include "PeripheralPins.h"
<> 149:156823d33999 24 #include "nu_modutil.h"
<> 149:156823d33999 25 #include "nu_miscutil.h"
<> 149:156823d33999 26 #include "nu_bitutil.h"
<> 149:156823d33999 27
<> 149:156823d33999 28 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 29 #include "dma_api.h"
<> 149:156823d33999 30 #include "dma.h"
<> 149:156823d33999 31 #endif
<> 149:156823d33999 32
<> 149:156823d33999 33 #define NU_SPI_FRAME_MIN 8
<> 149:156823d33999 34 #define NU_SPI_FRAME_MAX 32
<> 149:156823d33999 35 #define NU_SPI_FIFO_DEPTH 8
<> 149:156823d33999 36
<> 149:156823d33999 37 struct nu_spi_var {
<> 149:156823d33999 38 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 39 uint8_t pdma_perp_tx;
<> 149:156823d33999 40 uint8_t pdma_perp_rx;
<> 149:156823d33999 41 #endif
<> 149:156823d33999 42 };
<> 149:156823d33999 43
<> 149:156823d33999 44 static struct nu_spi_var spi0_var = {
<> 149:156823d33999 45 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 46 .pdma_perp_tx = PDMA_SPI0_TX,
<> 149:156823d33999 47 .pdma_perp_rx = PDMA_SPI0_RX
<> 149:156823d33999 48 #endif
<> 149:156823d33999 49 };
<> 149:156823d33999 50 static struct nu_spi_var spi1_var = {
<> 149:156823d33999 51 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 52 .pdma_perp_tx = PDMA_SPI1_TX,
<> 149:156823d33999 53 .pdma_perp_rx = PDMA_SPI1_RX
<> 149:156823d33999 54 #endif
<> 149:156823d33999 55 };
<> 149:156823d33999 56 static struct nu_spi_var spi2_var = {
<> 149:156823d33999 57 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 58 .pdma_perp_tx = PDMA_SPI2_TX,
<> 149:156823d33999 59 .pdma_perp_rx = PDMA_SPI2_RX
<> 149:156823d33999 60 #endif
<> 149:156823d33999 61 };
<> 149:156823d33999 62
Anna Bridge 186:707f6e361f3e 63 /* Synchronous version of SPI_ENABLE()/SPI_DISABLE() macros
Anna Bridge 186:707f6e361f3e 64 *
Anna Bridge 186:707f6e361f3e 65 * The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI
Anna Bridge 186:707f6e361f3e 66 * control logic is enabled/disabled, this bit indicates the real status of SPI controller.
Anna Bridge 186:707f6e361f3e 67 *
Anna Bridge 186:707f6e361f3e 68 * NOTE: All configurations shall be ready before calling SPI_ENABLE_SYNC().
Anna Bridge 186:707f6e361f3e 69 * NOTE: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers,
Anna Bridge 186:707f6e361f3e 70 * user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0
Anna Bridge 186:707f6e361f3e 71 * (by SPI_DISABLE_SYNC here).
Anna Bridge 186:707f6e361f3e 72 */
Anna Bridge 186:707f6e361f3e 73 __STATIC_INLINE void SPI_ENABLE_SYNC(SPI_T *spi_base)
Anna Bridge 186:707f6e361f3e 74 {
Anna Bridge 186:707f6e361f3e 75 if (! (spi_base->CTL & SPI_CTL_SPIEN_Msk)) {
Anna Bridge 186:707f6e361f3e 76 SPI_ENABLE(spi_base);
Anna Bridge 186:707f6e361f3e 77 }
Anna Bridge 186:707f6e361f3e 78 while (! (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk));
Anna Bridge 186:707f6e361f3e 79 }
Anna Bridge 186:707f6e361f3e 80 __STATIC_INLINE void SPI_DISABLE_SYNC(SPI_T *spi_base)
Anna Bridge 186:707f6e361f3e 81 {
Anna Bridge 186:707f6e361f3e 82 if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
Anna Bridge 186:707f6e361f3e 83 // NOTE: SPI H/W may get out of state without the busy check.
Anna Bridge 186:707f6e361f3e 84 while (SPI_IS_BUSY(spi_base));
Anna Bridge 186:707f6e361f3e 85
Anna Bridge 186:707f6e361f3e 86 SPI_DISABLE(spi_base);
Anna Bridge 186:707f6e361f3e 87 }
Anna Bridge 186:707f6e361f3e 88 while (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk);
Anna Bridge 186:707f6e361f3e 89 }
Anna Bridge 186:707f6e361f3e 90
<> 149:156823d33999 91 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 92 static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
<> 149:156823d33999 93 static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable);
<> 149:156823d33999 94 static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
<> 149:156823d33999 95 static uint32_t spi_master_read_asynch(spi_t *obj);
<> 149:156823d33999 96 static uint32_t spi_event_check(spi_t *obj);
<> 149:156823d33999 97 static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
<> 149:156823d33999 98 static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
<> 149:156823d33999 99 static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
<> 149:156823d33999 100 static uint8_t spi_get_data_width(spi_t *obj);
<> 149:156823d33999 101 static int spi_is_tx_complete(spi_t *obj);
<> 149:156823d33999 102 static int spi_is_rx_complete(spi_t *obj);
<> 149:156823d33999 103 static int spi_writeable(spi_t * obj);
<> 149:156823d33999 104 static int spi_readable(spi_t * obj);
<> 149:156823d33999 105 static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
<> 149:156823d33999 106 static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
<> 149:156823d33999 107 #endif
<> 149:156823d33999 108
<> 149:156823d33999 109 static uint32_t spi_modinit_mask = 0;
<> 149:156823d33999 110
<> 149:156823d33999 111 static const struct nu_modinit_s spi_modinit_tab[] = {
<> 149:156823d33999 112 {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var},
<> 149:156823d33999 113 {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK1, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var},
<> 149:156823d33999 114 {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK0, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var},
Anna Bridge 186:707f6e361f3e 115
<> 149:156823d33999 116 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
<> 149:156823d33999 117 };
<> 149:156823d33999 118
<> 149:156823d33999 119 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 149:156823d33999 120 // Determine which SPI_x the pins are used for
<> 149:156823d33999 121 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 122 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 149:156823d33999 123 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 124 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 125 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
<> 149:156823d33999 126 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
<> 149:156823d33999 127 obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl);
<> 149:156823d33999 128 MBED_ASSERT((int)obj->spi.spi != NC);
<> 149:156823d33999 129
<> 149:156823d33999 130 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
<> 149:156823d33999 131 MBED_ASSERT(modinit != NULL);
Anna Bridge 186:707f6e361f3e 132 MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
Anna Bridge 186:707f6e361f3e 133
<> 149:156823d33999 134 // Reset this module
<> 149:156823d33999 135 SYS_ResetModule(modinit->rsetidx);
Anna Bridge 186:707f6e361f3e 136
<> 149:156823d33999 137 // Select IP clock source
<> 149:156823d33999 138 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
<> 149:156823d33999 139 // Enable IP clock
<> 149:156823d33999 140 CLK_EnableModuleClock(modinit->clkidx);
<> 149:156823d33999 141
<> 149:156823d33999 142 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 143 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 149:156823d33999 144 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 145 pinmap_pinout(ssel, PinMap_SPI_SSEL);
Anna Bridge 186:707f6e361f3e 146
<> 149:156823d33999 147 obj->spi.pin_mosi = mosi;
<> 149:156823d33999 148 obj->spi.pin_miso = miso;
<> 149:156823d33999 149 obj->spi.pin_sclk = sclk;
<> 149:156823d33999 150 obj->spi.pin_ssel = ssel;
<> 149:156823d33999 151
Anna Bridge 186:707f6e361f3e 152
<> 149:156823d33999 153 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 154 obj->spi.dma_usage = DMA_USAGE_NEVER;
<> 149:156823d33999 155 obj->spi.event = 0;
<> 149:156823d33999 156 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 157 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
Anna Bridge 186:707f6e361f3e 158
Anna Bridge 186:707f6e361f3e 159 /* NOTE: We use vector to judge if asynchronous transfer is on-going (spi_active).
Anna Bridge 186:707f6e361f3e 160 * At initial time, asynchronous transfer is not on-going and so vector must
Anna Bridge 186:707f6e361f3e 161 * be cleared to zero for correct judgement. */
Anna Bridge 186:707f6e361f3e 162 NVIC_SetVector(modinit->irq_n, 0);
<> 149:156823d33999 163 #endif
<> 149:156823d33999 164
<> 149:156823d33999 165 // Mark this module to be inited.
<> 149:156823d33999 166 int i = modinit - spi_modinit_tab;
<> 149:156823d33999 167 spi_modinit_mask |= 1 << i;
<> 149:156823d33999 168 }
<> 149:156823d33999 169
<> 149:156823d33999 170 void spi_free(spi_t *obj)
<> 149:156823d33999 171 {
<> 149:156823d33999 172 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 173 if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 174 dma_channel_free(obj->spi.dma_chn_id_tx);
<> 149:156823d33999 175 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 176 }
<> 149:156823d33999 177 if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 178 dma_channel_free(obj->spi.dma_chn_id_rx);
<> 149:156823d33999 179 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 180 }
<> 149:156823d33999 181 #endif
<> 149:156823d33999 182
<> 149:156823d33999 183 SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
Anna Bridge 186:707f6e361f3e 184
<> 149:156823d33999 185 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
<> 149:156823d33999 186 MBED_ASSERT(modinit != NULL);
Anna Bridge 186:707f6e361f3e 187 MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
Anna Bridge 186:707f6e361f3e 188
<> 149:156823d33999 189 SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK));
<> 149:156823d33999 190 NVIC_DisableIRQ(modinit->irq_n);
Anna Bridge 186:707f6e361f3e 191
<> 149:156823d33999 192 // Disable IP clock
<> 149:156823d33999 193 CLK_DisableModuleClock(modinit->clkidx);
Anna Bridge 186:707f6e361f3e 194
<> 149:156823d33999 195 // Mark this module to be deinited.
<> 149:156823d33999 196 int i = modinit - spi_modinit_tab;
<> 149:156823d33999 197 spi_modinit_mask &= ~(1 << i);
<> 149:156823d33999 198 }
Anna Bridge 186:707f6e361f3e 199
<> 149:156823d33999 200 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 149:156823d33999 201 {
<> 149:156823d33999 202 MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
Anna Bridge 186:707f6e361f3e 203
<> 149:156823d33999 204 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 205
Anna Bridge 186:707f6e361f3e 206 SPI_DISABLE_SYNC(spi_base);
<> 149:156823d33999 207
<> 149:156823d33999 208 SPI_Open(spi_base,
<> 149:156823d33999 209 slave ? SPI_SLAVE : SPI_MASTER,
<> 149:156823d33999 210 (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
<> 149:156823d33999 211 bits,
<> 149:156823d33999 212 SPI_GetBusClock(spi_base));
<> 149:156823d33999 213 // NOTE: Hardcode to be MSB first.
<> 149:156823d33999 214 SPI_SET_MSB_FIRST(spi_base);
<> 149:156823d33999 215
<> 149:156823d33999 216 if (! slave) {
<> 149:156823d33999 217 // Master
<> 149:156823d33999 218 if (obj->spi.pin_ssel != NC) {
Anna Bridge 186:707f6e361f3e 219 // Configure SS as low active.
<> 149:156823d33999 220 SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW);
<> 149:156823d33999 221 }
<> 149:156823d33999 222 else {
<> 149:156823d33999 223 SPI_DisableAutoSS(spi_base);
<> 149:156823d33999 224 }
<> 149:156823d33999 225 }
<> 149:156823d33999 226 else {
<> 149:156823d33999 227 // Slave
<> 149:156823d33999 228 // Configure SS as low active.
<> 149:156823d33999 229 spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
<> 149:156823d33999 230 }
<> 149:156823d33999 231
Anna Bridge 186:707f6e361f3e 232 /* NOTE: M451's/M480's/M2351's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk).
Anna Bridge 186:707f6e361f3e 233 * We cannot use SPI_CTL_SPIEN_Msk for judgement of spi_active().
Anna Bridge 186:707f6e361f3e 234 * Judge with vector instead. */
<> 149:156823d33999 235 }
<> 149:156823d33999 236
<> 149:156823d33999 237 void spi_frequency(spi_t *obj, int hz)
<> 149:156823d33999 238 {
<> 149:156823d33999 239 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 240
Anna Bridge 186:707f6e361f3e 241 SPI_DISABLE_SYNC(spi_base);
<> 149:156823d33999 242
<> 149:156823d33999 243 SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
<> 149:156823d33999 244 }
<> 149:156823d33999 245
<> 149:156823d33999 246
<> 149:156823d33999 247 int spi_master_write(spi_t *obj, int value)
<> 149:156823d33999 248 {
<> 149:156823d33999 249 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 250
<> 149:156823d33999 251 // NOTE: Data in receive FIFO can be read out via ICE.
Anna Bridge 186:707f6e361f3e 252 SPI_ENABLE_SYNC(spi_base);
Anna Bridge 186:707f6e361f3e 253
<> 149:156823d33999 254 // Wait for tx buffer empty
<> 149:156823d33999 255 while(! spi_writeable(obj));
<> 149:156823d33999 256 SPI_WRITE_TX(spi_base, value);
<> 149:156823d33999 257
<> 149:156823d33999 258 // Wait for rx buffer full
<> 149:156823d33999 259 while (! spi_readable(obj));
<> 149:156823d33999 260 int value2 = SPI_READ_RX(spi_base);
Anna Bridge 186:707f6e361f3e 261
Anna Bridge 186:707f6e361f3e 262 /* We don't call SPI_DISABLE_SYNC here for performance. */
Anna Bridge 186:707f6e361f3e 263
<> 149:156823d33999 264 return value2;
<> 149:156823d33999 265 }
<> 149:156823d33999 266
Kojto 170:19eb464bc2be 267 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 170:19eb464bc2be 268 char *rx_buffer, int rx_length, char write_fill) {
AnnaBridge 167:e84263d55307 269 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 167:e84263d55307 270
AnnaBridge 167:e84263d55307 271 for (int i = 0; i < total; i++) {
Kojto 170:19eb464bc2be 272 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 167:e84263d55307 273 char in = spi_master_write(obj, out);
AnnaBridge 167:e84263d55307 274 if (i < rx_length) {
AnnaBridge 167:e84263d55307 275 rx_buffer[i] = in;
AnnaBridge 167:e84263d55307 276 }
AnnaBridge 167:e84263d55307 277 }
AnnaBridge 167:e84263d55307 278
AnnaBridge 167:e84263d55307 279 return total;
AnnaBridge 167:e84263d55307 280 }
AnnaBridge 167:e84263d55307 281
<> 149:156823d33999 282 #if DEVICE_SPISLAVE
<> 149:156823d33999 283 int spi_slave_receive(spi_t *obj)
<> 149:156823d33999 284 {
<> 149:156823d33999 285 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 286
Anna Bridge 186:707f6e361f3e 287 SPI_ENABLE_SYNC(spi_base);
Anna Bridge 186:707f6e361f3e 288
<> 149:156823d33999 289 return spi_readable(obj);
<> 149:156823d33999 290 };
<> 149:156823d33999 291
<> 149:156823d33999 292 int spi_slave_read(spi_t *obj)
<> 149:156823d33999 293 {
<> 149:156823d33999 294 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 295
Anna Bridge 186:707f6e361f3e 296 SPI_ENABLE_SYNC(spi_base);
Anna Bridge 186:707f6e361f3e 297
<> 149:156823d33999 298 // Wait for rx buffer full
<> 149:156823d33999 299 while (! spi_readable(obj));
<> 149:156823d33999 300 int value = SPI_READ_RX(spi_base);
<> 149:156823d33999 301 return value;
<> 149:156823d33999 302 }
<> 149:156823d33999 303
<> 149:156823d33999 304 void spi_slave_write(spi_t *obj, int value)
<> 149:156823d33999 305 {
<> 149:156823d33999 306 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 307
Anna Bridge 186:707f6e361f3e 308 SPI_ENABLE_SYNC(spi_base);
Anna Bridge 186:707f6e361f3e 309
<> 149:156823d33999 310 // Wait for tx buffer empty
<> 149:156823d33999 311 while(! spi_writeable(obj));
<> 149:156823d33999 312 SPI_WRITE_TX(spi_base, value);
<> 149:156823d33999 313 }
<> 149:156823d33999 314 #endif
<> 149:156823d33999 315
<> 149:156823d33999 316 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 317 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 318 {
<> 149:156823d33999 319 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
<> 149:156823d33999 320 SPI_SET_DATA_WIDTH(spi_base, bit_width);
<> 149:156823d33999 321
<> 149:156823d33999 322 obj->spi.dma_usage = hint;
<> 149:156823d33999 323 spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
<> 149:156823d33999 324 uint32_t data_width = spi_get_data_width(obj);
<> 149:156823d33999 325 // Conditions to go DMA way:
<> 149:156823d33999 326 // (1) No DMA support for non-8 multiple data width.
<> 149:156823d33999 327 // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
<> 149:156823d33999 328 if ((data_width % 8) ||
<> 149:156823d33999 329 (tx_length < rx_length)) {
<> 149:156823d33999 330 obj->spi.dma_usage = DMA_USAGE_NEVER;
<> 149:156823d33999 331 dma_channel_free(obj->spi.dma_chn_id_tx);
<> 149:156823d33999 332 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 333 dma_channel_free(obj->spi.dma_chn_id_rx);
<> 149:156823d33999 334 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 335 }
Anna Bridge 186:707f6e361f3e 336
<> 149:156823d33999 337 // SPI IRQ is necessary for both interrupt way and DMA way
<> 149:156823d33999 338 spi_enable_event(obj, event, 1);
<> 149:156823d33999 339 spi_buffer_set(obj, tx, tx_length, rx, rx_length);
Anna Bridge 186:707f6e361f3e 340
Anna Bridge 186:707f6e361f3e 341 SPI_ENABLE_SYNC(spi_base);
Anna Bridge 186:707f6e361f3e 342
<> 149:156823d33999 343 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
<> 149:156823d33999 344 // Interrupt way
<> 149:156823d33999 345 spi_master_write_asynch(obj, NU_SPI_FIFO_DEPTH / 2);
<> 149:156823d33999 346 spi_enable_vector_interrupt(obj, handler, 1);
<> 149:156823d33999 347 spi_master_enable_interrupt(obj, 1);
<> 149:156823d33999 348 } else {
<> 149:156823d33999 349 // DMA way
<> 149:156823d33999 350 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
<> 149:156823d33999 351 MBED_ASSERT(modinit != NULL);
Anna Bridge 186:707f6e361f3e 352 MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
Anna Bridge 186:707f6e361f3e 353
<> 161:2cc1468da177 354 PDMA_T *pdma_base = dma_modbase();
Anna Bridge 186:707f6e361f3e 355
<> 149:156823d33999 356 // Configure tx DMA
<> 161:2cc1468da177 357 pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
<> 149:156823d33999 358 PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
<> 149:156823d33999 359 ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
<> 149:156823d33999 360 0, // Scatter-gather disabled
<> 149:156823d33999 361 0); // Scatter-gather descriptor address
<> 149:156823d33999 362 PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx,
<> 149:156823d33999 363 (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 149:156823d33999 364 tx_length);
<> 149:156823d33999 365 PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
<> 149:156823d33999 366 (uint32_t) tx, // NOTE:
<> 149:156823d33999 367 // NUC472: End of source address
<> 149:156823d33999 368 // M451: Start of source address
<> 149:156823d33999 369 PDMA_SAR_INC, // Source address incremental
<> 149:156823d33999 370 (uint32_t) &spi_base->TX, // Destination address
<> 149:156823d33999 371 PDMA_DAR_FIX); // Destination address fixed
<> 149:156823d33999 372 PDMA_SetBurstType(obj->spi.dma_chn_id_tx,
<> 149:156823d33999 373 PDMA_REQ_SINGLE, // Single mode
<> 149:156823d33999 374 0); // Burst size
<> 149:156823d33999 375 PDMA_EnableInt(obj->spi.dma_chn_id_tx,
<> 149:156823d33999 376 PDMA_INT_TRANS_DONE); // Interrupt type
<> 149:156823d33999 377 // Register DMA event handler
<> 149:156823d33999 378 dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
Anna Bridge 186:707f6e361f3e 379
<> 149:156823d33999 380 // Configure rx DMA
<> 161:2cc1468da177 381 pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
<> 149:156823d33999 382 PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
<> 149:156823d33999 383 ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
<> 149:156823d33999 384 0, // Scatter-gather disabled
<> 149:156823d33999 385 0); // Scatter-gather descriptor address
<> 149:156823d33999 386 PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx,
<> 149:156823d33999 387 (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 149:156823d33999 388 rx_length);
<> 149:156823d33999 389 PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
<> 149:156823d33999 390 (uint32_t) &spi_base->RX, // Source address
<> 149:156823d33999 391 PDMA_SAR_FIX, // Source address fixed
<> 149:156823d33999 392 (uint32_t) rx, // NOTE:
<> 149:156823d33999 393 // NUC472: End of destination address
<> 149:156823d33999 394 // M451: Start of destination address
<> 149:156823d33999 395 PDMA_DAR_INC); // Destination address incremental
<> 149:156823d33999 396 PDMA_SetBurstType(obj->spi.dma_chn_id_rx,
<> 149:156823d33999 397 PDMA_REQ_SINGLE, // Single mode
<> 149:156823d33999 398 0); // Burst size
<> 149:156823d33999 399 PDMA_EnableInt(obj->spi.dma_chn_id_rx,
<> 149:156823d33999 400 PDMA_INT_TRANS_DONE); // Interrupt type
<> 149:156823d33999 401 // Register DMA event handler
<> 149:156823d33999 402 dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
Anna Bridge 186:707f6e361f3e 403
Anna Bridge 186:707f6e361f3e 404 /* Start tx/rx DMA transfer
Anna Bridge 186:707f6e361f3e 405 *
Anna Bridge 186:707f6e361f3e 406 * If we have both PDMA and SPI interrupts enabled and PDMA priority is lower than SPI priority,
Anna Bridge 186:707f6e361f3e 407 * we would trap in SPI interrupt handler endlessly with the sequence:
Anna Bridge 186:707f6e361f3e 408 *
Anna Bridge 186:707f6e361f3e 409 * 1. PDMA TX transfer done interrupt occurs and is well handled.
Anna Bridge 186:707f6e361f3e 410 * 2. SPI RX FIFO threshold interrupt occurs. Trap here because PDMA RX transfer done interrupt doesn't get handled.
Anna Bridge 186:707f6e361f3e 411 * 3. PDMA RX transfer done interrupt occurs but it cannot be handled due to above.
Anna Bridge 186:707f6e361f3e 412 *
Anna Bridge 186:707f6e361f3e 413 * To fix it, we don't enable SPI TX/RX threshold interrupts but keep SPI vector handler set to be called
Anna Bridge 186:707f6e361f3e 414 * in PDMA TX/RX transfer done interrupt handlers (spi_dma_handler_tx/spi_dma_handler_rx).
Anna Bridge 186:707f6e361f3e 415 */
Anna Bridge 186:707f6e361f3e 416 NVIC_SetVector(modinit->irq_n, handler);
Anna Bridge 186:707f6e361f3e 417
Anna Bridge 186:707f6e361f3e 418 /* Order to enable PDMA TX/RX functions
Anna Bridge 186:707f6e361f3e 419 *
Anna Bridge 186:707f6e361f3e 420 * H/W spec: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are
Anna Bridge 186:707f6e361f3e 421 * enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable
Anna Bridge 186:707f6e361f3e 422 * TX PDMA function firstly or enable both functions simultaneously.
Anna Bridge 186:707f6e361f3e 423 * Per real test, it is safer to start RX PDMA first and then TX PDMA. Otherwise, receive FIFO is
Anna Bridge 186:707f6e361f3e 424 * subject to overflow by TX DMA.
Anna Bridge 186:707f6e361f3e 425 *
Anna Bridge 186:707f6e361f3e 426 * With the above conflicts, we enable PDMA TX/RX functions simultaneously.
Anna Bridge 186:707f6e361f3e 427 */
Anna Bridge 186:707f6e361f3e 428 spi_base->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk);
Anna Bridge 186:707f6e361f3e 429
Anna Bridge 186:707f6e361f3e 430 /* Don't enable SPI TX/RX threshold interrupts as commented above */
<> 149:156823d33999 431 }
<> 149:156823d33999 432 }
<> 149:156823d33999 433
<> 149:156823d33999 434 /**
<> 149:156823d33999 435 * Abort an SPI transfer
<> 149:156823d33999 436 * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
<> 149:156823d33999 437 * transfers
<> 149:156823d33999 438 * @param[in] obj The SPI peripheral to stop
<> 149:156823d33999 439 */
<> 149:156823d33999 440 void spi_abort_asynch(spi_t *obj)
<> 149:156823d33999 441 {
<> 149:156823d33999 442 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
<> 161:2cc1468da177 443 PDMA_T *pdma_base = dma_modbase();
Anna Bridge 186:707f6e361f3e 444
<> 149:156823d33999 445 if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
<> 149:156823d33999 446 // Receive FIFO Overrun in case of tx length > rx length on DMA way
<> 149:156823d33999 447 if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
<> 149:156823d33999 448 spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
<> 149:156823d33999 449 }
Anna Bridge 186:707f6e361f3e 450
<> 149:156823d33999 451 if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 161:2cc1468da177 452 PDMA_DisableInt(obj->spi.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
Anna Bridge 186:707f6e361f3e 453 // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 161:2cc1468da177 454 pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
<> 149:156823d33999 455 }
<> 149:156823d33999 456 SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
Anna Bridge 186:707f6e361f3e 457
<> 149:156823d33999 458 if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 161:2cc1468da177 459 PDMA_DisableInt(obj->spi.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
Anna Bridge 186:707f6e361f3e 460 // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 161:2cc1468da177 461 pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
<> 149:156823d33999 462 }
<> 149:156823d33999 463 SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
<> 149:156823d33999 464 }
Anna Bridge 186:707f6e361f3e 465
<> 149:156823d33999 466 // Necessary for both interrupt way and DMA way
<> 149:156823d33999 467 spi_enable_vector_interrupt(obj, 0, 0);
<> 149:156823d33999 468 spi_master_enable_interrupt(obj, 0);
<> 149:156823d33999 469
Anna Bridge 186:707f6e361f3e 470 /* Necessary for accessing FIFOCTL below */
Anna Bridge 186:707f6e361f3e 471 SPI_DISABLE_SYNC(spi_base);
Anna Bridge 186:707f6e361f3e 472
<> 149:156823d33999 473 SPI_ClearRxFIFO(spi_base);
<> 149:156823d33999 474 SPI_ClearTxFIFO(spi_base);
<> 149:156823d33999 475 }
<> 149:156823d33999 476
<> 149:156823d33999 477 /**
<> 149:156823d33999 478 * Handle the SPI interrupt
<> 149:156823d33999 479 * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way,
<> 149:156823d33999 480 * it is unlikely that the RX FIFO will overflow.
<> 149:156823d33999 481 * @param[in] obj The SPI peripheral that generated the interrupt
<> 149:156823d33999 482 * @return
<> 149:156823d33999 483 */
<> 149:156823d33999 484 uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 149:156823d33999 485 {
<> 149:156823d33999 486 // Check for SPI events
<> 149:156823d33999 487 uint32_t event = spi_event_check(obj);
<> 149:156823d33999 488 if (event) {
<> 149:156823d33999 489 spi_abort_asynch(obj);
<> 149:156823d33999 490 }
<> 149:156823d33999 491
<> 149:156823d33999 492 return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
<> 149:156823d33999 493 }
<> 149:156823d33999 494
<> 149:156823d33999 495 uint8_t spi_active(spi_t *obj)
<> 149:156823d33999 496 {
Anna Bridge 186:707f6e361f3e 497 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
Anna Bridge 186:707f6e361f3e 498 MBED_ASSERT(modinit != NULL);
Anna Bridge 186:707f6e361f3e 499 MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
Anna Bridge 186:707f6e361f3e 500
Anna Bridge 186:707f6e361f3e 501 /* Vector will be cleared when asynchronous transfer is finished or aborted.
Anna Bridge 186:707f6e361f3e 502 Use it to judge if asynchronous transfer is on-going. */
Anna Bridge 186:707f6e361f3e 503 uint32_t vec = NVIC_GetVector(modinit->irq_n);
Anna Bridge 186:707f6e361f3e 504 return vec ? 1 : 0;
<> 149:156823d33999 505 }
<> 149:156823d33999 506
<> 149:156823d33999 507 static int spi_writeable(spi_t * obj)
<> 149:156823d33999 508 {
<> 149:156823d33999 509 // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
<> 149:156823d33999 510 return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
<> 149:156823d33999 511 }
<> 149:156823d33999 512
<> 149:156823d33999 513 static int spi_readable(spi_t * obj)
<> 149:156823d33999 514 {
<> 149:156823d33999 515 return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
<> 149:156823d33999 516 }
<> 149:156823d33999 517
<> 149:156823d33999 518 static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
Anna Bridge 186:707f6e361f3e 519 {
<> 149:156823d33999 520 obj->spi.event &= ~SPI_EVENT_ALL;
<> 149:156823d33999 521 obj->spi.event |= (event & SPI_EVENT_ALL);
<> 149:156823d33999 522 if (event & SPI_EVENT_RX_OVERFLOW) {
<> 149:156823d33999 523 SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK);
<> 149:156823d33999 524 }
<> 149:156823d33999 525 }
<> 149:156823d33999 526
<> 149:156823d33999 527 static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
<> 149:156823d33999 528 {
<> 149:156823d33999 529 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
<> 149:156823d33999 530 MBED_ASSERT(modinit != NULL);
Anna Bridge 186:707f6e361f3e 531 MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
Anna Bridge 186:707f6e361f3e 532
<> 149:156823d33999 533 if (enable) {
<> 149:156823d33999 534 NVIC_SetVector(modinit->irq_n, handler);
<> 149:156823d33999 535 NVIC_EnableIRQ(modinit->irq_n);
<> 149:156823d33999 536 }
<> 149:156823d33999 537 else {
<> 149:156823d33999 538 NVIC_DisableIRQ(modinit->irq_n);
Anna Bridge 186:707f6e361f3e 539 NVIC_SetVector(modinit->irq_n, 0);
<> 149:156823d33999 540 }
<> 149:156823d33999 541 }
<> 149:156823d33999 542
<> 149:156823d33999 543 static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
Anna Bridge 186:707f6e361f3e 544 {
<> 149:156823d33999 545 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 546
<> 149:156823d33999 547 if (enable) {
<> 149:156823d33999 548 // For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
<> 149:156823d33999 549 if (spi_base == (SPI_T *) SPI0_BASE) {
<> 149:156823d33999 550 SPI_SetFIFO(spi_base, 4, 4);
<> 149:156823d33999 551 }
<> 149:156823d33999 552 else {
<> 149:156823d33999 553 SPI_SetFIFO(spi_base, 2, 2);
<> 149:156823d33999 554 }
Anna Bridge 186:707f6e361f3e 555
<> 149:156823d33999 556 // Enable tx/rx FIFO threshold interrupt
<> 149:156823d33999 557 SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
<> 149:156823d33999 558 }
<> 149:156823d33999 559 else {
<> 149:156823d33999 560 SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
<> 149:156823d33999 561 }
<> 149:156823d33999 562 }
<> 149:156823d33999 563
<> 149:156823d33999 564 static uint32_t spi_event_check(spi_t *obj)
<> 149:156823d33999 565 {
<> 149:156823d33999 566 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
<> 149:156823d33999 567 uint32_t event = 0;
Anna Bridge 186:707f6e361f3e 568
<> 149:156823d33999 569 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
<> 149:156823d33999 570 uint32_t n_rec = spi_master_read_asynch(obj);
<> 149:156823d33999 571 spi_master_write_asynch(obj, n_rec);
<> 149:156823d33999 572 }
Anna Bridge 186:707f6e361f3e 573
<> 149:156823d33999 574 if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
<> 149:156823d33999 575 event |= SPI_EVENT_COMPLETE;
<> 149:156823d33999 576 }
Anna Bridge 186:707f6e361f3e 577
<> 149:156823d33999 578 // Receive FIFO Overrun
<> 149:156823d33999 579 if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
<> 149:156823d33999 580 spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
<> 149:156823d33999 581 // In case of tx length > rx length on DMA way
<> 149:156823d33999 582 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
<> 149:156823d33999 583 event |= SPI_EVENT_RX_OVERFLOW;
<> 149:156823d33999 584 }
<> 149:156823d33999 585 }
Anna Bridge 186:707f6e361f3e 586
<> 149:156823d33999 587 // Receive Time-Out
<> 149:156823d33999 588 if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
<> 149:156823d33999 589 spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
AnnaBridge 172:7d866c31b3c5 590 // Not using this IF. Just clear it.
<> 149:156823d33999 591 }
<> 149:156823d33999 592 // Transmit FIFO Under-Run
<> 149:156823d33999 593 if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {
<> 149:156823d33999 594 spi_base->STATUS = SPI_STATUS_TXUFIF_Msk;
<> 149:156823d33999 595 event |= SPI_EVENT_ERROR;
<> 149:156823d33999 596 }
Anna Bridge 186:707f6e361f3e 597
<> 149:156823d33999 598 return event;
<> 149:156823d33999 599 }
<> 149:156823d33999 600
<> 149:156823d33999 601 /**
<> 149:156823d33999 602 * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
<> 149:156823d33999 603 * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
<> 149:156823d33999 604 * @param[in] obj The SPI object on which to operate
<> 149:156823d33999 605 * @param[in] tx_limit The maximum number of words to send
<> 149:156823d33999 606 * @return The number of SPI words that have been transfered
<> 149:156823d33999 607 */
<> 149:156823d33999 608 static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
<> 149:156823d33999 609 {
<> 149:156823d33999 610 uint32_t n_words = 0;
<> 149:156823d33999 611 uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
<> 149:156823d33999 612 uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
<> 149:156823d33999 613 uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
<> 149:156823d33999 614 max_tx = NU_MIN(max_tx, tx_limit);
<> 149:156823d33999 615 uint8_t data_width = spi_get_data_width(obj);
<> 149:156823d33999 616 uint8_t bytes_per_word = (data_width + 7) / 8;
<> 149:156823d33999 617 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
<> 149:156823d33999 618 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 619
<> 149:156823d33999 620 while ((n_words < max_tx) && spi_writeable(obj)) {
<> 149:156823d33999 621 if (spi_is_tx_complete(obj)) {
<> 149:156823d33999 622 // Transmit dummy as transmit buffer is empty
<> 149:156823d33999 623 SPI_WRITE_TX(spi_base, 0);
<> 149:156823d33999 624 }
<> 149:156823d33999 625 else {
<> 149:156823d33999 626 switch (bytes_per_word) {
<> 149:156823d33999 627 case 4:
<> 149:156823d33999 628 SPI_WRITE_TX(spi_base, nu_get32_le(tx));
<> 149:156823d33999 629 tx += 4;
<> 149:156823d33999 630 break;
<> 149:156823d33999 631 case 2:
<> 149:156823d33999 632 SPI_WRITE_TX(spi_base, nu_get16_le(tx));
<> 149:156823d33999 633 tx += 2;
<> 149:156823d33999 634 break;
<> 149:156823d33999 635 case 1:
<> 149:156823d33999 636 SPI_WRITE_TX(spi_base, *((uint8_t *) tx));
<> 149:156823d33999 637 tx += 1;
<> 149:156823d33999 638 break;
<> 149:156823d33999 639 }
Anna Bridge 186:707f6e361f3e 640
<> 149:156823d33999 641 obj->tx_buff.pos ++;
<> 149:156823d33999 642 }
<> 149:156823d33999 643 n_words ++;
<> 149:156823d33999 644 }
Anna Bridge 186:707f6e361f3e 645
<> 149:156823d33999 646 //Return the number of words that have been sent
<> 149:156823d33999 647 return n_words;
<> 149:156823d33999 648 }
<> 149:156823d33999 649
<> 149:156823d33999 650 /**
<> 149:156823d33999 651 * Read SPI words out of the RX FIFO
<> 149:156823d33999 652 * Continues reading words out of the RX FIFO until the following condition is met:
<> 149:156823d33999 653 * o There are no more words in the FIFO
<> 149:156823d33999 654 * OR BOTH OF:
<> 149:156823d33999 655 * o At least as many words as the TX buffer have been received
<> 149:156823d33999 656 * o At least as many words as the RX buffer have been received
<> 149:156823d33999 657 * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
<> 149:156823d33999 658 * @param[in] obj The SPI object on which to operate
<> 149:156823d33999 659 * @return Returns the number of words extracted from the RX FIFO
<> 149:156823d33999 660 */
<> 149:156823d33999 661 static uint32_t spi_master_read_asynch(spi_t *obj)
<> 149:156823d33999 662 {
<> 149:156823d33999 663 uint32_t n_words = 0;
<> 149:156823d33999 664 uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
<> 149:156823d33999 665 uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
<> 149:156823d33999 666 uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
<> 149:156823d33999 667 uint8_t data_width = spi_get_data_width(obj);
<> 149:156823d33999 668 uint8_t bytes_per_word = (data_width + 7) / 8;
<> 149:156823d33999 669 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
<> 149:156823d33999 670 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 671
<> 149:156823d33999 672 while ((n_words < max_rx) && spi_readable(obj)) {
<> 149:156823d33999 673 if (spi_is_rx_complete(obj)) {
<> 149:156823d33999 674 // Disregard as receive buffer is full
<> 149:156823d33999 675 SPI_READ_RX(spi_base);
<> 149:156823d33999 676 }
<> 149:156823d33999 677 else {
<> 149:156823d33999 678 switch (bytes_per_word) {
<> 149:156823d33999 679 case 4: {
<> 149:156823d33999 680 uint32_t val = SPI_READ_RX(spi_base);
<> 149:156823d33999 681 nu_set32_le(rx, val);
<> 149:156823d33999 682 rx += 4;
<> 149:156823d33999 683 break;
<> 149:156823d33999 684 }
<> 149:156823d33999 685 case 2: {
<> 149:156823d33999 686 uint16_t val = SPI_READ_RX(spi_base);
<> 149:156823d33999 687 nu_set16_le(rx, val);
<> 149:156823d33999 688 rx += 2;
<> 149:156823d33999 689 break;
<> 149:156823d33999 690 }
<> 149:156823d33999 691 case 1:
<> 149:156823d33999 692 *rx ++ = SPI_READ_RX(spi_base);
<> 149:156823d33999 693 break;
<> 149:156823d33999 694 }
Anna Bridge 186:707f6e361f3e 695
<> 149:156823d33999 696 obj->rx_buff.pos ++;
<> 149:156823d33999 697 }
<> 149:156823d33999 698 n_words ++;
<> 149:156823d33999 699 }
Anna Bridge 186:707f6e361f3e 700
<> 149:156823d33999 701 // Return the number of words received
<> 149:156823d33999 702 return n_words;
<> 149:156823d33999 703 }
<> 149:156823d33999 704
<> 149:156823d33999 705 static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
<> 149:156823d33999 706 {
<> 149:156823d33999 707 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 708 obj->tx_buff.length = tx_length;
<> 149:156823d33999 709 obj->tx_buff.pos = 0;
<> 149:156823d33999 710 obj->tx_buff.width = spi_get_data_width(obj);
<> 149:156823d33999 711 obj->rx_buff.buffer = rx;
<> 149:156823d33999 712 obj->rx_buff.length = rx_length;
<> 149:156823d33999 713 obj->rx_buff.pos = 0;
<> 149:156823d33999 714 obj->rx_buff.width = spi_get_data_width(obj);
<> 149:156823d33999 715 }
<> 149:156823d33999 716
<> 149:156823d33999 717 static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
<> 149:156823d33999 718 {
<> 149:156823d33999 719 if (*dma_usage != DMA_USAGE_NEVER) {
<> 149:156823d33999 720 if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 721 *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
<> 149:156823d33999 722 }
<> 149:156823d33999 723 if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 724 *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
<> 149:156823d33999 725 }
Anna Bridge 186:707f6e361f3e 726
<> 149:156823d33999 727 if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 728 *dma_usage = DMA_USAGE_NEVER;
<> 149:156823d33999 729 }
<> 149:156823d33999 730 }
Anna Bridge 186:707f6e361f3e 731
<> 149:156823d33999 732 if (*dma_usage == DMA_USAGE_NEVER) {
<> 149:156823d33999 733 dma_channel_free(*dma_ch_tx);
<> 149:156823d33999 734 *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 735 dma_channel_free(*dma_ch_rx);
<> 149:156823d33999 736 *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 737 }
<> 149:156823d33999 738 }
<> 149:156823d33999 739
<> 149:156823d33999 740 static uint8_t spi_get_data_width(spi_t *obj)
Anna Bridge 186:707f6e361f3e 741 {
<> 149:156823d33999 742 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
Anna Bridge 186:707f6e361f3e 743
<> 153:fa9ff456f731 744 uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
<> 153:fa9ff456f731 745 if (data_width == 0) {
<> 153:fa9ff456f731 746 data_width = 32;
<> 153:fa9ff456f731 747 }
Anna Bridge 186:707f6e361f3e 748
<> 153:fa9ff456f731 749 return data_width;
<> 149:156823d33999 750 }
<> 149:156823d33999 751
<> 149:156823d33999 752 static int spi_is_tx_complete(spi_t *obj)
<> 149:156823d33999 753 {
<> 149:156823d33999 754 return (obj->tx_buff.pos == obj->tx_buff.length);
<> 149:156823d33999 755 }
<> 149:156823d33999 756
<> 149:156823d33999 757 static int spi_is_rx_complete(spi_t *obj)
<> 149:156823d33999 758 {
<> 149:156823d33999 759 return (obj->rx_buff.pos == obj->rx_buff.length);
<> 149:156823d33999 760 }
<> 149:156823d33999 761
<> 149:156823d33999 762 static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
<> 149:156823d33999 763 {
<> 149:156823d33999 764 spi_t *obj = (spi_t *) id;
Anna Bridge 186:707f6e361f3e 765
Anna Bridge 186:707f6e361f3e 766 // TODO: Pass this error to caller
<> 149:156823d33999 767 if (event_dma & DMA_EVENT_ABORT) {
<> 149:156823d33999 768 }
<> 149:156823d33999 769 // Expect SPI IRQ will catch this transfer done event
<> 149:156823d33999 770 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 149:156823d33999 771 obj->tx_buff.pos = obj->tx_buff.length;
<> 149:156823d33999 772 }
Anna Bridge 186:707f6e361f3e 773 // TODO: Pass this error to caller
<> 149:156823d33999 774 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 149:156823d33999 775 }
Anna Bridge 186:707f6e361f3e 776
<> 149:156823d33999 777 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
<> 149:156823d33999 778 MBED_ASSERT(modinit != NULL);
Anna Bridge 186:707f6e361f3e 779 MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
Anna Bridge 186:707f6e361f3e 780
<> 149:156823d33999 781 void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
<> 149:156823d33999 782 vec();
<> 149:156823d33999 783 }
<> 149:156823d33999 784
<> 149:156823d33999 785 static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
<> 149:156823d33999 786 {
<> 149:156823d33999 787 spi_t *obj = (spi_t *) id;
Anna Bridge 186:707f6e361f3e 788
Anna Bridge 186:707f6e361f3e 789 // TODO: Pass this error to caller
<> 149:156823d33999 790 if (event_dma & DMA_EVENT_ABORT) {
<> 149:156823d33999 791 }
<> 149:156823d33999 792 // Expect SPI IRQ will catch this transfer done event
<> 149:156823d33999 793 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 149:156823d33999 794 obj->rx_buff.pos = obj->rx_buff.length;
<> 149:156823d33999 795 }
Anna Bridge 186:707f6e361f3e 796 // TODO: Pass this error to caller
<> 149:156823d33999 797 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 149:156823d33999 798 }
Anna Bridge 186:707f6e361f3e 799
<> 149:156823d33999 800 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
<> 149:156823d33999 801 MBED_ASSERT(modinit != NULL);
Anna Bridge 186:707f6e361f3e 802 MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
Anna Bridge 186:707f6e361f3e 803
<> 149:156823d33999 804 void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
<> 149:156823d33999 805 vec();
<> 149:156823d33999 806 }
<> 149:156823d33999 807
<> 149:156823d33999 808 #endif
<> 149:156823d33999 809
<> 149:156823d33999 810 #endif