mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c@181:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
181:57724642e740
Parent:
167:e84263d55307 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_swpmi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief SWPMI LL module driver.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
AnnaBridge 167:e84263d55307 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 38 #include "stm32l4xx_ll_swpmi.h"
<> 144:ef7eb2e8f9f7 39 #include "stm32l4xx_ll_bus.h"
<> 144:ef7eb2e8f9f7 40 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 41 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 42 #else
<> 144:ef7eb2e8f9f7 43 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 #if defined (SWPMI1)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup SWPMI_LL
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /** @addtogroup SWPMI_LL_Private_Macros
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 #define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 #define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \
<> 144:ef7eb2e8f9f7 67 || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI))
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #define IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \
<> 144:ef7eb2e8f9f7 70 || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI))
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #define IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__) (((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \
<> 144:ef7eb2e8f9f7 73 || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B))
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /**
<> 144:ef7eb2e8f9f7 76 * @}
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 82 /** @addtogroup SWPMI_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @addtogroup SWPMI_LL_EF_Init
<> 144:ef7eb2e8f9f7 87 * @{
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief De-initialize the SWPMI peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 92 * @param SWPMIx SWPMI Instance
<> 144:ef7eb2e8f9f7 93 * @retval An ErrorStatus enumeration value
<> 144:ef7eb2e8f9f7 94 * - SUCCESS: SWPMI registers are de-initialized
<> 144:ef7eb2e8f9f7 95 * - ERROR: Not applicable
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx)
<> 144:ef7eb2e8f9f7 98 {
<> 144:ef7eb2e8f9f7 99 /* Check the parameter */
<> 144:ef7eb2e8f9f7 100 assert_param(IS_SWPMI_INSTANCE(SWPMIx));
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1);
<> 144:ef7eb2e8f9f7 103 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1);
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 return SUCCESS;
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /**
<> 144:ef7eb2e8f9f7 109 * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
<> 144:ef7eb2e8f9f7 110 * @note As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0),
<> 144:ef7eb2e8f9f7 111 * SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
<> 144:ef7eb2e8f9f7 112 * @param SWPMIx SWPMI Instance
<> 144:ef7eb2e8f9f7 113 * @param SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 114 * the configuration information for the SWPMI peripheral.
<> 144:ef7eb2e8f9f7 115 * @retval An ErrorStatus enumeration value
<> 144:ef7eb2e8f9f7 116 * - SUCCESS: SWPMI registers are initialized
<> 144:ef7eb2e8f9f7 117 * - ERROR: SWPMI registers are not initialized
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Check the parameters */
<> 144:ef7eb2e8f9f7 124 assert_param(IS_SWPMI_INSTANCE(SWPMIx));
<> 144:ef7eb2e8f9f7 125 assert_param(IS_LL_SWPMI_BITRATE_VALUE(SWPMI_InitStruct->BitRatePrescaler));
<> 144:ef7eb2e8f9f7 126 assert_param(IS_LL_SWPMI_SW_BUFFER_TX(SWPMI_InitStruct->TxBufferingMode));
<> 144:ef7eb2e8f9f7 127 assert_param(IS_LL_SWPMI_SW_BUFFER_RX(SWPMI_InitStruct->RxBufferingMode));
<> 144:ef7eb2e8f9f7 128 assert_param(IS_LL_SWPMI_VOLTAGE_CLASS(SWPMI_InitStruct->VoltageClass));
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* SWPMI needs to be in deactivated state, in order to be able to configure some bits */
<> 144:ef7eb2e8f9f7 131 if (LL_SWPMI_IsActivated(SWPMIx) == 0)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 /* Configure the BRR register (Bitrate) */
<> 144:ef7eb2e8f9f7 134 LL_SWPMI_SetBitRatePrescaler(SWPMIx, SWPMI_InitStruct->BitRatePrescaler);
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Configure the voltage class */
<> 144:ef7eb2e8f9f7 137 LL_SWPMI_SetVoltageClass(SWPMIx, SWPMI_InitStruct->VoltageClass);
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Set the new configuration of the SWPMI peripheral */
<> 144:ef7eb2e8f9f7 140 MODIFY_REG(SWPMIx->CR,
<> 144:ef7eb2e8f9f7 141 (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
<> 144:ef7eb2e8f9f7 142 (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144 /* Else (SWPMI not in deactivated state => return ERROR) */
<> 144:ef7eb2e8f9f7 145 else
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 status = ERROR;
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 return status;
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief Set each @ref LL_SWPMI_InitTypeDef field to default value.
<> 144:ef7eb2e8f9f7 155 * @param SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 156 * the configuration information for the SWPMI peripheral.
<> 144:ef7eb2e8f9f7 157 * @retval None
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 /* Set SWPMI_InitStruct fields to default values */
<> 144:ef7eb2e8f9f7 162 SWPMI_InitStruct->VoltageClass = LL_SWPMI_VOLTAGE_CLASS_C;
<> 144:ef7eb2e8f9f7 163 SWPMI_InitStruct->BitRatePrescaler = (uint32_t)0x00000001;
<> 144:ef7eb2e8f9f7 164 SWPMI_InitStruct->TxBufferingMode = LL_SWPMI_SW_BUFFER_TX_SINGLE;
<> 144:ef7eb2e8f9f7 165 SWPMI_InitStruct->RxBufferingMode = LL_SWPMI_SW_BUFFER_RX_SINGLE;
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @}
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #endif /* defined (SWPMI1) */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @}
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/