mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
Parent:
149:156823d33999
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_usart.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @version V1.0.5
<> 154:37f96f9d4de2 6 * @date 06-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of USART HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_USART_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_USART_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup USART
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup USART_Exported_Types USART Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief USART Init Structure definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
<> 144:ef7eb2e8f9f7 69 The baud rate is computed using the following formula:
<> 144:ef7eb2e8f9f7 70 - IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
<> 144:ef7eb2e8f9f7 71 - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref USART_Word_Length */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref USART_Stop_Bits */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t Parity; /*!< Specifies the parity mode.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref USART_Parity
<> 144:ef7eb2e8f9f7 81 @note When parity is enabled, the computed parity is inserted
<> 144:ef7eb2e8f9f7 82 at the MSB position of the transmitted data (9th bit when
<> 144:ef7eb2e8f9f7 83 the word length is set to 9 data bits; 8th bit when the
<> 144:ef7eb2e8f9f7 84 word length is set to 8 data bits). */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
<> 144:ef7eb2e8f9f7 87 This parameter can be a value of @ref USART_Mode */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref USART_Clock_Polarity */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref USART_Clock_Phase */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
<> 144:ef7eb2e8f9f7 96 data bit (MSB) has to be output on the SCLK pin in synchronous mode.
<> 144:ef7eb2e8f9f7 97 This parameter can be a value of @ref USART_Last_Bit */
<> 144:ef7eb2e8f9f7 98 }USART_InitTypeDef;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 typedef enum
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
<> 144:ef7eb2e8f9f7 106 HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 107 HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
<> 144:ef7eb2e8f9f7 108 HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 109 HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 110 HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
<> 144:ef7eb2e8f9f7 111 HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 112 HAL_USART_STATE_ERROR = 0x04 /*!< Error */
<> 144:ef7eb2e8f9f7 113 }HAL_USART_StateTypeDef;
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief USART handle Structure definition
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef struct
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 USART_TypeDef *Instance; /*!< USART registers base address */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 USART_InitTypeDef Init; /*!< Usart communication parameters */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 uint16_t TxXferSize; /*!< Usart Tx Transfer size */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 uint16_t RxXferSize; /*!< Usart Rx Transfer size */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 __IO uint32_t ErrorCode; /*!< USART Error code */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 }USART_HandleTypeDef;
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @}
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 154 /** @defgroup USART_Exported_Constants USART Exported constants
<> 144:ef7eb2e8f9f7 155 * @{
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /** @defgroup USART_Error_Codes USART Error Codes
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 #define HAL_USART_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 144:ef7eb2e8f9f7 162 #define HAL_USART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
<> 144:ef7eb2e8f9f7 163 #define HAL_USART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
<> 144:ef7eb2e8f9f7 164 #define HAL_USART_ERROR_FE ((uint32_t)0x04) /*!< frame error */
<> 144:ef7eb2e8f9f7 165 #define HAL_USART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
<> 144:ef7eb2e8f9f7 166 #define HAL_USART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @defgroup USART_Word_Length USART Word Length
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 #define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 175 #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 #define USART_STOPBITS_1 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 184 #define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
<> 144:ef7eb2e8f9f7 185 #define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
<> 144:ef7eb2e8f9f7 186 #define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
<> 144:ef7eb2e8f9f7 187 /**
<> 144:ef7eb2e8f9f7 188 * @}
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /** @defgroup USART_Parity USART Parity
<> 144:ef7eb2e8f9f7 192 * @{
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194 #define USART_PARITY_NONE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 195 #define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
<> 144:ef7eb2e8f9f7 196 #define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @}
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** @defgroup USART_Mode USART Mode
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 #define USART_MODE_RX ((uint32_t)USART_CR1_RE)
<> 144:ef7eb2e8f9f7 205 #define USART_MODE_TX ((uint32_t)USART_CR1_TE)
<> 144:ef7eb2e8f9f7 206 #define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @}
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /** @defgroup USART_Clock USART Clock
<> 144:ef7eb2e8f9f7 213 * @{
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 #define USART_CLOCK_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 216 #define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup USART_Clock_Polarity USART Clock Polarity
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 #define USART_POLARITY_LOW ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 225 #define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @}
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /** @defgroup USART_Clock_Phase USART Clock Phase
<> 144:ef7eb2e8f9f7 231 * @{
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define USART_PHASE_1EDGE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 234 #define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @}
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup USART_Last_Bit USART Last Bit
<> 144:ef7eb2e8f9f7 240 * @{
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 #define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 243 #define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @defgroup USART_NACK_State USART NACK State
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
<> 144:ef7eb2e8f9f7 252 #define USART_NACK_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /** @defgroup USART_Flags USART Flags
<> 144:ef7eb2e8f9f7 258 * Elements values convention: 0xXXXX
<> 144:ef7eb2e8f9f7 259 * - 0xXXXX : Flag mask in the SR register
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #define USART_FLAG_CTS ((uint32_t)USART_SR_CTS)
<> 144:ef7eb2e8f9f7 264 #define USART_FLAG_LBD ((uint32_t)USART_SR_LBD)
<> 144:ef7eb2e8f9f7 265 #define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
<> 144:ef7eb2e8f9f7 266 #define USART_FLAG_TC ((uint32_t)USART_SR_TC)
<> 144:ef7eb2e8f9f7 267 #define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
<> 144:ef7eb2e8f9f7 268 #define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
<> 144:ef7eb2e8f9f7 269 #define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
<> 144:ef7eb2e8f9f7 270 #define USART_FLAG_NE ((uint32_t)USART_SR_NE)
<> 144:ef7eb2e8f9f7 271 #define USART_FLAG_FE ((uint32_t)USART_SR_FE)
<> 144:ef7eb2e8f9f7 272 #define USART_FLAG_PE ((uint32_t)USART_SR_PE)
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @}
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
<> 144:ef7eb2e8f9f7 278 * Elements values convention: 0xY000XXXX
<> 144:ef7eb2e8f9f7 279 * - XXXX : Interrupt mask (16 bits) in the Y register
<> 144:ef7eb2e8f9f7 280 * - Y : Interrupt source register (4bits)
<> 144:ef7eb2e8f9f7 281 * - 0001: CR1 register
<> 144:ef7eb2e8f9f7 282 * - 0010: CR2 register
<> 144:ef7eb2e8f9f7 283 * - 0011: CR3 register
<> 144:ef7eb2e8f9f7 284 *
<> 144:ef7eb2e8f9f7 285 * @{
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 #define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
<> 144:ef7eb2e8f9f7 289 #define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
<> 144:ef7eb2e8f9f7 290 #define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
<> 144:ef7eb2e8f9f7 291 #define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
<> 144:ef7eb2e8f9f7 292 #define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 #define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 #define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
<> 144:ef7eb2e8f9f7 297 #define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @}
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 310 /** @defgroup USART_Exported_Macros USART Exported Macros
<> 144:ef7eb2e8f9f7 311 * @{
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /** @brief Reset USART handle state
<> 144:ef7eb2e8f9f7 316 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 317 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 318 * @retval None
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /** @brief Check whether the specified USART flag is set or not.
<> 144:ef7eb2e8f9f7 323 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 324 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 325 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 326 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 327 * @arg USART_FLAG_TXE: Transmit data register empty flag
<> 144:ef7eb2e8f9f7 328 * @arg USART_FLAG_TC: Transmission Complete flag
<> 144:ef7eb2e8f9f7 329 * @arg USART_FLAG_RXNE: Receive data register not empty flag
<> 144:ef7eb2e8f9f7 330 * @arg USART_FLAG_IDLE: Idle Line detection flag
<> 144:ef7eb2e8f9f7 331 * @arg USART_FLAG_ORE: OverRun Error flag
<> 144:ef7eb2e8f9f7 332 * @arg USART_FLAG_NE: Noise Error flag
<> 144:ef7eb2e8f9f7 333 * @arg USART_FLAG_FE: Framing Error flag
<> 144:ef7eb2e8f9f7 334 * @arg USART_FLAG_PE: Parity Error flag
<> 144:ef7eb2e8f9f7 335 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /** @brief Clear the specified USART pending flags.
<> 144:ef7eb2e8f9f7 341 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 342 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 343 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 344 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 345 * @arg USART_FLAG_TC: Transmission Complete flag.
<> 144:ef7eb2e8f9f7 346 * @arg USART_FLAG_RXNE: Receive data register not empty flag.
<> 144:ef7eb2e8f9f7 347 *
<> 144:ef7eb2e8f9f7 348 * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
<> 144:ef7eb2e8f9f7 349 * error) and IDLE (Idle line detected) flags are cleared by software
<> 144:ef7eb2e8f9f7 350 * sequence: a read operation to USART_SR register followed by a read
<> 144:ef7eb2e8f9f7 351 * operation to USART_DR register.
<> 144:ef7eb2e8f9f7 352 * @note RXNE flag can be also cleared by a read to the USART_DR register.
<> 144:ef7eb2e8f9f7 353 * @note TC flag can be also cleared by software sequence: a read operation to
<> 144:ef7eb2e8f9f7 354 * USART_SR register followed by a write operation to USART_DR register.
<> 144:ef7eb2e8f9f7 355 * @note TXE flag is cleared only by a write to the USART_DR register.
<> 144:ef7eb2e8f9f7 356 *
<> 144:ef7eb2e8f9f7 357 * @retval None
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /** @brief Clear the USART PE pending flag.
<> 144:ef7eb2e8f9f7 362 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 363 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 364 * @retval None
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 367 do{ \
<> 144:ef7eb2e8f9f7 368 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 369 tmpreg = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 370 tmpreg = (__HANDLE__)->Instance->DR; \
<> 144:ef7eb2e8f9f7 371 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 372 }while(0)
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /** @brief Clear the USART FE pending flag.
<> 144:ef7eb2e8f9f7 376 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 377 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 378 * @retval None
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /** @brief Clear the USART NE pending flag.
<> 144:ef7eb2e8f9f7 383 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 384 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 385 * @retval None
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /** @brief Clear the USART ORE pending flag.
<> 144:ef7eb2e8f9f7 390 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 391 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 392 * @retval None
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /** @brief Clear the USART IDLE pending flag.
<> 144:ef7eb2e8f9f7 397 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 398 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 399 * @retval None
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /** @brief Enable the specified Usart interrupts.
<> 144:ef7eb2e8f9f7 404 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 405 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 406 * @param __INTERRUPT__: specifies the USART interrupt source to enable.
<> 144:ef7eb2e8f9f7 407 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 408 * @arg USART_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 409 * @arg USART_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 410 * @arg USART_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 411 * @arg USART_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 412 * @arg USART_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 413 * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 414 * @retval None
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
<> 144:ef7eb2e8f9f7 417 (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
<> 144:ef7eb2e8f9f7 418 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /** @brief Disable the specified Usart interrupts.
<> 144:ef7eb2e8f9f7 422 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 423 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 424 * @param __INTERRUPT__: specifies the USART interrupt source to disable.
<> 144:ef7eb2e8f9f7 425 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 426 * @arg USART_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 427 * @arg USART_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 428 * @arg USART_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 429 * @arg USART_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 430 * @arg USART_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 431 * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 432 * @retval None
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
<> 144:ef7eb2e8f9f7 435 (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
<> 144:ef7eb2e8f9f7 436 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /** @brief Check whether the specified Usart interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 441 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 442 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 443 * @param __IT__: specifies the USART interrupt source to check.
<> 144:ef7eb2e8f9f7 444 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 445 * @arg USART_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 446 * @arg USART_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 447 * @arg USART_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 448 * @arg USART_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 449 * @arg USART_IT_ERR: Error interrupt
<> 144:ef7eb2e8f9f7 450 * @arg USART_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 451 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == USART_CR2_REG_INDEX)? \
<> 144:ef7eb2e8f9f7 454 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /** @brief Enable USART
<> 144:ef7eb2e8f9f7 457 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 458 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 459 * @retval None
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 #define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /** @brief Disable USART
<> 144:ef7eb2e8f9f7 464 * @param __HANDLE__: specifies the USART Handle.
<> 144:ef7eb2e8f9f7 465 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
<> 144:ef7eb2e8f9f7 466 * @retval None
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 #define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /**
<> 144:ef7eb2e8f9f7 472 * @}
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 477 /** @defgroup USART_Private_Macros USART Private Macros
<> 144:ef7eb2e8f9f7 478 * @{
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 #define USART_CR1_REG_INDEX 1
<> 144:ef7eb2e8f9f7 482 #define USART_CR2_REG_INDEX 2
<> 144:ef7eb2e8f9f7 483 #define USART_CR3_REG_INDEX 3
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__)))
<> 144:ef7eb2e8f9f7 486 #define USART_DIVMANT(__PCLK__, __BAUD__) (USART_DIV((__PCLK__), (__BAUD__))/100)
<> 144:ef7eb2e8f9f7 487 #define USART_DIVFRAQ(__PCLK__, __BAUD__) (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
<> 144:ef7eb2e8f9f7 488 #define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /** Check USART Baud rate
<> 144:ef7eb2e8f9f7 491 * __BAUDRATE__: Baudrate specified by the user
<> 144:ef7eb2e8f9f7 492 * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz)
<> 144:ef7eb2e8f9f7 493 * divided by the smallest oversampling used on the USART (i.e. 16)
<> 144:ef7eb2e8f9f7 494 * return : TRUE or FALSE
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 499 ((LENGTH) == USART_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
<> 144:ef7eb2e8f9f7 502 ((STOPBITS) == USART_STOPBITS_0_5) || \
<> 144:ef7eb2e8f9f7 503 ((STOPBITS) == USART_STOPBITS_1_5) || \
<> 144:ef7eb2e8f9f7 504 ((STOPBITS) == USART_STOPBITS_2))
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 #define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
<> 144:ef7eb2e8f9f7 507 ((PARITY) == USART_PARITY_EVEN) || \
<> 144:ef7eb2e8f9f7 508 ((PARITY) == USART_PARITY_ODD))
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 #define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00) && ((MODE) != (uint32_t)0x00000000))
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
<> 144:ef7eb2e8f9f7 513 ((CLOCK) == USART_CLOCK_ENABLE))
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 #define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 #define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
<> 144:ef7eb2e8f9f7 520 ((LASTBIT) == USART_LASTBIT_ENABLE))
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 #define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
<> 144:ef7eb2e8f9f7 523 ((NACK) == USART_NACK_DISABLE))
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /** USART interruptions flag mask
<> 144:ef7eb2e8f9f7 526 *
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 #define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
<> 144:ef7eb2e8f9f7 529 USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @}
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /** @addtogroup USART_Exported_Functions USART Exported Functions
<> 144:ef7eb2e8f9f7 539 * @{
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 543 * @{
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Initialization and de-initialization functions ******************************/
<> 144:ef7eb2e8f9f7 547 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 548 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 549 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 550 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /**
<> 144:ef7eb2e8f9f7 553 * @}
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 557 * @{
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* IO operation functions *******************************************************/
<> 144:ef7eb2e8f9f7 561 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 562 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 563 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 564 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 565 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 566 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 567 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 568 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 569 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 570 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 571 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 572 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 573 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 574 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 575 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 576 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 577 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 578 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 579 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @}
<> 144:ef7eb2e8f9f7 583 */
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 588 * @{
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 592 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 593 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @}
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /**
<> 144:ef7eb2e8f9f7 600 * @}
<> 144:ef7eb2e8f9f7 601 */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @}
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /**
<> 144:ef7eb2e8f9f7 608 * @}
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613 #endif
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 #endif /* __STM32F1xx_HAL_USART_H */
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/