mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c@170:19eb464bc2be, 2017-08-03 (annotated)
- Committer:
- Kojto
- Date:
- Thu Aug 03 13:13:39 2017 +0100
- Revision:
- 170:19eb464bc2be
- Child:
- 187:0387e8f68319
This updates the lib to the mbed lib v 148
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 170:19eb464bc2be | 1 | /* mbed Microcontroller Library |
Kojto | 170:19eb464bc2be | 2 | * Copyright (c) 2006-2017 ARM Limited |
Kojto | 170:19eb464bc2be | 3 | * |
Kojto | 170:19eb464bc2be | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
Kojto | 170:19eb464bc2be | 5 | * you may not use this file except in compliance with the License. |
Kojto | 170:19eb464bc2be | 6 | * You may obtain a copy of the License at |
Kojto | 170:19eb464bc2be | 7 | * |
Kojto | 170:19eb464bc2be | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
Kojto | 170:19eb464bc2be | 9 | * |
Kojto | 170:19eb464bc2be | 10 | * Unless required by applicable law or agreed to in writing, software |
Kojto | 170:19eb464bc2be | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
Kojto | 170:19eb464bc2be | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
Kojto | 170:19eb464bc2be | 13 | * See the License for the specific language governing permissions and |
Kojto | 170:19eb464bc2be | 14 | * limitations under the License. |
Kojto | 170:19eb464bc2be | 15 | */ |
Kojto | 170:19eb464bc2be | 16 | |
Kojto | 170:19eb464bc2be | 17 | /** |
Kojto | 170:19eb464bc2be | 18 | * This file configures the system clock as follows: |
Kojto | 170:19eb464bc2be | 19 | *----------------------------------------------------------------------------- |
Kojto | 170:19eb464bc2be | 20 | * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
Kojto | 170:19eb464bc2be | 21 | * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
Kojto | 170:19eb464bc2be | 22 | * | 3- USE_PLL_HSI (internal 16 MHz) |
Kojto | 170:19eb464bc2be | 23 | * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) |
Kojto | 170:19eb464bc2be | 24 | *----------------------------------------------------------------------------- |
Kojto | 170:19eb464bc2be | 25 | * SYSCLK(MHz) | 80 |
Kojto | 170:19eb464bc2be | 26 | * AHBCLK (MHz) | 80 |
Kojto | 170:19eb464bc2be | 27 | * APB1CLK (MHz) | 80 |
Kojto | 170:19eb464bc2be | 28 | * APB2CLK (MHz) | 80 |
Kojto | 170:19eb464bc2be | 29 | * USB capable | YES |
Kojto | 170:19eb464bc2be | 30 | *----------------------------------------------------------------------------- |
Kojto | 170:19eb464bc2be | 31 | **/ |
Kojto | 170:19eb464bc2be | 32 | |
Kojto | 170:19eb464bc2be | 33 | #include "stm32l4xx.h" |
Kojto | 170:19eb464bc2be | 34 | #include "nvic_addr.h" |
Kojto | 170:19eb464bc2be | 35 | #include "mbed_assert.h" |
Kojto | 170:19eb464bc2be | 36 | |
Kojto | 170:19eb464bc2be | 37 | /*!< Uncomment the following line if you need to relocate your vector Table in |
Kojto | 170:19eb464bc2be | 38 | Internal SRAM. */ |
Kojto | 170:19eb464bc2be | 39 | /* #define VECT_TAB_SRAM */ |
Kojto | 170:19eb464bc2be | 40 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
Kojto | 170:19eb464bc2be | 41 | This value must be a multiple of 0x200. */ |
Kojto | 170:19eb464bc2be | 42 | |
Kojto | 170:19eb464bc2be | 43 | |
Kojto | 170:19eb464bc2be | 44 | // clock source is selected with CLOCK_SOURCE in json config |
Kojto | 170:19eb464bc2be | 45 | #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) |
Kojto | 170:19eb464bc2be | 46 | #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) |
Kojto | 170:19eb464bc2be | 47 | #define USE_PLL_HSI 0x2 // Use HSI internal clock |
Kojto | 170:19eb464bc2be | 48 | #define USE_PLL_MSI 0x1 // Use MSI internal clock |
Kojto | 170:19eb464bc2be | 49 | |
Kojto | 170:19eb464bc2be | 50 | #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) |
Kojto | 170:19eb464bc2be | 51 | |
Kojto | 170:19eb464bc2be | 52 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
Kojto | 170:19eb464bc2be | 53 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
Kojto | 170:19eb464bc2be | 54 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
Kojto | 170:19eb464bc2be | 55 | |
Kojto | 170:19eb464bc2be | 56 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
Kojto | 170:19eb464bc2be | 57 | uint8_t SetSysClock_PLL_HSI(void); |
Kojto | 170:19eb464bc2be | 58 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
Kojto | 170:19eb464bc2be | 59 | |
Kojto | 170:19eb464bc2be | 60 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
Kojto | 170:19eb464bc2be | 61 | uint8_t SetSysClock_PLL_MSI(void); |
Kojto | 170:19eb464bc2be | 62 | #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ |
Kojto | 170:19eb464bc2be | 63 | |
Kojto | 170:19eb464bc2be | 64 | |
Kojto | 170:19eb464bc2be | 65 | /** |
Kojto | 170:19eb464bc2be | 66 | * @brief Setup the microcontroller system. |
Kojto | 170:19eb464bc2be | 67 | * @param None |
Kojto | 170:19eb464bc2be | 68 | * @retval None |
Kojto | 170:19eb464bc2be | 69 | */ |
Kojto | 170:19eb464bc2be | 70 | |
Kojto | 170:19eb464bc2be | 71 | void SystemInit(void) |
Kojto | 170:19eb464bc2be | 72 | { |
Kojto | 170:19eb464bc2be | 73 | /* FPU settings ------------------------------------------------------------*/ |
Kojto | 170:19eb464bc2be | 74 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
Kojto | 170:19eb464bc2be | 75 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
Kojto | 170:19eb464bc2be | 76 | #endif |
Kojto | 170:19eb464bc2be | 77 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
Kojto | 170:19eb464bc2be | 78 | /* Set MSION bit */ |
Kojto | 170:19eb464bc2be | 79 | RCC->CR |= RCC_CR_MSION; |
Kojto | 170:19eb464bc2be | 80 | |
Kojto | 170:19eb464bc2be | 81 | /* Reset CFGR register */ |
Kojto | 170:19eb464bc2be | 82 | RCC->CFGR = 0x00000000; |
Kojto | 170:19eb464bc2be | 83 | |
Kojto | 170:19eb464bc2be | 84 | /* Reset HSEON, CSSON , HSION, and PLLON bits */ |
Kojto | 170:19eb464bc2be | 85 | RCC->CR &= (uint32_t)0xEAF6FFFF; |
Kojto | 170:19eb464bc2be | 86 | |
Kojto | 170:19eb464bc2be | 87 | /* Reset PLLCFGR register */ |
Kojto | 170:19eb464bc2be | 88 | RCC->PLLCFGR = 0x00001000; |
Kojto | 170:19eb464bc2be | 89 | |
Kojto | 170:19eb464bc2be | 90 | /* Reset HSEBYP bit */ |
Kojto | 170:19eb464bc2be | 91 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
Kojto | 170:19eb464bc2be | 92 | |
Kojto | 170:19eb464bc2be | 93 | /* Disable all interrupts */ |
Kojto | 170:19eb464bc2be | 94 | RCC->CIER = 0x00000000; |
Kojto | 170:19eb464bc2be | 95 | |
Kojto | 170:19eb464bc2be | 96 | /* Configure the Vector Table location add offset address ------------------*/ |
Kojto | 170:19eb464bc2be | 97 | #ifdef VECT_TAB_SRAM |
Kojto | 170:19eb464bc2be | 98 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
Kojto | 170:19eb464bc2be | 99 | #else |
Kojto | 170:19eb464bc2be | 100 | SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ |
Kojto | 170:19eb464bc2be | 101 | #endif |
Kojto | 170:19eb464bc2be | 102 | |
Kojto | 170:19eb464bc2be | 103 | } |
Kojto | 170:19eb464bc2be | 104 | |
Kojto | 170:19eb464bc2be | 105 | |
Kojto | 170:19eb464bc2be | 106 | /** |
Kojto | 170:19eb464bc2be | 107 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
Kojto | 170:19eb464bc2be | 108 | * AHB/APBx prescalers and Flash settings |
Kojto | 170:19eb464bc2be | 109 | * @note This function should be called only once the RCC clock configuration |
Kojto | 170:19eb464bc2be | 110 | * is reset to the default reset state (done in SystemInit() function). |
Kojto | 170:19eb464bc2be | 111 | * @param None |
Kojto | 170:19eb464bc2be | 112 | * @retval None |
Kojto | 170:19eb464bc2be | 113 | */ |
Kojto | 170:19eb464bc2be | 114 | |
Kojto | 170:19eb464bc2be | 115 | void SetSysClock(void) |
Kojto | 170:19eb464bc2be | 116 | { |
Kojto | 170:19eb464bc2be | 117 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) |
Kojto | 170:19eb464bc2be | 118 | /* 1- Try to start with HSE and external clock */ |
Kojto | 170:19eb464bc2be | 119 | if (SetSysClock_PLL_HSE(1) == 0) |
Kojto | 170:19eb464bc2be | 120 | #endif |
Kojto | 170:19eb464bc2be | 121 | { |
Kojto | 170:19eb464bc2be | 122 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) |
Kojto | 170:19eb464bc2be | 123 | /* 2- If fail try to start with HSE and external xtal */ |
Kojto | 170:19eb464bc2be | 124 | if (SetSysClock_PLL_HSE(0) == 0) |
Kojto | 170:19eb464bc2be | 125 | #endif |
Kojto | 170:19eb464bc2be | 126 | { |
Kojto | 170:19eb464bc2be | 127 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
Kojto | 170:19eb464bc2be | 128 | /* 3- If fail start with HSI clock */ |
Kojto | 170:19eb464bc2be | 129 | if (SetSysClock_PLL_HSI()==0) |
Kojto | 170:19eb464bc2be | 130 | #endif |
Kojto | 170:19eb464bc2be | 131 | { |
Kojto | 170:19eb464bc2be | 132 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
Kojto | 170:19eb464bc2be | 133 | /* 4- If fail start with MSI clock */ |
Kojto | 170:19eb464bc2be | 134 | if (SetSysClock_PLL_MSI() == 0) |
Kojto | 170:19eb464bc2be | 135 | #endif |
Kojto | 170:19eb464bc2be | 136 | { |
Kojto | 170:19eb464bc2be | 137 | while(1) { |
Kojto | 170:19eb464bc2be | 138 | MBED_ASSERT(1); |
Kojto | 170:19eb464bc2be | 139 | } |
Kojto | 170:19eb464bc2be | 140 | } |
Kojto | 170:19eb464bc2be | 141 | } |
Kojto | 170:19eb464bc2be | 142 | } |
Kojto | 170:19eb464bc2be | 143 | } |
Kojto | 170:19eb464bc2be | 144 | |
Kojto | 170:19eb464bc2be | 145 | // Output clock on MCO1 pin(PA8) for debugging purpose |
Kojto | 170:19eb464bc2be | 146 | #if DEBUG_MCO == 1 |
Kojto | 170:19eb464bc2be | 147 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); |
Kojto | 170:19eb464bc2be | 148 | #endif |
Kojto | 170:19eb464bc2be | 149 | } |
Kojto | 170:19eb464bc2be | 150 | |
Kojto | 170:19eb464bc2be | 151 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
Kojto | 170:19eb464bc2be | 152 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 153 | /* PLL (clocked by HSE) used as System clock source */ |
Kojto | 170:19eb464bc2be | 154 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 155 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
Kojto | 170:19eb464bc2be | 156 | { |
Kojto | 170:19eb464bc2be | 157 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 158 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 159 | RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; |
Kojto | 170:19eb464bc2be | 160 | |
Kojto | 170:19eb464bc2be | 161 | // Used to gain time after DeepSleep in case HSI is used |
Kojto | 170:19eb464bc2be | 162 | if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { |
Kojto | 170:19eb464bc2be | 163 | return 0; |
Kojto | 170:19eb464bc2be | 164 | } |
Kojto | 170:19eb464bc2be | 165 | |
Kojto | 170:19eb464bc2be | 166 | // Select MSI as system clock source to allow modification of the PLL configuration |
Kojto | 170:19eb464bc2be | 167 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
Kojto | 170:19eb464bc2be | 168 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; |
Kojto | 170:19eb464bc2be | 169 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); |
Kojto | 170:19eb464bc2be | 170 | |
Kojto | 170:19eb464bc2be | 171 | // Enable HSE oscillator and activate PLL with HSE as source |
Kojto | 170:19eb464bc2be | 172 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; |
Kojto | 170:19eb464bc2be | 173 | if (bypass == 0) { |
Kojto | 170:19eb464bc2be | 174 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
Kojto | 170:19eb464bc2be | 175 | } else { |
Kojto | 170:19eb464bc2be | 176 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN |
Kojto | 170:19eb464bc2be | 177 | } |
Kojto | 170:19eb464bc2be | 178 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
Kojto | 170:19eb464bc2be | 179 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz |
Kojto | 170:19eb464bc2be | 180 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
Kojto | 170:19eb464bc2be | 181 | RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) |
Kojto | 170:19eb464bc2be | 182 | RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) |
Kojto | 170:19eb464bc2be | 183 | RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) |
Kojto | 170:19eb464bc2be | 184 | RCC_OscInitStruct.PLL.PLLQ = 2; |
Kojto | 170:19eb464bc2be | 185 | RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) |
Kojto | 170:19eb464bc2be | 186 | |
Kojto | 170:19eb464bc2be | 187 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 188 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 189 | } |
Kojto | 170:19eb464bc2be | 190 | |
Kojto | 170:19eb464bc2be | 191 | // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
Kojto | 170:19eb464bc2be | 192 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
Kojto | 170:19eb464bc2be | 193 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz |
Kojto | 170:19eb464bc2be | 194 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz |
Kojto | 170:19eb464bc2be | 195 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz |
Kojto | 170:19eb464bc2be | 196 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz |
Kojto | 170:19eb464bc2be | 197 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 198 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 199 | } |
Kojto | 170:19eb464bc2be | 200 | |
Kojto | 170:19eb464bc2be | 201 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; |
Kojto | 170:19eb464bc2be | 202 | RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; |
Kojto | 170:19eb464bc2be | 203 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; |
Kojto | 170:19eb464bc2be | 204 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; |
Kojto | 170:19eb464bc2be | 205 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; |
Kojto | 170:19eb464bc2be | 206 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; |
Kojto | 170:19eb464bc2be | 207 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; |
Kojto | 170:19eb464bc2be | 208 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; |
Kojto | 170:19eb464bc2be | 209 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; |
Kojto | 170:19eb464bc2be | 210 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 211 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 212 | } |
Kojto | 170:19eb464bc2be | 213 | |
Kojto | 170:19eb464bc2be | 214 | // Disable MSI Oscillator |
Kojto | 170:19eb464bc2be | 215 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; |
Kojto | 170:19eb464bc2be | 216 | RCC_OscInitStruct.MSIState = RCC_MSI_OFF; |
Kojto | 170:19eb464bc2be | 217 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
Kojto | 170:19eb464bc2be | 218 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
Kojto | 170:19eb464bc2be | 219 | |
Kojto | 170:19eb464bc2be | 220 | // Output clock on MCO1 pin(PA8) for debugging purpose |
Kojto | 170:19eb464bc2be | 221 | #if DEBUG_MCO == 2 |
Kojto | 170:19eb464bc2be | 222 | if (bypass == 0) |
Kojto | 170:19eb464bc2be | 223 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz |
Kojto | 170:19eb464bc2be | 224 | else |
Kojto | 170:19eb464bc2be | 225 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
Kojto | 170:19eb464bc2be | 226 | #endif |
Kojto | 170:19eb464bc2be | 227 | |
Kojto | 170:19eb464bc2be | 228 | return 1; // OK |
Kojto | 170:19eb464bc2be | 229 | } |
Kojto | 170:19eb464bc2be | 230 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
Kojto | 170:19eb464bc2be | 231 | |
Kojto | 170:19eb464bc2be | 232 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
Kojto | 170:19eb464bc2be | 233 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 234 | /* PLL (clocked by HSI) used as System clock source */ |
Kojto | 170:19eb464bc2be | 235 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 236 | uint8_t SetSysClock_PLL_HSI(void) |
Kojto | 170:19eb464bc2be | 237 | { |
Kojto | 170:19eb464bc2be | 238 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 239 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 240 | RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; |
Kojto | 170:19eb464bc2be | 241 | |
Kojto | 170:19eb464bc2be | 242 | // Select MSI as system clock source to allow modification of the PLL configuration |
Kojto | 170:19eb464bc2be | 243 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
Kojto | 170:19eb464bc2be | 244 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; |
Kojto | 170:19eb464bc2be | 245 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); |
Kojto | 170:19eb464bc2be | 246 | |
Kojto | 170:19eb464bc2be | 247 | // Enable HSI oscillator and activate PLL with HSI as source |
Kojto | 170:19eb464bc2be | 248 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
Kojto | 170:19eb464bc2be | 249 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
Kojto | 170:19eb464bc2be | 250 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
Kojto | 170:19eb464bc2be | 251 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
Kojto | 170:19eb464bc2be | 252 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
Kojto | 170:19eb464bc2be | 253 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz |
Kojto | 170:19eb464bc2be | 254 | RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) |
Kojto | 170:19eb464bc2be | 255 | RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) |
Kojto | 170:19eb464bc2be | 256 | RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) |
Kojto | 170:19eb464bc2be | 257 | RCC_OscInitStruct.PLL.PLLQ = 2; |
Kojto | 170:19eb464bc2be | 258 | RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) |
Kojto | 170:19eb464bc2be | 259 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 260 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 261 | } |
Kojto | 170:19eb464bc2be | 262 | |
Kojto | 170:19eb464bc2be | 263 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
Kojto | 170:19eb464bc2be | 264 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
Kojto | 170:19eb464bc2be | 265 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz |
Kojto | 170:19eb464bc2be | 266 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz |
Kojto | 170:19eb464bc2be | 267 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
Kojto | 170:19eb464bc2be | 268 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
Kojto | 170:19eb464bc2be | 269 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 270 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 271 | } |
Kojto | 170:19eb464bc2be | 272 | |
Kojto | 170:19eb464bc2be | 273 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; |
Kojto | 170:19eb464bc2be | 274 | RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; |
Kojto | 170:19eb464bc2be | 275 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; |
Kojto | 170:19eb464bc2be | 276 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; |
Kojto | 170:19eb464bc2be | 277 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; |
Kojto | 170:19eb464bc2be | 278 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; |
Kojto | 170:19eb464bc2be | 279 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; |
Kojto | 170:19eb464bc2be | 280 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; |
Kojto | 170:19eb464bc2be | 281 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; |
Kojto | 170:19eb464bc2be | 282 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 283 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 284 | } |
Kojto | 170:19eb464bc2be | 285 | |
Kojto | 170:19eb464bc2be | 286 | // Disable MSI Oscillator |
Kojto | 170:19eb464bc2be | 287 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; |
Kojto | 170:19eb464bc2be | 288 | RCC_OscInitStruct.MSIState = RCC_MSI_OFF; |
Kojto | 170:19eb464bc2be | 289 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
Kojto | 170:19eb464bc2be | 290 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
Kojto | 170:19eb464bc2be | 291 | |
Kojto | 170:19eb464bc2be | 292 | // Output clock on MCO1 pin(PA8) for debugging purpose |
Kojto | 170:19eb464bc2be | 293 | #if DEBUG_MCO == 3 |
Kojto | 170:19eb464bc2be | 294 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
Kojto | 170:19eb464bc2be | 295 | #endif |
Kojto | 170:19eb464bc2be | 296 | |
Kojto | 170:19eb464bc2be | 297 | return 1; // OK |
Kojto | 170:19eb464bc2be | 298 | } |
Kojto | 170:19eb464bc2be | 299 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
Kojto | 170:19eb464bc2be | 300 | |
Kojto | 170:19eb464bc2be | 301 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
Kojto | 170:19eb464bc2be | 302 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 303 | /* PLL (clocked by MSI) used as System clock source */ |
Kojto | 170:19eb464bc2be | 304 | /******************************************************************************/ |
Kojto | 170:19eb464bc2be | 305 | uint8_t SetSysClock_PLL_MSI(void) |
Kojto | 170:19eb464bc2be | 306 | { |
Kojto | 170:19eb464bc2be | 307 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 308 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 309 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; |
Kojto | 170:19eb464bc2be | 310 | |
Kojto | 170:19eb464bc2be | 311 | // Enable LSE Oscillator to automatically calibrate the MSI clock |
Kojto | 170:19eb464bc2be | 312 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; |
Kojto | 170:19eb464bc2be | 313 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
Kojto | 170:19eb464bc2be | 314 | RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT |
Kojto | 170:19eb464bc2be | 315 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { |
Kojto | 170:19eb464bc2be | 316 | RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode |
Kojto | 170:19eb464bc2be | 317 | } |
Kojto | 170:19eb464bc2be | 318 | |
Kojto | 170:19eb464bc2be | 319 | HAL_RCCEx_DisableLSECSS(); |
Kojto | 170:19eb464bc2be | 320 | /* Enable MSI Oscillator and activate PLL with MSI as source */ |
Kojto | 170:19eb464bc2be | 321 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
Kojto | 170:19eb464bc2be | 322 | RCC_OscInitStruct.MSIState = RCC_MSI_ON; |
Kojto | 170:19eb464bc2be | 323 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
Kojto | 170:19eb464bc2be | 324 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
Kojto | 170:19eb464bc2be | 325 | |
Kojto | 170:19eb464bc2be | 326 | RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; |
Kojto | 170:19eb464bc2be | 327 | RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ |
Kojto | 170:19eb464bc2be | 328 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
Kojto | 170:19eb464bc2be | 329 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; |
Kojto | 170:19eb464bc2be | 330 | RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ |
Kojto | 170:19eb464bc2be | 331 | RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ |
Kojto | 170:19eb464bc2be | 332 | RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ |
Kojto | 170:19eb464bc2be | 333 | RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ |
Kojto | 170:19eb464bc2be | 334 | RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ |
Kojto | 170:19eb464bc2be | 335 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 336 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 337 | } |
Kojto | 170:19eb464bc2be | 338 | /* Enable MSI Auto-calibration through LSE */ |
Kojto | 170:19eb464bc2be | 339 | HAL_RCCEx_EnableMSIPLLMode(); |
Kojto | 170:19eb464bc2be | 340 | /* Select MSI output as USB clock source */ |
Kojto | 170:19eb464bc2be | 341 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; |
Kojto | 170:19eb464bc2be | 342 | PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ |
Kojto | 170:19eb464bc2be | 343 | HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); |
Kojto | 170:19eb464bc2be | 344 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
Kojto | 170:19eb464bc2be | 345 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
Kojto | 170:19eb464bc2be | 346 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ |
Kojto | 170:19eb464bc2be | 347 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ |
Kojto | 170:19eb464bc2be | 348 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ |
Kojto | 170:19eb464bc2be | 349 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ |
Kojto | 170:19eb464bc2be | 350 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
Kojto | 170:19eb464bc2be | 351 | return 0; // FAIL |
Kojto | 170:19eb464bc2be | 352 | } |
Kojto | 170:19eb464bc2be | 353 | |
Kojto | 170:19eb464bc2be | 354 | // Output clock on MCO1 pin(PA8) for debugging purpose |
Kojto | 170:19eb464bc2be | 355 | #if DEBUG_MCO == 4 |
Kojto | 170:19eb464bc2be | 356 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz |
Kojto | 170:19eb464bc2be | 357 | #endif |
Kojto | 170:19eb464bc2be | 358 | |
Kojto | 170:19eb464bc2be | 359 | return 1; // OK |
Kojto | 170:19eb464bc2be | 360 | } |
Kojto | 170:19eb464bc2be | 361 | #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ |