mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_usart.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
184:08ed48f1de7f
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_usart.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief USART LL module driver.
<> 149:156823d33999 8 ******************************************************************************
<> 149:156823d33999 9 * @attention
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 12 *
<> 149:156823d33999 13 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 14 * are permitted provided that the following conditions are met:
<> 149:156823d33999 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer.
<> 149:156823d33999 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 18 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 19 * and/or other materials provided with the distribution.
<> 149:156823d33999 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 21 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 22 * without specific prior written permission.
<> 149:156823d33999 23 *
<> 149:156823d33999 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 34 *
<> 149:156823d33999 35 ******************************************************************************
<> 149:156823d33999 36 */
<> 149:156823d33999 37 #if defined(USE_FULL_LL_DRIVER)
<> 149:156823d33999 38
<> 149:156823d33999 39 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 40 #include "stm32l1xx_ll_usart.h"
<> 149:156823d33999 41 #include "stm32l1xx_ll_rcc.h"
<> 149:156823d33999 42 #include "stm32l1xx_ll_bus.h"
<> 149:156823d33999 43 #ifdef USE_FULL_ASSERT
<> 149:156823d33999 44 #include "stm32_assert.h"
<> 149:156823d33999 45 #else
<> 149:156823d33999 46 #define assert_param(expr) ((void)0U)
<> 149:156823d33999 47 #endif
<> 149:156823d33999 48
<> 149:156823d33999 49 /** @addtogroup STM32L1xx_LL_Driver
<> 149:156823d33999 50 * @{
<> 149:156823d33999 51 */
<> 149:156823d33999 52
<> 149:156823d33999 53 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
<> 149:156823d33999 54
<> 149:156823d33999 55 /** @addtogroup USART_LL
<> 149:156823d33999 56 * @{
<> 149:156823d33999 57 */
<> 149:156823d33999 58
<> 149:156823d33999 59 /* Private types -------------------------------------------------------------*/
<> 149:156823d33999 60 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 61 /* Private constants ---------------------------------------------------------*/
<> 149:156823d33999 62 /** @addtogroup USART_LL_Private_Constants
<> 149:156823d33999 63 * @{
<> 149:156823d33999 64 */
<> 149:156823d33999 65
<> 149:156823d33999 66 /**
<> 149:156823d33999 67 * @}
<> 149:156823d33999 68 */
<> 149:156823d33999 69
<> 149:156823d33999 70
<> 149:156823d33999 71 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 72 /** @addtogroup USART_LL_Private_Macros
<> 149:156823d33999 73 * @{
<> 149:156823d33999 74 */
<> 149:156823d33999 75
<> 149:156823d33999 76 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
<> 149:156823d33999 77 * divided by the smallest oversampling used on the USART (i.e. 8) */
<> 149:156823d33999 78 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
<> 149:156823d33999 79
<> 149:156823d33999 80 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
<> 149:156823d33999 81 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
<> 149:156823d33999 82 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
<> 149:156823d33999 83 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
<> 149:156823d33999 84
<> 149:156823d33999 85 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
<> 149:156823d33999 86 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
<> 149:156823d33999 87 || ((__VALUE__) == LL_USART_PARITY_ODD))
<> 149:156823d33999 88
<> 149:156823d33999 89 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
<> 149:156823d33999 90 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
<> 149:156823d33999 91
<> 149:156823d33999 92 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
<> 149:156823d33999 93 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
<> 149:156823d33999 94
<> 149:156823d33999 95 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
<> 149:156823d33999 96 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
<> 149:156823d33999 97
<> 149:156823d33999 98 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
<> 149:156823d33999 99 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
<> 149:156823d33999 100
<> 149:156823d33999 101 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
<> 149:156823d33999 102 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
<> 149:156823d33999 103
<> 149:156823d33999 104 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
<> 149:156823d33999 105 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
<> 149:156823d33999 106
<> 149:156823d33999 107 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
<> 149:156823d33999 108 || ((__VALUE__) == LL_USART_STOPBITS_1) \
<> 149:156823d33999 109 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
<> 149:156823d33999 110 || ((__VALUE__) == LL_USART_STOPBITS_2))
<> 149:156823d33999 111
<> 149:156823d33999 112 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
<> 149:156823d33999 113 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
<> 149:156823d33999 114 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
<> 149:156823d33999 115 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
<> 149:156823d33999 116
<> 149:156823d33999 117 /**
<> 149:156823d33999 118 * @}
<> 149:156823d33999 119 */
<> 149:156823d33999 120
<> 149:156823d33999 121 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 122
<> 149:156823d33999 123 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 124 /** @addtogroup USART_LL_Exported_Functions
<> 149:156823d33999 125 * @{
<> 149:156823d33999 126 */
<> 149:156823d33999 127
<> 149:156823d33999 128 /** @addtogroup USART_LL_EF_Init
<> 149:156823d33999 129 * @{
<> 149:156823d33999 130 */
<> 149:156823d33999 131
<> 149:156823d33999 132 /**
<> 149:156823d33999 133 * @brief De-initialize USART registers (Registers restored to their default values).
<> 149:156823d33999 134 * @param USARTx USART Instance
<> 149:156823d33999 135 * @retval An ErrorStatus enumeration value:
<> 149:156823d33999 136 * - SUCCESS: USART registers are de-initialized
<> 149:156823d33999 137 * - ERROR: USART registers are not de-initialized
<> 149:156823d33999 138 */
<> 149:156823d33999 139 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
<> 149:156823d33999 140 {
<> 149:156823d33999 141 ErrorStatus status = SUCCESS;
<> 149:156823d33999 142
<> 149:156823d33999 143 /* Check the parameters */
<> 149:156823d33999 144 assert_param(IS_UART_INSTANCE(USARTx));
<> 149:156823d33999 145
<> 149:156823d33999 146 if (USARTx == USART1)
<> 149:156823d33999 147 {
<> 149:156823d33999 148 /* Force reset of USART clock */
<> 149:156823d33999 149 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
<> 149:156823d33999 150
<> 149:156823d33999 151 /* Release reset of USART clock */
<> 149:156823d33999 152 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
<> 149:156823d33999 153 }
<> 149:156823d33999 154 else if (USARTx == USART2)
<> 149:156823d33999 155 {
<> 149:156823d33999 156 /* Force reset of USART clock */
<> 149:156823d33999 157 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
<> 149:156823d33999 158
<> 149:156823d33999 159 /* Release reset of USART clock */
<> 149:156823d33999 160 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
<> 149:156823d33999 161 }
<> 149:156823d33999 162 else if (USARTx == USART3)
<> 149:156823d33999 163 {
<> 149:156823d33999 164 /* Force reset of USART clock */
<> 149:156823d33999 165 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
<> 149:156823d33999 166
<> 149:156823d33999 167 /* Release reset of USART clock */
<> 149:156823d33999 168 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
<> 149:156823d33999 169 }
<> 149:156823d33999 170 #if defined(UART4)
<> 149:156823d33999 171 else if (USARTx == UART4)
<> 149:156823d33999 172 {
<> 149:156823d33999 173 /* Force reset of UART clock */
<> 149:156823d33999 174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
<> 149:156823d33999 175
<> 149:156823d33999 176 /* Release reset of UART clock */
<> 149:156823d33999 177 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
<> 149:156823d33999 178 }
<> 149:156823d33999 179 #endif /* UART4 */
<> 149:156823d33999 180 #if defined(UART5)
<> 149:156823d33999 181 else if (USARTx == UART5)
<> 149:156823d33999 182 {
<> 149:156823d33999 183 /* Force reset of UART clock */
<> 149:156823d33999 184 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
<> 149:156823d33999 185
<> 149:156823d33999 186 /* Release reset of UART clock */
<> 149:156823d33999 187 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
<> 149:156823d33999 188 }
<> 149:156823d33999 189 #endif /* UART5 */
<> 149:156823d33999 190 else
<> 149:156823d33999 191 {
<> 149:156823d33999 192 status = ERROR;
<> 149:156823d33999 193 }
<> 149:156823d33999 194
<> 149:156823d33999 195 return (status);
<> 149:156823d33999 196 }
<> 149:156823d33999 197
<> 149:156823d33999 198 /**
<> 149:156823d33999 199 * @brief Initialize USART registers according to the specified
<> 149:156823d33999 200 * parameters in USART_InitStruct.
<> 149:156823d33999 201 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 149:156823d33999 202 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 149:156823d33999 203 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
<> 149:156823d33999 204 * @param USARTx USART Instance
<> 149:156823d33999 205 * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
<> 149:156823d33999 206 * that contains the configuration information for the specified USART peripheral.
<> 149:156823d33999 207 * @retval An ErrorStatus enumeration value:
<> 149:156823d33999 208 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
<> 149:156823d33999 209 * - ERROR: Problem occurred during USART Registers initialization
<> 149:156823d33999 210 */
<> 149:156823d33999 211 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
<> 149:156823d33999 212 {
<> 149:156823d33999 213 ErrorStatus status = ERROR;
<> 149:156823d33999 214 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
<> 149:156823d33999 215 LL_RCC_ClocksTypeDef rcc_clocks;
<> 149:156823d33999 216
<> 149:156823d33999 217 /* Check the parameters */
<> 149:156823d33999 218 assert_param(IS_UART_INSTANCE(USARTx));
<> 149:156823d33999 219 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
<> 149:156823d33999 220 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
<> 149:156823d33999 221 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
<> 149:156823d33999 222 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
<> 149:156823d33999 223 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
<> 149:156823d33999 224 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
<> 149:156823d33999 225 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
<> 149:156823d33999 226
<> 149:156823d33999 227 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 149:156823d33999 228 CRx registers */
<> 149:156823d33999 229 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 149:156823d33999 230 {
<> 149:156823d33999 231 /*---------------------------- USART CR1 Configuration -----------------------
<> 149:156823d33999 232 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
<> 149:156823d33999 233 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
<> 149:156823d33999 234 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
<> 149:156823d33999 235 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
<> 149:156823d33999 236 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
<> 149:156823d33999 237 */
<> 149:156823d33999 238 MODIFY_REG(USARTx->CR1,
<> 149:156823d33999 239 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
<> 149:156823d33999 240 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
<> 149:156823d33999 241 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
<> 149:156823d33999 242 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
<> 149:156823d33999 243
<> 149:156823d33999 244 /*---------------------------- USART CR2 Configuration -----------------------
<> 149:156823d33999 245 * Configure USARTx CR2 (Stop bits) with parameters:
<> 149:156823d33999 246 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
<> 149:156823d33999 247 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
<> 149:156823d33999 248 */
<> 149:156823d33999 249 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
<> 149:156823d33999 250
<> 149:156823d33999 251 /*---------------------------- USART CR3 Configuration -----------------------
<> 149:156823d33999 252 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
<> 149:156823d33999 253 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
<> 149:156823d33999 254 */
<> 149:156823d33999 255 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
<> 149:156823d33999 256
<> 149:156823d33999 257 /*---------------------------- USART BRR Configuration -----------------------
<> 149:156823d33999 258 * Retrieve Clock frequency used for USART Peripheral
<> 149:156823d33999 259 */
<> 149:156823d33999 260 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
<> 149:156823d33999 261 if (USARTx == USART1)
<> 149:156823d33999 262 {
<> 149:156823d33999 263 periphclk = rcc_clocks.PCLK2_Frequency;
<> 149:156823d33999 264 }
<> 149:156823d33999 265 else if (USARTx == USART2)
<> 149:156823d33999 266 {
<> 149:156823d33999 267 periphclk = rcc_clocks.PCLK1_Frequency;
<> 149:156823d33999 268 }
<> 149:156823d33999 269 else if (USARTx == USART3)
<> 149:156823d33999 270 {
<> 149:156823d33999 271 periphclk = rcc_clocks.PCLK1_Frequency;
<> 149:156823d33999 272 }
<> 149:156823d33999 273 #if defined(UART4)
<> 149:156823d33999 274 else if (USARTx == UART4)
<> 149:156823d33999 275 {
<> 149:156823d33999 276 periphclk = rcc_clocks.PCLK1_Frequency;
<> 149:156823d33999 277 }
<> 149:156823d33999 278 #endif /* UART4 */
<> 149:156823d33999 279 #if defined(UART5)
<> 149:156823d33999 280 else if (USARTx == UART5)
<> 149:156823d33999 281 {
<> 149:156823d33999 282 periphclk = rcc_clocks.PCLK1_Frequency;
<> 149:156823d33999 283 }
<> 149:156823d33999 284 #endif /* UART5 */
<> 149:156823d33999 285 else
<> 149:156823d33999 286 {
<> 149:156823d33999 287 /* Nothing to do, as error code is already assigned to ERROR value */
<> 149:156823d33999 288 }
<> 149:156823d33999 289
<> 149:156823d33999 290 /* Configure the USART Baud Rate :
<> 149:156823d33999 291 - valid baud rate value (different from 0) is required
<> 149:156823d33999 292 - Peripheral clock as returned by RCC service, should be valid (different from 0).
<> 149:156823d33999 293 */
<> 149:156823d33999 294 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
<> 149:156823d33999 295 && (USART_InitStruct->BaudRate != 0U))
<> 149:156823d33999 296 {
<> 149:156823d33999 297 status = SUCCESS;
<> 149:156823d33999 298 LL_USART_SetBaudRate(USARTx,
<> 149:156823d33999 299 periphclk,
<> 149:156823d33999 300 USART_InitStruct->OverSampling,
<> 149:156823d33999 301 USART_InitStruct->BaudRate);
<> 149:156823d33999 302 }
<> 149:156823d33999 303 }
<> 149:156823d33999 304 /* Endif (=> USART not in Disabled state => return ERROR) */
<> 149:156823d33999 305
<> 149:156823d33999 306 return (status);
<> 149:156823d33999 307 }
<> 149:156823d33999 308
<> 149:156823d33999 309 /**
<> 149:156823d33999 310 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
<> 149:156823d33999 311 * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
<> 149:156823d33999 312 * whose fields will be set to default values.
<> 149:156823d33999 313 * @retval None
<> 149:156823d33999 314 */
<> 149:156823d33999 315
<> 149:156823d33999 316 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
<> 149:156823d33999 317 {
<> 149:156823d33999 318 /* Set USART_InitStruct fields to default values */
<> 149:156823d33999 319 USART_InitStruct->BaudRate = 9600U;
<> 149:156823d33999 320 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
<> 149:156823d33999 321 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
<> 149:156823d33999 322 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
<> 149:156823d33999 323 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
<> 149:156823d33999 324 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
<> 149:156823d33999 325 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
<> 149:156823d33999 326 }
<> 149:156823d33999 327
<> 149:156823d33999 328 /**
<> 149:156823d33999 329 * @brief Initialize USART Clock related settings according to the
<> 149:156823d33999 330 * specified parameters in the USART_ClockInitStruct.
<> 149:156823d33999 331 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 149:156823d33999 332 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 149:156823d33999 333 * @param USARTx USART Instance
<> 149:156823d33999 334 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 149:156823d33999 335 * that contains the Clock configuration information for the specified USART peripheral.
<> 149:156823d33999 336 * @retval An ErrorStatus enumeration value:
<> 149:156823d33999 337 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
<> 149:156823d33999 338 * - ERROR: Problem occurred during USART Registers initialization
<> 149:156823d33999 339 */
<> 149:156823d33999 340 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 149:156823d33999 341 {
<> 149:156823d33999 342 ErrorStatus status = SUCCESS;
<> 149:156823d33999 343
<> 149:156823d33999 344 /* Check USART Instance and Clock signal output parameters */
<> 149:156823d33999 345 assert_param(IS_UART_INSTANCE(USARTx));
<> 149:156823d33999 346 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
<> 149:156823d33999 347
<> 149:156823d33999 348 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 149:156823d33999 349 CRx registers */
<> 149:156823d33999 350 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 149:156823d33999 351 {
<> 149:156823d33999 352 /*---------------------------- USART CR2 Configuration -----------------------*/
<> 149:156823d33999 353 /* If Clock signal has to be output */
<> 149:156823d33999 354 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
<> 149:156823d33999 355 {
<> 149:156823d33999 356 /* Deactivate Clock signal delivery :
<> 149:156823d33999 357 * - Disable Clock Output: USART_CR2_CLKEN cleared
<> 149:156823d33999 358 */
<> 149:156823d33999 359 LL_USART_DisableSCLKOutput(USARTx);
<> 149:156823d33999 360 }
<> 149:156823d33999 361 else
<> 149:156823d33999 362 {
<> 149:156823d33999 363 /* Ensure USART instance is USART capable */
<> 149:156823d33999 364 assert_param(IS_USART_INSTANCE(USARTx));
<> 149:156823d33999 365
<> 149:156823d33999 366 /* Check clock related parameters */
<> 149:156823d33999 367 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
<> 149:156823d33999 368 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
<> 149:156823d33999 369 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
<> 149:156823d33999 370
<> 149:156823d33999 371 /*---------------------------- USART CR2 Configuration -----------------------
<> 149:156823d33999 372 * Configure USARTx CR2 (Clock signal related bits) with parameters:
<> 149:156823d33999 373 * - Enable Clock Output: USART_CR2_CLKEN set
<> 149:156823d33999 374 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
<> 149:156823d33999 375 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
<> 149:156823d33999 376 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
<> 149:156823d33999 377 */
<> 149:156823d33999 378 MODIFY_REG(USARTx->CR2,
<> 149:156823d33999 379 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
<> 149:156823d33999 380 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
<> 149:156823d33999 381 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
<> 149:156823d33999 382 }
<> 149:156823d33999 383 }
<> 149:156823d33999 384 /* Else (USART not in Disabled state => return ERROR */
<> 149:156823d33999 385 else
<> 149:156823d33999 386 {
<> 149:156823d33999 387 status = ERROR;
<> 149:156823d33999 388 }
<> 149:156823d33999 389
<> 149:156823d33999 390 return (status);
<> 149:156823d33999 391 }
<> 149:156823d33999 392
<> 149:156823d33999 393 /**
<> 149:156823d33999 394 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
<> 149:156823d33999 395 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 149:156823d33999 396 * whose fields will be set to default values.
<> 149:156823d33999 397 * @retval None
<> 149:156823d33999 398 */
<> 149:156823d33999 399 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 149:156823d33999 400 {
<> 149:156823d33999 401 /* Set LL_USART_ClockInitStruct fields with default values */
<> 149:156823d33999 402 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
<> 149:156823d33999 403 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 149:156823d33999 404 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 149:156823d33999 405 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 149:156823d33999 406 }
<> 149:156823d33999 407
<> 149:156823d33999 408 /**
<> 149:156823d33999 409 * @}
<> 149:156823d33999 410 */
<> 149:156823d33999 411
<> 149:156823d33999 412 /**
<> 149:156823d33999 413 * @}
<> 149:156823d33999 414 */
<> 149:156823d33999 415
<> 149:156823d33999 416 /**
<> 149:156823d33999 417 * @}
<> 149:156823d33999 418 */
<> 149:156823d33999 419
<> 149:156823d33999 420 #endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
<> 149:156823d33999 421
<> 149:156823d33999 422 /**
<> 149:156823d33999 423 * @}
<> 149:156823d33999 424 */
<> 149:156823d33999 425
<> 149:156823d33999 426 #endif /* USE_FULL_LL_DRIVER */
<> 149:156823d33999 427
<> 149:156823d33999 428 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 149:156823d33999 429