mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Child:
- 184:08ed48f1de7f
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /** |
<> | 149:156823d33999 | 2 | ****************************************************************************** |
<> | 149:156823d33999 | 3 | * @file stm32l1xx_ll_rcc.h |
<> | 149:156823d33999 | 4 | * @author MCD Application Team |
<> | 149:156823d33999 | 5 | * @version V1.2.0 |
<> | 149:156823d33999 | 6 | * @date 01-July-2016 |
<> | 149:156823d33999 | 7 | * @brief Header file of RCC LL module. |
<> | 149:156823d33999 | 8 | ****************************************************************************** |
<> | 149:156823d33999 | 9 | * @attention |
<> | 149:156823d33999 | 10 | * |
<> | 149:156823d33999 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 149:156823d33999 | 12 | * |
<> | 149:156823d33999 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 149:156823d33999 | 14 | * are permitted provided that the following conditions are met: |
<> | 149:156823d33999 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 149:156823d33999 | 16 | * this list of conditions and the following disclaimer. |
<> | 149:156823d33999 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 149:156823d33999 | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 149:156823d33999 | 19 | * and/or other materials provided with the distribution. |
<> | 149:156823d33999 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 149:156823d33999 | 21 | * may be used to endorse or promote products derived from this software |
<> | 149:156823d33999 | 22 | * without specific prior written permission. |
<> | 149:156823d33999 | 23 | * |
<> | 149:156823d33999 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 149:156823d33999 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 149:156823d33999 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 149:156823d33999 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 149:156823d33999 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 149:156823d33999 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 149:156823d33999 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 149:156823d33999 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 149:156823d33999 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 149:156823d33999 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 149:156823d33999 | 34 | * |
<> | 149:156823d33999 | 35 | ****************************************************************************** |
<> | 149:156823d33999 | 36 | */ |
<> | 149:156823d33999 | 37 | |
<> | 149:156823d33999 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 149:156823d33999 | 39 | #ifndef __STM32L1xx_LL_RCC_H |
<> | 149:156823d33999 | 40 | #define __STM32L1xx_LL_RCC_H |
<> | 149:156823d33999 | 41 | |
<> | 149:156823d33999 | 42 | #ifdef __cplusplus |
<> | 149:156823d33999 | 43 | extern "C" { |
<> | 149:156823d33999 | 44 | #endif |
<> | 149:156823d33999 | 45 | |
<> | 149:156823d33999 | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 47 | #include "stm32l1xx.h" |
<> | 149:156823d33999 | 48 | |
<> | 149:156823d33999 | 49 | /** @addtogroup STM32L1xx_LL_Driver |
<> | 149:156823d33999 | 50 | * @{ |
<> | 149:156823d33999 | 51 | */ |
<> | 149:156823d33999 | 52 | |
<> | 149:156823d33999 | 53 | #if defined(RCC) |
<> | 149:156823d33999 | 54 | |
<> | 149:156823d33999 | 55 | /** @defgroup RCC_LL RCC |
<> | 149:156823d33999 | 56 | * @{ |
<> | 149:156823d33999 | 57 | */ |
<> | 149:156823d33999 | 58 | |
<> | 149:156823d33999 | 59 | /* Private types -------------------------------------------------------------*/ |
<> | 149:156823d33999 | 60 | /* Private variables ---------------------------------------------------------*/ |
<> | 149:156823d33999 | 61 | /** @defgroup RCC_LL_Private_Variables RCC Private Variables |
<> | 149:156823d33999 | 62 | * @{ |
<> | 149:156823d33999 | 63 | */ |
<> | 149:156823d33999 | 64 | |
<> | 149:156823d33999 | 65 | /** |
<> | 149:156823d33999 | 66 | * @} |
<> | 149:156823d33999 | 67 | */ |
<> | 149:156823d33999 | 68 | |
<> | 149:156823d33999 | 69 | /* Private constants ---------------------------------------------------------*/ |
<> | 149:156823d33999 | 70 | /** @defgroup RCC_LL_Private_Constants RCC Private Constants |
<> | 149:156823d33999 | 71 | * @{ |
<> | 149:156823d33999 | 72 | */ |
<> | 149:156823d33999 | 73 | /* Defines used for the bit position in the register and perform offsets*/ |
<> | 149:156823d33999 | 74 | #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */ |
<> | 149:156823d33999 | 75 | #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */ |
<> | 149:156823d33999 | 76 | #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */ |
<> | 149:156823d33999 | 77 | #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL) /*!< field position in register RCC_ICSCR */ |
<> | 149:156823d33999 | 78 | #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM) /*!< field position in register RCC_ICSCR */ |
<> | 149:156823d33999 | 79 | #define RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL) /*!< field position in register RCC_ICSCR */ |
<> | 149:156823d33999 | 80 | #define RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM) /*!< field position in register RCC_ICSCR */ |
<> | 149:156823d33999 | 81 | #define RCC_POSITION_MSIRANGE (uint32_t)POSITION_VAL(RCC_ICSCR_MSIRANGE) /*!< field position in register RCC_ICSCR */ |
<> | 149:156823d33999 | 82 | #define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */ |
<> | 149:156823d33999 | 83 | #define RCC_POSITION_PLLDIV (uint32_t)POSITION_VAL(RCC_CFGR_PLLDIV) /*!< field position in register RCC_CFGR */ |
<> | 149:156823d33999 | 84 | |
<> | 149:156823d33999 | 85 | /** |
<> | 149:156823d33999 | 86 | * @} |
<> | 149:156823d33999 | 87 | */ |
<> | 149:156823d33999 | 88 | |
<> | 149:156823d33999 | 89 | /* Private macros ------------------------------------------------------------*/ |
<> | 149:156823d33999 | 90 | /* Exported types ------------------------------------------------------------*/ |
<> | 149:156823d33999 | 91 | #if defined(USE_FULL_LL_DRIVER) |
<> | 149:156823d33999 | 92 | /** @defgroup RCC_LL_Exported_Types RCC Exported Types |
<> | 149:156823d33999 | 93 | * @{ |
<> | 149:156823d33999 | 94 | */ |
<> | 149:156823d33999 | 95 | |
<> | 149:156823d33999 | 96 | /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure |
<> | 149:156823d33999 | 97 | * @{ |
<> | 149:156823d33999 | 98 | */ |
<> | 149:156823d33999 | 99 | |
<> | 149:156823d33999 | 100 | /** |
<> | 149:156823d33999 | 101 | * @brief RCC Clocks Frequency Structure |
<> | 149:156823d33999 | 102 | */ |
<> | 149:156823d33999 | 103 | typedef struct |
<> | 149:156823d33999 | 104 | { |
<> | 149:156823d33999 | 105 | uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ |
<> | 149:156823d33999 | 106 | uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ |
<> | 149:156823d33999 | 107 | uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ |
<> | 149:156823d33999 | 108 | uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ |
<> | 149:156823d33999 | 109 | } LL_RCC_ClocksTypeDef; |
<> | 149:156823d33999 | 110 | |
<> | 149:156823d33999 | 111 | /** |
<> | 149:156823d33999 | 112 | * @} |
<> | 149:156823d33999 | 113 | */ |
<> | 149:156823d33999 | 114 | |
<> | 149:156823d33999 | 115 | /** |
<> | 149:156823d33999 | 116 | * @} |
<> | 149:156823d33999 | 117 | */ |
<> | 149:156823d33999 | 118 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 149:156823d33999 | 119 | |
<> | 149:156823d33999 | 120 | /* Exported constants --------------------------------------------------------*/ |
<> | 149:156823d33999 | 121 | /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants |
<> | 149:156823d33999 | 122 | * @{ |
<> | 149:156823d33999 | 123 | */ |
<> | 149:156823d33999 | 124 | |
<> | 149:156823d33999 | 125 | /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation |
<> | 149:156823d33999 | 126 | * @brief Defines used to adapt values of different oscillators |
<> | 149:156823d33999 | 127 | * @note These values could be modified in the user environment according to |
<> | 149:156823d33999 | 128 | * HW set-up. |
<> | 149:156823d33999 | 129 | * @{ |
<> | 149:156823d33999 | 130 | */ |
<> | 149:156823d33999 | 131 | #if !defined (HSE_VALUE) |
<> | 149:156823d33999 | 132 | #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ |
<> | 149:156823d33999 | 133 | #endif /* HSE_VALUE */ |
<> | 149:156823d33999 | 134 | |
<> | 149:156823d33999 | 135 | #if !defined (HSI_VALUE) |
<> | 149:156823d33999 | 136 | #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the HSI oscillator in Hz */ |
<> | 149:156823d33999 | 137 | #endif /* HSI_VALUE */ |
<> | 149:156823d33999 | 138 | |
<> | 149:156823d33999 | 139 | #if !defined (LSE_VALUE) |
<> | 149:156823d33999 | 140 | #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ |
<> | 149:156823d33999 | 141 | #endif /* LSE_VALUE */ |
<> | 149:156823d33999 | 142 | |
<> | 149:156823d33999 | 143 | #if !defined (LSI_VALUE) |
<> | 149:156823d33999 | 144 | #define LSI_VALUE ((uint32_t)32000U) /*!< Value of the LSI oscillator in Hz */ |
<> | 149:156823d33999 | 145 | #endif /* LSI_VALUE */ |
<> | 149:156823d33999 | 146 | /** |
<> | 149:156823d33999 | 147 | * @} |
<> | 149:156823d33999 | 148 | */ |
<> | 149:156823d33999 | 149 | |
<> | 149:156823d33999 | 150 | /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines |
<> | 149:156823d33999 | 151 | * @brief Flags defines which can be used with LL_RCC_WriteReg function |
<> | 149:156823d33999 | 152 | * @{ |
<> | 149:156823d33999 | 153 | */ |
<> | 149:156823d33999 | 154 | #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ |
<> | 149:156823d33999 | 155 | #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ |
<> | 149:156823d33999 | 156 | #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ |
<> | 149:156823d33999 | 157 | #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ |
<> | 149:156823d33999 | 158 | #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ |
<> | 149:156823d33999 | 159 | #define LL_RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC /*!< MSI Ready Interrupt Clear */ |
<> | 149:156823d33999 | 160 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 161 | #define LL_RCC_CIR_LSECSSC RCC_CIR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ |
<> | 149:156823d33999 | 162 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 163 | #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ |
<> | 149:156823d33999 | 164 | /** |
<> | 149:156823d33999 | 165 | * @} |
<> | 149:156823d33999 | 166 | */ |
<> | 149:156823d33999 | 167 | |
<> | 149:156823d33999 | 168 | /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines |
<> | 149:156823d33999 | 169 | * @brief Flags defines which can be used with LL_RCC_ReadReg function |
<> | 149:156823d33999 | 170 | * @{ |
<> | 149:156823d33999 | 171 | */ |
<> | 149:156823d33999 | 172 | #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ |
<> | 149:156823d33999 | 173 | #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ |
<> | 149:156823d33999 | 174 | #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ |
<> | 149:156823d33999 | 175 | #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ |
<> | 149:156823d33999 | 176 | #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ |
<> | 149:156823d33999 | 177 | #define LL_RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF /*!< MSI Ready Interrupt flag */ |
<> | 149:156823d33999 | 178 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 179 | #define LL_RCC_CIR_LSECSSF RCC_CIR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ |
<> | 149:156823d33999 | 180 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 181 | #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ |
<> | 149:156823d33999 | 182 | #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ |
<> | 149:156823d33999 | 183 | #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ |
<> | 149:156823d33999 | 184 | #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ |
<> | 149:156823d33999 | 185 | #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ |
<> | 149:156823d33999 | 186 | #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ |
<> | 149:156823d33999 | 187 | #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ |
<> | 149:156823d33999 | 188 | #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ |
<> | 149:156823d33999 | 189 | /** |
<> | 149:156823d33999 | 190 | * @} |
<> | 149:156823d33999 | 191 | */ |
<> | 149:156823d33999 | 192 | |
<> | 149:156823d33999 | 193 | /** @defgroup RCC_LL_EC_IT IT Defines |
<> | 149:156823d33999 | 194 | * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions |
<> | 149:156823d33999 | 195 | * @{ |
<> | 149:156823d33999 | 196 | */ |
<> | 149:156823d33999 | 197 | #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ |
<> | 149:156823d33999 | 198 | #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ |
<> | 149:156823d33999 | 199 | #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ |
<> | 149:156823d33999 | 200 | #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ |
<> | 149:156823d33999 | 201 | #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ |
<> | 149:156823d33999 | 202 | #define LL_RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE /*!< MSI Ready Interrupt Enable */ |
<> | 149:156823d33999 | 203 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 204 | #define LL_RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE /*!< LSE CSS Interrupt Enable */ |
<> | 149:156823d33999 | 205 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 206 | /** |
<> | 149:156823d33999 | 207 | * @} |
<> | 149:156823d33999 | 208 | */ |
<> | 149:156823d33999 | 209 | |
<> | 149:156823d33999 | 210 | /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler |
<> | 149:156823d33999 | 211 | * @{ |
<> | 149:156823d33999 | 212 | */ |
<> | 149:156823d33999 | 213 | #define LL_RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U/*!< HSE is divided by 2 for RTC clock */ |
<> | 149:156823d33999 | 214 | #define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ |
<> | 149:156823d33999 | 215 | #define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ |
<> | 149:156823d33999 | 216 | #define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ |
<> | 149:156823d33999 | 217 | /** |
<> | 149:156823d33999 | 218 | * @} |
<> | 149:156823d33999 | 219 | */ |
<> | 149:156823d33999 | 220 | |
<> | 149:156823d33999 | 221 | /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges |
<> | 149:156823d33999 | 222 | * @{ |
<> | 149:156823d33999 | 223 | */ |
<> | 149:156823d33999 | 224 | #define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ |
<> | 149:156823d33999 | 225 | #define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz*/ |
<> | 149:156823d33999 | 226 | #define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ |
<> | 149:156823d33999 | 227 | #define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ |
<> | 149:156823d33999 | 228 | #define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ |
<> | 149:156823d33999 | 229 | #define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ |
<> | 149:156823d33999 | 230 | #define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ |
<> | 149:156823d33999 | 231 | /** |
<> | 149:156823d33999 | 232 | * @} |
<> | 149:156823d33999 | 233 | */ |
<> | 149:156823d33999 | 234 | |
<> | 149:156823d33999 | 235 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch |
<> | 149:156823d33999 | 236 | * @{ |
<> | 149:156823d33999 | 237 | */ |
<> | 149:156823d33999 | 238 | #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ |
<> | 149:156823d33999 | 239 | #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ |
<> | 149:156823d33999 | 240 | #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ |
<> | 149:156823d33999 | 241 | #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ |
<> | 149:156823d33999 | 242 | /** |
<> | 149:156823d33999 | 243 | * @} |
<> | 149:156823d33999 | 244 | */ |
<> | 149:156823d33999 | 245 | |
<> | 149:156823d33999 | 246 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status |
<> | 149:156823d33999 | 247 | * @{ |
<> | 149:156823d33999 | 248 | */ |
<> | 149:156823d33999 | 249 | #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ |
<> | 149:156823d33999 | 250 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
<> | 149:156823d33999 | 251 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
<> | 149:156823d33999 | 252 | #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
<> | 149:156823d33999 | 253 | /** |
<> | 149:156823d33999 | 254 | * @} |
<> | 149:156823d33999 | 255 | */ |
<> | 149:156823d33999 | 256 | |
<> | 149:156823d33999 | 257 | /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler |
<> | 149:156823d33999 | 258 | * @{ |
<> | 149:156823d33999 | 259 | */ |
<> | 149:156823d33999 | 260 | #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
<> | 149:156823d33999 | 261 | #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
<> | 149:156823d33999 | 262 | #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
<> | 149:156823d33999 | 263 | #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
<> | 149:156823d33999 | 264 | #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
<> | 149:156823d33999 | 265 | #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
<> | 149:156823d33999 | 266 | #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
<> | 149:156823d33999 | 267 | #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
<> | 149:156823d33999 | 268 | #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
<> | 149:156823d33999 | 269 | /** |
<> | 149:156823d33999 | 270 | * @} |
<> | 149:156823d33999 | 271 | */ |
<> | 149:156823d33999 | 272 | |
<> | 149:156823d33999 | 273 | /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) |
<> | 149:156823d33999 | 274 | * @{ |
<> | 149:156823d33999 | 275 | */ |
<> | 149:156823d33999 | 276 | #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
<> | 149:156823d33999 | 277 | #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
<> | 149:156823d33999 | 278 | #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
<> | 149:156823d33999 | 279 | #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
<> | 149:156823d33999 | 280 | #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
<> | 149:156823d33999 | 281 | /** |
<> | 149:156823d33999 | 282 | * @} |
<> | 149:156823d33999 | 283 | */ |
<> | 149:156823d33999 | 284 | |
<> | 149:156823d33999 | 285 | /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) |
<> | 149:156823d33999 | 286 | * @{ |
<> | 149:156823d33999 | 287 | */ |
<> | 149:156823d33999 | 288 | #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ |
<> | 149:156823d33999 | 289 | #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ |
<> | 149:156823d33999 | 290 | #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ |
<> | 149:156823d33999 | 291 | #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ |
<> | 149:156823d33999 | 292 | #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ |
<> | 149:156823d33999 | 293 | /** |
<> | 149:156823d33999 | 294 | * @} |
<> | 149:156823d33999 | 295 | */ |
<> | 149:156823d33999 | 296 | |
<> | 149:156823d33999 | 297 | /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection |
<> | 149:156823d33999 | 298 | * @{ |
<> | 149:156823d33999 | 299 | */ |
<> | 149:156823d33999 | 300 | #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ |
<> | 149:156823d33999 | 301 | #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ |
<> | 149:156823d33999 | 302 | #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ |
<> | 149:156823d33999 | 303 | #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /*!< MSI selection as MCO source */ |
<> | 149:156823d33999 | 304 | #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ |
<> | 149:156823d33999 | 305 | #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ |
<> | 149:156823d33999 | 306 | #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ |
<> | 149:156823d33999 | 307 | #define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MCO source */ |
<> | 149:156823d33999 | 308 | /** |
<> | 149:156823d33999 | 309 | * @} |
<> | 149:156823d33999 | 310 | */ |
<> | 149:156823d33999 | 311 | |
<> | 149:156823d33999 | 312 | /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler |
<> | 149:156823d33999 | 313 | * @{ |
<> | 149:156823d33999 | 314 | */ |
<> | 149:156823d33999 | 315 | #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO Clock divided by 1 */ |
<> | 149:156823d33999 | 316 | #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ |
<> | 149:156823d33999 | 317 | #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ |
<> | 149:156823d33999 | 318 | #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ |
<> | 149:156823d33999 | 319 | #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ |
<> | 149:156823d33999 | 320 | /** |
<> | 149:156823d33999 | 321 | * @} |
<> | 149:156823d33999 | 322 | */ |
<> | 149:156823d33999 | 323 | #if defined(USE_FULL_LL_DRIVER) |
<> | 149:156823d33999 | 324 | /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency |
<> | 149:156823d33999 | 325 | * @{ |
<> | 149:156823d33999 | 326 | */ |
<> | 149:156823d33999 | 327 | #define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */ |
<> | 149:156823d33999 | 328 | #define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ |
<> | 149:156823d33999 | 329 | /** |
<> | 149:156823d33999 | 330 | * @} |
<> | 149:156823d33999 | 331 | */ |
<> | 149:156823d33999 | 332 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 149:156823d33999 | 333 | |
<> | 149:156823d33999 | 334 | |
<> | 149:156823d33999 | 335 | |
<> | 149:156823d33999 | 336 | /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection |
<> | 149:156823d33999 | 337 | * @{ |
<> | 149:156823d33999 | 338 | */ |
<> | 149:156823d33999 | 339 | #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */ |
<> | 149:156823d33999 | 340 | #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ |
<> | 149:156823d33999 | 341 | #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ |
<> | 149:156823d33999 | 342 | #define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler |
<> | 149:156823d33999 | 343 | (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */ |
<> | 149:156823d33999 | 344 | /** |
<> | 149:156823d33999 | 345 | * @} |
<> | 149:156823d33999 | 346 | */ |
<> | 149:156823d33999 | 347 | |
<> | 149:156823d33999 | 348 | /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor |
<> | 149:156823d33999 | 349 | * @{ |
<> | 149:156823d33999 | 350 | */ |
<> | 149:156823d33999 | 351 | #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock * 3 */ |
<> | 149:156823d33999 | 352 | #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock * 4 */ |
<> | 149:156823d33999 | 353 | #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock * 6 */ |
<> | 149:156823d33999 | 354 | #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock * 8 */ |
<> | 149:156823d33999 | 355 | #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */ |
<> | 149:156823d33999 | 356 | #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */ |
<> | 149:156823d33999 | 357 | #define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */ |
<> | 149:156823d33999 | 358 | #define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */ |
<> | 149:156823d33999 | 359 | #define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */ |
<> | 149:156823d33999 | 360 | /** |
<> | 149:156823d33999 | 361 | * @} |
<> | 149:156823d33999 | 362 | */ |
<> | 149:156823d33999 | 363 | |
<> | 149:156823d33999 | 364 | /** @defgroup RCC_LL_EC_PLL_DIV PLL division factor |
<> | 149:156823d33999 | 365 | * @{ |
<> | 149:156823d33999 | 366 | */ |
<> | 149:156823d33999 | 367 | #define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */ |
<> | 149:156823d33999 | 368 | #define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */ |
<> | 149:156823d33999 | 369 | #define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */ |
<> | 149:156823d33999 | 370 | /** |
<> | 149:156823d33999 | 371 | * @} |
<> | 149:156823d33999 | 372 | */ |
<> | 149:156823d33999 | 373 | |
<> | 149:156823d33999 | 374 | /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE |
<> | 149:156823d33999 | 375 | * @{ |
<> | 149:156823d33999 | 376 | */ |
<> | 149:156823d33999 | 377 | #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ |
<> | 149:156823d33999 | 378 | #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ |
<> | 149:156823d33999 | 379 | /** |
<> | 149:156823d33999 | 380 | * @} |
<> | 149:156823d33999 | 381 | */ |
<> | 149:156823d33999 | 382 | |
<> | 149:156823d33999 | 383 | /** |
<> | 149:156823d33999 | 384 | * @} |
<> | 149:156823d33999 | 385 | */ |
<> | 149:156823d33999 | 386 | |
<> | 149:156823d33999 | 387 | /* Exported macro ------------------------------------------------------------*/ |
<> | 149:156823d33999 | 388 | /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros |
<> | 149:156823d33999 | 389 | * @{ |
<> | 149:156823d33999 | 390 | */ |
<> | 149:156823d33999 | 391 | |
<> | 149:156823d33999 | 392 | /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros |
<> | 149:156823d33999 | 393 | * @{ |
<> | 149:156823d33999 | 394 | */ |
<> | 149:156823d33999 | 395 | |
<> | 149:156823d33999 | 396 | /** |
<> | 149:156823d33999 | 397 | * @brief Write a value in RCC register |
<> | 149:156823d33999 | 398 | * @param __REG__ Register to be written |
<> | 149:156823d33999 | 399 | * @param __VALUE__ Value to be written in the register |
<> | 149:156823d33999 | 400 | * @retval None |
<> | 149:156823d33999 | 401 | */ |
<> | 149:156823d33999 | 402 | #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
<> | 149:156823d33999 | 403 | |
<> | 149:156823d33999 | 404 | /** |
<> | 149:156823d33999 | 405 | * @brief Read a value in RCC register |
<> | 149:156823d33999 | 406 | * @param __REG__ Register to be read |
<> | 149:156823d33999 | 407 | * @retval Register value |
<> | 149:156823d33999 | 408 | */ |
<> | 149:156823d33999 | 409 | #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
<> | 149:156823d33999 | 410 | /** |
<> | 149:156823d33999 | 411 | * @} |
<> | 149:156823d33999 | 412 | */ |
<> | 149:156823d33999 | 413 | |
<> | 149:156823d33999 | 414 | /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies |
<> | 149:156823d33999 | 415 | * @{ |
<> | 149:156823d33999 | 416 | */ |
<> | 149:156823d33999 | 417 | |
<> | 149:156823d33999 | 418 | /** |
<> | 149:156823d33999 | 419 | * @brief Helper macro to calculate the PLLCLK frequency |
<> | 149:156823d33999 | 420 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, |
<> | 149:156823d33999 | 421 | * @ref LL_RCC_PLL_GetMultiplicator (), |
<> | 149:156823d33999 | 422 | * @ref LL_RCC_PLL_GetDivider ()); |
<> | 149:156823d33999 | 423 | * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) |
<> | 149:156823d33999 | 424 | * @param __PLLMUL__ This parameter can be one of the following values: |
<> | 149:156823d33999 | 425 | * @arg @ref LL_RCC_PLL_MUL_3 |
<> | 149:156823d33999 | 426 | * @arg @ref LL_RCC_PLL_MUL_4 |
<> | 149:156823d33999 | 427 | * @arg @ref LL_RCC_PLL_MUL_6 |
<> | 149:156823d33999 | 428 | * @arg @ref LL_RCC_PLL_MUL_8 |
<> | 149:156823d33999 | 429 | * @arg @ref LL_RCC_PLL_MUL_12 |
<> | 149:156823d33999 | 430 | * @arg @ref LL_RCC_PLL_MUL_16 |
<> | 149:156823d33999 | 431 | * @arg @ref LL_RCC_PLL_MUL_24 |
<> | 149:156823d33999 | 432 | * @arg @ref LL_RCC_PLL_MUL_32 |
<> | 149:156823d33999 | 433 | * @arg @ref LL_RCC_PLL_MUL_48 |
<> | 149:156823d33999 | 434 | * @param __PLLDIV__ This parameter can be one of the following values: |
<> | 149:156823d33999 | 435 | * @arg @ref LL_RCC_PLL_DIV_2 |
<> | 149:156823d33999 | 436 | * @arg @ref LL_RCC_PLL_DIV_3 |
<> | 149:156823d33999 | 437 | * @arg @ref LL_RCC_PLL_DIV_4 |
<> | 149:156823d33999 | 438 | * @retval PLL clock frequency (in Hz) |
<> | 149:156823d33999 | 439 | */ |
<> | 149:156823d33999 | 440 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_POSITION_PLLMUL]) / (((__PLLDIV__) >> RCC_POSITION_PLLDIV)+1U)) |
<> | 149:156823d33999 | 441 | |
<> | 149:156823d33999 | 442 | /** |
<> | 149:156823d33999 | 443 | * @brief Helper macro to calculate the HCLK frequency |
<> | 149:156823d33999 | 444 | * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler |
<> | 149:156823d33999 | 445 | * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) |
<> | 149:156823d33999 | 446 | * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) |
<> | 149:156823d33999 | 447 | * @param __AHBPRESCALER__: This parameter can be one of the following values: |
<> | 149:156823d33999 | 448 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
<> | 149:156823d33999 | 449 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
<> | 149:156823d33999 | 450 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
<> | 149:156823d33999 | 451 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
<> | 149:156823d33999 | 452 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
<> | 149:156823d33999 | 453 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
<> | 149:156823d33999 | 454 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
<> | 149:156823d33999 | 455 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
<> | 149:156823d33999 | 456 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
<> | 149:156823d33999 | 457 | * @retval HCLK clock frequency (in Hz) |
<> | 149:156823d33999 | 458 | */ |
<> | 149:156823d33999 | 459 | #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]) |
<> | 149:156823d33999 | 460 | |
<> | 149:156823d33999 | 461 | /** |
<> | 149:156823d33999 | 462 | * @brief Helper macro to calculate the PCLK1 frequency (ABP1) |
<> | 149:156823d33999 | 463 | * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler |
<> | 149:156823d33999 | 464 | * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) |
<> | 149:156823d33999 | 465 | * @param __HCLKFREQ__ HCLK frequency |
<> | 149:156823d33999 | 466 | * @param __APB1PRESCALER__: This parameter can be one of the following values: |
<> | 149:156823d33999 | 467 | * @arg @ref LL_RCC_APB1_DIV_1 |
<> | 149:156823d33999 | 468 | * @arg @ref LL_RCC_APB1_DIV_2 |
<> | 149:156823d33999 | 469 | * @arg @ref LL_RCC_APB1_DIV_4 |
<> | 149:156823d33999 | 470 | * @arg @ref LL_RCC_APB1_DIV_8 |
<> | 149:156823d33999 | 471 | * @arg @ref LL_RCC_APB1_DIV_16 |
<> | 149:156823d33999 | 472 | * @retval PCLK1 clock frequency (in Hz) |
<> | 149:156823d33999 | 473 | */ |
<> | 149:156823d33999 | 474 | #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1]) |
<> | 149:156823d33999 | 475 | |
<> | 149:156823d33999 | 476 | /** |
<> | 149:156823d33999 | 477 | * @brief Helper macro to calculate the PCLK2 frequency (ABP2) |
<> | 149:156823d33999 | 478 | * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler |
<> | 149:156823d33999 | 479 | * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) |
<> | 149:156823d33999 | 480 | * @param __HCLKFREQ__ HCLK frequency |
<> | 149:156823d33999 | 481 | * @param __APB2PRESCALER__: This parameter can be one of the following values: |
<> | 149:156823d33999 | 482 | * @arg @ref LL_RCC_APB2_DIV_1 |
<> | 149:156823d33999 | 483 | * @arg @ref LL_RCC_APB2_DIV_2 |
<> | 149:156823d33999 | 484 | * @arg @ref LL_RCC_APB2_DIV_4 |
<> | 149:156823d33999 | 485 | * @arg @ref LL_RCC_APB2_DIV_8 |
<> | 149:156823d33999 | 486 | * @arg @ref LL_RCC_APB2_DIV_16 |
<> | 149:156823d33999 | 487 | * @retval PCLK2 clock frequency (in Hz) |
<> | 149:156823d33999 | 488 | */ |
<> | 149:156823d33999 | 489 | #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2]) |
<> | 149:156823d33999 | 490 | |
<> | 149:156823d33999 | 491 | /** |
<> | 149:156823d33999 | 492 | * @brief Helper macro to calculate the MSI frequency (in Hz) |
<> | 149:156823d33999 | 493 | * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange |
<> | 149:156823d33999 | 494 | * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) |
<> | 149:156823d33999 | 495 | * @param __MSIRANGE__: This parameter can be one of the following values: |
<> | 149:156823d33999 | 496 | * @arg @ref LL_RCC_MSIRANGE_0 |
<> | 149:156823d33999 | 497 | * @arg @ref LL_RCC_MSIRANGE_1 |
<> | 149:156823d33999 | 498 | * @arg @ref LL_RCC_MSIRANGE_2 |
<> | 149:156823d33999 | 499 | * @arg @ref LL_RCC_MSIRANGE_3 |
<> | 149:156823d33999 | 500 | * @arg @ref LL_RCC_MSIRANGE_4 |
<> | 149:156823d33999 | 501 | * @arg @ref LL_RCC_MSIRANGE_5 |
<> | 149:156823d33999 | 502 | * @arg @ref LL_RCC_MSIRANGE_6 |
<> | 149:156823d33999 | 503 | * @retval MSI clock frequency (in Hz) |
<> | 149:156823d33999 | 504 | */ |
<> | 149:156823d33999 | 505 | #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1U << (((__MSIRANGE__) >> RCC_POSITION_MSIRANGE) + 1U)))) |
<> | 149:156823d33999 | 506 | |
<> | 149:156823d33999 | 507 | /** |
<> | 149:156823d33999 | 508 | * @} |
<> | 149:156823d33999 | 509 | */ |
<> | 149:156823d33999 | 510 | |
<> | 149:156823d33999 | 511 | /** |
<> | 149:156823d33999 | 512 | * @} |
<> | 149:156823d33999 | 513 | */ |
<> | 149:156823d33999 | 514 | |
<> | 149:156823d33999 | 515 | /* Exported functions --------------------------------------------------------*/ |
<> | 149:156823d33999 | 516 | /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions |
<> | 149:156823d33999 | 517 | * @{ |
<> | 149:156823d33999 | 518 | */ |
<> | 149:156823d33999 | 519 | |
<> | 149:156823d33999 | 520 | /** @defgroup RCC_LL_EF_HSE HSE |
<> | 149:156823d33999 | 521 | * @{ |
<> | 149:156823d33999 | 522 | */ |
<> | 149:156823d33999 | 523 | |
<> | 149:156823d33999 | 524 | /** |
<> | 149:156823d33999 | 525 | * @brief Enable the Clock Security System. |
<> | 149:156823d33999 | 526 | * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS |
<> | 149:156823d33999 | 527 | * @retval None |
<> | 149:156823d33999 | 528 | */ |
<> | 149:156823d33999 | 529 | __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) |
<> | 149:156823d33999 | 530 | { |
<> | 149:156823d33999 | 531 | SET_BIT(RCC->CR, RCC_CR_CSSON); |
<> | 149:156823d33999 | 532 | } |
<> | 149:156823d33999 | 533 | |
<> | 149:156823d33999 | 534 | /** |
<> | 149:156823d33999 | 535 | * @brief Disable the Clock Security System. |
<> | 149:156823d33999 | 536 | * @note Cannot be disabled in HSE is ready (only by hardware) |
<> | 149:156823d33999 | 537 | * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS |
<> | 149:156823d33999 | 538 | * @retval None |
<> | 149:156823d33999 | 539 | */ |
<> | 149:156823d33999 | 540 | __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) |
<> | 149:156823d33999 | 541 | { |
<> | 149:156823d33999 | 542 | CLEAR_BIT(RCC->CR, RCC_CR_CSSON); |
<> | 149:156823d33999 | 543 | } |
<> | 149:156823d33999 | 544 | |
<> | 149:156823d33999 | 545 | /** |
<> | 149:156823d33999 | 546 | * @brief Enable HSE external oscillator (HSE Bypass) |
<> | 149:156823d33999 | 547 | * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass |
<> | 149:156823d33999 | 548 | * @retval None |
<> | 149:156823d33999 | 549 | */ |
<> | 149:156823d33999 | 550 | __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) |
<> | 149:156823d33999 | 551 | { |
<> | 149:156823d33999 | 552 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); |
<> | 149:156823d33999 | 553 | } |
<> | 149:156823d33999 | 554 | |
<> | 149:156823d33999 | 555 | /** |
<> | 149:156823d33999 | 556 | * @brief Disable HSE external oscillator (HSE Bypass) |
<> | 149:156823d33999 | 557 | * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass |
<> | 149:156823d33999 | 558 | * @retval None |
<> | 149:156823d33999 | 559 | */ |
<> | 149:156823d33999 | 560 | __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) |
<> | 149:156823d33999 | 561 | { |
<> | 149:156823d33999 | 562 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
<> | 149:156823d33999 | 563 | } |
<> | 149:156823d33999 | 564 | |
<> | 149:156823d33999 | 565 | /** |
<> | 149:156823d33999 | 566 | * @brief Enable HSE crystal oscillator (HSE ON) |
<> | 149:156823d33999 | 567 | * @rmtoll CR HSEON LL_RCC_HSE_Enable |
<> | 149:156823d33999 | 568 | * @retval None |
<> | 149:156823d33999 | 569 | */ |
<> | 149:156823d33999 | 570 | __STATIC_INLINE void LL_RCC_HSE_Enable(void) |
<> | 149:156823d33999 | 571 | { |
<> | 149:156823d33999 | 572 | SET_BIT(RCC->CR, RCC_CR_HSEON); |
<> | 149:156823d33999 | 573 | } |
<> | 149:156823d33999 | 574 | |
<> | 149:156823d33999 | 575 | /** |
<> | 149:156823d33999 | 576 | * @brief Disable HSE crystal oscillator (HSE ON) |
<> | 149:156823d33999 | 577 | * @rmtoll CR HSEON LL_RCC_HSE_Disable |
<> | 149:156823d33999 | 578 | * @retval None |
<> | 149:156823d33999 | 579 | */ |
<> | 149:156823d33999 | 580 | __STATIC_INLINE void LL_RCC_HSE_Disable(void) |
<> | 149:156823d33999 | 581 | { |
<> | 149:156823d33999 | 582 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); |
<> | 149:156823d33999 | 583 | } |
<> | 149:156823d33999 | 584 | |
<> | 149:156823d33999 | 585 | /** |
<> | 149:156823d33999 | 586 | * @brief Check if HSE oscillator Ready |
<> | 149:156823d33999 | 587 | * @rmtoll CR HSERDY LL_RCC_HSE_IsReady |
<> | 149:156823d33999 | 588 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 589 | */ |
<> | 149:156823d33999 | 590 | __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) |
<> | 149:156823d33999 | 591 | { |
<> | 149:156823d33999 | 592 | return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); |
<> | 149:156823d33999 | 593 | } |
<> | 149:156823d33999 | 594 | |
<> | 149:156823d33999 | 595 | /** |
<> | 149:156823d33999 | 596 | * @brief Configure the RTC prescaler (divider) |
<> | 149:156823d33999 | 597 | * @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler |
<> | 149:156823d33999 | 598 | * @param Div This parameter can be one of the following values: |
<> | 149:156823d33999 | 599 | * @arg @ref LL_RCC_RTC_HSE_DIV_2 |
<> | 149:156823d33999 | 600 | * @arg @ref LL_RCC_RTC_HSE_DIV_4 |
<> | 149:156823d33999 | 601 | * @arg @ref LL_RCC_RTC_HSE_DIV_8 |
<> | 149:156823d33999 | 602 | * @arg @ref LL_RCC_RTC_HSE_DIV_16 |
<> | 149:156823d33999 | 603 | * @retval None |
<> | 149:156823d33999 | 604 | */ |
<> | 149:156823d33999 | 605 | __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div) |
<> | 149:156823d33999 | 606 | { |
<> | 149:156823d33999 | 607 | MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); |
<> | 149:156823d33999 | 608 | } |
<> | 149:156823d33999 | 609 | |
<> | 149:156823d33999 | 610 | /** |
<> | 149:156823d33999 | 611 | * @brief Get the RTC divider (prescaler) |
<> | 149:156823d33999 | 612 | * @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler |
<> | 149:156823d33999 | 613 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 614 | * @arg @ref LL_RCC_RTC_HSE_DIV_2 |
<> | 149:156823d33999 | 615 | * @arg @ref LL_RCC_RTC_HSE_DIV_4 |
<> | 149:156823d33999 | 616 | * @arg @ref LL_RCC_RTC_HSE_DIV_8 |
<> | 149:156823d33999 | 617 | * @arg @ref LL_RCC_RTC_HSE_DIV_16 |
<> | 149:156823d33999 | 618 | */ |
<> | 149:156823d33999 | 619 | __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) |
<> | 149:156823d33999 | 620 | { |
<> | 149:156823d33999 | 621 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)); |
<> | 149:156823d33999 | 622 | } |
<> | 149:156823d33999 | 623 | |
<> | 149:156823d33999 | 624 | /** |
<> | 149:156823d33999 | 625 | * @} |
<> | 149:156823d33999 | 626 | */ |
<> | 149:156823d33999 | 627 | |
<> | 149:156823d33999 | 628 | /** @defgroup RCC_LL_EF_HSI HSI |
<> | 149:156823d33999 | 629 | * @{ |
<> | 149:156823d33999 | 630 | */ |
<> | 149:156823d33999 | 631 | |
<> | 149:156823d33999 | 632 | /** |
<> | 149:156823d33999 | 633 | * @brief Enable HSI oscillator |
<> | 149:156823d33999 | 634 | * @rmtoll CR HSION LL_RCC_HSI_Enable |
<> | 149:156823d33999 | 635 | * @retval None |
<> | 149:156823d33999 | 636 | */ |
<> | 149:156823d33999 | 637 | __STATIC_INLINE void LL_RCC_HSI_Enable(void) |
<> | 149:156823d33999 | 638 | { |
<> | 149:156823d33999 | 639 | SET_BIT(RCC->CR, RCC_CR_HSION); |
<> | 149:156823d33999 | 640 | } |
<> | 149:156823d33999 | 641 | |
<> | 149:156823d33999 | 642 | /** |
<> | 149:156823d33999 | 643 | * @brief Disable HSI oscillator |
<> | 149:156823d33999 | 644 | * @rmtoll CR HSION LL_RCC_HSI_Disable |
<> | 149:156823d33999 | 645 | * @retval None |
<> | 149:156823d33999 | 646 | */ |
<> | 149:156823d33999 | 647 | __STATIC_INLINE void LL_RCC_HSI_Disable(void) |
<> | 149:156823d33999 | 648 | { |
<> | 149:156823d33999 | 649 | CLEAR_BIT(RCC->CR, RCC_CR_HSION); |
<> | 149:156823d33999 | 650 | } |
<> | 149:156823d33999 | 651 | |
<> | 149:156823d33999 | 652 | /** |
<> | 149:156823d33999 | 653 | * @brief Check if HSI clock is ready |
<> | 149:156823d33999 | 654 | * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady |
<> | 149:156823d33999 | 655 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 656 | */ |
<> | 149:156823d33999 | 657 | __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) |
<> | 149:156823d33999 | 658 | { |
<> | 149:156823d33999 | 659 | return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); |
<> | 149:156823d33999 | 660 | } |
<> | 149:156823d33999 | 661 | |
<> | 149:156823d33999 | 662 | /** |
<> | 149:156823d33999 | 663 | * @brief Get HSI Calibration value |
<> | 149:156823d33999 | 664 | * @note When HSITRIM is written, HSICAL is updated with the sum of |
<> | 149:156823d33999 | 665 | * HSITRIM and the factory trim value |
<> | 149:156823d33999 | 666 | * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration |
<> | 149:156823d33999 | 667 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
<> | 149:156823d33999 | 668 | */ |
<> | 149:156823d33999 | 669 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) |
<> | 149:156823d33999 | 670 | { |
<> | 149:156823d33999 | 671 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL); |
<> | 149:156823d33999 | 672 | } |
<> | 149:156823d33999 | 673 | |
<> | 149:156823d33999 | 674 | /** |
<> | 149:156823d33999 | 675 | * @brief Set HSI Calibration trimming |
<> | 149:156823d33999 | 676 | * @note user-programmable trimming value that is added to the HSICAL |
<> | 149:156823d33999 | 677 | * @note Default value is 16, which, when added to the HSICAL value, |
<> | 149:156823d33999 | 678 | * should trim the HSI to 16 MHz +/- 1 % |
<> | 149:156823d33999 | 679 | * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming |
<> | 149:156823d33999 | 680 | * @param Value between Min_Data = 0x00 and Max_Data = 0x1F |
<> | 149:156823d33999 | 681 | * @retval None |
<> | 149:156823d33999 | 682 | */ |
<> | 149:156823d33999 | 683 | __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) |
<> | 149:156823d33999 | 684 | { |
<> | 149:156823d33999 | 685 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM); |
<> | 149:156823d33999 | 686 | } |
<> | 149:156823d33999 | 687 | |
<> | 149:156823d33999 | 688 | /** |
<> | 149:156823d33999 | 689 | * @brief Get HSI Calibration trimming |
<> | 149:156823d33999 | 690 | * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming |
<> | 149:156823d33999 | 691 | * @retval Between Min_Data = 0x00 and Max_Data = 0x1F |
<> | 149:156823d33999 | 692 | */ |
<> | 149:156823d33999 | 693 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) |
<> | 149:156823d33999 | 694 | { |
<> | 149:156823d33999 | 695 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM); |
<> | 149:156823d33999 | 696 | } |
<> | 149:156823d33999 | 697 | |
<> | 149:156823d33999 | 698 | /** |
<> | 149:156823d33999 | 699 | * @} |
<> | 149:156823d33999 | 700 | */ |
<> | 149:156823d33999 | 701 | |
<> | 149:156823d33999 | 702 | /** @defgroup RCC_LL_EF_LSE LSE |
<> | 149:156823d33999 | 703 | * @{ |
<> | 149:156823d33999 | 704 | */ |
<> | 149:156823d33999 | 705 | |
<> | 149:156823d33999 | 706 | /** |
<> | 149:156823d33999 | 707 | * @brief Enable Low Speed External (LSE) crystal. |
<> | 149:156823d33999 | 708 | * @rmtoll CSR LSEON LL_RCC_LSE_Enable |
<> | 149:156823d33999 | 709 | * @retval None |
<> | 149:156823d33999 | 710 | */ |
<> | 149:156823d33999 | 711 | __STATIC_INLINE void LL_RCC_LSE_Enable(void) |
<> | 149:156823d33999 | 712 | { |
<> | 149:156823d33999 | 713 | SET_BIT(RCC->CSR, RCC_CSR_LSEON); |
<> | 149:156823d33999 | 714 | } |
<> | 149:156823d33999 | 715 | |
<> | 149:156823d33999 | 716 | /** |
<> | 149:156823d33999 | 717 | * @brief Disable Low Speed External (LSE) crystal. |
<> | 149:156823d33999 | 718 | * @rmtoll CSR LSEON LL_RCC_LSE_Disable |
<> | 149:156823d33999 | 719 | * @retval None |
<> | 149:156823d33999 | 720 | */ |
<> | 149:156823d33999 | 721 | __STATIC_INLINE void LL_RCC_LSE_Disable(void) |
<> | 149:156823d33999 | 722 | { |
<> | 149:156823d33999 | 723 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); |
<> | 149:156823d33999 | 724 | } |
<> | 149:156823d33999 | 725 | |
<> | 149:156823d33999 | 726 | /** |
<> | 149:156823d33999 | 727 | * @brief Enable external clock source (LSE bypass). |
<> | 149:156823d33999 | 728 | * @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass |
<> | 149:156823d33999 | 729 | * @retval None |
<> | 149:156823d33999 | 730 | */ |
<> | 149:156823d33999 | 731 | __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) |
<> | 149:156823d33999 | 732 | { |
<> | 149:156823d33999 | 733 | SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); |
<> | 149:156823d33999 | 734 | } |
<> | 149:156823d33999 | 735 | |
<> | 149:156823d33999 | 736 | /** |
<> | 149:156823d33999 | 737 | * @brief Disable external clock source (LSE bypass). |
<> | 149:156823d33999 | 738 | * @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass |
<> | 149:156823d33999 | 739 | * @retval None |
<> | 149:156823d33999 | 740 | */ |
<> | 149:156823d33999 | 741 | __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) |
<> | 149:156823d33999 | 742 | { |
<> | 149:156823d33999 | 743 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); |
<> | 149:156823d33999 | 744 | } |
<> | 149:156823d33999 | 745 | |
<> | 149:156823d33999 | 746 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 747 | /** |
<> | 149:156823d33999 | 748 | * @brief Enable Clock security system on LSE. |
<> | 149:156823d33999 | 749 | * @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS |
<> | 149:156823d33999 | 750 | * @retval None |
<> | 149:156823d33999 | 751 | */ |
<> | 149:156823d33999 | 752 | __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) |
<> | 149:156823d33999 | 753 | { |
<> | 149:156823d33999 | 754 | SET_BIT(RCC->CSR, RCC_CSR_LSECSSON); |
<> | 149:156823d33999 | 755 | } |
<> | 149:156823d33999 | 756 | |
<> | 149:156823d33999 | 757 | /** |
<> | 149:156823d33999 | 758 | * @brief Disable Clock security system on LSE. |
<> | 149:156823d33999 | 759 | * @note Clock security system can be disabled only after a LSE |
<> | 149:156823d33999 | 760 | * failure detection. In that case it MUST be disabled by software. |
<> | 149:156823d33999 | 761 | * @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS |
<> | 149:156823d33999 | 762 | * @retval None |
<> | 149:156823d33999 | 763 | */ |
<> | 149:156823d33999 | 764 | __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) |
<> | 149:156823d33999 | 765 | { |
<> | 149:156823d33999 | 766 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON); |
<> | 149:156823d33999 | 767 | } |
<> | 149:156823d33999 | 768 | |
<> | 149:156823d33999 | 769 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 770 | /** |
<> | 149:156823d33999 | 771 | * @brief Check if LSE oscillator Ready |
<> | 149:156823d33999 | 772 | * @rmtoll CSR LSERDY LL_RCC_LSE_IsReady |
<> | 149:156823d33999 | 773 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 774 | */ |
<> | 149:156823d33999 | 775 | __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) |
<> | 149:156823d33999 | 776 | { |
<> | 149:156823d33999 | 777 | return (READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == (RCC_CSR_LSERDY)); |
<> | 149:156823d33999 | 778 | } |
<> | 149:156823d33999 | 779 | |
<> | 149:156823d33999 | 780 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 781 | /** |
<> | 149:156823d33999 | 782 | * @brief Check if CSS on LSE failure Detection |
<> | 149:156823d33999 | 783 | * @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected |
<> | 149:156823d33999 | 784 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 785 | */ |
<> | 149:156823d33999 | 786 | __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) |
<> | 149:156823d33999 | 787 | { |
<> | 149:156823d33999 | 788 | return (READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == (RCC_CSR_LSECSSD)); |
<> | 149:156823d33999 | 789 | } |
<> | 149:156823d33999 | 790 | |
<> | 149:156823d33999 | 791 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 792 | /** |
<> | 149:156823d33999 | 793 | * @} |
<> | 149:156823d33999 | 794 | */ |
<> | 149:156823d33999 | 795 | |
<> | 149:156823d33999 | 796 | /** @defgroup RCC_LL_EF_LSI LSI |
<> | 149:156823d33999 | 797 | * @{ |
<> | 149:156823d33999 | 798 | */ |
<> | 149:156823d33999 | 799 | |
<> | 149:156823d33999 | 800 | /** |
<> | 149:156823d33999 | 801 | * @brief Enable LSI Oscillator |
<> | 149:156823d33999 | 802 | * @rmtoll CSR LSION LL_RCC_LSI_Enable |
<> | 149:156823d33999 | 803 | * @retval None |
<> | 149:156823d33999 | 804 | */ |
<> | 149:156823d33999 | 805 | __STATIC_INLINE void LL_RCC_LSI_Enable(void) |
<> | 149:156823d33999 | 806 | { |
<> | 149:156823d33999 | 807 | SET_BIT(RCC->CSR, RCC_CSR_LSION); |
<> | 149:156823d33999 | 808 | } |
<> | 149:156823d33999 | 809 | |
<> | 149:156823d33999 | 810 | /** |
<> | 149:156823d33999 | 811 | * @brief Disable LSI Oscillator |
<> | 149:156823d33999 | 812 | * @rmtoll CSR LSION LL_RCC_LSI_Disable |
<> | 149:156823d33999 | 813 | * @retval None |
<> | 149:156823d33999 | 814 | */ |
<> | 149:156823d33999 | 815 | __STATIC_INLINE void LL_RCC_LSI_Disable(void) |
<> | 149:156823d33999 | 816 | { |
<> | 149:156823d33999 | 817 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); |
<> | 149:156823d33999 | 818 | } |
<> | 149:156823d33999 | 819 | |
<> | 149:156823d33999 | 820 | /** |
<> | 149:156823d33999 | 821 | * @brief Check if LSI is Ready |
<> | 149:156823d33999 | 822 | * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady |
<> | 149:156823d33999 | 823 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 824 | */ |
<> | 149:156823d33999 | 825 | __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) |
<> | 149:156823d33999 | 826 | { |
<> | 149:156823d33999 | 827 | return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); |
<> | 149:156823d33999 | 828 | } |
<> | 149:156823d33999 | 829 | |
<> | 149:156823d33999 | 830 | /** |
<> | 149:156823d33999 | 831 | * @} |
<> | 149:156823d33999 | 832 | */ |
<> | 149:156823d33999 | 833 | |
<> | 149:156823d33999 | 834 | /** @defgroup RCC_LL_EF_MSI MSI |
<> | 149:156823d33999 | 835 | * @{ |
<> | 149:156823d33999 | 836 | */ |
<> | 149:156823d33999 | 837 | |
<> | 149:156823d33999 | 838 | /** |
<> | 149:156823d33999 | 839 | * @brief Enable MSI oscillator |
<> | 149:156823d33999 | 840 | * @rmtoll CR MSION LL_RCC_MSI_Enable |
<> | 149:156823d33999 | 841 | * @retval None |
<> | 149:156823d33999 | 842 | */ |
<> | 149:156823d33999 | 843 | __STATIC_INLINE void LL_RCC_MSI_Enable(void) |
<> | 149:156823d33999 | 844 | { |
<> | 149:156823d33999 | 845 | SET_BIT(RCC->CR, RCC_CR_MSION); |
<> | 149:156823d33999 | 846 | } |
<> | 149:156823d33999 | 847 | |
<> | 149:156823d33999 | 848 | /** |
<> | 149:156823d33999 | 849 | * @brief Disable MSI oscillator |
<> | 149:156823d33999 | 850 | * @rmtoll CR MSION LL_RCC_MSI_Disable |
<> | 149:156823d33999 | 851 | * @retval None |
<> | 149:156823d33999 | 852 | */ |
<> | 149:156823d33999 | 853 | __STATIC_INLINE void LL_RCC_MSI_Disable(void) |
<> | 149:156823d33999 | 854 | { |
<> | 149:156823d33999 | 855 | CLEAR_BIT(RCC->CR, RCC_CR_MSION); |
<> | 149:156823d33999 | 856 | } |
<> | 149:156823d33999 | 857 | |
<> | 149:156823d33999 | 858 | /** |
<> | 149:156823d33999 | 859 | * @brief Check if MSI oscillator Ready |
<> | 149:156823d33999 | 860 | * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady |
<> | 149:156823d33999 | 861 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 862 | */ |
<> | 149:156823d33999 | 863 | __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) |
<> | 149:156823d33999 | 864 | { |
<> | 149:156823d33999 | 865 | return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)); |
<> | 149:156823d33999 | 866 | } |
<> | 149:156823d33999 | 867 | |
<> | 149:156823d33999 | 868 | /** |
<> | 149:156823d33999 | 869 | * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. |
<> | 149:156823d33999 | 870 | * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange |
<> | 149:156823d33999 | 871 | * @param Range This parameter can be one of the following values: |
<> | 149:156823d33999 | 872 | * @arg @ref LL_RCC_MSIRANGE_0 |
<> | 149:156823d33999 | 873 | * @arg @ref LL_RCC_MSIRANGE_1 |
<> | 149:156823d33999 | 874 | * @arg @ref LL_RCC_MSIRANGE_2 |
<> | 149:156823d33999 | 875 | * @arg @ref LL_RCC_MSIRANGE_3 |
<> | 149:156823d33999 | 876 | * @arg @ref LL_RCC_MSIRANGE_4 |
<> | 149:156823d33999 | 877 | * @arg @ref LL_RCC_MSIRANGE_5 |
<> | 149:156823d33999 | 878 | * @arg @ref LL_RCC_MSIRANGE_6 |
<> | 149:156823d33999 | 879 | * @retval None |
<> | 149:156823d33999 | 880 | */ |
<> | 149:156823d33999 | 881 | __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) |
<> | 149:156823d33999 | 882 | { |
<> | 149:156823d33999 | 883 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range); |
<> | 149:156823d33999 | 884 | } |
<> | 149:156823d33999 | 885 | |
<> | 149:156823d33999 | 886 | /** |
<> | 149:156823d33999 | 887 | * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. |
<> | 149:156823d33999 | 888 | * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange |
<> | 149:156823d33999 | 889 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 890 | * @arg @ref LL_RCC_MSIRANGE_0 |
<> | 149:156823d33999 | 891 | * @arg @ref LL_RCC_MSIRANGE_1 |
<> | 149:156823d33999 | 892 | * @arg @ref LL_RCC_MSIRANGE_2 |
<> | 149:156823d33999 | 893 | * @arg @ref LL_RCC_MSIRANGE_3 |
<> | 149:156823d33999 | 894 | * @arg @ref LL_RCC_MSIRANGE_4 |
<> | 149:156823d33999 | 895 | * @arg @ref LL_RCC_MSIRANGE_5 |
<> | 149:156823d33999 | 896 | * @arg @ref LL_RCC_MSIRANGE_6 |
<> | 149:156823d33999 | 897 | */ |
<> | 149:156823d33999 | 898 | __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) |
<> | 149:156823d33999 | 899 | { |
<> | 149:156823d33999 | 900 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)); |
<> | 149:156823d33999 | 901 | } |
<> | 149:156823d33999 | 902 | |
<> | 149:156823d33999 | 903 | /** |
<> | 149:156823d33999 | 904 | * @brief Get MSI Calibration value |
<> | 149:156823d33999 | 905 | * @note When MSITRIM is written, MSICAL is updated with the sum of |
<> | 149:156823d33999 | 906 | * MSITRIM and the factory trim value |
<> | 149:156823d33999 | 907 | * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration |
<> | 149:156823d33999 | 908 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
<> | 149:156823d33999 | 909 | */ |
<> | 149:156823d33999 | 910 | __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) |
<> | 149:156823d33999 | 911 | { |
<> | 149:156823d33999 | 912 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL); |
<> | 149:156823d33999 | 913 | } |
<> | 149:156823d33999 | 914 | |
<> | 149:156823d33999 | 915 | /** |
<> | 149:156823d33999 | 916 | * @brief Set MSI Calibration trimming |
<> | 149:156823d33999 | 917 | * @note user-programmable trimming value that is added to the MSICAL |
<> | 149:156823d33999 | 918 | * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming |
<> | 149:156823d33999 | 919 | * @param Value between Min_Data = 0x00 and Max_Data = 0xFF |
<> | 149:156823d33999 | 920 | * @retval None |
<> | 149:156823d33999 | 921 | */ |
<> | 149:156823d33999 | 922 | __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) |
<> | 149:156823d33999 | 923 | { |
<> | 149:156823d33999 | 924 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM); |
<> | 149:156823d33999 | 925 | } |
<> | 149:156823d33999 | 926 | |
<> | 149:156823d33999 | 927 | /** |
<> | 149:156823d33999 | 928 | * @brief Get MSI Calibration trimming |
<> | 149:156823d33999 | 929 | * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming |
<> | 149:156823d33999 | 930 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
<> | 149:156823d33999 | 931 | */ |
<> | 149:156823d33999 | 932 | __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) |
<> | 149:156823d33999 | 933 | { |
<> | 149:156823d33999 | 934 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM); |
<> | 149:156823d33999 | 935 | } |
<> | 149:156823d33999 | 936 | |
<> | 149:156823d33999 | 937 | /** |
<> | 149:156823d33999 | 938 | * @} |
<> | 149:156823d33999 | 939 | */ |
<> | 149:156823d33999 | 940 | |
<> | 149:156823d33999 | 941 | /** @defgroup RCC_LL_EF_System System |
<> | 149:156823d33999 | 942 | * @{ |
<> | 149:156823d33999 | 943 | */ |
<> | 149:156823d33999 | 944 | |
<> | 149:156823d33999 | 945 | /** |
<> | 149:156823d33999 | 946 | * @brief Configure the system clock source |
<> | 149:156823d33999 | 947 | * @rmtoll CFGR SW LL_RCC_SetSysClkSource |
<> | 149:156823d33999 | 948 | * @param Source This parameter can be one of the following values: |
<> | 149:156823d33999 | 949 | * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI |
<> | 149:156823d33999 | 950 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI |
<> | 149:156823d33999 | 951 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE |
<> | 149:156823d33999 | 952 | * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL |
<> | 149:156823d33999 | 953 | * @retval None |
<> | 149:156823d33999 | 954 | */ |
<> | 149:156823d33999 | 955 | __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) |
<> | 149:156823d33999 | 956 | { |
<> | 149:156823d33999 | 957 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); |
<> | 149:156823d33999 | 958 | } |
<> | 149:156823d33999 | 959 | |
<> | 149:156823d33999 | 960 | /** |
<> | 149:156823d33999 | 961 | * @brief Get the system clock source |
<> | 149:156823d33999 | 962 | * @rmtoll CFGR SWS LL_RCC_GetSysClkSource |
<> | 149:156823d33999 | 963 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 964 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI |
<> | 149:156823d33999 | 965 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI |
<> | 149:156823d33999 | 966 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE |
<> | 149:156823d33999 | 967 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL |
<> | 149:156823d33999 | 968 | */ |
<> | 149:156823d33999 | 969 | __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) |
<> | 149:156823d33999 | 970 | { |
<> | 149:156823d33999 | 971 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); |
<> | 149:156823d33999 | 972 | } |
<> | 149:156823d33999 | 973 | |
<> | 149:156823d33999 | 974 | /** |
<> | 149:156823d33999 | 975 | * @brief Set AHB prescaler |
<> | 149:156823d33999 | 976 | * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler |
<> | 149:156823d33999 | 977 | * @param Prescaler This parameter can be one of the following values: |
<> | 149:156823d33999 | 978 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
<> | 149:156823d33999 | 979 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
<> | 149:156823d33999 | 980 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
<> | 149:156823d33999 | 981 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
<> | 149:156823d33999 | 982 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
<> | 149:156823d33999 | 983 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
<> | 149:156823d33999 | 984 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
<> | 149:156823d33999 | 985 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
<> | 149:156823d33999 | 986 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
<> | 149:156823d33999 | 987 | * @retval None |
<> | 149:156823d33999 | 988 | */ |
<> | 149:156823d33999 | 989 | __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) |
<> | 149:156823d33999 | 990 | { |
<> | 149:156823d33999 | 991 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); |
<> | 149:156823d33999 | 992 | } |
<> | 149:156823d33999 | 993 | |
<> | 149:156823d33999 | 994 | /** |
<> | 149:156823d33999 | 995 | * @brief Set APB1 prescaler |
<> | 149:156823d33999 | 996 | * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler |
<> | 149:156823d33999 | 997 | * @param Prescaler This parameter can be one of the following values: |
<> | 149:156823d33999 | 998 | * @arg @ref LL_RCC_APB1_DIV_1 |
<> | 149:156823d33999 | 999 | * @arg @ref LL_RCC_APB1_DIV_2 |
<> | 149:156823d33999 | 1000 | * @arg @ref LL_RCC_APB1_DIV_4 |
<> | 149:156823d33999 | 1001 | * @arg @ref LL_RCC_APB1_DIV_8 |
<> | 149:156823d33999 | 1002 | * @arg @ref LL_RCC_APB1_DIV_16 |
<> | 149:156823d33999 | 1003 | * @retval None |
<> | 149:156823d33999 | 1004 | */ |
<> | 149:156823d33999 | 1005 | __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) |
<> | 149:156823d33999 | 1006 | { |
<> | 149:156823d33999 | 1007 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); |
<> | 149:156823d33999 | 1008 | } |
<> | 149:156823d33999 | 1009 | |
<> | 149:156823d33999 | 1010 | /** |
<> | 149:156823d33999 | 1011 | * @brief Set APB2 prescaler |
<> | 149:156823d33999 | 1012 | * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler |
<> | 149:156823d33999 | 1013 | * @param Prescaler This parameter can be one of the following values: |
<> | 149:156823d33999 | 1014 | * @arg @ref LL_RCC_APB2_DIV_1 |
<> | 149:156823d33999 | 1015 | * @arg @ref LL_RCC_APB2_DIV_2 |
<> | 149:156823d33999 | 1016 | * @arg @ref LL_RCC_APB2_DIV_4 |
<> | 149:156823d33999 | 1017 | * @arg @ref LL_RCC_APB2_DIV_8 |
<> | 149:156823d33999 | 1018 | * @arg @ref LL_RCC_APB2_DIV_16 |
<> | 149:156823d33999 | 1019 | * @retval None |
<> | 149:156823d33999 | 1020 | */ |
<> | 149:156823d33999 | 1021 | __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) |
<> | 149:156823d33999 | 1022 | { |
<> | 149:156823d33999 | 1023 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); |
<> | 149:156823d33999 | 1024 | } |
<> | 149:156823d33999 | 1025 | |
<> | 149:156823d33999 | 1026 | /** |
<> | 149:156823d33999 | 1027 | * @brief Get AHB prescaler |
<> | 149:156823d33999 | 1028 | * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler |
<> | 149:156823d33999 | 1029 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 1030 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
<> | 149:156823d33999 | 1031 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
<> | 149:156823d33999 | 1032 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
<> | 149:156823d33999 | 1033 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
<> | 149:156823d33999 | 1034 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
<> | 149:156823d33999 | 1035 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
<> | 149:156823d33999 | 1036 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
<> | 149:156823d33999 | 1037 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
<> | 149:156823d33999 | 1038 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
<> | 149:156823d33999 | 1039 | */ |
<> | 149:156823d33999 | 1040 | __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) |
<> | 149:156823d33999 | 1041 | { |
<> | 149:156823d33999 | 1042 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); |
<> | 149:156823d33999 | 1043 | } |
<> | 149:156823d33999 | 1044 | |
<> | 149:156823d33999 | 1045 | /** |
<> | 149:156823d33999 | 1046 | * @brief Get APB1 prescaler |
<> | 149:156823d33999 | 1047 | * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler |
<> | 149:156823d33999 | 1048 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 1049 | * @arg @ref LL_RCC_APB1_DIV_1 |
<> | 149:156823d33999 | 1050 | * @arg @ref LL_RCC_APB1_DIV_2 |
<> | 149:156823d33999 | 1051 | * @arg @ref LL_RCC_APB1_DIV_4 |
<> | 149:156823d33999 | 1052 | * @arg @ref LL_RCC_APB1_DIV_8 |
<> | 149:156823d33999 | 1053 | * @arg @ref LL_RCC_APB1_DIV_16 |
<> | 149:156823d33999 | 1054 | */ |
<> | 149:156823d33999 | 1055 | __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) |
<> | 149:156823d33999 | 1056 | { |
<> | 149:156823d33999 | 1057 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); |
<> | 149:156823d33999 | 1058 | } |
<> | 149:156823d33999 | 1059 | |
<> | 149:156823d33999 | 1060 | /** |
<> | 149:156823d33999 | 1061 | * @brief Get APB2 prescaler |
<> | 149:156823d33999 | 1062 | * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler |
<> | 149:156823d33999 | 1063 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 1064 | * @arg @ref LL_RCC_APB2_DIV_1 |
<> | 149:156823d33999 | 1065 | * @arg @ref LL_RCC_APB2_DIV_2 |
<> | 149:156823d33999 | 1066 | * @arg @ref LL_RCC_APB2_DIV_4 |
<> | 149:156823d33999 | 1067 | * @arg @ref LL_RCC_APB2_DIV_8 |
<> | 149:156823d33999 | 1068 | * @arg @ref LL_RCC_APB2_DIV_16 |
<> | 149:156823d33999 | 1069 | */ |
<> | 149:156823d33999 | 1070 | __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) |
<> | 149:156823d33999 | 1071 | { |
<> | 149:156823d33999 | 1072 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); |
<> | 149:156823d33999 | 1073 | } |
<> | 149:156823d33999 | 1074 | |
<> | 149:156823d33999 | 1075 | /** |
<> | 149:156823d33999 | 1076 | * @} |
<> | 149:156823d33999 | 1077 | */ |
<> | 149:156823d33999 | 1078 | |
<> | 149:156823d33999 | 1079 | /** @defgroup RCC_LL_EF_MCO MCO |
<> | 149:156823d33999 | 1080 | * @{ |
<> | 149:156823d33999 | 1081 | */ |
<> | 149:156823d33999 | 1082 | |
<> | 149:156823d33999 | 1083 | /** |
<> | 149:156823d33999 | 1084 | * @brief Configure MCOx |
<> | 149:156823d33999 | 1085 | * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n |
<> | 149:156823d33999 | 1086 | * CFGR MCOPRE LL_RCC_ConfigMCO |
<> | 149:156823d33999 | 1087 | * @param MCOxSource This parameter can be one of the following values: |
<> | 149:156823d33999 | 1088 | * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK |
<> | 149:156823d33999 | 1089 | * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK |
<> | 149:156823d33999 | 1090 | * @arg @ref LL_RCC_MCO1SOURCE_HSI |
<> | 149:156823d33999 | 1091 | * @arg @ref LL_RCC_MCO1SOURCE_MSI |
<> | 149:156823d33999 | 1092 | * @arg @ref LL_RCC_MCO1SOURCE_HSE |
<> | 149:156823d33999 | 1093 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK |
<> | 149:156823d33999 | 1094 | * @arg @ref LL_RCC_MCO1SOURCE_LSI |
<> | 149:156823d33999 | 1095 | * @arg @ref LL_RCC_MCO1SOURCE_LSE |
<> | 149:156823d33999 | 1096 | * @param MCOxPrescaler This parameter can be one of the following values: |
<> | 149:156823d33999 | 1097 | * @arg @ref LL_RCC_MCO1_DIV_1 |
<> | 149:156823d33999 | 1098 | * @arg @ref LL_RCC_MCO1_DIV_2 |
<> | 149:156823d33999 | 1099 | * @arg @ref LL_RCC_MCO1_DIV_4 |
<> | 149:156823d33999 | 1100 | * @arg @ref LL_RCC_MCO1_DIV_8 |
<> | 149:156823d33999 | 1101 | * @arg @ref LL_RCC_MCO1_DIV_16 |
<> | 149:156823d33999 | 1102 | * @retval None |
<> | 149:156823d33999 | 1103 | */ |
<> | 149:156823d33999 | 1104 | __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) |
<> | 149:156823d33999 | 1105 | { |
<> | 149:156823d33999 | 1106 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); |
<> | 149:156823d33999 | 1107 | } |
<> | 149:156823d33999 | 1108 | |
<> | 149:156823d33999 | 1109 | /** |
<> | 149:156823d33999 | 1110 | * @} |
<> | 149:156823d33999 | 1111 | */ |
<> | 149:156823d33999 | 1112 | |
<> | 149:156823d33999 | 1113 | |
<> | 149:156823d33999 | 1114 | |
<> | 149:156823d33999 | 1115 | /** @defgroup RCC_LL_EF_RTC RTC |
<> | 149:156823d33999 | 1116 | * @{ |
<> | 149:156823d33999 | 1117 | */ |
<> | 149:156823d33999 | 1118 | |
<> | 149:156823d33999 | 1119 | /** |
<> | 149:156823d33999 | 1120 | * @brief Set RTC Clock Source |
<> | 149:156823d33999 | 1121 | * @note Once the RTC clock source has been selected, it cannot be changed any more unless |
<> | 149:156823d33999 | 1122 | * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is |
<> | 149:156823d33999 | 1123 | * set). The RTCRST bit can be used to reset them. |
<> | 149:156823d33999 | 1124 | * @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource |
<> | 149:156823d33999 | 1125 | * @param Source This parameter can be one of the following values: |
<> | 149:156823d33999 | 1126 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
<> | 149:156823d33999 | 1127 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
<> | 149:156823d33999 | 1128 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
<> | 149:156823d33999 | 1129 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE |
<> | 149:156823d33999 | 1130 | * @retval None |
<> | 149:156823d33999 | 1131 | */ |
<> | 149:156823d33999 | 1132 | __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) |
<> | 149:156823d33999 | 1133 | { |
<> | 149:156823d33999 | 1134 | MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source); |
<> | 149:156823d33999 | 1135 | } |
<> | 149:156823d33999 | 1136 | |
<> | 149:156823d33999 | 1137 | /** |
<> | 149:156823d33999 | 1138 | * @brief Get RTC Clock Source |
<> | 149:156823d33999 | 1139 | * @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource |
<> | 149:156823d33999 | 1140 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 1141 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
<> | 149:156823d33999 | 1142 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
<> | 149:156823d33999 | 1143 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
<> | 149:156823d33999 | 1144 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE |
<> | 149:156823d33999 | 1145 | */ |
<> | 149:156823d33999 | 1146 | __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) |
<> | 149:156823d33999 | 1147 | { |
<> | 149:156823d33999 | 1148 | return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)); |
<> | 149:156823d33999 | 1149 | } |
<> | 149:156823d33999 | 1150 | |
<> | 149:156823d33999 | 1151 | /** |
<> | 149:156823d33999 | 1152 | * @brief Enable RTC |
<> | 149:156823d33999 | 1153 | * @rmtoll CSR RTCEN LL_RCC_EnableRTC |
<> | 149:156823d33999 | 1154 | * @retval None |
<> | 149:156823d33999 | 1155 | */ |
<> | 149:156823d33999 | 1156 | __STATIC_INLINE void LL_RCC_EnableRTC(void) |
<> | 149:156823d33999 | 1157 | { |
<> | 149:156823d33999 | 1158 | SET_BIT(RCC->CSR, RCC_CSR_RTCEN); |
<> | 149:156823d33999 | 1159 | } |
<> | 149:156823d33999 | 1160 | |
<> | 149:156823d33999 | 1161 | /** |
<> | 149:156823d33999 | 1162 | * @brief Disable RTC |
<> | 149:156823d33999 | 1163 | * @rmtoll CSR RTCEN LL_RCC_DisableRTC |
<> | 149:156823d33999 | 1164 | * @retval None |
<> | 149:156823d33999 | 1165 | */ |
<> | 149:156823d33999 | 1166 | __STATIC_INLINE void LL_RCC_DisableRTC(void) |
<> | 149:156823d33999 | 1167 | { |
<> | 149:156823d33999 | 1168 | CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN); |
<> | 149:156823d33999 | 1169 | } |
<> | 149:156823d33999 | 1170 | |
<> | 149:156823d33999 | 1171 | /** |
<> | 149:156823d33999 | 1172 | * @brief Check if RTC has been enabled or not |
<> | 149:156823d33999 | 1173 | * @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC |
<> | 149:156823d33999 | 1174 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1175 | */ |
<> | 149:156823d33999 | 1176 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) |
<> | 149:156823d33999 | 1177 | { |
<> | 149:156823d33999 | 1178 | return (READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == (RCC_CSR_RTCEN)); |
<> | 149:156823d33999 | 1179 | } |
<> | 149:156823d33999 | 1180 | |
<> | 149:156823d33999 | 1181 | /** |
<> | 149:156823d33999 | 1182 | * @brief Force the Backup domain reset |
<> | 149:156823d33999 | 1183 | * @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset |
<> | 149:156823d33999 | 1184 | * @retval None |
<> | 149:156823d33999 | 1185 | */ |
<> | 149:156823d33999 | 1186 | __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) |
<> | 149:156823d33999 | 1187 | { |
<> | 149:156823d33999 | 1188 | SET_BIT(RCC->CSR, RCC_CSR_RTCRST); |
<> | 149:156823d33999 | 1189 | } |
<> | 149:156823d33999 | 1190 | |
<> | 149:156823d33999 | 1191 | /** |
<> | 149:156823d33999 | 1192 | * @brief Release the Backup domain reset |
<> | 149:156823d33999 | 1193 | * @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset |
<> | 149:156823d33999 | 1194 | * @retval None |
<> | 149:156823d33999 | 1195 | */ |
<> | 149:156823d33999 | 1196 | __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) |
<> | 149:156823d33999 | 1197 | { |
<> | 149:156823d33999 | 1198 | CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST); |
<> | 149:156823d33999 | 1199 | } |
<> | 149:156823d33999 | 1200 | |
<> | 149:156823d33999 | 1201 | /** |
<> | 149:156823d33999 | 1202 | * @} |
<> | 149:156823d33999 | 1203 | */ |
<> | 149:156823d33999 | 1204 | |
<> | 149:156823d33999 | 1205 | /** @defgroup RCC_LL_EF_PLL PLL |
<> | 149:156823d33999 | 1206 | * @{ |
<> | 149:156823d33999 | 1207 | */ |
<> | 149:156823d33999 | 1208 | |
<> | 149:156823d33999 | 1209 | /** |
<> | 149:156823d33999 | 1210 | * @brief Enable PLL |
<> | 149:156823d33999 | 1211 | * @rmtoll CR PLLON LL_RCC_PLL_Enable |
<> | 149:156823d33999 | 1212 | * @retval None |
<> | 149:156823d33999 | 1213 | */ |
<> | 149:156823d33999 | 1214 | __STATIC_INLINE void LL_RCC_PLL_Enable(void) |
<> | 149:156823d33999 | 1215 | { |
<> | 149:156823d33999 | 1216 | SET_BIT(RCC->CR, RCC_CR_PLLON); |
<> | 149:156823d33999 | 1217 | } |
<> | 149:156823d33999 | 1218 | |
<> | 149:156823d33999 | 1219 | /** |
<> | 149:156823d33999 | 1220 | * @brief Disable PLL |
<> | 149:156823d33999 | 1221 | * @note Cannot be disabled if the PLL clock is used as the system clock |
<> | 149:156823d33999 | 1222 | * @rmtoll CR PLLON LL_RCC_PLL_Disable |
<> | 149:156823d33999 | 1223 | * @retval None |
<> | 149:156823d33999 | 1224 | */ |
<> | 149:156823d33999 | 1225 | __STATIC_INLINE void LL_RCC_PLL_Disable(void) |
<> | 149:156823d33999 | 1226 | { |
<> | 149:156823d33999 | 1227 | CLEAR_BIT(RCC->CR, RCC_CR_PLLON); |
<> | 149:156823d33999 | 1228 | } |
<> | 149:156823d33999 | 1229 | |
<> | 149:156823d33999 | 1230 | /** |
<> | 149:156823d33999 | 1231 | * @brief Check if PLL Ready |
<> | 149:156823d33999 | 1232 | * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady |
<> | 149:156823d33999 | 1233 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1234 | */ |
<> | 149:156823d33999 | 1235 | __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) |
<> | 149:156823d33999 | 1236 | { |
<> | 149:156823d33999 | 1237 | return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); |
<> | 149:156823d33999 | 1238 | } |
<> | 149:156823d33999 | 1239 | |
<> | 149:156823d33999 | 1240 | /** |
<> | 149:156823d33999 | 1241 | * @brief Configure PLL used for SYSCLK Domain |
<> | 149:156823d33999 | 1242 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
<> | 149:156823d33999 | 1243 | * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n |
<> | 149:156823d33999 | 1244 | * CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS |
<> | 149:156823d33999 | 1245 | * @param Source This parameter can be one of the following values: |
<> | 149:156823d33999 | 1246 | * @arg @ref LL_RCC_PLLSOURCE_HSI |
<> | 149:156823d33999 | 1247 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
<> | 149:156823d33999 | 1248 | * @param PLLMul This parameter can be one of the following values: |
<> | 149:156823d33999 | 1249 | * @arg @ref LL_RCC_PLL_MUL_3 |
<> | 149:156823d33999 | 1250 | * @arg @ref LL_RCC_PLL_MUL_4 |
<> | 149:156823d33999 | 1251 | * @arg @ref LL_RCC_PLL_MUL_6 |
<> | 149:156823d33999 | 1252 | * @arg @ref LL_RCC_PLL_MUL_8 |
<> | 149:156823d33999 | 1253 | * @arg @ref LL_RCC_PLL_MUL_12 |
<> | 149:156823d33999 | 1254 | * @arg @ref LL_RCC_PLL_MUL_16 |
<> | 149:156823d33999 | 1255 | * @arg @ref LL_RCC_PLL_MUL_24 |
<> | 149:156823d33999 | 1256 | * @arg @ref LL_RCC_PLL_MUL_32 |
<> | 149:156823d33999 | 1257 | * @arg @ref LL_RCC_PLL_MUL_48 |
<> | 149:156823d33999 | 1258 | * @param PLLDiv This parameter can be one of the following values: |
<> | 149:156823d33999 | 1259 | * @arg @ref LL_RCC_PLL_DIV_2 |
<> | 149:156823d33999 | 1260 | * @arg @ref LL_RCC_PLL_DIV_3 |
<> | 149:156823d33999 | 1261 | * @arg @ref LL_RCC_PLL_DIV_4 |
<> | 149:156823d33999 | 1262 | * @retval None |
<> | 149:156823d33999 | 1263 | */ |
<> | 149:156823d33999 | 1264 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) |
<> | 149:156823d33999 | 1265 | { |
<> | 149:156823d33999 | 1266 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv); |
<> | 149:156823d33999 | 1267 | } |
<> | 149:156823d33999 | 1268 | |
<> | 149:156823d33999 | 1269 | /** |
<> | 149:156823d33999 | 1270 | * @brief Get the oscillator used as PLL clock source. |
<> | 149:156823d33999 | 1271 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource |
<> | 149:156823d33999 | 1272 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 1273 | * @arg @ref LL_RCC_PLLSOURCE_HSI |
<> | 149:156823d33999 | 1274 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
<> | 149:156823d33999 | 1275 | */ |
<> | 149:156823d33999 | 1276 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
<> | 149:156823d33999 | 1277 | { |
<> | 149:156823d33999 | 1278 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); |
<> | 149:156823d33999 | 1279 | } |
<> | 149:156823d33999 | 1280 | |
<> | 149:156823d33999 | 1281 | /** |
<> | 149:156823d33999 | 1282 | * @brief Get PLL multiplication Factor |
<> | 149:156823d33999 | 1283 | * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator |
<> | 149:156823d33999 | 1284 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 1285 | * @arg @ref LL_RCC_PLL_MUL_3 |
<> | 149:156823d33999 | 1286 | * @arg @ref LL_RCC_PLL_MUL_4 |
<> | 149:156823d33999 | 1287 | * @arg @ref LL_RCC_PLL_MUL_6 |
<> | 149:156823d33999 | 1288 | * @arg @ref LL_RCC_PLL_MUL_8 |
<> | 149:156823d33999 | 1289 | * @arg @ref LL_RCC_PLL_MUL_12 |
<> | 149:156823d33999 | 1290 | * @arg @ref LL_RCC_PLL_MUL_16 |
<> | 149:156823d33999 | 1291 | * @arg @ref LL_RCC_PLL_MUL_24 |
<> | 149:156823d33999 | 1292 | * @arg @ref LL_RCC_PLL_MUL_32 |
<> | 149:156823d33999 | 1293 | * @arg @ref LL_RCC_PLL_MUL_48 |
<> | 149:156823d33999 | 1294 | */ |
<> | 149:156823d33999 | 1295 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) |
<> | 149:156823d33999 | 1296 | { |
<> | 149:156823d33999 | 1297 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); |
<> | 149:156823d33999 | 1298 | } |
<> | 149:156823d33999 | 1299 | |
<> | 149:156823d33999 | 1300 | /** |
<> | 149:156823d33999 | 1301 | * @brief Get Division factor for the main PLL and other PLL |
<> | 149:156823d33999 | 1302 | * @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider |
<> | 149:156823d33999 | 1303 | * @retval Returned value can be one of the following values: |
<> | 149:156823d33999 | 1304 | * @arg @ref LL_RCC_PLL_DIV_2 |
<> | 149:156823d33999 | 1305 | * @arg @ref LL_RCC_PLL_DIV_3 |
<> | 149:156823d33999 | 1306 | * @arg @ref LL_RCC_PLL_DIV_4 |
<> | 149:156823d33999 | 1307 | */ |
<> | 149:156823d33999 | 1308 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) |
<> | 149:156823d33999 | 1309 | { |
<> | 149:156823d33999 | 1310 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV)); |
<> | 149:156823d33999 | 1311 | } |
<> | 149:156823d33999 | 1312 | |
<> | 149:156823d33999 | 1313 | /** |
<> | 149:156823d33999 | 1314 | * @} |
<> | 149:156823d33999 | 1315 | */ |
<> | 149:156823d33999 | 1316 | |
<> | 149:156823d33999 | 1317 | /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management |
<> | 149:156823d33999 | 1318 | * @{ |
<> | 149:156823d33999 | 1319 | */ |
<> | 149:156823d33999 | 1320 | |
<> | 149:156823d33999 | 1321 | /** |
<> | 149:156823d33999 | 1322 | * @brief Clear LSI ready interrupt flag |
<> | 149:156823d33999 | 1323 | * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY |
<> | 149:156823d33999 | 1324 | * @retval None |
<> | 149:156823d33999 | 1325 | */ |
<> | 149:156823d33999 | 1326 | __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) |
<> | 149:156823d33999 | 1327 | { |
<> | 149:156823d33999 | 1328 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); |
<> | 149:156823d33999 | 1329 | } |
<> | 149:156823d33999 | 1330 | |
<> | 149:156823d33999 | 1331 | /** |
<> | 149:156823d33999 | 1332 | * @brief Clear LSE ready interrupt flag |
<> | 149:156823d33999 | 1333 | * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY |
<> | 149:156823d33999 | 1334 | * @retval None |
<> | 149:156823d33999 | 1335 | */ |
<> | 149:156823d33999 | 1336 | __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) |
<> | 149:156823d33999 | 1337 | { |
<> | 149:156823d33999 | 1338 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); |
<> | 149:156823d33999 | 1339 | } |
<> | 149:156823d33999 | 1340 | |
<> | 149:156823d33999 | 1341 | /** |
<> | 149:156823d33999 | 1342 | * @brief Clear MSI ready interrupt flag |
<> | 149:156823d33999 | 1343 | * @rmtoll CIR MSIRDYC LL_RCC_ClearFlag_MSIRDY |
<> | 149:156823d33999 | 1344 | * @retval None |
<> | 149:156823d33999 | 1345 | */ |
<> | 149:156823d33999 | 1346 | __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) |
<> | 149:156823d33999 | 1347 | { |
<> | 149:156823d33999 | 1348 | SET_BIT(RCC->CIR, RCC_CIR_MSIRDYC); |
<> | 149:156823d33999 | 1349 | } |
<> | 149:156823d33999 | 1350 | |
<> | 149:156823d33999 | 1351 | /** |
<> | 149:156823d33999 | 1352 | * @brief Clear HSI ready interrupt flag |
<> | 149:156823d33999 | 1353 | * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY |
<> | 149:156823d33999 | 1354 | * @retval None |
<> | 149:156823d33999 | 1355 | */ |
<> | 149:156823d33999 | 1356 | __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) |
<> | 149:156823d33999 | 1357 | { |
<> | 149:156823d33999 | 1358 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); |
<> | 149:156823d33999 | 1359 | } |
<> | 149:156823d33999 | 1360 | |
<> | 149:156823d33999 | 1361 | /** |
<> | 149:156823d33999 | 1362 | * @brief Clear HSE ready interrupt flag |
<> | 149:156823d33999 | 1363 | * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY |
<> | 149:156823d33999 | 1364 | * @retval None |
<> | 149:156823d33999 | 1365 | */ |
<> | 149:156823d33999 | 1366 | __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) |
<> | 149:156823d33999 | 1367 | { |
<> | 149:156823d33999 | 1368 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); |
<> | 149:156823d33999 | 1369 | } |
<> | 149:156823d33999 | 1370 | |
<> | 149:156823d33999 | 1371 | /** |
<> | 149:156823d33999 | 1372 | * @brief Clear PLL ready interrupt flag |
<> | 149:156823d33999 | 1373 | * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY |
<> | 149:156823d33999 | 1374 | * @retval None |
<> | 149:156823d33999 | 1375 | */ |
<> | 149:156823d33999 | 1376 | __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) |
<> | 149:156823d33999 | 1377 | { |
<> | 149:156823d33999 | 1378 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); |
<> | 149:156823d33999 | 1379 | } |
<> | 149:156823d33999 | 1380 | |
<> | 149:156823d33999 | 1381 | /** |
<> | 149:156823d33999 | 1382 | * @brief Clear Clock security system interrupt flag |
<> | 149:156823d33999 | 1383 | * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS |
<> | 149:156823d33999 | 1384 | * @retval None |
<> | 149:156823d33999 | 1385 | */ |
<> | 149:156823d33999 | 1386 | __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) |
<> | 149:156823d33999 | 1387 | { |
<> | 149:156823d33999 | 1388 | SET_BIT(RCC->CIR, RCC_CIR_CSSC); |
<> | 149:156823d33999 | 1389 | } |
<> | 149:156823d33999 | 1390 | |
<> | 149:156823d33999 | 1391 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 1392 | /** |
<> | 149:156823d33999 | 1393 | * @brief Clear LSE Clock security system interrupt flag |
<> | 149:156823d33999 | 1394 | * @rmtoll CIR LSECSSC LL_RCC_ClearFlag_LSECSS |
<> | 149:156823d33999 | 1395 | * @retval None |
<> | 149:156823d33999 | 1396 | */ |
<> | 149:156823d33999 | 1397 | __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) |
<> | 149:156823d33999 | 1398 | { |
<> | 149:156823d33999 | 1399 | SET_BIT(RCC->CIR, RCC_CIR_LSECSSC); |
<> | 149:156823d33999 | 1400 | } |
<> | 149:156823d33999 | 1401 | |
<> | 149:156823d33999 | 1402 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 1403 | /** |
<> | 149:156823d33999 | 1404 | * @brief Check if LSI ready interrupt occurred or not |
<> | 149:156823d33999 | 1405 | * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY |
<> | 149:156823d33999 | 1406 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1407 | */ |
<> | 149:156823d33999 | 1408 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) |
<> | 149:156823d33999 | 1409 | { |
<> | 149:156823d33999 | 1410 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); |
<> | 149:156823d33999 | 1411 | } |
<> | 149:156823d33999 | 1412 | |
<> | 149:156823d33999 | 1413 | /** |
<> | 149:156823d33999 | 1414 | * @brief Check if LSE ready interrupt occurred or not |
<> | 149:156823d33999 | 1415 | * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY |
<> | 149:156823d33999 | 1416 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1417 | */ |
<> | 149:156823d33999 | 1418 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) |
<> | 149:156823d33999 | 1419 | { |
<> | 149:156823d33999 | 1420 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); |
<> | 149:156823d33999 | 1421 | } |
<> | 149:156823d33999 | 1422 | |
<> | 149:156823d33999 | 1423 | /** |
<> | 149:156823d33999 | 1424 | * @brief Check if MSI ready interrupt occurred or not |
<> | 149:156823d33999 | 1425 | * @rmtoll CIR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY |
<> | 149:156823d33999 | 1426 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1427 | */ |
<> | 149:156823d33999 | 1428 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) |
<> | 149:156823d33999 | 1429 | { |
<> | 149:156823d33999 | 1430 | return (READ_BIT(RCC->CIR, RCC_CIR_MSIRDYF) == (RCC_CIR_MSIRDYF)); |
<> | 149:156823d33999 | 1431 | } |
<> | 149:156823d33999 | 1432 | |
<> | 149:156823d33999 | 1433 | /** |
<> | 149:156823d33999 | 1434 | * @brief Check if HSI ready interrupt occurred or not |
<> | 149:156823d33999 | 1435 | * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY |
<> | 149:156823d33999 | 1436 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1437 | */ |
<> | 149:156823d33999 | 1438 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) |
<> | 149:156823d33999 | 1439 | { |
<> | 149:156823d33999 | 1440 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); |
<> | 149:156823d33999 | 1441 | } |
<> | 149:156823d33999 | 1442 | |
<> | 149:156823d33999 | 1443 | /** |
<> | 149:156823d33999 | 1444 | * @brief Check if HSE ready interrupt occurred or not |
<> | 149:156823d33999 | 1445 | * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY |
<> | 149:156823d33999 | 1446 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1447 | */ |
<> | 149:156823d33999 | 1448 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) |
<> | 149:156823d33999 | 1449 | { |
<> | 149:156823d33999 | 1450 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); |
<> | 149:156823d33999 | 1451 | } |
<> | 149:156823d33999 | 1452 | |
<> | 149:156823d33999 | 1453 | /** |
<> | 149:156823d33999 | 1454 | * @brief Check if PLL ready interrupt occurred or not |
<> | 149:156823d33999 | 1455 | * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY |
<> | 149:156823d33999 | 1456 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1457 | */ |
<> | 149:156823d33999 | 1458 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) |
<> | 149:156823d33999 | 1459 | { |
<> | 149:156823d33999 | 1460 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); |
<> | 149:156823d33999 | 1461 | } |
<> | 149:156823d33999 | 1462 | |
<> | 149:156823d33999 | 1463 | /** |
<> | 149:156823d33999 | 1464 | * @brief Check if Clock security system interrupt occurred or not |
<> | 149:156823d33999 | 1465 | * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS |
<> | 149:156823d33999 | 1466 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1467 | */ |
<> | 149:156823d33999 | 1468 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) |
<> | 149:156823d33999 | 1469 | { |
<> | 149:156823d33999 | 1470 | return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); |
<> | 149:156823d33999 | 1471 | } |
<> | 149:156823d33999 | 1472 | |
<> | 149:156823d33999 | 1473 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 1474 | /** |
<> | 149:156823d33999 | 1475 | * @brief Check if LSE Clock security system interrupt occurred or not |
<> | 149:156823d33999 | 1476 | * @rmtoll CIR LSECSSF LL_RCC_IsActiveFlag_LSECSS |
<> | 149:156823d33999 | 1477 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1478 | */ |
<> | 149:156823d33999 | 1479 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) |
<> | 149:156823d33999 | 1480 | { |
<> | 149:156823d33999 | 1481 | return (READ_BIT(RCC->CIR, RCC_CIR_LSECSSF) == (RCC_CIR_LSECSSF)); |
<> | 149:156823d33999 | 1482 | } |
<> | 149:156823d33999 | 1483 | |
<> | 149:156823d33999 | 1484 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 1485 | /** |
<> | 149:156823d33999 | 1486 | * @brief Check if RCC flag Independent Watchdog reset is set or not. |
<> | 149:156823d33999 | 1487 | * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST |
<> | 149:156823d33999 | 1488 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1489 | */ |
<> | 149:156823d33999 | 1490 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) |
<> | 149:156823d33999 | 1491 | { |
<> | 149:156823d33999 | 1492 | return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); |
<> | 149:156823d33999 | 1493 | } |
<> | 149:156823d33999 | 1494 | |
<> | 149:156823d33999 | 1495 | /** |
<> | 149:156823d33999 | 1496 | * @brief Check if RCC flag Low Power reset is set or not. |
<> | 149:156823d33999 | 1497 | * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST |
<> | 149:156823d33999 | 1498 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1499 | */ |
<> | 149:156823d33999 | 1500 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) |
<> | 149:156823d33999 | 1501 | { |
<> | 149:156823d33999 | 1502 | return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); |
<> | 149:156823d33999 | 1503 | } |
<> | 149:156823d33999 | 1504 | |
<> | 149:156823d33999 | 1505 | /** |
<> | 149:156823d33999 | 1506 | * @brief Check if RCC flag is set or not. |
<> | 149:156823d33999 | 1507 | * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST |
<> | 149:156823d33999 | 1508 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1509 | */ |
<> | 149:156823d33999 | 1510 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) |
<> | 149:156823d33999 | 1511 | { |
<> | 149:156823d33999 | 1512 | return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); |
<> | 149:156823d33999 | 1513 | } |
<> | 149:156823d33999 | 1514 | |
<> | 149:156823d33999 | 1515 | /** |
<> | 149:156823d33999 | 1516 | * @brief Check if RCC flag Pin reset is set or not. |
<> | 149:156823d33999 | 1517 | * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST |
<> | 149:156823d33999 | 1518 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1519 | */ |
<> | 149:156823d33999 | 1520 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) |
<> | 149:156823d33999 | 1521 | { |
<> | 149:156823d33999 | 1522 | return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); |
<> | 149:156823d33999 | 1523 | } |
<> | 149:156823d33999 | 1524 | |
<> | 149:156823d33999 | 1525 | /** |
<> | 149:156823d33999 | 1526 | * @brief Check if RCC flag POR/PDR reset is set or not. |
<> | 149:156823d33999 | 1527 | * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST |
<> | 149:156823d33999 | 1528 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1529 | */ |
<> | 149:156823d33999 | 1530 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) |
<> | 149:156823d33999 | 1531 | { |
<> | 149:156823d33999 | 1532 | return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); |
<> | 149:156823d33999 | 1533 | } |
<> | 149:156823d33999 | 1534 | |
<> | 149:156823d33999 | 1535 | /** |
<> | 149:156823d33999 | 1536 | * @brief Check if RCC flag Software reset is set or not. |
<> | 149:156823d33999 | 1537 | * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST |
<> | 149:156823d33999 | 1538 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1539 | */ |
<> | 149:156823d33999 | 1540 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) |
<> | 149:156823d33999 | 1541 | { |
<> | 149:156823d33999 | 1542 | return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); |
<> | 149:156823d33999 | 1543 | } |
<> | 149:156823d33999 | 1544 | |
<> | 149:156823d33999 | 1545 | /** |
<> | 149:156823d33999 | 1546 | * @brief Check if RCC flag Window Watchdog reset is set or not. |
<> | 149:156823d33999 | 1547 | * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST |
<> | 149:156823d33999 | 1548 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1549 | */ |
<> | 149:156823d33999 | 1550 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) |
<> | 149:156823d33999 | 1551 | { |
<> | 149:156823d33999 | 1552 | return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); |
<> | 149:156823d33999 | 1553 | } |
<> | 149:156823d33999 | 1554 | |
<> | 149:156823d33999 | 1555 | /** |
<> | 149:156823d33999 | 1556 | * @brief Set RMVF bit to clear the reset flags. |
<> | 149:156823d33999 | 1557 | * @rmtoll CSR RMVF LL_RCC_ClearResetFlags |
<> | 149:156823d33999 | 1558 | * @retval None |
<> | 149:156823d33999 | 1559 | */ |
<> | 149:156823d33999 | 1560 | __STATIC_INLINE void LL_RCC_ClearResetFlags(void) |
<> | 149:156823d33999 | 1561 | { |
<> | 149:156823d33999 | 1562 | SET_BIT(RCC->CSR, RCC_CSR_RMVF); |
<> | 149:156823d33999 | 1563 | } |
<> | 149:156823d33999 | 1564 | |
<> | 149:156823d33999 | 1565 | /** |
<> | 149:156823d33999 | 1566 | * @} |
<> | 149:156823d33999 | 1567 | */ |
<> | 149:156823d33999 | 1568 | |
<> | 149:156823d33999 | 1569 | /** @defgroup RCC_LL_EF_IT_Management IT Management |
<> | 149:156823d33999 | 1570 | * @{ |
<> | 149:156823d33999 | 1571 | */ |
<> | 149:156823d33999 | 1572 | |
<> | 149:156823d33999 | 1573 | /** |
<> | 149:156823d33999 | 1574 | * @brief Enable LSI ready interrupt |
<> | 149:156823d33999 | 1575 | * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY |
<> | 149:156823d33999 | 1576 | * @retval None |
<> | 149:156823d33999 | 1577 | */ |
<> | 149:156823d33999 | 1578 | __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) |
<> | 149:156823d33999 | 1579 | { |
<> | 149:156823d33999 | 1580 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
<> | 149:156823d33999 | 1581 | } |
<> | 149:156823d33999 | 1582 | |
<> | 149:156823d33999 | 1583 | /** |
<> | 149:156823d33999 | 1584 | * @brief Enable LSE ready interrupt |
<> | 149:156823d33999 | 1585 | * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY |
<> | 149:156823d33999 | 1586 | * @retval None |
<> | 149:156823d33999 | 1587 | */ |
<> | 149:156823d33999 | 1588 | __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) |
<> | 149:156823d33999 | 1589 | { |
<> | 149:156823d33999 | 1590 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
<> | 149:156823d33999 | 1591 | } |
<> | 149:156823d33999 | 1592 | |
<> | 149:156823d33999 | 1593 | /** |
<> | 149:156823d33999 | 1594 | * @brief Enable MSI ready interrupt |
<> | 149:156823d33999 | 1595 | * @rmtoll CIR MSIRDYIE LL_RCC_EnableIT_MSIRDY |
<> | 149:156823d33999 | 1596 | * @retval None |
<> | 149:156823d33999 | 1597 | */ |
<> | 149:156823d33999 | 1598 | __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) |
<> | 149:156823d33999 | 1599 | { |
<> | 149:156823d33999 | 1600 | SET_BIT(RCC->CIR, RCC_CIR_MSIRDYIE); |
<> | 149:156823d33999 | 1601 | } |
<> | 149:156823d33999 | 1602 | |
<> | 149:156823d33999 | 1603 | /** |
<> | 149:156823d33999 | 1604 | * @brief Enable HSI ready interrupt |
<> | 149:156823d33999 | 1605 | * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY |
<> | 149:156823d33999 | 1606 | * @retval None |
<> | 149:156823d33999 | 1607 | */ |
<> | 149:156823d33999 | 1608 | __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) |
<> | 149:156823d33999 | 1609 | { |
<> | 149:156823d33999 | 1610 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
<> | 149:156823d33999 | 1611 | } |
<> | 149:156823d33999 | 1612 | |
<> | 149:156823d33999 | 1613 | /** |
<> | 149:156823d33999 | 1614 | * @brief Enable HSE ready interrupt |
<> | 149:156823d33999 | 1615 | * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY |
<> | 149:156823d33999 | 1616 | * @retval None |
<> | 149:156823d33999 | 1617 | */ |
<> | 149:156823d33999 | 1618 | __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) |
<> | 149:156823d33999 | 1619 | { |
<> | 149:156823d33999 | 1620 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
<> | 149:156823d33999 | 1621 | } |
<> | 149:156823d33999 | 1622 | |
<> | 149:156823d33999 | 1623 | /** |
<> | 149:156823d33999 | 1624 | * @brief Enable PLL ready interrupt |
<> | 149:156823d33999 | 1625 | * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY |
<> | 149:156823d33999 | 1626 | * @retval None |
<> | 149:156823d33999 | 1627 | */ |
<> | 149:156823d33999 | 1628 | __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) |
<> | 149:156823d33999 | 1629 | { |
<> | 149:156823d33999 | 1630 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
<> | 149:156823d33999 | 1631 | } |
<> | 149:156823d33999 | 1632 | |
<> | 149:156823d33999 | 1633 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 1634 | /** |
<> | 149:156823d33999 | 1635 | * @brief Enable LSE clock security system interrupt |
<> | 149:156823d33999 | 1636 | * @rmtoll CIR LSECSSIE LL_RCC_EnableIT_LSECSS |
<> | 149:156823d33999 | 1637 | * @retval None |
<> | 149:156823d33999 | 1638 | */ |
<> | 149:156823d33999 | 1639 | __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) |
<> | 149:156823d33999 | 1640 | { |
<> | 149:156823d33999 | 1641 | SET_BIT(RCC->CIR, RCC_CIR_LSECSSIE); |
<> | 149:156823d33999 | 1642 | } |
<> | 149:156823d33999 | 1643 | |
<> | 149:156823d33999 | 1644 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 1645 | /** |
<> | 149:156823d33999 | 1646 | * @brief Disable LSI ready interrupt |
<> | 149:156823d33999 | 1647 | * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY |
<> | 149:156823d33999 | 1648 | * @retval None |
<> | 149:156823d33999 | 1649 | */ |
<> | 149:156823d33999 | 1650 | __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) |
<> | 149:156823d33999 | 1651 | { |
<> | 149:156823d33999 | 1652 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
<> | 149:156823d33999 | 1653 | } |
<> | 149:156823d33999 | 1654 | |
<> | 149:156823d33999 | 1655 | /** |
<> | 149:156823d33999 | 1656 | * @brief Disable LSE ready interrupt |
<> | 149:156823d33999 | 1657 | * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY |
<> | 149:156823d33999 | 1658 | * @retval None |
<> | 149:156823d33999 | 1659 | */ |
<> | 149:156823d33999 | 1660 | __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) |
<> | 149:156823d33999 | 1661 | { |
<> | 149:156823d33999 | 1662 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
<> | 149:156823d33999 | 1663 | } |
<> | 149:156823d33999 | 1664 | |
<> | 149:156823d33999 | 1665 | /** |
<> | 149:156823d33999 | 1666 | * @brief Disable MSI ready interrupt |
<> | 149:156823d33999 | 1667 | * @rmtoll CIR MSIRDYIE LL_RCC_DisableIT_MSIRDY |
<> | 149:156823d33999 | 1668 | * @retval None |
<> | 149:156823d33999 | 1669 | */ |
<> | 149:156823d33999 | 1670 | __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) |
<> | 149:156823d33999 | 1671 | { |
<> | 149:156823d33999 | 1672 | CLEAR_BIT(RCC->CIR, RCC_CIR_MSIRDYIE); |
<> | 149:156823d33999 | 1673 | } |
<> | 149:156823d33999 | 1674 | |
<> | 149:156823d33999 | 1675 | /** |
<> | 149:156823d33999 | 1676 | * @brief Disable HSI ready interrupt |
<> | 149:156823d33999 | 1677 | * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY |
<> | 149:156823d33999 | 1678 | * @retval None |
<> | 149:156823d33999 | 1679 | */ |
<> | 149:156823d33999 | 1680 | __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) |
<> | 149:156823d33999 | 1681 | { |
<> | 149:156823d33999 | 1682 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
<> | 149:156823d33999 | 1683 | } |
<> | 149:156823d33999 | 1684 | |
<> | 149:156823d33999 | 1685 | /** |
<> | 149:156823d33999 | 1686 | * @brief Disable HSE ready interrupt |
<> | 149:156823d33999 | 1687 | * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY |
<> | 149:156823d33999 | 1688 | * @retval None |
<> | 149:156823d33999 | 1689 | */ |
<> | 149:156823d33999 | 1690 | __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) |
<> | 149:156823d33999 | 1691 | { |
<> | 149:156823d33999 | 1692 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
<> | 149:156823d33999 | 1693 | } |
<> | 149:156823d33999 | 1694 | |
<> | 149:156823d33999 | 1695 | /** |
<> | 149:156823d33999 | 1696 | * @brief Disable PLL ready interrupt |
<> | 149:156823d33999 | 1697 | * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY |
<> | 149:156823d33999 | 1698 | * @retval None |
<> | 149:156823d33999 | 1699 | */ |
<> | 149:156823d33999 | 1700 | __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) |
<> | 149:156823d33999 | 1701 | { |
<> | 149:156823d33999 | 1702 | CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
<> | 149:156823d33999 | 1703 | } |
<> | 149:156823d33999 | 1704 | |
<> | 149:156823d33999 | 1705 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 1706 | /** |
<> | 149:156823d33999 | 1707 | * @brief Disable LSE clock security system interrupt |
<> | 149:156823d33999 | 1708 | * @rmtoll CIR LSECSSIE LL_RCC_DisableIT_LSECSS |
<> | 149:156823d33999 | 1709 | * @retval None |
<> | 149:156823d33999 | 1710 | */ |
<> | 149:156823d33999 | 1711 | __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) |
<> | 149:156823d33999 | 1712 | { |
<> | 149:156823d33999 | 1713 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSECSSIE); |
<> | 149:156823d33999 | 1714 | } |
<> | 149:156823d33999 | 1715 | |
<> | 149:156823d33999 | 1716 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 1717 | /** |
<> | 149:156823d33999 | 1718 | * @brief Checks if LSI ready interrupt source is enabled or disabled. |
<> | 149:156823d33999 | 1719 | * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY |
<> | 149:156823d33999 | 1720 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1721 | */ |
<> | 149:156823d33999 | 1722 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) |
<> | 149:156823d33999 | 1723 | { |
<> | 149:156823d33999 | 1724 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); |
<> | 149:156823d33999 | 1725 | } |
<> | 149:156823d33999 | 1726 | |
<> | 149:156823d33999 | 1727 | /** |
<> | 149:156823d33999 | 1728 | * @brief Checks if LSE ready interrupt source is enabled or disabled. |
<> | 149:156823d33999 | 1729 | * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY |
<> | 149:156823d33999 | 1730 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1731 | */ |
<> | 149:156823d33999 | 1732 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) |
<> | 149:156823d33999 | 1733 | { |
<> | 149:156823d33999 | 1734 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); |
<> | 149:156823d33999 | 1735 | } |
<> | 149:156823d33999 | 1736 | |
<> | 149:156823d33999 | 1737 | /** |
<> | 149:156823d33999 | 1738 | * @brief Checks if MSI ready interrupt source is enabled or disabled. |
<> | 149:156823d33999 | 1739 | * @rmtoll CIR MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY |
<> | 149:156823d33999 | 1740 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1741 | */ |
<> | 149:156823d33999 | 1742 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) |
<> | 149:156823d33999 | 1743 | { |
<> | 149:156823d33999 | 1744 | return (READ_BIT(RCC->CIR, RCC_CIR_MSIRDYIE) == (RCC_CIR_MSIRDYIE)); |
<> | 149:156823d33999 | 1745 | } |
<> | 149:156823d33999 | 1746 | |
<> | 149:156823d33999 | 1747 | /** |
<> | 149:156823d33999 | 1748 | * @brief Checks if HSI ready interrupt source is enabled or disabled. |
<> | 149:156823d33999 | 1749 | * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY |
<> | 149:156823d33999 | 1750 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1751 | */ |
<> | 149:156823d33999 | 1752 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) |
<> | 149:156823d33999 | 1753 | { |
<> | 149:156823d33999 | 1754 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); |
<> | 149:156823d33999 | 1755 | } |
<> | 149:156823d33999 | 1756 | |
<> | 149:156823d33999 | 1757 | /** |
<> | 149:156823d33999 | 1758 | * @brief Checks if HSE ready interrupt source is enabled or disabled. |
<> | 149:156823d33999 | 1759 | * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY |
<> | 149:156823d33999 | 1760 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1761 | */ |
<> | 149:156823d33999 | 1762 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) |
<> | 149:156823d33999 | 1763 | { |
<> | 149:156823d33999 | 1764 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); |
<> | 149:156823d33999 | 1765 | } |
<> | 149:156823d33999 | 1766 | |
<> | 149:156823d33999 | 1767 | /** |
<> | 149:156823d33999 | 1768 | * @brief Checks if PLL ready interrupt source is enabled or disabled. |
<> | 149:156823d33999 | 1769 | * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY |
<> | 149:156823d33999 | 1770 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1771 | */ |
<> | 149:156823d33999 | 1772 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) |
<> | 149:156823d33999 | 1773 | { |
<> | 149:156823d33999 | 1774 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); |
<> | 149:156823d33999 | 1775 | } |
<> | 149:156823d33999 | 1776 | |
<> | 149:156823d33999 | 1777 | #if defined(RCC_LSECSS_SUPPORT) |
<> | 149:156823d33999 | 1778 | /** |
<> | 149:156823d33999 | 1779 | * @brief Checks if LSECSS interrupt source is enabled or disabled. |
<> | 149:156823d33999 | 1780 | * @rmtoll CIR LSECSSIE LL_RCC_IsEnabledIT_LSECSS |
<> | 149:156823d33999 | 1781 | * @retval State of bit (1 or 0). |
<> | 149:156823d33999 | 1782 | */ |
<> | 149:156823d33999 | 1783 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) |
<> | 149:156823d33999 | 1784 | { |
<> | 149:156823d33999 | 1785 | return (READ_BIT(RCC->CIR, RCC_CIR_LSECSSIE) == (RCC_CIR_LSECSSIE)); |
<> | 149:156823d33999 | 1786 | } |
<> | 149:156823d33999 | 1787 | |
<> | 149:156823d33999 | 1788 | #endif /* RCC_LSECSS_SUPPORT */ |
<> | 149:156823d33999 | 1789 | /** |
<> | 149:156823d33999 | 1790 | * @} |
<> | 149:156823d33999 | 1791 | */ |
<> | 149:156823d33999 | 1792 | |
<> | 149:156823d33999 | 1793 | #if defined(USE_FULL_LL_DRIVER) |
<> | 149:156823d33999 | 1794 | /** @defgroup RCC_LL_EF_Init De-initialization function |
<> | 149:156823d33999 | 1795 | * @{ |
<> | 149:156823d33999 | 1796 | */ |
<> | 149:156823d33999 | 1797 | ErrorStatus LL_RCC_DeInit(void); |
<> | 149:156823d33999 | 1798 | /** |
<> | 149:156823d33999 | 1799 | * @} |
<> | 149:156823d33999 | 1800 | */ |
<> | 149:156823d33999 | 1801 | |
<> | 149:156823d33999 | 1802 | /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions |
<> | 149:156823d33999 | 1803 | * @{ |
<> | 149:156823d33999 | 1804 | */ |
<> | 149:156823d33999 | 1805 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); |
<> | 149:156823d33999 | 1806 | /** |
<> | 149:156823d33999 | 1807 | * @} |
<> | 149:156823d33999 | 1808 | */ |
<> | 149:156823d33999 | 1809 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 149:156823d33999 | 1810 | |
<> | 149:156823d33999 | 1811 | /** |
<> | 149:156823d33999 | 1812 | * @} |
<> | 149:156823d33999 | 1813 | */ |
<> | 149:156823d33999 | 1814 | |
<> | 149:156823d33999 | 1815 | /** |
<> | 149:156823d33999 | 1816 | * @} |
<> | 149:156823d33999 | 1817 | */ |
<> | 149:156823d33999 | 1818 | |
<> | 149:156823d33999 | 1819 | #endif /* RCC */ |
<> | 149:156823d33999 | 1820 | |
<> | 149:156823d33999 | 1821 | /** |
<> | 149:156823d33999 | 1822 | * @} |
<> | 149:156823d33999 | 1823 | */ |
<> | 149:156823d33999 | 1824 | |
<> | 149:156823d33999 | 1825 | #ifdef __cplusplus |
<> | 149:156823d33999 | 1826 | } |
<> | 149:156823d33999 | 1827 | #endif |
<> | 149:156823d33999 | 1828 | |
<> | 149:156823d33999 | 1829 | #endif /* __STM32L1xx_LL_RCC_H */ |
<> | 149:156823d33999 | 1830 | |
<> | 149:156823d33999 | 1831 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |