mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Parent:
- targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c@144:ef7eb2e8f9f7
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include <stddef.h> |
<> | 144:ef7eb2e8f9f7 | 17 | |
<> | 144:ef7eb2e8f9f7 | 18 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 19 | #include "gpio_irq_api.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | #define CHANNEL_NUM 8 |
<> | 144:ef7eb2e8f9f7 | 23 | #define LPC_GPIO_X LPC_PINT |
<> | 144:ef7eb2e8f9f7 | 24 | #define PININT_IRQ PIN_INT0_IRQn |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | static uint32_t channel_ids[CHANNEL_NUM] = {0}; |
<> | 144:ef7eb2e8f9f7 | 27 | static gpio_irq_handler irq_handler; |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | static inline void handle_interrupt_in(uint32_t channel) { |
<> | 144:ef7eb2e8f9f7 | 30 | uint32_t ch_bit = (1 << channel); |
<> | 144:ef7eb2e8f9f7 | 31 | // Return immediately if: |
<> | 144:ef7eb2e8f9f7 | 32 | // * The interrupt was already served |
<> | 144:ef7eb2e8f9f7 | 33 | // * There is no user handler |
<> | 144:ef7eb2e8f9f7 | 34 | // * It is a level interrupt, not an edge interrupt |
<> | 144:ef7eb2e8f9f7 | 35 | if ( ((LPC_GPIO_X->IST & ch_bit) == 0) || |
<> | 144:ef7eb2e8f9f7 | 36 | (channel_ids[channel] == 0 ) || |
<> | 144:ef7eb2e8f9f7 | 37 | (LPC_GPIO_X->ISEL & ch_bit ) ) return; |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) { |
<> | 144:ef7eb2e8f9f7 | 40 | irq_handler(channel_ids[channel], IRQ_RISE); |
<> | 144:ef7eb2e8f9f7 | 41 | LPC_GPIO_X->RISE = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 42 | } |
<> | 144:ef7eb2e8f9f7 | 43 | if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) { |
<> | 144:ef7eb2e8f9f7 | 44 | irq_handler(channel_ids[channel], IRQ_FALL); |
<> | 144:ef7eb2e8f9f7 | 45 | LPC_GPIO_X->FALL = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 46 | } |
<> | 144:ef7eb2e8f9f7 | 47 | LPC_GPIO_X->IST = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 48 | } |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | void gpio_irq0(void) {handle_interrupt_in(0);} |
<> | 144:ef7eb2e8f9f7 | 51 | void gpio_irq1(void) {handle_interrupt_in(1);} |
<> | 144:ef7eb2e8f9f7 | 52 | void gpio_irq2(void) {handle_interrupt_in(2);} |
<> | 144:ef7eb2e8f9f7 | 53 | void gpio_irq3(void) {handle_interrupt_in(3);} |
<> | 144:ef7eb2e8f9f7 | 54 | void gpio_irq4(void) {handle_interrupt_in(4);} |
<> | 144:ef7eb2e8f9f7 | 55 | void gpio_irq5(void) {handle_interrupt_in(5);} |
<> | 144:ef7eb2e8f9f7 | 56 | void gpio_irq6(void) {handle_interrupt_in(6);} |
<> | 144:ef7eb2e8f9f7 | 57 | void gpio_irq7(void) {handle_interrupt_in(7);} |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { |
<> | 144:ef7eb2e8f9f7 | 60 | // PINT only supprt GPIO port 0 and 1 interrupt |
<> | 144:ef7eb2e8f9f7 | 61 | if (pin >= P2_0) return -1; |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | irq_handler = handler; |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | int found_free_channel = 0; |
<> | 144:ef7eb2e8f9f7 | 66 | int i = 0; |
<> | 144:ef7eb2e8f9f7 | 67 | for (i=0; i<CHANNEL_NUM; i++) { |
<> | 144:ef7eb2e8f9f7 | 68 | if (channel_ids[i] == 0) { |
<> | 144:ef7eb2e8f9f7 | 69 | channel_ids[i] = id; |
<> | 144:ef7eb2e8f9f7 | 70 | obj->ch = i; |
<> | 144:ef7eb2e8f9f7 | 71 | found_free_channel = 1; |
<> | 144:ef7eb2e8f9f7 | 72 | break; |
<> | 144:ef7eb2e8f9f7 | 73 | } |
<> | 144:ef7eb2e8f9f7 | 74 | } |
<> | 144:ef7eb2e8f9f7 | 75 | if (!found_free_channel) return -1; |
<> | 144:ef7eb2e8f9f7 | 76 | |
<> | 144:ef7eb2e8f9f7 | 77 | /* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */ |
<> | 144:ef7eb2e8f9f7 | 78 | LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11)); |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | LPC_INMUX->PINTSEL[obj->ch] = pin; |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | // Interrupt Wake-Up Enable |
<> | 144:ef7eb2e8f9f7 | 83 | LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5)); |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F)); |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | void (*channels_irq)(void) = NULL; |
<> | 144:ef7eb2e8f9f7 | 88 | switch (obj->ch) { |
<> | 144:ef7eb2e8f9f7 | 89 | case 0: channels_irq = &gpio_irq0; break; |
<> | 144:ef7eb2e8f9f7 | 90 | case 1: channels_irq = &gpio_irq1; break; |
<> | 144:ef7eb2e8f9f7 | 91 | case 2: channels_irq = &gpio_irq2; break; |
<> | 144:ef7eb2e8f9f7 | 92 | case 3: channels_irq = &gpio_irq3; break; |
<> | 144:ef7eb2e8f9f7 | 93 | case 4: channels_irq = &gpio_irq4; break; |
<> | 144:ef7eb2e8f9f7 | 94 | case 5: channels_irq = &gpio_irq5; break; |
<> | 144:ef7eb2e8f9f7 | 95 | case 6: channels_irq = &gpio_irq6; break; |
<> | 144:ef7eb2e8f9f7 | 96 | case 7: channels_irq = &gpio_irq7; break; |
<> | 144:ef7eb2e8f9f7 | 97 | } |
<> | 144:ef7eb2e8f9f7 | 98 | NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); |
<> | 144:ef7eb2e8f9f7 | 99 | NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | return 0; |
<> | 144:ef7eb2e8f9f7 | 102 | } |
<> | 144:ef7eb2e8f9f7 | 103 | |
<> | 144:ef7eb2e8f9f7 | 104 | void gpio_irq_free(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 105 | channel_ids[obj->ch] = 0; |
<> | 144:ef7eb2e8f9f7 | 106 | LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5)); |
<> | 144:ef7eb2e8f9f7 | 107 | } |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { |
<> | 144:ef7eb2e8f9f7 | 110 | unsigned int ch_bit = (1 << obj->ch); |
<> | 144:ef7eb2e8f9f7 | 111 | |
<> | 144:ef7eb2e8f9f7 | 112 | // Clear interrupt |
<> | 144:ef7eb2e8f9f7 | 113 | if (!(LPC_GPIO_X->ISEL & ch_bit)) |
<> | 144:ef7eb2e8f9f7 | 114 | LPC_GPIO_X->IST = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | // Edge trigger |
<> | 144:ef7eb2e8f9f7 | 117 | LPC_GPIO_X->ISEL &= ~ch_bit; |
<> | 144:ef7eb2e8f9f7 | 118 | if (event == IRQ_RISE) { |
<> | 144:ef7eb2e8f9f7 | 119 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 120 | LPC_GPIO_X->IENR |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 121 | } else { |
<> | 144:ef7eb2e8f9f7 | 122 | LPC_GPIO_X->IENR &= ~ch_bit; |
<> | 144:ef7eb2e8f9f7 | 123 | } |
<> | 144:ef7eb2e8f9f7 | 124 | } else { |
<> | 144:ef7eb2e8f9f7 | 125 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 126 | LPC_GPIO_X->IENF |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 127 | } else { |
<> | 144:ef7eb2e8f9f7 | 128 | LPC_GPIO_X->IENF &= ~ch_bit; |
<> | 144:ef7eb2e8f9f7 | 129 | } |
<> | 144:ef7eb2e8f9f7 | 130 | } |
<> | 144:ef7eb2e8f9f7 | 131 | } |
<> | 144:ef7eb2e8f9f7 | 132 | |
<> | 144:ef7eb2e8f9f7 | 133 | void gpio_irq_enable(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 134 | NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
<> | 144:ef7eb2e8f9f7 | 135 | } |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | void gpio_irq_disable(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 138 | NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
<> | 144:ef7eb2e8f9f7 | 139 | } |