mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sram.h@184:08ed48f1de7f, 2018-04-19 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Apr 19 17:12:19 2018 +0100
- Revision:
- 184:08ed48f1de7f
- Parent:
- 149:156823d33999
mbed-dev library. Release version 161
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 149:156823d33999 | 1 | /** |
<> | 149:156823d33999 | 2 | ****************************************************************************** |
<> | 149:156823d33999 | 3 | * @file stm32l1xx_hal_sram.h |
<> | 149:156823d33999 | 4 | * @author MCD Application Team |
<> | 149:156823d33999 | 5 | * @brief Header file of SRAM HAL module. |
<> | 149:156823d33999 | 6 | ****************************************************************************** |
<> | 149:156823d33999 | 7 | * @attention |
<> | 149:156823d33999 | 8 | * |
AnnaBridge | 184:08ed48f1de7f | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 149:156823d33999 | 10 | * |
<> | 149:156823d33999 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 149:156823d33999 | 12 | * are permitted provided that the following conditions are met: |
<> | 149:156823d33999 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 149:156823d33999 | 14 | * this list of conditions and the following disclaimer. |
<> | 149:156823d33999 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 149:156823d33999 | 16 | * this list of conditions and the following disclaimer in the documentation |
<> | 149:156823d33999 | 17 | * and/or other materials provided with the distribution. |
<> | 149:156823d33999 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 149:156823d33999 | 19 | * may be used to endorse or promote products derived from this software |
<> | 149:156823d33999 | 20 | * without specific prior written permission. |
<> | 149:156823d33999 | 21 | * |
<> | 149:156823d33999 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 149:156823d33999 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 149:156823d33999 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 149:156823d33999 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 149:156823d33999 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 149:156823d33999 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 149:156823d33999 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 149:156823d33999 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 149:156823d33999 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 149:156823d33999 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 149:156823d33999 | 32 | * |
<> | 149:156823d33999 | 33 | ****************************************************************************** |
<> | 149:156823d33999 | 34 | */ |
<> | 149:156823d33999 | 35 | |
<> | 149:156823d33999 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 149:156823d33999 | 37 | #ifndef __STM32L1xx_HAL_SRAM_H |
<> | 149:156823d33999 | 38 | #define __STM32L1xx_HAL_SRAM_H |
<> | 149:156823d33999 | 39 | |
<> | 149:156823d33999 | 40 | #ifdef __cplusplus |
<> | 149:156823d33999 | 41 | extern "C" { |
<> | 149:156823d33999 | 42 | #endif |
<> | 149:156823d33999 | 43 | |
<> | 149:156823d33999 | 44 | /* Includes ------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 45 | #include "stm32l1xx_ll_fsmc.h" |
<> | 149:156823d33999 | 46 | |
<> | 149:156823d33999 | 47 | /** @addtogroup STM32L1xx_HAL_Driver |
<> | 149:156823d33999 | 48 | * @{ |
<> | 149:156823d33999 | 49 | */ |
<> | 149:156823d33999 | 50 | |
<> | 149:156823d33999 | 51 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
<> | 149:156823d33999 | 52 | |
<> | 149:156823d33999 | 53 | /** @addtogroup SRAM |
<> | 149:156823d33999 | 54 | * @{ |
<> | 149:156823d33999 | 55 | */ |
<> | 149:156823d33999 | 56 | |
<> | 149:156823d33999 | 57 | /* Exported typedef ----------------------------------------------------------*/ |
<> | 149:156823d33999 | 58 | |
<> | 149:156823d33999 | 59 | /** @defgroup SRAM_Exported_Types SRAM Exported Types |
<> | 149:156823d33999 | 60 | * @{ |
<> | 149:156823d33999 | 61 | */ |
<> | 149:156823d33999 | 62 | /** |
<> | 149:156823d33999 | 63 | * @brief HAL SRAM State structures definition |
<> | 149:156823d33999 | 64 | */ |
<> | 149:156823d33999 | 65 | typedef enum |
<> | 149:156823d33999 | 66 | { |
<> | 149:156823d33999 | 67 | HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ |
<> | 149:156823d33999 | 68 | HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ |
<> | 149:156823d33999 | 69 | HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ |
<> | 149:156823d33999 | 70 | HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ |
<> | 149:156823d33999 | 71 | HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ |
<> | 149:156823d33999 | 72 | |
<> | 149:156823d33999 | 73 | }HAL_SRAM_StateTypeDef; |
<> | 149:156823d33999 | 74 | |
<> | 149:156823d33999 | 75 | /** |
<> | 149:156823d33999 | 76 | * @brief SRAM handle Structure definition |
<> | 149:156823d33999 | 77 | */ |
<> | 149:156823d33999 | 78 | typedef struct |
<> | 149:156823d33999 | 79 | { |
<> | 149:156823d33999 | 80 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
<> | 149:156823d33999 | 81 | |
<> | 149:156823d33999 | 82 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
<> | 149:156823d33999 | 83 | |
<> | 149:156823d33999 | 84 | FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ |
<> | 149:156823d33999 | 85 | |
<> | 149:156823d33999 | 86 | HAL_LockTypeDef Lock; /*!< SRAM locking object */ |
<> | 149:156823d33999 | 87 | |
<> | 149:156823d33999 | 88 | __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ |
<> | 149:156823d33999 | 89 | |
<> | 149:156823d33999 | 90 | DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
<> | 149:156823d33999 | 91 | |
<> | 149:156823d33999 | 92 | }SRAM_HandleTypeDef; |
<> | 149:156823d33999 | 93 | |
<> | 149:156823d33999 | 94 | /** |
<> | 149:156823d33999 | 95 | * @} |
<> | 149:156823d33999 | 96 | */ |
<> | 149:156823d33999 | 97 | |
<> | 149:156823d33999 | 98 | /* Exported constants --------------------------------------------------------*/ |
<> | 149:156823d33999 | 99 | /* Exported macro ------------------------------------------------------------*/ |
<> | 149:156823d33999 | 100 | |
<> | 149:156823d33999 | 101 | /** @defgroup SRAM_Exported_Macros SRAM Exported Macros |
<> | 149:156823d33999 | 102 | * @{ |
<> | 149:156823d33999 | 103 | */ |
<> | 149:156823d33999 | 104 | |
<> | 149:156823d33999 | 105 | /** @brief Reset SRAM handle state |
<> | 149:156823d33999 | 106 | * @param __HANDLE__: SRAM handle |
<> | 149:156823d33999 | 107 | * @retval None |
<> | 149:156823d33999 | 108 | */ |
<> | 149:156823d33999 | 109 | #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) |
<> | 149:156823d33999 | 110 | |
<> | 149:156823d33999 | 111 | /** |
<> | 149:156823d33999 | 112 | * @} |
<> | 149:156823d33999 | 113 | */ |
<> | 149:156823d33999 | 114 | |
<> | 149:156823d33999 | 115 | /* Exported functions --------------------------------------------------------*/ |
<> | 149:156823d33999 | 116 | |
<> | 149:156823d33999 | 117 | /** @addtogroup SRAM_Exported_Functions |
<> | 149:156823d33999 | 118 | * @{ |
<> | 149:156823d33999 | 119 | */ |
<> | 149:156823d33999 | 120 | |
<> | 149:156823d33999 | 121 | /** @addtogroup SRAM_Exported_Functions_Group1 |
<> | 149:156823d33999 | 122 | * @{ |
<> | 149:156823d33999 | 123 | */ |
<> | 149:156823d33999 | 124 | |
<> | 149:156823d33999 | 125 | /* Initialization/de-initialization functions **********************************/ |
<> | 149:156823d33999 | 126 | HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
<> | 149:156823d33999 | 127 | HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); |
<> | 149:156823d33999 | 128 | void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); |
<> | 149:156823d33999 | 129 | void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); |
<> | 149:156823d33999 | 130 | |
<> | 149:156823d33999 | 131 | void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
<> | 149:156823d33999 | 132 | void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
<> | 149:156823d33999 | 133 | |
<> | 149:156823d33999 | 134 | /** |
<> | 149:156823d33999 | 135 | * @} |
<> | 149:156823d33999 | 136 | */ |
<> | 149:156823d33999 | 137 | |
<> | 149:156823d33999 | 138 | /** @addtogroup SRAM_Exported_Functions_Group2 |
<> | 149:156823d33999 | 139 | * @{ |
<> | 149:156823d33999 | 140 | */ |
<> | 149:156823d33999 | 141 | |
<> | 149:156823d33999 | 142 | /* I/O operation functions *****************************************************/ |
<> | 149:156823d33999 | 143 | HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); |
<> | 149:156823d33999 | 144 | HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); |
<> | 149:156823d33999 | 145 | HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); |
<> | 149:156823d33999 | 146 | HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); |
<> | 149:156823d33999 | 147 | HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); |
<> | 149:156823d33999 | 148 | HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); |
<> | 149:156823d33999 | 149 | HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); |
<> | 149:156823d33999 | 150 | HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); |
<> | 149:156823d33999 | 151 | |
<> | 149:156823d33999 | 152 | /** |
<> | 149:156823d33999 | 153 | * @} |
<> | 149:156823d33999 | 154 | */ |
<> | 149:156823d33999 | 155 | |
<> | 149:156823d33999 | 156 | /** @addtogroup SRAM_Exported_Functions_Group3 |
<> | 149:156823d33999 | 157 | * @{ |
<> | 149:156823d33999 | 158 | */ |
<> | 149:156823d33999 | 159 | |
<> | 149:156823d33999 | 160 | /* SRAM Control functions ******************************************************/ |
<> | 149:156823d33999 | 161 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); |
<> | 149:156823d33999 | 162 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); |
<> | 149:156823d33999 | 163 | |
<> | 149:156823d33999 | 164 | /** |
<> | 149:156823d33999 | 165 | * @} |
<> | 149:156823d33999 | 166 | */ |
<> | 149:156823d33999 | 167 | |
<> | 149:156823d33999 | 168 | /** @addtogroup SRAM_Exported_Functions_Group4 |
<> | 149:156823d33999 | 169 | * @{ |
<> | 149:156823d33999 | 170 | */ |
<> | 149:156823d33999 | 171 | |
<> | 149:156823d33999 | 172 | /* SRAM State functions *********************************************************/ |
<> | 149:156823d33999 | 173 | HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); |
<> | 149:156823d33999 | 174 | |
<> | 149:156823d33999 | 175 | /** |
<> | 149:156823d33999 | 176 | * @} |
<> | 149:156823d33999 | 177 | */ |
<> | 149:156823d33999 | 178 | |
<> | 149:156823d33999 | 179 | /** |
<> | 149:156823d33999 | 180 | * @} |
<> | 149:156823d33999 | 181 | */ |
<> | 149:156823d33999 | 182 | |
<> | 149:156823d33999 | 183 | /** |
<> | 149:156823d33999 | 184 | * @} |
<> | 149:156823d33999 | 185 | */ |
<> | 149:156823d33999 | 186 | |
<> | 149:156823d33999 | 187 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
<> | 149:156823d33999 | 188 | |
<> | 149:156823d33999 | 189 | /** |
<> | 149:156823d33999 | 190 | * @} |
<> | 149:156823d33999 | 191 | */ |
<> | 149:156823d33999 | 192 | |
<> | 149:156823d33999 | 193 | #ifdef __cplusplus |
<> | 149:156823d33999 | 194 | } |
<> | 149:156823d33999 | 195 | #endif |
<> | 149:156823d33999 | 196 | |
<> | 149:156823d33999 | 197 | #endif /* __STM32L1xx_HAL_SRAM_H */ |
<> | 149:156823d33999 | 198 | |
<> | 149:156823d33999 | 199 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |