Austin Blackstone / Mbed 2 deprecated murataDemo

demo of the murata wifi chip. This demo tries to connect to an open wifi access point and prints out all the relevant information about the connection. It then scans all wifi access points nearby and reports their information.

Dependencies:   SNICInterface mbed-rtos mbed

Fork of SNIC-xively-jumpstart-demo by muRata

PowerControl/EthernetPowerControl.cpp@16:ed9b9c28f860, 2014-05-30 (annotated)

Committer:
kishino
Date:
Fri May 30 08:32:20 2014 +0000
Revision:
16:ed9b9c28f860
Child:
22:e567f0d4b05d
Xively demo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kishino 16:ed9b9c28f860 1 #include "EthernetPowerControl.h"
kishino 16:ed9b9c28f860 2
kishino 16:ed9b9c28f860 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
kishino 16:ed9b9c28f860 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
kishino 16:ed9b9c28f860 5 unsigned int tout;
kishino 16:ed9b9c28f860 6 /* Hardware MII Management for LPC176x devices. */
kishino 16:ed9b9c28f860 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
kishino 16:ed9b9c28f860 8 LPC_EMAC->MWTD = Value;
kishino 16:ed9b9c28f860 9
kishino 16:ed9b9c28f860 10 /* Wait utill operation completed */
kishino 16:ed9b9c28f860 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
kishino 16:ed9b9c28f860 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
kishino 16:ed9b9c28f860 13 break;
kishino 16:ed9b9c28f860 14 }
kishino 16:ed9b9c28f860 15 }
kishino 16:ed9b9c28f860 16 }
kishino 16:ed9b9c28f860 17
kishino 16:ed9b9c28f860 18 static unsigned short read_PHY (unsigned int PhyReg) {
kishino 16:ed9b9c28f860 19 /* Read a PHY register 'PhyReg'. */
kishino 16:ed9b9c28f860 20 unsigned int tout, val;
kishino 16:ed9b9c28f860 21
kishino 16:ed9b9c28f860 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
kishino 16:ed9b9c28f860 23 LPC_EMAC->MCMD = MCMD_READ;
kishino 16:ed9b9c28f860 24
kishino 16:ed9b9c28f860 25 /* Wait until operation completed */
kishino 16:ed9b9c28f860 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
kishino 16:ed9b9c28f860 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
kishino 16:ed9b9c28f860 28 break;
kishino 16:ed9b9c28f860 29 }
kishino 16:ed9b9c28f860 30 }
kishino 16:ed9b9c28f860 31 LPC_EMAC->MCMD = 0;
kishino 16:ed9b9c28f860 32 val = LPC_EMAC->MRDD;
kishino 16:ed9b9c28f860 33
kishino 16:ed9b9c28f860 34 return (val);
kishino 16:ed9b9c28f860 35 }
kishino 16:ed9b9c28f860 36
kishino 16:ed9b9c28f860 37 void EMAC_Init()
kishino 16:ed9b9c28f860 38 {
kishino 16:ed9b9c28f860 39 unsigned int tout,regv;
kishino 16:ed9b9c28f860 40 /* Power Up the EMAC controller. */
kishino 16:ed9b9c28f860 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
kishino 16:ed9b9c28f860 42
kishino 16:ed9b9c28f860 43 LPC_PINCON->PINSEL2 = 0x50150105;
kishino 16:ed9b9c28f860 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
kishino 16:ed9b9c28f860 45 LPC_PINCON->PINSEL3 |= 0x00000005;
kishino 16:ed9b9c28f860 46
kishino 16:ed9b9c28f860 47 /* Reset all EMAC internal modules. */
kishino 16:ed9b9c28f860 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
kishino 16:ed9b9c28f860 49 MAC1_SIM_RES | MAC1_SOFT_RES;
kishino 16:ed9b9c28f860 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
kishino 16:ed9b9c28f860 51
kishino 16:ed9b9c28f860 52 /* A short delay after reset. */
kishino 16:ed9b9c28f860 53 for (tout = 100; tout; tout--);
kishino 16:ed9b9c28f860 54
kishino 16:ed9b9c28f860 55 /* Initialize MAC control registers. */
kishino 16:ed9b9c28f860 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
kishino 16:ed9b9c28f860 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
kishino 16:ed9b9c28f860 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
kishino 16:ed9b9c28f860 59 LPC_EMAC->CLRT = CLRT_DEF;
kishino 16:ed9b9c28f860 60 LPC_EMAC->IPGR = IPGR_DEF;
kishino 16:ed9b9c28f860 61
kishino 16:ed9b9c28f860 62 /* Enable Reduced MII interface. */
kishino 16:ed9b9c28f860 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
kishino 16:ed9b9c28f860 64
kishino 16:ed9b9c28f860 65 /* Reset Reduced MII Logic. */
kishino 16:ed9b9c28f860 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
kishino 16:ed9b9c28f860 67 for (tout = 100; tout; tout--);
kishino 16:ed9b9c28f860 68 LPC_EMAC->SUPP = 0;
kishino 16:ed9b9c28f860 69
kishino 16:ed9b9c28f860 70 /* Put the DP83848C in reset mode */
kishino 16:ed9b9c28f860 71 write_PHY (PHY_REG_BMCR, 0x8000);
kishino 16:ed9b9c28f860 72
kishino 16:ed9b9c28f860 73 /* Wait for hardware reset to end. */
kishino 16:ed9b9c28f860 74 for (tout = 0; tout < 0x100000; tout++) {
kishino 16:ed9b9c28f860 75 regv = read_PHY (PHY_REG_BMCR);
kishino 16:ed9b9c28f860 76 if (!(regv & 0x8000)) {
kishino 16:ed9b9c28f860 77 /* Reset complete */
kishino 16:ed9b9c28f860 78 break;
kishino 16:ed9b9c28f860 79 }
kishino 16:ed9b9c28f860 80 }
kishino 16:ed9b9c28f860 81 }
kishino 16:ed9b9c28f860 82
kishino 16:ed9b9c28f860 83
kishino 16:ed9b9c28f860 84 void PHY_PowerDown()
kishino 16:ed9b9c28f860 85 {
kishino 16:ed9b9c28f860 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
kishino 16:ed9b9c28f860 87 EMAC_Init(); //init EMAC if it is not already init'd
kishino 16:ed9b9c28f860 88
kishino 16:ed9b9c28f860 89 unsigned int regv;
kishino 16:ed9b9c28f860 90 regv = read_PHY(PHY_REG_BMCR);
kishino 16:ed9b9c28f860 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
kishino 16:ed9b9c28f860 92 regv = read_PHY(PHY_REG_BMCR);
kishino 16:ed9b9c28f860 93
kishino 16:ed9b9c28f860 94 //shouldn't need the EMAC now.
kishino 16:ed9b9c28f860 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
kishino 16:ed9b9c28f860 96
kishino 16:ed9b9c28f860 97 //and turn off the PHY OSC
kishino 16:ed9b9c28f860 98 LPC_GPIO1->FIODIR |= 0x8000000;
kishino 16:ed9b9c28f860 99 LPC_GPIO1->FIOCLR = 0x8000000;
kishino 16:ed9b9c28f860 100 }
kishino 16:ed9b9c28f860 101
kishino 16:ed9b9c28f860 102 void PHY_PowerUp()
kishino 16:ed9b9c28f860 103 {
kishino 16:ed9b9c28f860 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
kishino 16:ed9b9c28f860 105 EMAC_Init(); //init EMAC if it is not already init'd
kishino 16:ed9b9c28f860 106
kishino 16:ed9b9c28f860 107 LPC_GPIO1->FIODIR |= 0x8000000;
kishino 16:ed9b9c28f860 108 LPC_GPIO1->FIOSET = 0x8000000;
kishino 16:ed9b9c28f860 109
kishino 16:ed9b9c28f860 110 //wait for osc to be stable
kishino 16:ed9b9c28f860 111 wait_ms(200);
kishino 16:ed9b9c28f860 112
kishino 16:ed9b9c28f860 113 unsigned int regv;
kishino 16:ed9b9c28f860 114 regv = read_PHY(PHY_REG_BMCR);
kishino 16:ed9b9c28f860 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
kishino 16:ed9b9c28f860 116 regv = read_PHY(PHY_REG_BMCR);
kishino 16:ed9b9c28f860 117 }
kishino 16:ed9b9c28f860 118
kishino 16:ed9b9c28f860 119 void PHY_EnergyDetect_Enable()
kishino 16:ed9b9c28f860 120 {
kishino 16:ed9b9c28f860 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
kishino 16:ed9b9c28f860 122 EMAC_Init(); //init EMAC if it is not already init'd
kishino 16:ed9b9c28f860 123
kishino 16:ed9b9c28f860 124 unsigned int regv;
kishino 16:ed9b9c28f860 125 regv = read_PHY(PHY_REG_EDCR);
kishino 16:ed9b9c28f860 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
kishino 16:ed9b9c28f860 127 regv = read_PHY(PHY_REG_EDCR);
kishino 16:ed9b9c28f860 128 }
kishino 16:ed9b9c28f860 129
kishino 16:ed9b9c28f860 130 void PHY_EnergyDetect_Disable()
kishino 16:ed9b9c28f860 131 {
kishino 16:ed9b9c28f860 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
kishino 16:ed9b9c28f860 133 EMAC_Init(); //init EMAC if it is not already init'd
kishino 16:ed9b9c28f860 134 unsigned int regv;
kishino 16:ed9b9c28f860 135 regv = read_PHY(PHY_REG_EDCR);
kishino 16:ed9b9c28f860 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
kishino 16:ed9b9c28f860 137 regv = read_PHY(PHY_REG_EDCR);
kishino 16:ed9b9c28f860 138 }