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//******************************************************************************
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//*
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//* FULLNAME: Single-Chip Microcontroller Real-Time Operating System
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//*
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//* NICKNAME: scmRTOS
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//*
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//* PROCESSOR: ARM Cortex-M3
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//*
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//* TOOLKIT: EWARM (IAR Systems)
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//*
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//* PURPOSE: Device Definitions
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//*
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//* Version: 3.10
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//*
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//* $Revision: 196 $
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//* $Date:: 2008-06-19 #$
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//*
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//* Copyright (c) 2003-2010, Harry E. Zhurov
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//*
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//* Permission is hereby granted, free of charge, to any person
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//* obtaining a copy of this software and associated documentation
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//* files (the "Software"), to deal in the Software without restriction,
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//* including without limitation the rights to use, copy, modify, merge,
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//* publish, distribute, sublicense, and/or sell copies of the Software,
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//* and to permit persons to whom the Software is furnished to do so,
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//* subject to the following conditions:
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//*
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//* The above copyright notice and this permission notice shall be included
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//* in all copies or substantial portions of the Software.
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//*
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//* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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//* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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//* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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//* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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//* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
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//* THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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//*
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//* =================================================================
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//* See http://scmrtos.sourceforge.net for documentation, latest
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//* information, license and contact details.
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//* =================================================================
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//*
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//******************************************************************************
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//* Ported by Andrey Chuikin, Copyright (c) 2008-2010
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#ifndef DEVICE_H
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#define DEVICE_H
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#include <commdefs.h>
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//------------------------------------------------------------------------------
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// Definitions for some processor registers in order to not include specific
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// header file for various Cortex-M3 processor derivatives.
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#define CPU_ICSR ( ( sfr_dword *) 0xE000ED04 ) // Interrupt Control State Register
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#define CPU_SYSTICKCSR ( ( sfr_dword *) 0xE000E010 ) // SysTick Control and Status Register
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#define CPU_SYSTICKCSR_EINT 0x02 // Bit for enable/disable SysTick interrupt
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#endif /* DEVICE_H */
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Daniel Peter