mbed-dev - mbed library sources. Supersedes mbed-src. Fixed …

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mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents: Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

cmsis/core_cm7.h@167:e84263d55307, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:46:44 2017 +0100
Revision:: 167:e84263d55307
Parent:: 152:9a67f0b066fc

This updates the lib to the mbed lib v 145

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/************************************************************************//
<>	144:ef7eb2e8f9f7	2	* @file core_cm7.h
<>	144:ef7eb2e8f9f7	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
AnnaBridge	167:e84263d55307	4	* @version V5.0.2
AnnaBridge	167:e84263d55307	5	* @date 13. February 2017
<>	144:ef7eb2e8f9f7	6	******************************************************************************/
AnnaBridge	167:e84263d55307	7	/*
AnnaBridge	167:e84263d55307	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	167:e84263d55307	9	*
AnnaBridge	167:e84263d55307	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	167:e84263d55307	11	*
AnnaBridge	167:e84263d55307	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:e84263d55307	13	* not use this file except in compliance with the License.
AnnaBridge	167:e84263d55307	14	* You may obtain a copy of the License at
AnnaBridge	167:e84263d55307	15	*
AnnaBridge	167:e84263d55307	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	167:e84263d55307	17	*
AnnaBridge	167:e84263d55307	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:e84263d55307	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:e84263d55307	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:e84263d55307	21	* See the License for the specific language governing permissions and
AnnaBridge	167:e84263d55307	22	* limitations under the License.
AnnaBridge	167:e84263d55307	23	*/
AnnaBridge	167:e84263d55307	24
AnnaBridge	167:e84263d55307	25	#if defined ( __ICCARM__ )
AnnaBridge	167:e84263d55307	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	167:e84263d55307	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:e84263d55307	28	#pragma clang system_header /* treat file as system include file */
<>	144:ef7eb2e8f9f7	29	#endif
<>	144:ef7eb2e8f9f7	30
<>	144:ef7eb2e8f9f7	31	#ifndef __CORE_CM7_H_GENERIC
<>	144:ef7eb2e8f9f7	32	#define __CORE_CM7_H_GENERIC
<>	144:ef7eb2e8f9f7	33
AnnaBridge	167:e84263d55307	34	#include <stdint.h>
AnnaBridge	167:e84263d55307	35
<>	144:ef7eb2e8f9f7	36	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	37	extern "C" {
<>	144:ef7eb2e8f9f7	38	#endif
<>	144:ef7eb2e8f9f7	39
AnnaBridge	167:e84263d55307	40	/**
AnnaBridge	167:e84263d55307	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<>	144:ef7eb2e8f9f7	42	CMSIS violates the following MISRA-C:2004 rules:
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	\li Required Rule 8.5, object/function definition in header file.<br>
<>	144:ef7eb2e8f9f7	45	Function definitions in header files are used to allow 'inlining'.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<>	144:ef7eb2e8f9f7	48	Unions are used for effective representation of core registers.
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
<>	144:ef7eb2e8f9f7	51	Function-like macros are used to allow more efficient code.
<>	144:ef7eb2e8f9f7	52	*/
<>	144:ef7eb2e8f9f7	53
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	/*******************************************************************************
<>	144:ef7eb2e8f9f7	56	* CMSIS definitions
<>	144:ef7eb2e8f9f7	57	******************************************************************************/
AnnaBridge	167:e84263d55307	58	/**
AnnaBridge	167:e84263d55307	59	\ingroup Cortex_M7
<>	144:ef7eb2e8f9f7	60	@{
<>	144:ef7eb2e8f9f7	61	*/
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	/* CMSIS CM7 definitions */
AnnaBridge	167:e84263d55307	64	#define __CM7_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
AnnaBridge	167:e84263d55307	65	#define __CM7_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
AnnaBridge	167:e84263d55307	66	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	167:e84263d55307	67	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
AnnaBridge	167:e84263d55307	68
AnnaBridge	167:e84263d55307	69	#define __CORTEX_M (7U) /!< Cortex-M Core /
<>	144:ef7eb2e8f9f7	70
<>	144:ef7eb2e8f9f7	71	/** __FPU_USED indicates whether an FPU is used or not.
<>	144:ef7eb2e8f9f7	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<>	144:ef7eb2e8f9f7	73	*/
<>	144:ef7eb2e8f9f7	74	#if defined ( __CC_ARM )
<>	144:ef7eb2e8f9f7	75	#if defined __TARGET_FPU_VFP
AnnaBridge	167:e84263d55307	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	77	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	78	#else
AnnaBridge	167:e84263d55307	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	80	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	81	#endif
AnnaBridge	167:e84263d55307	82	#else
AnnaBridge	167:e84263d55307	83	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	84	#endif
AnnaBridge	167:e84263d55307	85
AnnaBridge	167:e84263d55307	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:e84263d55307	87	#if defined __ARM_PCS_VFP
AnnaBridge	167:e84263d55307	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	89	#define __FPU_USED 1U
<>	144:ef7eb2e8f9f7	90	#else
<>	144:ef7eb2e8f9f7	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	92	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	93	#endif
<>	144:ef7eb2e8f9f7	94	#else
AnnaBridge	167:e84263d55307	95	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	96	#endif
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	#elif defined ( __GNUC__ )
<>	144:ef7eb2e8f9f7	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	167:e84263d55307	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	101	#define __FPU_USED 1U
<>	144:ef7eb2e8f9f7	102	#else
AnnaBridge	167:e84263d55307	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	104	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	105	#endif
<>	144:ef7eb2e8f9f7	106	#else
AnnaBridge	167:e84263d55307	107	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	108	#endif
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	#elif defined ( __ICCARM__ )
<>	144:ef7eb2e8f9f7	111	#if defined __ARMVFP__
AnnaBridge	167:e84263d55307	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	113	#define __FPU_USED 1U
<>	144:ef7eb2e8f9f7	114	#else
AnnaBridge	167:e84263d55307	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	116	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	117	#endif
<>	144:ef7eb2e8f9f7	118	#else
AnnaBridge	167:e84263d55307	119	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	120	#endif
<>	144:ef7eb2e8f9f7	121
AnnaBridge	167:e84263d55307	122	#elif defined ( __TI_ARM__ )
<>	144:ef7eb2e8f9f7	123	#if defined __TI_VFP_SUPPORT__
AnnaBridge	167:e84263d55307	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	125	#define __FPU_USED 1U
<>	144:ef7eb2e8f9f7	126	#else
AnnaBridge	167:e84263d55307	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	128	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	129	#endif
<>	144:ef7eb2e8f9f7	130	#else
AnnaBridge	167:e84263d55307	131	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	132	#endif
<>	144:ef7eb2e8f9f7	133
<>	144:ef7eb2e8f9f7	134	#elif defined ( __TASKING__ )
<>	144:ef7eb2e8f9f7	135	#if defined __FPU_VFP__
AnnaBridge	167:e84263d55307	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	137	#define __FPU_USED 1U
<>	144:ef7eb2e8f9f7	138	#else
<>	144:ef7eb2e8f9f7	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	140	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	141	#endif
<>	144:ef7eb2e8f9f7	142	#else
AnnaBridge	167:e84263d55307	143	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	144	#endif
<>	144:ef7eb2e8f9f7	145
AnnaBridge	167:e84263d55307	146	#elif defined ( __CSMC__ )
AnnaBridge	167:e84263d55307	147	#if ( __CSMC__ & 0x400U)
AnnaBridge	167:e84263d55307	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	149	#define __FPU_USED 1U
<>	144:ef7eb2e8f9f7	150	#else
<>	144:ef7eb2e8f9f7	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	152	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	153	#endif
<>	144:ef7eb2e8f9f7	154	#else
AnnaBridge	167:e84263d55307	155	#define __FPU_USED 0U
<>	144:ef7eb2e8f9f7	156	#endif
AnnaBridge	167:e84263d55307	157
<>	144:ef7eb2e8f9f7	158	#endif
<>	144:ef7eb2e8f9f7	159
AnnaBridge	167:e84263d55307	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	167:e84263d55307	161
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	164	}
<>	144:ef7eb2e8f9f7	165	#endif
<>	144:ef7eb2e8f9f7	166
<>	144:ef7eb2e8f9f7	167	#endif /* __CORE_CM7_H_GENERIC */
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	#ifndef __CMSIS_GENERIC
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	#ifndef __CORE_CM7_H_DEPENDANT
<>	144:ef7eb2e8f9f7	172	#define __CORE_CM7_H_DEPENDANT
<>	144:ef7eb2e8f9f7	173
<>	144:ef7eb2e8f9f7	174	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	175	extern "C" {
<>	144:ef7eb2e8f9f7	176	#endif
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	/* check device defines and use defaults */
<>	144:ef7eb2e8f9f7	179	#if defined __CHECK_DEVICE_DEFINES
<>	144:ef7eb2e8f9f7	180	#ifndef __CM7_REV
AnnaBridge	167:e84263d55307	181	#define __CM7_REV 0x0000U
<>	144:ef7eb2e8f9f7	182	#warning "__CM7_REV not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	183	#endif
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	#ifndef __FPU_PRESENT
AnnaBridge	167:e84263d55307	186	#define __FPU_PRESENT 0U
<>	144:ef7eb2e8f9f7	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	188	#endif
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	#ifndef __MPU_PRESENT
AnnaBridge	167:e84263d55307	191	#define __MPU_PRESENT 0U
<>	144:ef7eb2e8f9f7	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	193	#endif
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	#ifndef __ICACHE_PRESENT
AnnaBridge	167:e84263d55307	196	#define __ICACHE_PRESENT 0U
<>	144:ef7eb2e8f9f7	197	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	198	#endif
<>	144:ef7eb2e8f9f7	199
<>	144:ef7eb2e8f9f7	200	#ifndef __DCACHE_PRESENT
AnnaBridge	167:e84263d55307	201	#define __DCACHE_PRESENT 0U
<>	144:ef7eb2e8f9f7	202	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	203	#endif
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	#ifndef __DTCM_PRESENT
AnnaBridge	167:e84263d55307	206	#define __DTCM_PRESENT 0U
<>	144:ef7eb2e8f9f7	207	#warning "__DTCM_PRESENT not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	208	#endif
<>	144:ef7eb2e8f9f7	209
<>	144:ef7eb2e8f9f7	210	#ifndef __NVIC_PRIO_BITS
AnnaBridge	167:e84263d55307	211	#define __NVIC_PRIO_BITS 3U
<>	144:ef7eb2e8f9f7	212	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	213	#endif
<>	144:ef7eb2e8f9f7	214
<>	144:ef7eb2e8f9f7	215	#ifndef __Vendor_SysTickConfig
AnnaBridge	167:e84263d55307	216	#define __Vendor_SysTickConfig 0U
<>	144:ef7eb2e8f9f7	217	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	218	#endif
<>	144:ef7eb2e8f9f7	219	#endif
<>	144:ef7eb2e8f9f7	220
<>	144:ef7eb2e8f9f7	221	/* IO definitions (access restrictions to peripheral registers) */
<>	144:ef7eb2e8f9f7	222	/**
<>	144:ef7eb2e8f9f7	223	\defgroup CMSIS_glob_defs CMSIS Global Defines
<>	144:ef7eb2e8f9f7	224
<>	144:ef7eb2e8f9f7	225	<strong>IO Type Qualifiers</strong> are used
<>	144:ef7eb2e8f9f7	226	\li to specify the access to peripheral variables.
<>	144:ef7eb2e8f9f7	227	\li for automatic generation of peripheral register debug information.
<>	144:ef7eb2e8f9f7	228	*/
<>	144:ef7eb2e8f9f7	229	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	230	#define __I volatile /!< Defines 'read only' permissions /
<>	144:ef7eb2e8f9f7	231	#else
AnnaBridge	167:e84263d55307	232	#define __I volatile const /!< Defines 'read only' permissions /
<>	144:ef7eb2e8f9f7	233	#endif
AnnaBridge	167:e84263d55307	234	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	167:e84263d55307	235	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	167:e84263d55307	236
AnnaBridge	167:e84263d55307	237	/* following defines should be used for structure members */
AnnaBridge	167:e84263d55307	238	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	167:e84263d55307	239	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	167:e84263d55307	240	#define __IOM volatile /! Defines 'read / write' structure member permissions /
<>	150:02e0a0aed4ec	241
<>	144:ef7eb2e8f9f7	242	/@} end of group Cortex_M7 /
<>	144:ef7eb2e8f9f7	243
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245
<>	144:ef7eb2e8f9f7	246	/*******************************************************************************
<>	144:ef7eb2e8f9f7	247	* Register Abstraction
<>	144:ef7eb2e8f9f7	248	Core Register contain:
<>	144:ef7eb2e8f9f7	249	- Core Register
<>	144:ef7eb2e8f9f7	250	- Core NVIC Register
<>	144:ef7eb2e8f9f7	251	- Core SCB Register
<>	144:ef7eb2e8f9f7	252	- Core SysTick Register
<>	144:ef7eb2e8f9f7	253	- Core Debug Register
<>	144:ef7eb2e8f9f7	254	- Core MPU Register
<>	144:ef7eb2e8f9f7	255	- Core FPU Register
<>	144:ef7eb2e8f9f7	256	******************************************************************************/
AnnaBridge	167:e84263d55307	257	/**
AnnaBridge	167:e84263d55307	258	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	167:e84263d55307	259	\brief Type definitions and defines for Cortex-M processor based devices.
<>	144:ef7eb2e8f9f7	260	*/
<>	144:ef7eb2e8f9f7	261
AnnaBridge	167:e84263d55307	262	/**
AnnaBridge	167:e84263d55307	263	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	264	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	167:e84263d55307	265	\brief Core Register type definitions.
<>	144:ef7eb2e8f9f7	266	@{
<>	144:ef7eb2e8f9f7	267	*/
<>	144:ef7eb2e8f9f7	268
AnnaBridge	167:e84263d55307	269	/**
AnnaBridge	167:e84263d55307	270	\brief Union type to access the Application Program Status Register (APSR).
<>	144:ef7eb2e8f9f7	271	*/
<>	144:ef7eb2e8f9f7	272	typedef union
<>	144:ef7eb2e8f9f7	273	{
<>	144:ef7eb2e8f9f7	274	struct
<>	144:ef7eb2e8f9f7	275	{
AnnaBridge	167:e84263d55307	276	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	167:e84263d55307	277	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	167:e84263d55307	278	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	167:e84263d55307	279	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:e84263d55307	280	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	281	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	282	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	283	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	284	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	285	uint32_t w; /!< Type used for word access /
<>	144:ef7eb2e8f9f7	286	} APSR_Type;
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	/* APSR Register Definitions */
AnnaBridge	167:e84263d55307	289	#define APSR_N_Pos 31U /!< APSR: N Position /
<>	144:ef7eb2e8f9f7	290	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
<>	144:ef7eb2e8f9f7	291
AnnaBridge	167:e84263d55307	292	#define APSR_Z_Pos 30U /!< APSR: Z Position /
<>	144:ef7eb2e8f9f7	293	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
<>	144:ef7eb2e8f9f7	294
AnnaBridge	167:e84263d55307	295	#define APSR_C_Pos 29U /!< APSR: C Position /
<>	144:ef7eb2e8f9f7	296	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
<>	144:ef7eb2e8f9f7	297
AnnaBridge	167:e84263d55307	298	#define APSR_V_Pos 28U /!< APSR: V Position /
<>	144:ef7eb2e8f9f7	299	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
<>	144:ef7eb2e8f9f7	300
AnnaBridge	167:e84263d55307	301	#define APSR_Q_Pos 27U /!< APSR: Q Position /
<>	144:ef7eb2e8f9f7	302	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
<>	144:ef7eb2e8f9f7	303
AnnaBridge	167:e84263d55307	304	#define APSR_GE_Pos 16U /!< APSR: GE Position /
<>	144:ef7eb2e8f9f7	305	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
<>	144:ef7eb2e8f9f7	306
<>	144:ef7eb2e8f9f7	307
AnnaBridge	167:e84263d55307	308	/**
AnnaBridge	167:e84263d55307	309	\brief Union type to access the Interrupt Program Status Register (IPSR).
<>	144:ef7eb2e8f9f7	310	*/
<>	144:ef7eb2e8f9f7	311	typedef union
<>	144:ef7eb2e8f9f7	312	{
<>	144:ef7eb2e8f9f7	313	struct
<>	144:ef7eb2e8f9f7	314	{
AnnaBridge	167:e84263d55307	315	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:e84263d55307	316	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	167:e84263d55307	317	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	318	uint32_t w; /!< Type used for word access /
<>	144:ef7eb2e8f9f7	319	} IPSR_Type;
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	/* IPSR Register Definitions */
AnnaBridge	167:e84263d55307	322	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
<>	144:ef7eb2e8f9f7	323	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325
AnnaBridge	167:e84263d55307	326	/**
AnnaBridge	167:e84263d55307	327	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<>	144:ef7eb2e8f9f7	328	*/
<>	144:ef7eb2e8f9f7	329	typedef union
<>	144:ef7eb2e8f9f7	330	{
<>	144:ef7eb2e8f9f7	331	struct
<>	144:ef7eb2e8f9f7	332	{
AnnaBridge	167:e84263d55307	333	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:e84263d55307	334	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	167:e84263d55307	335	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	167:e84263d55307	336	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	167:e84263d55307	337	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	167:e84263d55307	338	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	167:e84263d55307	339	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	167:e84263d55307	340	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:e84263d55307	341	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	342	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	343	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	344	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	345	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	346	uint32_t w; /!< Type used for word access /
<>	144:ef7eb2e8f9f7	347	} xPSR_Type;
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	/* xPSR Register Definitions */
AnnaBridge	167:e84263d55307	350	#define xPSR_N_Pos 31U /!< xPSR: N Position /
<>	144:ef7eb2e8f9f7	351	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
<>	144:ef7eb2e8f9f7	352
AnnaBridge	167:e84263d55307	353	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
<>	144:ef7eb2e8f9f7	354	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
<>	144:ef7eb2e8f9f7	355
AnnaBridge	167:e84263d55307	356	#define xPSR_C_Pos 29U /!< xPSR: C Position /
<>	144:ef7eb2e8f9f7	357	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
<>	144:ef7eb2e8f9f7	358
AnnaBridge	167:e84263d55307	359	#define xPSR_V_Pos 28U /!< xPSR: V Position /
<>	144:ef7eb2e8f9f7	360	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
<>	144:ef7eb2e8f9f7	361
AnnaBridge	167:e84263d55307	362	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
<>	144:ef7eb2e8f9f7	363	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
<>	144:ef7eb2e8f9f7	364
AnnaBridge	167:e84263d55307	365	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	167:e84263d55307	366	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
AnnaBridge	167:e84263d55307	367
AnnaBridge	167:e84263d55307	368	#define xPSR_T_Pos 24U /!< xPSR: T Position /
<>	144:ef7eb2e8f9f7	369	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
<>	144:ef7eb2e8f9f7	370
AnnaBridge	167:e84263d55307	371	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
<>	144:ef7eb2e8f9f7	372	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
<>	144:ef7eb2e8f9f7	373
AnnaBridge	167:e84263d55307	374	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	167:e84263d55307	375	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	167:e84263d55307	376
AnnaBridge	167:e84263d55307	377	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
<>	144:ef7eb2e8f9f7	378	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
<>	144:ef7eb2e8f9f7	379
<>	144:ef7eb2e8f9f7	380
AnnaBridge	167:e84263d55307	381	/**
AnnaBridge	167:e84263d55307	382	\brief Union type to access the Control Registers (CONTROL).
<>	144:ef7eb2e8f9f7	383	*/
<>	144:ef7eb2e8f9f7	384	typedef union
<>	144:ef7eb2e8f9f7	385	{
<>	144:ef7eb2e8f9f7	386	struct
<>	144:ef7eb2e8f9f7	387	{
<>	144:ef7eb2e8f9f7	388	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	167:e84263d55307	389	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	167:e84263d55307	390	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
AnnaBridge	167:e84263d55307	391	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
AnnaBridge	167:e84263d55307	392	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	393	uint32_t w; /!< Type used for word access /
<>	144:ef7eb2e8f9f7	394	} CONTROL_Type;
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/* CONTROL Register Definitions */
AnnaBridge	167:e84263d55307	397	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
<>	144:ef7eb2e8f9f7	398	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
<>	144:ef7eb2e8f9f7	399
AnnaBridge	167:e84263d55307	400	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
<>	144:ef7eb2e8f9f7	401	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
<>	144:ef7eb2e8f9f7	402
AnnaBridge	167:e84263d55307	403	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
<>	144:ef7eb2e8f9f7	404	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
<>	144:ef7eb2e8f9f7	405
<>	144:ef7eb2e8f9f7	406	/@} end of group CMSIS_CORE /
<>	144:ef7eb2e8f9f7	407
<>	144:ef7eb2e8f9f7	408
AnnaBridge	167:e84263d55307	409	/**
AnnaBridge	167:e84263d55307	410	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	411	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	167:e84263d55307	412	\brief Type definitions for the NVIC Registers
<>	144:ef7eb2e8f9f7	413	@{
<>	144:ef7eb2e8f9f7	414	*/
<>	144:ef7eb2e8f9f7	415
AnnaBridge	167:e84263d55307	416	/**
AnnaBridge	167:e84263d55307	417	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<>	144:ef7eb2e8f9f7	418	*/
<>	144:ef7eb2e8f9f7	419	typedef struct
<>	144:ef7eb2e8f9f7	420	{
AnnaBridge	167:e84263d55307	421	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	167:e84263d55307	422	uint32_t RESERVED0[24U];
AnnaBridge	167:e84263d55307	423	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	167:e84263d55307	424	uint32_t RSERVED1[24U];
AnnaBridge	167:e84263d55307	425	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	167:e84263d55307	426	uint32_t RESERVED2[24U];
AnnaBridge	167:e84263d55307	427	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	167:e84263d55307	428	uint32_t RESERVED3[24U];
AnnaBridge	167:e84263d55307	429	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	167:e84263d55307	430	uint32_t RESERVED4[56U];
AnnaBridge	167:e84263d55307	431	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	167:e84263d55307	432	uint32_t RESERVED5[644U];
AnnaBridge	167:e84263d55307	433	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
<>	144:ef7eb2e8f9f7	434	} NVIC_Type;
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	167:e84263d55307	437	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
<>	144:ef7eb2e8f9f7	438	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	/@} end of group CMSIS_NVIC /
<>	144:ef7eb2e8f9f7	441
<>	144:ef7eb2e8f9f7	442
AnnaBridge	167:e84263d55307	443	/**
AnnaBridge	167:e84263d55307	444	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	445	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	167:e84263d55307	446	\brief Type definitions for the System Control Block Registers
<>	144:ef7eb2e8f9f7	447	@{
<>	144:ef7eb2e8f9f7	448	*/
<>	144:ef7eb2e8f9f7	449
AnnaBridge	167:e84263d55307	450	/**
AnnaBridge	167:e84263d55307	451	\brief Structure type to access the System Control Block (SCB).
<>	144:ef7eb2e8f9f7	452	*/
<>	144:ef7eb2e8f9f7	453	typedef struct
<>	144:ef7eb2e8f9f7	454	{
AnnaBridge	167:e84263d55307	455	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	167:e84263d55307	456	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	167:e84263d55307	457	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	167:e84263d55307	458	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	167:e84263d55307	459	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	167:e84263d55307	460	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	167:e84263d55307	461	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	167:e84263d55307	462	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	167:e84263d55307	463	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	167:e84263d55307	464	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	167:e84263d55307	465	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	167:e84263d55307	466	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	167:e84263d55307	467	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	167:e84263d55307	468	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	167:e84263d55307	469	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	167:e84263d55307	470	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	167:e84263d55307	471	__IM uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	167:e84263d55307	472	__IM uint32_t ID_MFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	167:e84263d55307	473	__IM uint32_t ID_ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	167:e84263d55307	474	uint32_t RESERVED0[1U];
AnnaBridge	167:e84263d55307	475	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
AnnaBridge	167:e84263d55307	476	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
AnnaBridge	167:e84263d55307	477	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
AnnaBridge	167:e84263d55307	478	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
AnnaBridge	167:e84263d55307	479	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	167:e84263d55307	480	uint32_t RESERVED3[93U];
AnnaBridge	167:e84263d55307	481	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
AnnaBridge	167:e84263d55307	482	uint32_t RESERVED4[15U];
AnnaBridge	167:e84263d55307	483	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
AnnaBridge	167:e84263d55307	484	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
AnnaBridge	167:e84263d55307	485	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
AnnaBridge	167:e84263d55307	486	uint32_t RESERVED5[1U];
AnnaBridge	167:e84263d55307	487	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
AnnaBridge	167:e84263d55307	488	uint32_t RESERVED6[1U];
AnnaBridge	167:e84263d55307	489	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
AnnaBridge	167:e84263d55307	490	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
AnnaBridge	167:e84263d55307	491	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
AnnaBridge	167:e84263d55307	492	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
AnnaBridge	167:e84263d55307	493	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
AnnaBridge	167:e84263d55307	494	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
AnnaBridge	167:e84263d55307	495	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
AnnaBridge	167:e84263d55307	496	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
AnnaBridge	167:e84263d55307	497	uint32_t RESERVED7[6U];
AnnaBridge	167:e84263d55307	498	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
AnnaBridge	167:e84263d55307	499	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
AnnaBridge	167:e84263d55307	500	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
AnnaBridge	167:e84263d55307	501	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
AnnaBridge	167:e84263d55307	502	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
AnnaBridge	167:e84263d55307	503	uint32_t RESERVED8[1U];
AnnaBridge	167:e84263d55307	504	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
<>	144:ef7eb2e8f9f7	505	} SCB_Type;
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	/* SCB CPUID Register Definitions */
AnnaBridge	167:e84263d55307	508	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
<>	144:ef7eb2e8f9f7	509	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
<>	144:ef7eb2e8f9f7	510
AnnaBridge	167:e84263d55307	511	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
<>	144:ef7eb2e8f9f7	512	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
<>	144:ef7eb2e8f9f7	513
AnnaBridge	167:e84263d55307	514	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
<>	144:ef7eb2e8f9f7	515	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
<>	144:ef7eb2e8f9f7	516
AnnaBridge	167:e84263d55307	517	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
<>	144:ef7eb2e8f9f7	518	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
<>	144:ef7eb2e8f9f7	519
AnnaBridge	167:e84263d55307	520	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
<>	144:ef7eb2e8f9f7	521	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	167:e84263d55307	524	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
<>	144:ef7eb2e8f9f7	525	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
<>	144:ef7eb2e8f9f7	526
AnnaBridge	167:e84263d55307	527	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
<>	144:ef7eb2e8f9f7	528	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
<>	144:ef7eb2e8f9f7	529
AnnaBridge	167:e84263d55307	530	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
<>	144:ef7eb2e8f9f7	531	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
<>	144:ef7eb2e8f9f7	532
AnnaBridge	167:e84263d55307	533	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
<>	144:ef7eb2e8f9f7	534	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
<>	144:ef7eb2e8f9f7	535
AnnaBridge	167:e84263d55307	536	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
<>	144:ef7eb2e8f9f7	537	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
<>	144:ef7eb2e8f9f7	538
AnnaBridge	167:e84263d55307	539	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
<>	144:ef7eb2e8f9f7	540	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
<>	144:ef7eb2e8f9f7	541
AnnaBridge	167:e84263d55307	542	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
<>	144:ef7eb2e8f9f7	543	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
<>	144:ef7eb2e8f9f7	544
AnnaBridge	167:e84263d55307	545	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
<>	144:ef7eb2e8f9f7	546	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
<>	144:ef7eb2e8f9f7	547
AnnaBridge	167:e84263d55307	548	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
<>	144:ef7eb2e8f9f7	549	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
<>	144:ef7eb2e8f9f7	550
AnnaBridge	167:e84263d55307	551	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
<>	144:ef7eb2e8f9f7	552	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
<>	144:ef7eb2e8f9f7	553
<>	144:ef7eb2e8f9f7	554	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	167:e84263d55307	555	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
<>	144:ef7eb2e8f9f7	556	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	167:e84263d55307	559	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
<>	144:ef7eb2e8f9f7	560	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
<>	144:ef7eb2e8f9f7	561
AnnaBridge	167:e84263d55307	562	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
<>	144:ef7eb2e8f9f7	563	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
<>	144:ef7eb2e8f9f7	564
AnnaBridge	167:e84263d55307	565	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
<>	144:ef7eb2e8f9f7	566	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
<>	144:ef7eb2e8f9f7	567
AnnaBridge	167:e84263d55307	568	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
<>	144:ef7eb2e8f9f7	569	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
<>	144:ef7eb2e8f9f7	570
AnnaBridge	167:e84263d55307	571	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
<>	144:ef7eb2e8f9f7	572	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
<>	144:ef7eb2e8f9f7	573
AnnaBridge	167:e84263d55307	574	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
<>	144:ef7eb2e8f9f7	575	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
<>	144:ef7eb2e8f9f7	576
AnnaBridge	167:e84263d55307	577	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
<>	144:ef7eb2e8f9f7	578	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
<>	144:ef7eb2e8f9f7	579
<>	144:ef7eb2e8f9f7	580	/* SCB System Control Register Definitions */
AnnaBridge	167:e84263d55307	581	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
<>	144:ef7eb2e8f9f7	582	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
<>	144:ef7eb2e8f9f7	583
AnnaBridge	167:e84263d55307	584	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
<>	144:ef7eb2e8f9f7	585	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
<>	144:ef7eb2e8f9f7	586
AnnaBridge	167:e84263d55307	587	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
<>	144:ef7eb2e8f9f7	588	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
<>	144:ef7eb2e8f9f7	589
<>	144:ef7eb2e8f9f7	590	/* SCB Configuration Control Register Definitions */
AnnaBridge	167:e84263d55307	591	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: Branch prediction enable bit Position /
<>	144:ef7eb2e8f9f7	592	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
<>	144:ef7eb2e8f9f7	593
AnnaBridge	167:e84263d55307	594	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: Instruction cache enable bit Position /
<>	144:ef7eb2e8f9f7	595	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
<>	144:ef7eb2e8f9f7	596
AnnaBridge	167:e84263d55307	597	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: Cache enable bit Position /
<>	144:ef7eb2e8f9f7	598	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
<>	144:ef7eb2e8f9f7	599
AnnaBridge	167:e84263d55307	600	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
<>	144:ef7eb2e8f9f7	601	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
<>	144:ef7eb2e8f9f7	602
AnnaBridge	167:e84263d55307	603	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
<>	144:ef7eb2e8f9f7	604	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
<>	144:ef7eb2e8f9f7	605
AnnaBridge	167:e84263d55307	606	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
<>	144:ef7eb2e8f9f7	607	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
<>	144:ef7eb2e8f9f7	608
AnnaBridge	167:e84263d55307	609	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
<>	144:ef7eb2e8f9f7	610	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
<>	144:ef7eb2e8f9f7	611
AnnaBridge	167:e84263d55307	612	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
<>	144:ef7eb2e8f9f7	613	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
<>	144:ef7eb2e8f9f7	614
AnnaBridge	167:e84263d55307	615	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
<>	144:ef7eb2e8f9f7	616	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
<>	144:ef7eb2e8f9f7	617
<>	144:ef7eb2e8f9f7	618	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	167:e84263d55307	619	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
<>	144:ef7eb2e8f9f7	620	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
<>	144:ef7eb2e8f9f7	621
AnnaBridge	167:e84263d55307	622	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
<>	144:ef7eb2e8f9f7	623	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
<>	144:ef7eb2e8f9f7	624
AnnaBridge	167:e84263d55307	625	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
<>	144:ef7eb2e8f9f7	626	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
<>	144:ef7eb2e8f9f7	627
AnnaBridge	167:e84263d55307	628	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
<>	144:ef7eb2e8f9f7	629	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
<>	144:ef7eb2e8f9f7	630
AnnaBridge	167:e84263d55307	631	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
<>	144:ef7eb2e8f9f7	632	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
<>	144:ef7eb2e8f9f7	633
AnnaBridge	167:e84263d55307	634	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
<>	144:ef7eb2e8f9f7	635	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
<>	144:ef7eb2e8f9f7	636
AnnaBridge	167:e84263d55307	637	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
<>	144:ef7eb2e8f9f7	638	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
<>	144:ef7eb2e8f9f7	639
AnnaBridge	167:e84263d55307	640	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
<>	144:ef7eb2e8f9f7	641	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
<>	144:ef7eb2e8f9f7	642
AnnaBridge	167:e84263d55307	643	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
<>	144:ef7eb2e8f9f7	644	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
<>	144:ef7eb2e8f9f7	645
AnnaBridge	167:e84263d55307	646	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
<>	144:ef7eb2e8f9f7	647	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
<>	144:ef7eb2e8f9f7	648
AnnaBridge	167:e84263d55307	649	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
<>	144:ef7eb2e8f9f7	650	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
<>	144:ef7eb2e8f9f7	651
AnnaBridge	167:e84263d55307	652	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
<>	144:ef7eb2e8f9f7	653	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
<>	144:ef7eb2e8f9f7	654
AnnaBridge	167:e84263d55307	655	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
<>	144:ef7eb2e8f9f7	656	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
<>	144:ef7eb2e8f9f7	657
AnnaBridge	167:e84263d55307	658	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
<>	144:ef7eb2e8f9f7	659	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
<>	144:ef7eb2e8f9f7	660
AnnaBridge	167:e84263d55307	661	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	662	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
<>	144:ef7eb2e8f9f7	663	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
<>	144:ef7eb2e8f9f7	664
AnnaBridge	167:e84263d55307	665	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
<>	144:ef7eb2e8f9f7	666	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
<>	144:ef7eb2e8f9f7	667
AnnaBridge	167:e84263d55307	668	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
<>	144:ef7eb2e8f9f7	669	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
<>	144:ef7eb2e8f9f7	670
AnnaBridge	167:e84263d55307	671	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	672	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	167:e84263d55307	673	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	167:e84263d55307	674
AnnaBridge	167:e84263d55307	675	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	167:e84263d55307	676	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	167:e84263d55307	677
AnnaBridge	167:e84263d55307	678	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	167:e84263d55307	679	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	167:e84263d55307	680
AnnaBridge	167:e84263d55307	681	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	167:e84263d55307	682	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	167:e84263d55307	683
AnnaBridge	167:e84263d55307	684	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	167:e84263d55307	685	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	167:e84263d55307	686
AnnaBridge	167:e84263d55307	687	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	167:e84263d55307	688	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	167:e84263d55307	689
AnnaBridge	167:e84263d55307	690	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	691	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	167:e84263d55307	692	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	167:e84263d55307	693
AnnaBridge	167:e84263d55307	694	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	167:e84263d55307	695	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	167:e84263d55307	696
AnnaBridge	167:e84263d55307	697	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	167:e84263d55307	698	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	167:e84263d55307	699
AnnaBridge	167:e84263d55307	700	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	167:e84263d55307	701	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	167:e84263d55307	702
AnnaBridge	167:e84263d55307	703	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	167:e84263d55307	704	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	167:e84263d55307	705
AnnaBridge	167:e84263d55307	706	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	167:e84263d55307	707	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	167:e84263d55307	708
AnnaBridge	167:e84263d55307	709	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	167:e84263d55307	710	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	167:e84263d55307	711
AnnaBridge	167:e84263d55307	712	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	713	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	167:e84263d55307	714	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	167:e84263d55307	715
AnnaBridge	167:e84263d55307	716	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	167:e84263d55307	717	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	167:e84263d55307	718
AnnaBridge	167:e84263d55307	719	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	167:e84263d55307	720	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	167:e84263d55307	721
AnnaBridge	167:e84263d55307	722	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	167:e84263d55307	723	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	167:e84263d55307	724
AnnaBridge	167:e84263d55307	725	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	167:e84263d55307	726	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	167:e84263d55307	727
AnnaBridge	167:e84263d55307	728	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	167:e84263d55307	729	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	167:e84263d55307	730
AnnaBridge	167:e84263d55307	731	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	732	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
<>	144:ef7eb2e8f9f7	733	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
<>	144:ef7eb2e8f9f7	734
AnnaBridge	167:e84263d55307	735	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
<>	144:ef7eb2e8f9f7	736	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
<>	144:ef7eb2e8f9f7	737
AnnaBridge	167:e84263d55307	738	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
<>	144:ef7eb2e8f9f7	739	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	742	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
<>	144:ef7eb2e8f9f7	743	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
<>	144:ef7eb2e8f9f7	744
AnnaBridge	167:e84263d55307	745	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
<>	144:ef7eb2e8f9f7	746	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
<>	144:ef7eb2e8f9f7	747
AnnaBridge	167:e84263d55307	748	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
<>	144:ef7eb2e8f9f7	749	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
<>	144:ef7eb2e8f9f7	750
AnnaBridge	167:e84263d55307	751	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
<>	144:ef7eb2e8f9f7	752	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
<>	144:ef7eb2e8f9f7	753
AnnaBridge	167:e84263d55307	754	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
<>	144:ef7eb2e8f9f7	755	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
<>	144:ef7eb2e8f9f7	756
AnnaBridge	167:e84263d55307	757	/* SCB Cache Level ID Register Definitions */
AnnaBridge	167:e84263d55307	758	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
<>	144:ef7eb2e8f9f7	759	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
<>	144:ef7eb2e8f9f7	760
AnnaBridge	167:e84263d55307	761	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
AnnaBridge	167:e84263d55307	762	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
AnnaBridge	167:e84263d55307	763
AnnaBridge	167:e84263d55307	764	/* SCB Cache Type Register Definitions */
AnnaBridge	167:e84263d55307	765	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
<>	144:ef7eb2e8f9f7	766	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
<>	144:ef7eb2e8f9f7	767
AnnaBridge	167:e84263d55307	768	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
<>	144:ef7eb2e8f9f7	769	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
<>	144:ef7eb2e8f9f7	770
AnnaBridge	167:e84263d55307	771	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
<>	144:ef7eb2e8f9f7	772	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
<>	144:ef7eb2e8f9f7	773
AnnaBridge	167:e84263d55307	774	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
<>	144:ef7eb2e8f9f7	775	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
<>	144:ef7eb2e8f9f7	776
AnnaBridge	167:e84263d55307	777	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
<>	144:ef7eb2e8f9f7	778	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
<>	144:ef7eb2e8f9f7	779
AnnaBridge	167:e84263d55307	780	/* SCB Cache Size ID Register Definitions */
AnnaBridge	167:e84263d55307	781	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
AnnaBridge	167:e84263d55307	782	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
AnnaBridge	167:e84263d55307	783
AnnaBridge	167:e84263d55307	784	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
AnnaBridge	167:e84263d55307	785	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
AnnaBridge	167:e84263d55307	786
AnnaBridge	167:e84263d55307	787	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
AnnaBridge	167:e84263d55307	788	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
AnnaBridge	167:e84263d55307	789
AnnaBridge	167:e84263d55307	790	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
AnnaBridge	167:e84263d55307	791	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
AnnaBridge	167:e84263d55307	792
AnnaBridge	167:e84263d55307	793	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
<>	144:ef7eb2e8f9f7	794	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
<>	144:ef7eb2e8f9f7	795
AnnaBridge	167:e84263d55307	796	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
<>	144:ef7eb2e8f9f7	797	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
<>	144:ef7eb2e8f9f7	798
AnnaBridge	167:e84263d55307	799	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
<>	144:ef7eb2e8f9f7	800	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
<>	144:ef7eb2e8f9f7	801
AnnaBridge	167:e84263d55307	802	/* SCB Cache Size Selection Register Definitions */
AnnaBridge	167:e84263d55307	803	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
<>	144:ef7eb2e8f9f7	804	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
<>	144:ef7eb2e8f9f7	805
AnnaBridge	167:e84263d55307	806	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
<>	144:ef7eb2e8f9f7	807	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
<>	144:ef7eb2e8f9f7	808
AnnaBridge	167:e84263d55307	809	/* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge	167:e84263d55307	810	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
<>	144:ef7eb2e8f9f7	811	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
<>	144:ef7eb2e8f9f7	812
AnnaBridge	167:e84263d55307	813	/* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge	167:e84263d55307	814	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
AnnaBridge	167:e84263d55307	815	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
AnnaBridge	167:e84263d55307	816
AnnaBridge	167:e84263d55307	817	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
AnnaBridge	167:e84263d55307	818	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
AnnaBridge	167:e84263d55307	819
AnnaBridge	167:e84263d55307	820	/* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge	167:e84263d55307	821	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
AnnaBridge	167:e84263d55307	822	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
AnnaBridge	167:e84263d55307	823
AnnaBridge	167:e84263d55307	824	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
AnnaBridge	167:e84263d55307	825	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
AnnaBridge	167:e84263d55307	826
AnnaBridge	167:e84263d55307	827	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge	167:e84263d55307	828	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
AnnaBridge	167:e84263d55307	829	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
AnnaBridge	167:e84263d55307	830
AnnaBridge	167:e84263d55307	831	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
AnnaBridge	167:e84263d55307	832	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
AnnaBridge	167:e84263d55307	833
AnnaBridge	167:e84263d55307	834	/* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	167:e84263d55307	835	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
<>	144:ef7eb2e8f9f7	836	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
<>	144:ef7eb2e8f9f7	837
AnnaBridge	167:e84263d55307	838	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
<>	144:ef7eb2e8f9f7	839	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
<>	144:ef7eb2e8f9f7	840
AnnaBridge	167:e84263d55307	841	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
<>	144:ef7eb2e8f9f7	842	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
<>	144:ef7eb2e8f9f7	843
AnnaBridge	167:e84263d55307	844	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
<>	144:ef7eb2e8f9f7	845	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
<>	144:ef7eb2e8f9f7	846
AnnaBridge	167:e84263d55307	847	/* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	167:e84263d55307	848	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
<>	144:ef7eb2e8f9f7	849	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
<>	144:ef7eb2e8f9f7	850
AnnaBridge	167:e84263d55307	851	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
<>	144:ef7eb2e8f9f7	852	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
<>	144:ef7eb2e8f9f7	853
AnnaBridge	167:e84263d55307	854	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
<>	144:ef7eb2e8f9f7	855	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
<>	144:ef7eb2e8f9f7	856
AnnaBridge	167:e84263d55307	857	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
<>	144:ef7eb2e8f9f7	858	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
<>	144:ef7eb2e8f9f7	859
AnnaBridge	167:e84263d55307	860	/* AHBP Control Register Definitions */
AnnaBridge	167:e84263d55307	861	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
<>	144:ef7eb2e8f9f7	862	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
<>	144:ef7eb2e8f9f7	863
AnnaBridge	167:e84263d55307	864	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
<>	144:ef7eb2e8f9f7	865	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
<>	144:ef7eb2e8f9f7	866
AnnaBridge	167:e84263d55307	867	/* L1 Cache Control Register Definitions */
AnnaBridge	167:e84263d55307	868	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
<>	144:ef7eb2e8f9f7	869	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
<>	144:ef7eb2e8f9f7	870
AnnaBridge	167:e84263d55307	871	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
<>	144:ef7eb2e8f9f7	872	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
<>	144:ef7eb2e8f9f7	873
AnnaBridge	167:e84263d55307	874	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
<>	144:ef7eb2e8f9f7	875	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
<>	144:ef7eb2e8f9f7	876
AnnaBridge	167:e84263d55307	877	/* AHBS Control Register Definitions */
AnnaBridge	167:e84263d55307	878	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
<>	144:ef7eb2e8f9f7	879	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
<>	144:ef7eb2e8f9f7	880
AnnaBridge	167:e84263d55307	881	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
<>	144:ef7eb2e8f9f7	882	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
<>	144:ef7eb2e8f9f7	883
AnnaBridge	167:e84263d55307	884	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
<>	144:ef7eb2e8f9f7	885	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
<>	144:ef7eb2e8f9f7	886
AnnaBridge	167:e84263d55307	887	/* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	888	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
<>	144:ef7eb2e8f9f7	889	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
<>	144:ef7eb2e8f9f7	890
AnnaBridge	167:e84263d55307	891	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
<>	144:ef7eb2e8f9f7	892	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
<>	144:ef7eb2e8f9f7	893
AnnaBridge	167:e84263d55307	894	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
<>	144:ef7eb2e8f9f7	895	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
<>	144:ef7eb2e8f9f7	896
AnnaBridge	167:e84263d55307	897	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
<>	144:ef7eb2e8f9f7	898	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
<>	144:ef7eb2e8f9f7	899
AnnaBridge	167:e84263d55307	900	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
<>	144:ef7eb2e8f9f7	901	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
<>	144:ef7eb2e8f9f7	902
AnnaBridge	167:e84263d55307	903	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
<>	144:ef7eb2e8f9f7	904	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/@} end of group CMSIS_SCB /
<>	144:ef7eb2e8f9f7	907
<>	144:ef7eb2e8f9f7	908
AnnaBridge	167:e84263d55307	909	/**
AnnaBridge	167:e84263d55307	910	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	911	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	167:e84263d55307	912	\brief Type definitions for the System Control and ID Register not in the SCB
<>	144:ef7eb2e8f9f7	913	@{
<>	144:ef7eb2e8f9f7	914	*/
<>	144:ef7eb2e8f9f7	915
AnnaBridge	167:e84263d55307	916	/**
AnnaBridge	167:e84263d55307	917	\brief Structure type to access the System Control and ID Register not in the SCB.
<>	144:ef7eb2e8f9f7	918	*/
<>	144:ef7eb2e8f9f7	919	typedef struct
<>	144:ef7eb2e8f9f7	920	{
AnnaBridge	167:e84263d55307	921	uint32_t RESERVED0[1U];
AnnaBridge	167:e84263d55307	922	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	167:e84263d55307	923	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
<>	144:ef7eb2e8f9f7	924	} SCnSCB_Type;
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	/* Interrupt Controller Type Register Definitions */
AnnaBridge	167:e84263d55307	927	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
<>	144:ef7eb2e8f9f7	928	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
<>	144:ef7eb2e8f9f7	929
<>	144:ef7eb2e8f9f7	930	/* Auxiliary Control Register Definitions */
AnnaBridge	167:e84263d55307	931	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /!< ACTLR: DISITMATBFLUSH Position /
<>	144:ef7eb2e8f9f7	932	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
<>	144:ef7eb2e8f9f7	933
AnnaBridge	167:e84263d55307	934	#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /!< ACTLR: DISRAMODE Position /
<>	144:ef7eb2e8f9f7	935	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
<>	144:ef7eb2e8f9f7	936
AnnaBridge	167:e84263d55307	937	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /!< ACTLR: FPEXCODIS Position /
<>	144:ef7eb2e8f9f7	938	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
<>	144:ef7eb2e8f9f7	939
AnnaBridge	167:e84263d55307	940	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
<>	144:ef7eb2e8f9f7	941	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
<>	144:ef7eb2e8f9f7	942
AnnaBridge	167:e84263d55307	943	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
<>	144:ef7eb2e8f9f7	944	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
<>	144:ef7eb2e8f9f7	945
<>	144:ef7eb2e8f9f7	946	/@} end of group CMSIS_SCnotSCB /
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948
AnnaBridge	167:e84263d55307	949	/**
AnnaBridge	167:e84263d55307	950	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	951	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	167:e84263d55307	952	\brief Type definitions for the System Timer Registers.
<>	144:ef7eb2e8f9f7	953	@{
<>	144:ef7eb2e8f9f7	954	*/
<>	144:ef7eb2e8f9f7	955
AnnaBridge	167:e84263d55307	956	/**
AnnaBridge	167:e84263d55307	957	\brief Structure type to access the System Timer (SysTick).
<>	144:ef7eb2e8f9f7	958	*/
<>	144:ef7eb2e8f9f7	959	typedef struct
<>	144:ef7eb2e8f9f7	960	{
AnnaBridge	167:e84263d55307	961	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	167:e84263d55307	962	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	167:e84263d55307	963	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	167:e84263d55307	964	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
<>	144:ef7eb2e8f9f7	965	} SysTick_Type;
<>	144:ef7eb2e8f9f7	966
<>	144:ef7eb2e8f9f7	967	/* SysTick Control / Status Register Definitions */
AnnaBridge	167:e84263d55307	968	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
<>	144:ef7eb2e8f9f7	969	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
<>	144:ef7eb2e8f9f7	970
AnnaBridge	167:e84263d55307	971	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
<>	144:ef7eb2e8f9f7	972	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
<>	144:ef7eb2e8f9f7	973
AnnaBridge	167:e84263d55307	974	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
<>	144:ef7eb2e8f9f7	975	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
<>	144:ef7eb2e8f9f7	976
AnnaBridge	167:e84263d55307	977	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
<>	144:ef7eb2e8f9f7	978	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	/* SysTick Reload Register Definitions */
AnnaBridge	167:e84263d55307	981	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
<>	144:ef7eb2e8f9f7	982	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
<>	144:ef7eb2e8f9f7	983
<>	144:ef7eb2e8f9f7	984	/* SysTick Current Register Definitions */
AnnaBridge	167:e84263d55307	985	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
<>	144:ef7eb2e8f9f7	986	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	/* SysTick Calibration Register Definitions */
AnnaBridge	167:e84263d55307	989	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
<>	144:ef7eb2e8f9f7	990	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
<>	144:ef7eb2e8f9f7	991
AnnaBridge	167:e84263d55307	992	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
<>	144:ef7eb2e8f9f7	993	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
<>	144:ef7eb2e8f9f7	994
AnnaBridge	167:e84263d55307	995	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
<>	144:ef7eb2e8f9f7	996	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	/@} end of group CMSIS_SysTick /
<>	144:ef7eb2e8f9f7	999
<>	144:ef7eb2e8f9f7	1000
AnnaBridge	167:e84263d55307	1001	/**
AnnaBridge	167:e84263d55307	1002	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1003	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	167:e84263d55307	1004	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<>	144:ef7eb2e8f9f7	1005	@{
<>	144:ef7eb2e8f9f7	1006	*/
<>	144:ef7eb2e8f9f7	1007
AnnaBridge	167:e84263d55307	1008	/**
AnnaBridge	167:e84263d55307	1009	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<>	144:ef7eb2e8f9f7	1010	*/
<>	144:ef7eb2e8f9f7	1011	typedef struct
<>	144:ef7eb2e8f9f7	1012	{
AnnaBridge	167:e84263d55307	1013	__OM union
<>	144:ef7eb2e8f9f7	1014	{
AnnaBridge	167:e84263d55307	1015	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	167:e84263d55307	1016	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	167:e84263d55307	1017	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	167:e84263d55307	1018	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	167:e84263d55307	1019	uint32_t RESERVED0[864U];
AnnaBridge	167:e84263d55307	1020	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	167:e84263d55307	1021	uint32_t RESERVED1[15U];
AnnaBridge	167:e84263d55307	1022	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	167:e84263d55307	1023	uint32_t RESERVED2[15U];
AnnaBridge	167:e84263d55307	1024	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	167:e84263d55307	1025	uint32_t RESERVED3[29U];
AnnaBridge	167:e84263d55307	1026	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	167:e84263d55307	1027	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	167:e84263d55307	1028	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	167:e84263d55307	1029	uint32_t RESERVED4[43U];
AnnaBridge	167:e84263d55307	1030	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	167:e84263d55307	1031	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	167:e84263d55307	1032	uint32_t RESERVED5[6U];
AnnaBridge	167:e84263d55307	1033	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	167:e84263d55307	1034	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	167:e84263d55307	1035	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	167:e84263d55307	1036	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	167:e84263d55307	1037	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	167:e84263d55307	1038	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	167:e84263d55307	1039	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	167:e84263d55307	1040	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	167:e84263d55307	1041	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	167:e84263d55307	1042	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	167:e84263d55307	1043	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	167:e84263d55307	1044	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
<>	144:ef7eb2e8f9f7	1045	} ITM_Type;
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/* ITM Trace Privilege Register Definitions */
AnnaBridge	167:e84263d55307	1048	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
<>	144:ef7eb2e8f9f7	1049	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	/* ITM Trace Control Register Definitions */
AnnaBridge	167:e84263d55307	1052	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
<>	144:ef7eb2e8f9f7	1053	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
<>	144:ef7eb2e8f9f7	1054
AnnaBridge	167:e84263d55307	1055	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
<>	144:ef7eb2e8f9f7	1056	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
<>	144:ef7eb2e8f9f7	1057
AnnaBridge	167:e84263d55307	1058	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
<>	144:ef7eb2e8f9f7	1059	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
<>	144:ef7eb2e8f9f7	1060
AnnaBridge	167:e84263d55307	1061	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
<>	144:ef7eb2e8f9f7	1062	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
<>	144:ef7eb2e8f9f7	1063
AnnaBridge	167:e84263d55307	1064	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
<>	144:ef7eb2e8f9f7	1065	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
<>	144:ef7eb2e8f9f7	1066
AnnaBridge	167:e84263d55307	1067	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
<>	144:ef7eb2e8f9f7	1068	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
<>	144:ef7eb2e8f9f7	1069
AnnaBridge	167:e84263d55307	1070	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
<>	144:ef7eb2e8f9f7	1071	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
<>	144:ef7eb2e8f9f7	1072
AnnaBridge	167:e84263d55307	1073	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
<>	144:ef7eb2e8f9f7	1074	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
<>	144:ef7eb2e8f9f7	1075
AnnaBridge	167:e84263d55307	1076	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
<>	144:ef7eb2e8f9f7	1077	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
<>	144:ef7eb2e8f9f7	1078
<>	144:ef7eb2e8f9f7	1079	/* ITM Integration Write Register Definitions */
AnnaBridge	167:e84263d55307	1080	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
<>	144:ef7eb2e8f9f7	1081	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
<>	144:ef7eb2e8f9f7	1082
<>	144:ef7eb2e8f9f7	1083	/* ITM Integration Read Register Definitions */
AnnaBridge	167:e84263d55307	1084	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
<>	144:ef7eb2e8f9f7	1085	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
<>	144:ef7eb2e8f9f7	1086
<>	144:ef7eb2e8f9f7	1087	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	167:e84263d55307	1088	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
<>	144:ef7eb2e8f9f7	1089	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	/* ITM Lock Status Register Definitions */
AnnaBridge	167:e84263d55307	1092	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
<>	144:ef7eb2e8f9f7	1093	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
<>	144:ef7eb2e8f9f7	1094
AnnaBridge	167:e84263d55307	1095	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
<>	144:ef7eb2e8f9f7	1096	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
<>	144:ef7eb2e8f9f7	1097
AnnaBridge	167:e84263d55307	1098	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
<>	144:ef7eb2e8f9f7	1099	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
<>	144:ef7eb2e8f9f7	1100
<>	144:ef7eb2e8f9f7	1101	/@}/ /* end of group CMSIS_ITM */
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103
AnnaBridge	167:e84263d55307	1104	/**
AnnaBridge	167:e84263d55307	1105	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1106	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	167:e84263d55307	1107	\brief Type definitions for the Data Watchpoint and Trace (DWT)
<>	144:ef7eb2e8f9f7	1108	@{
<>	144:ef7eb2e8f9f7	1109	*/
<>	144:ef7eb2e8f9f7	1110
AnnaBridge	167:e84263d55307	1111	/**
AnnaBridge	167:e84263d55307	1112	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<>	144:ef7eb2e8f9f7	1113	*/
<>	144:ef7eb2e8f9f7	1114	typedef struct
<>	144:ef7eb2e8f9f7	1115	{
AnnaBridge	167:e84263d55307	1116	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	167:e84263d55307	1117	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	167:e84263d55307	1118	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	167:e84263d55307	1119	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	167:e84263d55307	1120	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	167:e84263d55307	1121	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	167:e84263d55307	1122	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	167:e84263d55307	1123	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	167:e84263d55307	1124	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	167:e84263d55307	1125	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	167:e84263d55307	1126	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	167:e84263d55307	1127	uint32_t RESERVED0[1U];
AnnaBridge	167:e84263d55307	1128	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	167:e84263d55307	1129	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	167:e84263d55307	1130	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	167:e84263d55307	1131	uint32_t RESERVED1[1U];
AnnaBridge	167:e84263d55307	1132	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	167:e84263d55307	1133	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	167:e84263d55307	1134	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	167:e84263d55307	1135	uint32_t RESERVED2[1U];
AnnaBridge	167:e84263d55307	1136	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	167:e84263d55307	1137	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	167:e84263d55307	1138	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	167:e84263d55307	1139	uint32_t RESERVED3[981U];
AnnaBridge	167:e84263d55307	1140	__OM uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
AnnaBridge	167:e84263d55307	1141	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
<>	144:ef7eb2e8f9f7	1142	} DWT_Type;
<>	144:ef7eb2e8f9f7	1143
<>	144:ef7eb2e8f9f7	1144	/* DWT Control Register Definitions */
AnnaBridge	167:e84263d55307	1145	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
<>	144:ef7eb2e8f9f7	1146	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
<>	144:ef7eb2e8f9f7	1147
AnnaBridge	167:e84263d55307	1148	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
<>	144:ef7eb2e8f9f7	1149	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
<>	144:ef7eb2e8f9f7	1150
AnnaBridge	167:e84263d55307	1151	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
<>	144:ef7eb2e8f9f7	1152	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
<>	144:ef7eb2e8f9f7	1153
AnnaBridge	167:e84263d55307	1154	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
<>	144:ef7eb2e8f9f7	1155	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
<>	144:ef7eb2e8f9f7	1156
AnnaBridge	167:e84263d55307	1157	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
<>	144:ef7eb2e8f9f7	1158	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
<>	144:ef7eb2e8f9f7	1159
AnnaBridge	167:e84263d55307	1160	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
<>	144:ef7eb2e8f9f7	1161	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
<>	144:ef7eb2e8f9f7	1162
AnnaBridge	167:e84263d55307	1163	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
<>	144:ef7eb2e8f9f7	1164	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
<>	144:ef7eb2e8f9f7	1165
AnnaBridge	167:e84263d55307	1166	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
<>	144:ef7eb2e8f9f7	1167	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
<>	144:ef7eb2e8f9f7	1168
AnnaBridge	167:e84263d55307	1169	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
<>	144:ef7eb2e8f9f7	1170	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
<>	144:ef7eb2e8f9f7	1171
AnnaBridge	167:e84263d55307	1172	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
<>	144:ef7eb2e8f9f7	1173	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
<>	144:ef7eb2e8f9f7	1174
AnnaBridge	167:e84263d55307	1175	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
<>	144:ef7eb2e8f9f7	1176	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
<>	144:ef7eb2e8f9f7	1177
AnnaBridge	167:e84263d55307	1178	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
<>	144:ef7eb2e8f9f7	1179	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
<>	144:ef7eb2e8f9f7	1180
AnnaBridge	167:e84263d55307	1181	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
<>	144:ef7eb2e8f9f7	1182	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
<>	144:ef7eb2e8f9f7	1183
AnnaBridge	167:e84263d55307	1184	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
<>	144:ef7eb2e8f9f7	1185	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
<>	144:ef7eb2e8f9f7	1186
AnnaBridge	167:e84263d55307	1187	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
<>	144:ef7eb2e8f9f7	1188	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
<>	144:ef7eb2e8f9f7	1189
AnnaBridge	167:e84263d55307	1190	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
<>	144:ef7eb2e8f9f7	1191	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
<>	144:ef7eb2e8f9f7	1192
AnnaBridge	167:e84263d55307	1193	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
<>	144:ef7eb2e8f9f7	1194	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
<>	144:ef7eb2e8f9f7	1195
AnnaBridge	167:e84263d55307	1196	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
<>	144:ef7eb2e8f9f7	1197	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	/* DWT CPI Count Register Definitions */
AnnaBridge	167:e84263d55307	1200	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
<>	144:ef7eb2e8f9f7	1201	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
<>	144:ef7eb2e8f9f7	1202
<>	144:ef7eb2e8f9f7	1203	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	167:e84263d55307	1204	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
<>	144:ef7eb2e8f9f7	1205	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
<>	144:ef7eb2e8f9f7	1206
<>	144:ef7eb2e8f9f7	1207	/* DWT Sleep Count Register Definitions */
AnnaBridge	167:e84263d55307	1208	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
<>	144:ef7eb2e8f9f7	1209	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	/* DWT LSU Count Register Definitions */
AnnaBridge	167:e84263d55307	1212	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
<>	144:ef7eb2e8f9f7	1213	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
<>	144:ef7eb2e8f9f7	1214
<>	144:ef7eb2e8f9f7	1215	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	167:e84263d55307	1216	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
<>	144:ef7eb2e8f9f7	1217	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
<>	144:ef7eb2e8f9f7	1218
<>	144:ef7eb2e8f9f7	1219	/* DWT Comparator Mask Register Definitions */
AnnaBridge	167:e84263d55307	1220	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
<>	144:ef7eb2e8f9f7	1221	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	/* DWT Comparator Function Register Definitions */
AnnaBridge	167:e84263d55307	1224	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
<>	144:ef7eb2e8f9f7	1225	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
<>	144:ef7eb2e8f9f7	1226
AnnaBridge	167:e84263d55307	1227	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
<>	144:ef7eb2e8f9f7	1228	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
<>	144:ef7eb2e8f9f7	1229
AnnaBridge	167:e84263d55307	1230	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
<>	144:ef7eb2e8f9f7	1231	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
<>	144:ef7eb2e8f9f7	1232
AnnaBridge	167:e84263d55307	1233	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
<>	144:ef7eb2e8f9f7	1234	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
<>	144:ef7eb2e8f9f7	1235
AnnaBridge	167:e84263d55307	1236	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
<>	144:ef7eb2e8f9f7	1237	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
<>	144:ef7eb2e8f9f7	1238
AnnaBridge	167:e84263d55307	1239	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
<>	144:ef7eb2e8f9f7	1240	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
<>	144:ef7eb2e8f9f7	1241
AnnaBridge	167:e84263d55307	1242	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
<>	144:ef7eb2e8f9f7	1243	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
<>	144:ef7eb2e8f9f7	1244
AnnaBridge	167:e84263d55307	1245	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
<>	144:ef7eb2e8f9f7	1246	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
<>	144:ef7eb2e8f9f7	1247
AnnaBridge	167:e84263d55307	1248	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
<>	144:ef7eb2e8f9f7	1249	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	/@}/ /* end of group CMSIS_DWT */
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253
AnnaBridge	167:e84263d55307	1254	/**
AnnaBridge	167:e84263d55307	1255	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1256	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	167:e84263d55307	1257	\brief Type definitions for the Trace Port Interface (TPI)
<>	144:ef7eb2e8f9f7	1258	@{
<>	144:ef7eb2e8f9f7	1259	*/
<>	144:ef7eb2e8f9f7	1260
AnnaBridge	167:e84263d55307	1261	/**
AnnaBridge	167:e84263d55307	1262	\brief Structure type to access the Trace Port Interface Register (TPI).
<>	144:ef7eb2e8f9f7	1263	*/
<>	144:ef7eb2e8f9f7	1264	typedef struct
<>	144:ef7eb2e8f9f7	1265	{
AnnaBridge	167:e84263d55307	1266	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	167:e84263d55307	1267	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	167:e84263d55307	1268	uint32_t RESERVED0[2U];
AnnaBridge	167:e84263d55307	1269	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	167:e84263d55307	1270	uint32_t RESERVED1[55U];
AnnaBridge	167:e84263d55307	1271	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	167:e84263d55307	1272	uint32_t RESERVED2[131U];
AnnaBridge	167:e84263d55307	1273	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	167:e84263d55307	1274	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	167:e84263d55307	1275	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	167:e84263d55307	1276	uint32_t RESERVED3[759U];
AnnaBridge	167:e84263d55307	1277	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	167:e84263d55307	1278	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	167:e84263d55307	1279	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	167:e84263d55307	1280	uint32_t RESERVED4[1U];
AnnaBridge	167:e84263d55307	1281	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	167:e84263d55307	1282	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	167:e84263d55307	1283	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	167:e84263d55307	1284	uint32_t RESERVED5[39U];
AnnaBridge	167:e84263d55307	1285	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	167:e84263d55307	1286	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	167:e84263d55307	1287	uint32_t RESERVED7[8U];
AnnaBridge	167:e84263d55307	1288	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	167:e84263d55307	1289	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
<>	144:ef7eb2e8f9f7	1290	} TPI_Type;
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	167:e84263d55307	1293	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
<>	144:ef7eb2e8f9f7	1294	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
<>	144:ef7eb2e8f9f7	1295
<>	144:ef7eb2e8f9f7	1296	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	167:e84263d55307	1297	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
<>	144:ef7eb2e8f9f7	1298	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	167:e84263d55307	1301	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
<>	144:ef7eb2e8f9f7	1302	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
<>	144:ef7eb2e8f9f7	1303
AnnaBridge	167:e84263d55307	1304	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
<>	144:ef7eb2e8f9f7	1305	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
<>	144:ef7eb2e8f9f7	1306
AnnaBridge	167:e84263d55307	1307	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
<>	144:ef7eb2e8f9f7	1308	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
<>	144:ef7eb2e8f9f7	1309
AnnaBridge	167:e84263d55307	1310	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
<>	144:ef7eb2e8f9f7	1311	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
<>	144:ef7eb2e8f9f7	1312
<>	144:ef7eb2e8f9f7	1313	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	167:e84263d55307	1314	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
<>	144:ef7eb2e8f9f7	1315	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
<>	144:ef7eb2e8f9f7	1316
AnnaBridge	167:e84263d55307	1317	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
<>	144:ef7eb2e8f9f7	1318	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
<>	144:ef7eb2e8f9f7	1319
<>	144:ef7eb2e8f9f7	1320	/* TPI TRIGGER Register Definitions */
AnnaBridge	167:e84263d55307	1321	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
<>	144:ef7eb2e8f9f7	1322	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	167:e84263d55307	1325	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
<>	144:ef7eb2e8f9f7	1326	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
<>	144:ef7eb2e8f9f7	1327
AnnaBridge	167:e84263d55307	1328	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
<>	144:ef7eb2e8f9f7	1329	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
<>	144:ef7eb2e8f9f7	1330
AnnaBridge	167:e84263d55307	1331	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
<>	144:ef7eb2e8f9f7	1332	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
<>	144:ef7eb2e8f9f7	1333
AnnaBridge	167:e84263d55307	1334	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
<>	144:ef7eb2e8f9f7	1335	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
<>	144:ef7eb2e8f9f7	1336
AnnaBridge	167:e84263d55307	1337	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
<>	144:ef7eb2e8f9f7	1338	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
<>	144:ef7eb2e8f9f7	1339
AnnaBridge	167:e84263d55307	1340	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
<>	144:ef7eb2e8f9f7	1341	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
<>	144:ef7eb2e8f9f7	1342
AnnaBridge	167:e84263d55307	1343	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
<>	144:ef7eb2e8f9f7	1344	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
<>	144:ef7eb2e8f9f7	1345
<>	144:ef7eb2e8f9f7	1346	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	167:e84263d55307	1347	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
<>	144:ef7eb2e8f9f7	1348	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	167:e84263d55307	1351	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
<>	144:ef7eb2e8f9f7	1352	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
<>	144:ef7eb2e8f9f7	1353
AnnaBridge	167:e84263d55307	1354	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
<>	144:ef7eb2e8f9f7	1355	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
<>	144:ef7eb2e8f9f7	1356
AnnaBridge	167:e84263d55307	1357	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
<>	144:ef7eb2e8f9f7	1358	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
<>	144:ef7eb2e8f9f7	1359
AnnaBridge	167:e84263d55307	1360	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
<>	144:ef7eb2e8f9f7	1361	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
<>	144:ef7eb2e8f9f7	1362
AnnaBridge	167:e84263d55307	1363	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
<>	144:ef7eb2e8f9f7	1364	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
<>	144:ef7eb2e8f9f7	1365
AnnaBridge	167:e84263d55307	1366	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
<>	144:ef7eb2e8f9f7	1367	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
<>	144:ef7eb2e8f9f7	1368
AnnaBridge	167:e84263d55307	1369	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
<>	144:ef7eb2e8f9f7	1370	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
<>	144:ef7eb2e8f9f7	1371
<>	144:ef7eb2e8f9f7	1372	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	167:e84263d55307	1373	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
<>	144:ef7eb2e8f9f7	1374	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
<>	144:ef7eb2e8f9f7	1375
<>	144:ef7eb2e8f9f7	1376	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	167:e84263d55307	1377	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
<>	144:ef7eb2e8f9f7	1378	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
<>	144:ef7eb2e8f9f7	1379
<>	144:ef7eb2e8f9f7	1380	/* TPI DEVID Register Definitions */
AnnaBridge	167:e84263d55307	1381	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
<>	144:ef7eb2e8f9f7	1382	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
<>	144:ef7eb2e8f9f7	1383
AnnaBridge	167:e84263d55307	1384	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
<>	144:ef7eb2e8f9f7	1385	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
<>	144:ef7eb2e8f9f7	1386
AnnaBridge	167:e84263d55307	1387	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
<>	144:ef7eb2e8f9f7	1388	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
<>	144:ef7eb2e8f9f7	1389
AnnaBridge	167:e84263d55307	1390	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
<>	144:ef7eb2e8f9f7	1391	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
<>	144:ef7eb2e8f9f7	1392
AnnaBridge	167:e84263d55307	1393	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
<>	144:ef7eb2e8f9f7	1394	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
<>	144:ef7eb2e8f9f7	1395
AnnaBridge	167:e84263d55307	1396	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
<>	144:ef7eb2e8f9f7	1397	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
<>	144:ef7eb2e8f9f7	1398
<>	144:ef7eb2e8f9f7	1399	/* TPI DEVTYPE Register Definitions */
AnnaBridge	167:e84263d55307	1400	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
<>	144:ef7eb2e8f9f7	1401	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
<>	144:ef7eb2e8f9f7	1402
AnnaBridge	167:e84263d55307	1403	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
<>	144:ef7eb2e8f9f7	1404	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
<>	144:ef7eb2e8f9f7	1405
<>	144:ef7eb2e8f9f7	1406	/@}/ /* end of group CMSIS_TPI */
<>	144:ef7eb2e8f9f7	1407
<>	144:ef7eb2e8f9f7	1408
AnnaBridge	167:e84263d55307	1409	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1410	/**
AnnaBridge	167:e84263d55307	1411	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1412	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	167:e84263d55307	1413	\brief Type definitions for the Memory Protection Unit (MPU)
<>	144:ef7eb2e8f9f7	1414	@{
<>	144:ef7eb2e8f9f7	1415	*/
<>	144:ef7eb2e8f9f7	1416
AnnaBridge	167:e84263d55307	1417	/**
AnnaBridge	167:e84263d55307	1418	\brief Structure type to access the Memory Protection Unit (MPU).
<>	144:ef7eb2e8f9f7	1419	*/
<>	144:ef7eb2e8f9f7	1420	typedef struct
<>	144:ef7eb2e8f9f7	1421	{
AnnaBridge	167:e84263d55307	1422	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	167:e84263d55307	1423	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	167:e84263d55307	1424	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	167:e84263d55307	1425	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	167:e84263d55307	1426	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	167:e84263d55307	1427	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	167:e84263d55307	1428	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	167:e84263d55307	1429	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	167:e84263d55307	1430	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	167:e84263d55307	1431	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	167:e84263d55307	1432	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
<>	144:ef7eb2e8f9f7	1433	} MPU_Type;
<>	144:ef7eb2e8f9f7	1434
AnnaBridge	167:e84263d55307	1435	/* MPU Type Register Definitions */
AnnaBridge	167:e84263d55307	1436	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
<>	144:ef7eb2e8f9f7	1437	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
<>	144:ef7eb2e8f9f7	1438
AnnaBridge	167:e84263d55307	1439	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
<>	144:ef7eb2e8f9f7	1440	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
<>	144:ef7eb2e8f9f7	1441
AnnaBridge	167:e84263d55307	1442	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
<>	144:ef7eb2e8f9f7	1443	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
<>	144:ef7eb2e8f9f7	1444
AnnaBridge	167:e84263d55307	1445	/* MPU Control Register Definitions */
AnnaBridge	167:e84263d55307	1446	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
<>	144:ef7eb2e8f9f7	1447	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
<>	144:ef7eb2e8f9f7	1448
AnnaBridge	167:e84263d55307	1449	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
<>	144:ef7eb2e8f9f7	1450	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
<>	144:ef7eb2e8f9f7	1451
AnnaBridge	167:e84263d55307	1452	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
<>	144:ef7eb2e8f9f7	1453	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
<>	144:ef7eb2e8f9f7	1454
AnnaBridge	167:e84263d55307	1455	/* MPU Region Number Register Definitions */
AnnaBridge	167:e84263d55307	1456	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
<>	144:ef7eb2e8f9f7	1457	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
<>	144:ef7eb2e8f9f7	1458
AnnaBridge	167:e84263d55307	1459	/* MPU Region Base Address Register Definitions */
AnnaBridge	167:e84263d55307	1460	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
<>	144:ef7eb2e8f9f7	1461	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
<>	144:ef7eb2e8f9f7	1462
AnnaBridge	167:e84263d55307	1463	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
<>	144:ef7eb2e8f9f7	1464	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
<>	144:ef7eb2e8f9f7	1465
AnnaBridge	167:e84263d55307	1466	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
<>	144:ef7eb2e8f9f7	1467	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
<>	144:ef7eb2e8f9f7	1468
AnnaBridge	167:e84263d55307	1469	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	167:e84263d55307	1470	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
<>	144:ef7eb2e8f9f7	1471	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
<>	144:ef7eb2e8f9f7	1472
AnnaBridge	167:e84263d55307	1473	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
<>	144:ef7eb2e8f9f7	1474	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
<>	144:ef7eb2e8f9f7	1475
AnnaBridge	167:e84263d55307	1476	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
<>	144:ef7eb2e8f9f7	1477	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
<>	144:ef7eb2e8f9f7	1478
AnnaBridge	167:e84263d55307	1479	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
<>	144:ef7eb2e8f9f7	1480	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
<>	144:ef7eb2e8f9f7	1481
AnnaBridge	167:e84263d55307	1482	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
<>	144:ef7eb2e8f9f7	1483	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
<>	144:ef7eb2e8f9f7	1484
AnnaBridge	167:e84263d55307	1485	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
<>	144:ef7eb2e8f9f7	1486	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
<>	144:ef7eb2e8f9f7	1487
AnnaBridge	167:e84263d55307	1488	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
<>	144:ef7eb2e8f9f7	1489	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
<>	144:ef7eb2e8f9f7	1490
AnnaBridge	167:e84263d55307	1491	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
<>	144:ef7eb2e8f9f7	1492	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
<>	144:ef7eb2e8f9f7	1493
AnnaBridge	167:e84263d55307	1494	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
<>	144:ef7eb2e8f9f7	1495	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
<>	144:ef7eb2e8f9f7	1496
AnnaBridge	167:e84263d55307	1497	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
<>	144:ef7eb2e8f9f7	1498	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
<>	144:ef7eb2e8f9f7	1499
<>	144:ef7eb2e8f9f7	1500	/@} end of group CMSIS_MPU /
AnnaBridge	167:e84263d55307	1501	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
AnnaBridge	167:e84263d55307	1502
AnnaBridge	167:e84263d55307	1503
AnnaBridge	167:e84263d55307	1504	/**
AnnaBridge	167:e84263d55307	1505	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1506	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	167:e84263d55307	1507	\brief Type definitions for the Floating Point Unit (FPU)
<>	144:ef7eb2e8f9f7	1508	@{
<>	144:ef7eb2e8f9f7	1509	*/
<>	144:ef7eb2e8f9f7	1510
AnnaBridge	167:e84263d55307	1511	/**
AnnaBridge	167:e84263d55307	1512	\brief Structure type to access the Floating Point Unit (FPU).
<>	144:ef7eb2e8f9f7	1513	*/
<>	144:ef7eb2e8f9f7	1514	typedef struct
<>	144:ef7eb2e8f9f7	1515	{
AnnaBridge	167:e84263d55307	1516	uint32_t RESERVED0[1U];
AnnaBridge	167:e84263d55307	1517	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	167:e84263d55307	1518	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	167:e84263d55307	1519	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	167:e84263d55307	1520	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	167:e84263d55307	1521	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	167:e84263d55307	1522	__IM uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
<>	144:ef7eb2e8f9f7	1523	} FPU_Type;
<>	144:ef7eb2e8f9f7	1524
AnnaBridge	167:e84263d55307	1525	/* Floating-Point Context Control Register Definitions */
AnnaBridge	167:e84263d55307	1526	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
<>	144:ef7eb2e8f9f7	1527	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
<>	144:ef7eb2e8f9f7	1528
AnnaBridge	167:e84263d55307	1529	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
<>	144:ef7eb2e8f9f7	1530	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
<>	144:ef7eb2e8f9f7	1531
AnnaBridge	167:e84263d55307	1532	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
<>	144:ef7eb2e8f9f7	1533	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
<>	144:ef7eb2e8f9f7	1534
AnnaBridge	167:e84263d55307	1535	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
<>	144:ef7eb2e8f9f7	1536	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
<>	144:ef7eb2e8f9f7	1537
AnnaBridge	167:e84263d55307	1538	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
<>	144:ef7eb2e8f9f7	1539	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
<>	144:ef7eb2e8f9f7	1540
AnnaBridge	167:e84263d55307	1541	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
<>	144:ef7eb2e8f9f7	1542	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
<>	144:ef7eb2e8f9f7	1543
AnnaBridge	167:e84263d55307	1544	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
<>	144:ef7eb2e8f9f7	1545	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
<>	144:ef7eb2e8f9f7	1546
AnnaBridge	167:e84263d55307	1547	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
<>	144:ef7eb2e8f9f7	1548	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
<>	144:ef7eb2e8f9f7	1549
AnnaBridge	167:e84263d55307	1550	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
<>	144:ef7eb2e8f9f7	1551	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
<>	144:ef7eb2e8f9f7	1552
AnnaBridge	167:e84263d55307	1553	/* Floating-Point Context Address Register Definitions */
AnnaBridge	167:e84263d55307	1554	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
<>	144:ef7eb2e8f9f7	1555	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
<>	144:ef7eb2e8f9f7	1556
AnnaBridge	167:e84263d55307	1557	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	167:e84263d55307	1558	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
<>	144:ef7eb2e8f9f7	1559	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
<>	144:ef7eb2e8f9f7	1560
AnnaBridge	167:e84263d55307	1561	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
<>	144:ef7eb2e8f9f7	1562	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
<>	144:ef7eb2e8f9f7	1563
AnnaBridge	167:e84263d55307	1564	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
<>	144:ef7eb2e8f9f7	1565	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
<>	144:ef7eb2e8f9f7	1566
AnnaBridge	167:e84263d55307	1567	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
<>	144:ef7eb2e8f9f7	1568	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
<>	144:ef7eb2e8f9f7	1569
AnnaBridge	167:e84263d55307	1570	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	167:e84263d55307	1571	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
<>	144:ef7eb2e8f9f7	1572	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
<>	144:ef7eb2e8f9f7	1573
AnnaBridge	167:e84263d55307	1574	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
<>	144:ef7eb2e8f9f7	1575	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
<>	144:ef7eb2e8f9f7	1576
AnnaBridge	167:e84263d55307	1577	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
<>	144:ef7eb2e8f9f7	1578	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
<>	144:ef7eb2e8f9f7	1579
AnnaBridge	167:e84263d55307	1580	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
<>	144:ef7eb2e8f9f7	1581	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
<>	144:ef7eb2e8f9f7	1582
AnnaBridge	167:e84263d55307	1583	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
<>	144:ef7eb2e8f9f7	1584	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
<>	144:ef7eb2e8f9f7	1585
AnnaBridge	167:e84263d55307	1586	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
<>	144:ef7eb2e8f9f7	1587	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
<>	144:ef7eb2e8f9f7	1588
AnnaBridge	167:e84263d55307	1589	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
<>	144:ef7eb2e8f9f7	1590	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
<>	144:ef7eb2e8f9f7	1591
AnnaBridge	167:e84263d55307	1592	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
<>	144:ef7eb2e8f9f7	1593	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
<>	144:ef7eb2e8f9f7	1594
AnnaBridge	167:e84263d55307	1595	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	167:e84263d55307	1596	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
<>	144:ef7eb2e8f9f7	1597	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
<>	144:ef7eb2e8f9f7	1598
AnnaBridge	167:e84263d55307	1599	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
<>	144:ef7eb2e8f9f7	1600	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
<>	144:ef7eb2e8f9f7	1601
AnnaBridge	167:e84263d55307	1602	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
<>	144:ef7eb2e8f9f7	1603	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
<>	144:ef7eb2e8f9f7	1604
AnnaBridge	167:e84263d55307	1605	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
<>	144:ef7eb2e8f9f7	1606	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
<>	144:ef7eb2e8f9f7	1607
AnnaBridge	167:e84263d55307	1608	/* Media and FP Feature Register 2 Definitions */
<>	144:ef7eb2e8f9f7	1609
<>	144:ef7eb2e8f9f7	1610	/@} end of group CMSIS_FPU /
AnnaBridge	167:e84263d55307	1611
AnnaBridge	167:e84263d55307	1612
AnnaBridge	167:e84263d55307	1613	/**
AnnaBridge	167:e84263d55307	1614	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1615	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	167:e84263d55307	1616	\brief Type definitions for the Core Debug Registers
<>	144:ef7eb2e8f9f7	1617	@{
<>	144:ef7eb2e8f9f7	1618	*/
<>	144:ef7eb2e8f9f7	1619
AnnaBridge	167:e84263d55307	1620	/**
AnnaBridge	167:e84263d55307	1621	\brief Structure type to access the Core Debug Register (CoreDebug).
<>	144:ef7eb2e8f9f7	1622	*/
<>	144:ef7eb2e8f9f7	1623	typedef struct
<>	144:ef7eb2e8f9f7	1624	{
AnnaBridge	167:e84263d55307	1625	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	167:e84263d55307	1626	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	167:e84263d55307	1627	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	167:e84263d55307	1628	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
<>	144:ef7eb2e8f9f7	1629	} CoreDebug_Type;
<>	144:ef7eb2e8f9f7	1630
AnnaBridge	167:e84263d55307	1631	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	167:e84263d55307	1632	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
<>	144:ef7eb2e8f9f7	1633	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
<>	144:ef7eb2e8f9f7	1634
AnnaBridge	167:e84263d55307	1635	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
<>	144:ef7eb2e8f9f7	1636	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
<>	144:ef7eb2e8f9f7	1637
AnnaBridge	167:e84263d55307	1638	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
<>	144:ef7eb2e8f9f7	1639	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
<>	144:ef7eb2e8f9f7	1640
AnnaBridge	167:e84263d55307	1641	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
<>	144:ef7eb2e8f9f7	1642	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
<>	144:ef7eb2e8f9f7	1643
AnnaBridge	167:e84263d55307	1644	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
<>	144:ef7eb2e8f9f7	1645	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
<>	144:ef7eb2e8f9f7	1646
AnnaBridge	167:e84263d55307	1647	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
<>	144:ef7eb2e8f9f7	1648	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
<>	144:ef7eb2e8f9f7	1649
AnnaBridge	167:e84263d55307	1650	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
<>	144:ef7eb2e8f9f7	1651	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
<>	144:ef7eb2e8f9f7	1652
AnnaBridge	167:e84263d55307	1653	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
<>	144:ef7eb2e8f9f7	1654	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
<>	144:ef7eb2e8f9f7	1655
AnnaBridge	167:e84263d55307	1656	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
<>	144:ef7eb2e8f9f7	1657	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
<>	144:ef7eb2e8f9f7	1658
AnnaBridge	167:e84263d55307	1659	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
<>	144:ef7eb2e8f9f7	1660	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
<>	144:ef7eb2e8f9f7	1661
AnnaBridge	167:e84263d55307	1662	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
<>	144:ef7eb2e8f9f7	1663	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
<>	144:ef7eb2e8f9f7	1664
AnnaBridge	167:e84263d55307	1665	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
<>	144:ef7eb2e8f9f7	1666	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
<>	144:ef7eb2e8f9f7	1667
AnnaBridge	167:e84263d55307	1668	/* Debug Core Register Selector Register Definitions */
AnnaBridge	167:e84263d55307	1669	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
<>	144:ef7eb2e8f9f7	1670	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
<>	144:ef7eb2e8f9f7	1671
AnnaBridge	167:e84263d55307	1672	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
<>	144:ef7eb2e8f9f7	1673	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
<>	144:ef7eb2e8f9f7	1674
AnnaBridge	167:e84263d55307	1675	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	167:e84263d55307	1676	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
<>	144:ef7eb2e8f9f7	1677	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
<>	144:ef7eb2e8f9f7	1678
AnnaBridge	167:e84263d55307	1679	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
<>	144:ef7eb2e8f9f7	1680	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
<>	144:ef7eb2e8f9f7	1681
AnnaBridge	167:e84263d55307	1682	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
<>	144:ef7eb2e8f9f7	1683	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
<>	144:ef7eb2e8f9f7	1684
AnnaBridge	167:e84263d55307	1685	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
<>	144:ef7eb2e8f9f7	1686	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
<>	144:ef7eb2e8f9f7	1687
AnnaBridge	167:e84263d55307	1688	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
<>	144:ef7eb2e8f9f7	1689	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
<>	144:ef7eb2e8f9f7	1690
AnnaBridge	167:e84263d55307	1691	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
<>	144:ef7eb2e8f9f7	1692	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
<>	144:ef7eb2e8f9f7	1693
AnnaBridge	167:e84263d55307	1694	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
<>	144:ef7eb2e8f9f7	1695	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
<>	144:ef7eb2e8f9f7	1696
AnnaBridge	167:e84263d55307	1697	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
<>	144:ef7eb2e8f9f7	1698	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
<>	144:ef7eb2e8f9f7	1699
AnnaBridge	167:e84263d55307	1700	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
<>	144:ef7eb2e8f9f7	1701	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
<>	144:ef7eb2e8f9f7	1702
AnnaBridge	167:e84263d55307	1703	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
<>	144:ef7eb2e8f9f7	1704	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
<>	144:ef7eb2e8f9f7	1705
AnnaBridge	167:e84263d55307	1706	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
<>	144:ef7eb2e8f9f7	1707	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
<>	144:ef7eb2e8f9f7	1708
AnnaBridge	167:e84263d55307	1709	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
<>	144:ef7eb2e8f9f7	1710	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
<>	144:ef7eb2e8f9f7	1711
AnnaBridge	167:e84263d55307	1712	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
<>	144:ef7eb2e8f9f7	1713	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
<>	144:ef7eb2e8f9f7	1714
<>	144:ef7eb2e8f9f7	1715	/@} end of group CMSIS_CoreDebug /
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717
AnnaBridge	167:e84263d55307	1718	/**
AnnaBridge	167:e84263d55307	1719	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1720	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	167:e84263d55307	1721	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
<>	144:ef7eb2e8f9f7	1722	@{
<>	144:ef7eb2e8f9f7	1723	*/
<>	144:ef7eb2e8f9f7	1724
AnnaBridge	167:e84263d55307	1725	/**
AnnaBridge	167:e84263d55307	1726	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	167:e84263d55307	1727	\param[in] field Name of the register bit field.
AnnaBridge	167:e84263d55307	1728	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:e84263d55307	1729	\return Masked and shifted value.
AnnaBridge	167:e84263d55307	1730	*/
AnnaBridge	167:e84263d55307	1731	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	167:e84263d55307	1732
AnnaBridge	167:e84263d55307	1733	/**
AnnaBridge	167:e84263d55307	1734	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	167:e84263d55307	1735	\param[in] field Name of the register bit field.
AnnaBridge	167:e84263d55307	1736	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:e84263d55307	1737	\return Masked and shifted bit field value.
AnnaBridge	167:e84263d55307	1738	*/
AnnaBridge	167:e84263d55307	1739	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	167:e84263d55307	1740
AnnaBridge	167:e84263d55307	1741	/@} end of group CMSIS_core_bitfield /
AnnaBridge	167:e84263d55307	1742
AnnaBridge	167:e84263d55307	1743
AnnaBridge	167:e84263d55307	1744	/**
AnnaBridge	167:e84263d55307	1745	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1746	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	167:e84263d55307	1747	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	167:e84263d55307	1748	@{
AnnaBridge	167:e84263d55307	1749	*/
AnnaBridge	167:e84263d55307	1750
AnnaBridge	167:e84263d55307	1751	/* Memory mapping of Core Hardware */
AnnaBridge	167:e84263d55307	1752	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	167:e84263d55307	1753	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	167:e84263d55307	1754	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	167:e84263d55307	1755	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	167:e84263d55307	1756	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	167:e84263d55307	1757	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	167:e84263d55307	1758	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	167:e84263d55307	1759	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
<>	144:ef7eb2e8f9f7	1760
<>	144:ef7eb2e8f9f7	1761	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	167:e84263d55307	1762	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	167:e84263d55307	1763	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	167:e84263d55307	1764	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	167:e84263d55307	1765	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	167:e84263d55307	1766	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	167:e84263d55307	1767	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	167:e84263d55307	1768	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	167:e84263d55307	1769
AnnaBridge	167:e84263d55307	1770	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1771	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	167:e84263d55307	1772	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
<>	144:ef7eb2e8f9f7	1773	#endif
<>	144:ef7eb2e8f9f7	1774
AnnaBridge	167:e84263d55307	1775	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	167:e84263d55307	1776	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
<>	144:ef7eb2e8f9f7	1777
<>	144:ef7eb2e8f9f7	1778	/@} /
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780
<>	144:ef7eb2e8f9f7	1781
<>	144:ef7eb2e8f9f7	1782	/*******************************************************************************
<>	144:ef7eb2e8f9f7	1783	* Hardware Abstraction Layer
<>	144:ef7eb2e8f9f7	1784	Core Function Interface contains:
<>	144:ef7eb2e8f9f7	1785	- Core NVIC Functions
<>	144:ef7eb2e8f9f7	1786	- Core SysTick Functions
<>	144:ef7eb2e8f9f7	1787	- Core Debug Functions
<>	144:ef7eb2e8f9f7	1788	- Core Register Access Functions
<>	144:ef7eb2e8f9f7	1789	******************************************************************************/
AnnaBridge	167:e84263d55307	1790	/**
AnnaBridge	167:e84263d55307	1791	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<>	144:ef7eb2e8f9f7	1792	*/
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794
<>	144:ef7eb2e8f9f7	1795
<>	144:ef7eb2e8f9f7	1796	/* ########################## NVIC functions #################################### */
AnnaBridge	167:e84263d55307	1797	/**
AnnaBridge	167:e84263d55307	1798	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1799	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	167:e84263d55307	1800	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	167:e84263d55307	1801	@{
<>	144:ef7eb2e8f9f7	1802	*/
<>	144:ef7eb2e8f9f7	1803
AnnaBridge	167:e84263d55307	1804	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	167:e84263d55307	1805	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1806	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	167:e84263d55307	1807	#endif
AnnaBridge	167:e84263d55307	1808	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1809	#else
AnnaBridge	167:e84263d55307	1810	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	167:e84263d55307	1811	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	167:e84263d55307	1812	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	167:e84263d55307	1813	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	167:e84263d55307	1814	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	167:e84263d55307	1815	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	167:e84263d55307	1816	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	167:e84263d55307	1817	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	167:e84263d55307	1818	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	167:e84263d55307	1819	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	167:e84263d55307	1820	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	167:e84263d55307	1821	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	167:e84263d55307	1822	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	167:e84263d55307	1823
AnnaBridge	167:e84263d55307	1824	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	167:e84263d55307	1825	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1826	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	167:e84263d55307	1827	#endif
AnnaBridge	167:e84263d55307	1828	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1829	#else
AnnaBridge	167:e84263d55307	1830	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	167:e84263d55307	1831	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	167:e84263d55307	1832	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	167:e84263d55307	1833
AnnaBridge	167:e84263d55307	1834	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	167:e84263d55307	1835
AnnaBridge	167:e84263d55307	1836
AnnaBridge	167:e84263d55307	1837
AnnaBridge	167:e84263d55307	1838	/**
AnnaBridge	167:e84263d55307	1839	\brief Set Priority Grouping
AnnaBridge	167:e84263d55307	1840	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	167:e84263d55307	1841	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	167:e84263d55307	1842	Only values from 0..7 are used.
AnnaBridge	167:e84263d55307	1843	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	1844	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	1845	\param [in] PriorityGroup Priority grouping field.
<>	144:ef7eb2e8f9f7	1846	*/
AnnaBridge	167:e84263d55307	1847	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<>	144:ef7eb2e8f9f7	1848	{
<>	144:ef7eb2e8f9f7	1849	uint32_t reg_value;
<>	144:ef7eb2e8f9f7	1850	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	144:ef7eb2e8f9f7	1851
<>	144:ef7eb2e8f9f7	1852	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	167:e84263d55307	1853	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<>	144:ef7eb2e8f9f7	1854	reg_value = (reg_value \|
<>	144:ef7eb2e8f9f7	1855	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	167:e84263d55307	1856	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
<>	144:ef7eb2e8f9f7	1857	SCB->AIRCR = reg_value;
<>	144:ef7eb2e8f9f7	1858	}
<>	144:ef7eb2e8f9f7	1859
<>	144:ef7eb2e8f9f7	1860
AnnaBridge	167:e84263d55307	1861	/**
AnnaBridge	167:e84263d55307	1862	\brief Get Priority Grouping
AnnaBridge	167:e84263d55307	1863	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	167:e84263d55307	1864	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<>	144:ef7eb2e8f9f7	1865	*/
AnnaBridge	167:e84263d55307	1866	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
<>	144:ef7eb2e8f9f7	1867	{
<>	144:ef7eb2e8f9f7	1868	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<>	144:ef7eb2e8f9f7	1869	}
<>	144:ef7eb2e8f9f7	1870
<>	144:ef7eb2e8f9f7	1871
AnnaBridge	167:e84263d55307	1872	/**
AnnaBridge	167:e84263d55307	1873	\brief Enable Interrupt
AnnaBridge	167:e84263d55307	1874	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1875	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1876	\note IRQn must not be negative.
<>	144:ef7eb2e8f9f7	1877	*/
AnnaBridge	167:e84263d55307	1878	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1879	{
AnnaBridge	167:e84263d55307	1880	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1881	{
AnnaBridge	167:e84263d55307	1882	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1883	}
<>	144:ef7eb2e8f9f7	1884	}
<>	144:ef7eb2e8f9f7	1885
<>	144:ef7eb2e8f9f7	1886
AnnaBridge	167:e84263d55307	1887	/**
AnnaBridge	167:e84263d55307	1888	\brief Get Interrupt Enable status
AnnaBridge	167:e84263d55307	1889	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1890	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1891	\return 0 Interrupt is not enabled.
AnnaBridge	167:e84263d55307	1892	\return 1 Interrupt is enabled.
AnnaBridge	167:e84263d55307	1893	\note IRQn must not be negative.
<>	144:ef7eb2e8f9f7	1894	*/
AnnaBridge	167:e84263d55307	1895	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1896	{
AnnaBridge	167:e84263d55307	1897	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1898	{
AnnaBridge	167:e84263d55307	1899	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1900	}
AnnaBridge	167:e84263d55307	1901	else
AnnaBridge	167:e84263d55307	1902	{
AnnaBridge	167:e84263d55307	1903	return(0U);
AnnaBridge	167:e84263d55307	1904	}
<>	144:ef7eb2e8f9f7	1905	}
<>	144:ef7eb2e8f9f7	1906
<>	144:ef7eb2e8f9f7	1907
AnnaBridge	167:e84263d55307	1908	/**
AnnaBridge	167:e84263d55307	1909	\brief Disable Interrupt
AnnaBridge	167:e84263d55307	1910	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1911	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1912	\note IRQn must not be negative.
<>	144:ef7eb2e8f9f7	1913	*/
AnnaBridge	167:e84263d55307	1914	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1915	{
AnnaBridge	167:e84263d55307	1916	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1917	{
AnnaBridge	167:e84263d55307	1918	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1919	__DSB();
AnnaBridge	167:e84263d55307	1920	__ISB();
AnnaBridge	167:e84263d55307	1921	}
<>	144:ef7eb2e8f9f7	1922	}
<>	144:ef7eb2e8f9f7	1923
<>	144:ef7eb2e8f9f7	1924
AnnaBridge	167:e84263d55307	1925	/**
AnnaBridge	167:e84263d55307	1926	\brief Get Pending Interrupt
AnnaBridge	167:e84263d55307	1927	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:e84263d55307	1928	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1929	\return 0 Interrupt status is not pending.
AnnaBridge	167:e84263d55307	1930	\return 1 Interrupt status is pending.
AnnaBridge	167:e84263d55307	1931	\note IRQn must not be negative.
<>	144:ef7eb2e8f9f7	1932	*/
AnnaBridge	167:e84263d55307	1933	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1934	{
AnnaBridge	167:e84263d55307	1935	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1936	{
AnnaBridge	167:e84263d55307	1937	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1938	}
AnnaBridge	167:e84263d55307	1939	else
AnnaBridge	167:e84263d55307	1940	{
AnnaBridge	167:e84263d55307	1941	return(0U);
AnnaBridge	167:e84263d55307	1942	}
<>	144:ef7eb2e8f9f7	1943	}
<>	144:ef7eb2e8f9f7	1944
<>	144:ef7eb2e8f9f7	1945
AnnaBridge	167:e84263d55307	1946	/**
AnnaBridge	167:e84263d55307	1947	\brief Set Pending Interrupt
AnnaBridge	167:e84263d55307	1948	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:e84263d55307	1949	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1950	\note IRQn must not be negative.
<>	144:ef7eb2e8f9f7	1951	*/
AnnaBridge	167:e84263d55307	1952	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1953	{
AnnaBridge	167:e84263d55307	1954	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1955	{
AnnaBridge	167:e84263d55307	1956	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	144:ef7eb2e8f9f7	1957	}
<>	144:ef7eb2e8f9f7	1958	}
<>	144:ef7eb2e8f9f7	1959
<>	144:ef7eb2e8f9f7	1960
AnnaBridge	167:e84263d55307	1961	/**
AnnaBridge	167:e84263d55307	1962	\brief Clear Pending Interrupt
AnnaBridge	167:e84263d55307	1963	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:e84263d55307	1964	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1965	\note IRQn must not be negative.
<>	144:ef7eb2e8f9f7	1966	*/
AnnaBridge	167:e84263d55307	1967	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1968	{
AnnaBridge	167:e84263d55307	1969	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1970	{
AnnaBridge	167:e84263d55307	1971	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	144:ef7eb2e8f9f7	1972	}
AnnaBridge	167:e84263d55307	1973	}
AnnaBridge	167:e84263d55307	1974
AnnaBridge	167:e84263d55307	1975
AnnaBridge	167:e84263d55307	1976	/**
AnnaBridge	167:e84263d55307	1977	\brief Get Active Interrupt
AnnaBridge	167:e84263d55307	1978	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	1979	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1980	\return 0 Interrupt status is not active.
AnnaBridge	167:e84263d55307	1981	\return 1 Interrupt status is active.
AnnaBridge	167:e84263d55307	1982	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1983	*/
AnnaBridge	167:e84263d55307	1984	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1985	{
AnnaBridge	167:e84263d55307	1986	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1987	{
AnnaBridge	167:e84263d55307	1988	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1989	}
AnnaBridge	167:e84263d55307	1990	else
AnnaBridge	167:e84263d55307	1991	{
AnnaBridge	167:e84263d55307	1992	return(0U);
<>	144:ef7eb2e8f9f7	1993	}
<>	144:ef7eb2e8f9f7	1994	}
<>	144:ef7eb2e8f9f7	1995
<>	144:ef7eb2e8f9f7	1996
AnnaBridge	167:e84263d55307	1997	/**
AnnaBridge	167:e84263d55307	1998	\brief Set Interrupt Priority
AnnaBridge	167:e84263d55307	1999	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:e84263d55307	2000	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2001	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2002	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	2003	\param [in] priority Priority to set.
AnnaBridge	167:e84263d55307	2004	\note The priority cannot be set for every processor exception.
AnnaBridge	167:e84263d55307	2005	*/
AnnaBridge	167:e84263d55307	2006	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:e84263d55307	2007	{
AnnaBridge	167:e84263d55307	2008	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2009	{
AnnaBridge	167:e84263d55307	2010	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:e84263d55307	2011	}
AnnaBridge	167:e84263d55307	2012	else
AnnaBridge	167:e84263d55307	2013	{
AnnaBridge	167:e84263d55307	2014	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:e84263d55307	2015	}
AnnaBridge	167:e84263d55307	2016	}
AnnaBridge	167:e84263d55307	2017
AnnaBridge	167:e84263d55307	2018
AnnaBridge	167:e84263d55307	2019	/**
AnnaBridge	167:e84263d55307	2020	\brief Get Interrupt Priority
AnnaBridge	167:e84263d55307	2021	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:e84263d55307	2022	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2023	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2024	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	2025	\return Interrupt Priority.
AnnaBridge	167:e84263d55307	2026	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:e84263d55307	2027	*/
AnnaBridge	167:e84263d55307	2028	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2029	{
AnnaBridge	167:e84263d55307	2030
AnnaBridge	167:e84263d55307	2031	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	2032	{
AnnaBridge	167:e84263d55307	2033	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	2034	}
AnnaBridge	167:e84263d55307	2035	else
AnnaBridge	167:e84263d55307	2036	{
AnnaBridge	167:e84263d55307	2037	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	2038	}
AnnaBridge	167:e84263d55307	2039	}
AnnaBridge	167:e84263d55307	2040
AnnaBridge	167:e84263d55307	2041
AnnaBridge	167:e84263d55307	2042	/**
AnnaBridge	167:e84263d55307	2043	\brief Encode Priority
AnnaBridge	167:e84263d55307	2044	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	167:e84263d55307	2045	preemptive priority value, and subpriority value.
AnnaBridge	167:e84263d55307	2046	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	2047	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	2048	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:e84263d55307	2049	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:e84263d55307	2050	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	167:e84263d55307	2051	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<>	144:ef7eb2e8f9f7	2052	*/
<>	144:ef7eb2e8f9f7	2053	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<>	144:ef7eb2e8f9f7	2054	{
<>	144:ef7eb2e8f9f7	2055	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	144:ef7eb2e8f9f7	2056	uint32_t PreemptPriorityBits;
<>	144:ef7eb2e8f9f7	2057	uint32_t SubPriorityBits;
<>	144:ef7eb2e8f9f7	2058
<>	144:ef7eb2e8f9f7	2059	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	144:ef7eb2e8f9f7	2060	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	144:ef7eb2e8f9f7	2061
<>	144:ef7eb2e8f9f7	2062	return (
<>	144:ef7eb2e8f9f7	2063	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
<>	144:ef7eb2e8f9f7	2064	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<>	144:ef7eb2e8f9f7	2065	);
<>	144:ef7eb2e8f9f7	2066	}
<>	144:ef7eb2e8f9f7	2067
<>	144:ef7eb2e8f9f7	2068
AnnaBridge	167:e84263d55307	2069	/**
AnnaBridge	167:e84263d55307	2070	\brief Decode Priority
AnnaBridge	167:e84263d55307	2071	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	167:e84263d55307	2072	preemptive priority value and subpriority value.
AnnaBridge	167:e84263d55307	2073	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	2074	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	2075	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	167:e84263d55307	2076	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:e84263d55307	2077	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:e84263d55307	2078	\param [out] pSubPriority Subpriority value (starting from 0).
<>	144:ef7eb2e8f9f7	2079	*/
AnnaBridge	167:e84263d55307	2080	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
<>	144:ef7eb2e8f9f7	2081	{
<>	144:ef7eb2e8f9f7	2082	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	144:ef7eb2e8f9f7	2083	uint32_t PreemptPriorityBits;
<>	144:ef7eb2e8f9f7	2084	uint32_t SubPriorityBits;
<>	144:ef7eb2e8f9f7	2085
<>	144:ef7eb2e8f9f7	2086	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	144:ef7eb2e8f9f7	2087	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	144:ef7eb2e8f9f7	2088
<>	144:ef7eb2e8f9f7	2089	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<>	144:ef7eb2e8f9f7	2090	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<>	144:ef7eb2e8f9f7	2091	}
<>	144:ef7eb2e8f9f7	2092
<>	144:ef7eb2e8f9f7	2093
AnnaBridge	167:e84263d55307	2094	/**
AnnaBridge	167:e84263d55307	2095	\brief Set Interrupt Vector
AnnaBridge	167:e84263d55307	2096	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	167:e84263d55307	2097	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2098	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2099	VTOR must been relocated to SRAM before.
AnnaBridge	167:e84263d55307	2100	\param [in] IRQn Interrupt number
AnnaBridge	167:e84263d55307	2101	\param [in] vector Address of interrupt handler function
<>	144:ef7eb2e8f9f7	2102	*/
AnnaBridge	167:e84263d55307	2103	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	167:e84263d55307	2104	{
AnnaBridge	167:e84263d55307	2105	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:e84263d55307	2106	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	167:e84263d55307	2107	}
AnnaBridge	167:e84263d55307	2108
AnnaBridge	167:e84263d55307	2109
AnnaBridge	167:e84263d55307	2110	/**
AnnaBridge	167:e84263d55307	2111	\brief Get Interrupt Vector
AnnaBridge	167:e84263d55307	2112	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	167:e84263d55307	2113	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	2114	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	2115	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	2116	\return Address of interrupt handler function
AnnaBridge	167:e84263d55307	2117	*/
AnnaBridge	167:e84263d55307	2118	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	2119	{
AnnaBridge	167:e84263d55307	2120	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:e84263d55307	2121	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	167:e84263d55307	2122	}
AnnaBridge	167:e84263d55307	2123
AnnaBridge	167:e84263d55307	2124
AnnaBridge	167:e84263d55307	2125	/**
AnnaBridge	167:e84263d55307	2126	\brief System Reset
AnnaBridge	167:e84263d55307	2127	\details Initiates a system reset request to reset the MCU.
AnnaBridge	167:e84263d55307	2128	*/
AnnaBridge	167:e84263d55307	2129	__STATIC_INLINE void __NVIC_SystemReset(void)
<>	144:ef7eb2e8f9f7	2130	{
<>	144:ef7eb2e8f9f7	2131	__DSB(); /* Ensure all outstanding memory accesses included
<>	144:ef7eb2e8f9f7	2132	buffered write are completed before reset */
<>	144:ef7eb2e8f9f7	2133	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
<>	144:ef7eb2e8f9f7	2134	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
<>	144:ef7eb2e8f9f7	2135	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<>	144:ef7eb2e8f9f7	2136	__DSB(); /* Ensure completion of memory access */
AnnaBridge	167:e84263d55307	2137
AnnaBridge	167:e84263d55307	2138	for(;;) /* wait until reset */
AnnaBridge	167:e84263d55307	2139	{
AnnaBridge	167:e84263d55307	2140	__NOP();
AnnaBridge	167:e84263d55307	2141	}
<>	144:ef7eb2e8f9f7	2142	}
<>	144:ef7eb2e8f9f7	2143
<>	144:ef7eb2e8f9f7	2144	/@} end of CMSIS_Core_NVICFunctions /
<>	144:ef7eb2e8f9f7	2145
<>	144:ef7eb2e8f9f7	2146
<>	144:ef7eb2e8f9f7	2147	/* ########################## FPU functions #################################### */
AnnaBridge	167:e84263d55307	2148	/**
AnnaBridge	167:e84263d55307	2149	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2150	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	167:e84263d55307	2151	\brief Function that provides FPU type.
AnnaBridge	167:e84263d55307	2152	@{
<>	144:ef7eb2e8f9f7	2153	*/
<>	144:ef7eb2e8f9f7	2154
<>	144:ef7eb2e8f9f7	2155	/**
AnnaBridge	167:e84263d55307	2156	\brief get FPU type
AnnaBridge	167:e84263d55307	2157	\details returns the FPU type
<>	144:ef7eb2e8f9f7	2158	\returns
<>	144:ef7eb2e8f9f7	2159	- \b 0: No FPU
<>	144:ef7eb2e8f9f7	2160	- \b 1: Single precision FPU
<>	144:ef7eb2e8f9f7	2161	- \b 2: Double + Single precision FPU
<>	144:ef7eb2e8f9f7	2162	*/
<>	144:ef7eb2e8f9f7	2163	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
<>	144:ef7eb2e8f9f7	2164	{
<>	144:ef7eb2e8f9f7	2165	uint32_t mvfr0;
<>	144:ef7eb2e8f9f7	2166
<>	144:ef7eb2e8f9f7	2167	mvfr0 = SCB->MVFR0;
AnnaBridge	167:e84263d55307	2168	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge	167:e84263d55307	2169	{
AnnaBridge	167:e84263d55307	2170	return 2U; /* Double + Single precision FPU */
AnnaBridge	167:e84263d55307	2171	}
AnnaBridge	167:e84263d55307	2172	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	167:e84263d55307	2173	{
AnnaBridge	167:e84263d55307	2174	return 1U; /* Single precision FPU */
AnnaBridge	167:e84263d55307	2175	}
AnnaBridge	167:e84263d55307	2176	else
AnnaBridge	167:e84263d55307	2177	{
AnnaBridge	167:e84263d55307	2178	return 0U; /* No FPU */
<>	144:ef7eb2e8f9f7	2179	}
<>	144:ef7eb2e8f9f7	2180	}
<>	144:ef7eb2e8f9f7	2181
<>	144:ef7eb2e8f9f7	2182
<>	144:ef7eb2e8f9f7	2183	/@} end of CMSIS_Core_FpuFunctions /
<>	144:ef7eb2e8f9f7	2184
<>	144:ef7eb2e8f9f7	2185
<>	144:ef7eb2e8f9f7	2186
<>	144:ef7eb2e8f9f7	2187	/* ########################## Cache functions #################################### */
AnnaBridge	167:e84263d55307	2188	/**
AnnaBridge	167:e84263d55307	2189	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2190	\defgroup CMSIS_Core_CacheFunctions Cache Functions
AnnaBridge	167:e84263d55307	2191	\brief Functions that configure Instruction and Data cache.
AnnaBridge	167:e84263d55307	2192	@{
<>	144:ef7eb2e8f9f7	2193	*/
<>	144:ef7eb2e8f9f7	2194
<>	144:ef7eb2e8f9f7	2195	/* Cache Size ID Register Macros */
<>	144:ef7eb2e8f9f7	2196	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
<>	144:ef7eb2e8f9f7	2197	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
AnnaBridge	167:e84263d55307	2198
AnnaBridge	167:e84263d55307	2199
AnnaBridge	167:e84263d55307	2200	/**
AnnaBridge	167:e84263d55307	2201	\brief Enable I-Cache
AnnaBridge	167:e84263d55307	2202	\details Turns on I-Cache
<>	144:ef7eb2e8f9f7	2203	*/
<>	144:ef7eb2e8f9f7	2204	__STATIC_INLINE void SCB_EnableICache (void)
<>	144:ef7eb2e8f9f7	2205	{
AnnaBridge	167:e84263d55307	2206	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
<>	144:ef7eb2e8f9f7	2207	__DSB();
<>	144:ef7eb2e8f9f7	2208	__ISB();
AnnaBridge	167:e84263d55307	2209	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge	167:e84263d55307	2210	__DSB();
AnnaBridge	167:e84263d55307	2211	__ISB();
AnnaBridge	167:e84263d55307	2212	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
<>	144:ef7eb2e8f9f7	2213	__DSB();
<>	144:ef7eb2e8f9f7	2214	__ISB();
<>	144:ef7eb2e8f9f7	2215	#endif
<>	144:ef7eb2e8f9f7	2216	}
<>	144:ef7eb2e8f9f7	2217
<>	144:ef7eb2e8f9f7	2218
AnnaBridge	167:e84263d55307	2219	/**
AnnaBridge	167:e84263d55307	2220	\brief Disable I-Cache
AnnaBridge	167:e84263d55307	2221	\details Turns off I-Cache
<>	144:ef7eb2e8f9f7	2222	*/
<>	144:ef7eb2e8f9f7	2223	__STATIC_INLINE void SCB_DisableICache (void)
<>	144:ef7eb2e8f9f7	2224	{
AnnaBridge	167:e84263d55307	2225	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
<>	144:ef7eb2e8f9f7	2226	__DSB();
<>	144:ef7eb2e8f9f7	2227	__ISB();
AnnaBridge	167:e84263d55307	2228	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
AnnaBridge	167:e84263d55307	2229	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
<>	144:ef7eb2e8f9f7	2230	__DSB();
<>	144:ef7eb2e8f9f7	2231	__ISB();
<>	144:ef7eb2e8f9f7	2232	#endif
<>	144:ef7eb2e8f9f7	2233	}
<>	144:ef7eb2e8f9f7	2234
<>	144:ef7eb2e8f9f7	2235
AnnaBridge	167:e84263d55307	2236	/**
AnnaBridge	167:e84263d55307	2237	\brief Invalidate I-Cache
AnnaBridge	167:e84263d55307	2238	\details Invalidates I-Cache
<>	144:ef7eb2e8f9f7	2239	*/
<>	144:ef7eb2e8f9f7	2240	__STATIC_INLINE void SCB_InvalidateICache (void)
<>	144:ef7eb2e8f9f7	2241	{
AnnaBridge	167:e84263d55307	2242	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
<>	144:ef7eb2e8f9f7	2243	__DSB();
<>	144:ef7eb2e8f9f7	2244	__ISB();
<>	144:ef7eb2e8f9f7	2245	SCB->ICIALLU = 0UL;
<>	144:ef7eb2e8f9f7	2246	__DSB();
<>	144:ef7eb2e8f9f7	2247	__ISB();
<>	144:ef7eb2e8f9f7	2248	#endif
<>	144:ef7eb2e8f9f7	2249	}
<>	144:ef7eb2e8f9f7	2250
<>	144:ef7eb2e8f9f7	2251
AnnaBridge	167:e84263d55307	2252	/**
AnnaBridge	167:e84263d55307	2253	\brief Enable D-Cache
AnnaBridge	167:e84263d55307	2254	\details Turns on D-Cache
<>	144:ef7eb2e8f9f7	2255	*/
<>	144:ef7eb2e8f9f7	2256	__STATIC_INLINE void SCB_EnableDCache (void)
<>	144:ef7eb2e8f9f7	2257	{
AnnaBridge	167:e84263d55307	2258	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2259	uint32_t ccsidr;
AnnaBridge	167:e84263d55307	2260	uint32_t sets;
AnnaBridge	167:e84263d55307	2261	uint32_t ways;
AnnaBridge	167:e84263d55307	2262
AnnaBridge	167:e84263d55307	2263	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
<>	144:ef7eb2e8f9f7	2264	__DSB();
AnnaBridge	167:e84263d55307	2265
AnnaBridge	167:e84263d55307	2266	ccsidr = SCB->CCSIDR;
AnnaBridge	167:e84263d55307	2267
AnnaBridge	167:e84263d55307	2268	/* invalidate D-Cache */
AnnaBridge	167:e84263d55307	2269	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	167:e84263d55307	2270	do {
AnnaBridge	167:e84263d55307	2271	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	167:e84263d55307	2272	do {
AnnaBridge	167:e84263d55307	2273	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
AnnaBridge	167:e84263d55307	2274	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge	167:e84263d55307	2275	#if defined ( __CC_ARM )
AnnaBridge	167:e84263d55307	2276	__schedule_barrier();
AnnaBridge	167:e84263d55307	2277	#endif
AnnaBridge	167:e84263d55307	2278	} while (ways-- != 0U);
AnnaBridge	167:e84263d55307	2279	} while(sets-- != 0U);
<>	144:ef7eb2e8f9f7	2280	__DSB();
AnnaBridge	167:e84263d55307	2281
AnnaBridge	167:e84263d55307	2282	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
<>	144:ef7eb2e8f9f7	2283
<>	144:ef7eb2e8f9f7	2284	__DSB();
<>	144:ef7eb2e8f9f7	2285	__ISB();
<>	144:ef7eb2e8f9f7	2286	#endif
<>	144:ef7eb2e8f9f7	2287	}
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289
<>	144:ef7eb2e8f9f7	2290	/**
AnnaBridge	167:e84263d55307	2291	\brief Disable D-Cache
AnnaBridge	167:e84263d55307	2292	\details Turns off D-Cache
AnnaBridge	167:e84263d55307	2293	*/
AnnaBridge	167:e84263d55307	2294	__STATIC_INLINE void SCB_DisableDCache (void)
AnnaBridge	167:e84263d55307	2295	{
AnnaBridge	167:e84263d55307	2296	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2297	register uint32_t ccsidr;
AnnaBridge	167:e84263d55307	2298	register uint32_t sets;
AnnaBridge	167:e84263d55307	2299	register uint32_t ways;
AnnaBridge	167:e84263d55307	2300
AnnaBridge	167:e84263d55307	2301	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	167:e84263d55307	2302	__DSB();
AnnaBridge	167:e84263d55307	2303
AnnaBridge	167:e84263d55307	2304	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
AnnaBridge	167:e84263d55307	2305	__DSB();
AnnaBridge	167:e84263d55307	2306
AnnaBridge	167:e84263d55307	2307	ccsidr = SCB->CCSIDR;
AnnaBridge	167:e84263d55307	2308
AnnaBridge	167:e84263d55307	2309	/* clean & invalidate D-Cache */
AnnaBridge	167:e84263d55307	2310	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	167:e84263d55307	2311	do {
AnnaBridge	167:e84263d55307	2312	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	167:e84263d55307	2313	do {
AnnaBridge	167:e84263d55307	2314	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
AnnaBridge	167:e84263d55307	2315	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge	167:e84263d55307	2316	#if defined ( __CC_ARM )
AnnaBridge	167:e84263d55307	2317	__schedule_barrier();
AnnaBridge	167:e84263d55307	2318	#endif
AnnaBridge	167:e84263d55307	2319	} while (ways-- != 0U);
AnnaBridge	167:e84263d55307	2320	} while(sets-- != 0U);
AnnaBridge	167:e84263d55307	2321
AnnaBridge	167:e84263d55307	2322	__DSB();
AnnaBridge	167:e84263d55307	2323	__ISB();
AnnaBridge	167:e84263d55307	2324	#endif
AnnaBridge	167:e84263d55307	2325	}
AnnaBridge	167:e84263d55307	2326
AnnaBridge	167:e84263d55307	2327
AnnaBridge	167:e84263d55307	2328	/**
AnnaBridge	167:e84263d55307	2329	\brief Invalidate D-Cache
AnnaBridge	167:e84263d55307	2330	\details Invalidates D-Cache
AnnaBridge	167:e84263d55307	2331	*/
AnnaBridge	167:e84263d55307	2332	__STATIC_INLINE void SCB_InvalidateDCache (void)
AnnaBridge	167:e84263d55307	2333	{
AnnaBridge	167:e84263d55307	2334	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2335	uint32_t ccsidr;
AnnaBridge	167:e84263d55307	2336	uint32_t sets;
AnnaBridge	167:e84263d55307	2337	uint32_t ways;
AnnaBridge	167:e84263d55307	2338
AnnaBridge	167:e84263d55307	2339	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	167:e84263d55307	2340	__DSB();
AnnaBridge	167:e84263d55307	2341
AnnaBridge	167:e84263d55307	2342	ccsidr = SCB->CCSIDR;
AnnaBridge	167:e84263d55307	2343
AnnaBridge	167:e84263d55307	2344	/* invalidate D-Cache */
AnnaBridge	167:e84263d55307	2345	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	167:e84263d55307	2346	do {
AnnaBridge	167:e84263d55307	2347	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	167:e84263d55307	2348	do {
AnnaBridge	167:e84263d55307	2349	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
AnnaBridge	167:e84263d55307	2350	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge	167:e84263d55307	2351	#if defined ( __CC_ARM )
AnnaBridge	167:e84263d55307	2352	__schedule_barrier();
AnnaBridge	167:e84263d55307	2353	#endif
AnnaBridge	167:e84263d55307	2354	} while (ways-- != 0U);
AnnaBridge	167:e84263d55307	2355	} while(sets-- != 0U);
AnnaBridge	167:e84263d55307	2356
AnnaBridge	167:e84263d55307	2357	__DSB();
AnnaBridge	167:e84263d55307	2358	__ISB();
AnnaBridge	167:e84263d55307	2359	#endif
AnnaBridge	167:e84263d55307	2360	}
AnnaBridge	167:e84263d55307	2361
AnnaBridge	167:e84263d55307	2362
AnnaBridge	167:e84263d55307	2363	/**
AnnaBridge	167:e84263d55307	2364	\brief Clean D-Cache
AnnaBridge	167:e84263d55307	2365	\details Cleans D-Cache
AnnaBridge	167:e84263d55307	2366	*/
AnnaBridge	167:e84263d55307	2367	__STATIC_INLINE void SCB_CleanDCache (void)
AnnaBridge	167:e84263d55307	2368	{
AnnaBridge	167:e84263d55307	2369	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2370	uint32_t ccsidr;
AnnaBridge	167:e84263d55307	2371	uint32_t sets;
AnnaBridge	167:e84263d55307	2372	uint32_t ways;
AnnaBridge	167:e84263d55307	2373
AnnaBridge	167:e84263d55307	2374	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	167:e84263d55307	2375	__DSB();
AnnaBridge	167:e84263d55307	2376
AnnaBridge	167:e84263d55307	2377	ccsidr = SCB->CCSIDR;
AnnaBridge	167:e84263d55307	2378
AnnaBridge	167:e84263d55307	2379	/* clean D-Cache */
AnnaBridge	167:e84263d55307	2380	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	167:e84263d55307	2381	do {
AnnaBridge	167:e84263d55307	2382	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	167:e84263d55307	2383	do {
AnnaBridge	167:e84263d55307	2384	SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
AnnaBridge	167:e84263d55307	2385	((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
AnnaBridge	167:e84263d55307	2386	#if defined ( __CC_ARM )
AnnaBridge	167:e84263d55307	2387	__schedule_barrier();
AnnaBridge	167:e84263d55307	2388	#endif
AnnaBridge	167:e84263d55307	2389	} while (ways-- != 0U);
AnnaBridge	167:e84263d55307	2390	} while(sets-- != 0U);
AnnaBridge	167:e84263d55307	2391
AnnaBridge	167:e84263d55307	2392	__DSB();
AnnaBridge	167:e84263d55307	2393	__ISB();
AnnaBridge	167:e84263d55307	2394	#endif
AnnaBridge	167:e84263d55307	2395	}
AnnaBridge	167:e84263d55307	2396
AnnaBridge	167:e84263d55307	2397
AnnaBridge	167:e84263d55307	2398	/**
AnnaBridge	167:e84263d55307	2399	\brief Clean & Invalidate D-Cache
AnnaBridge	167:e84263d55307	2400	\details Cleans and Invalidates D-Cache
AnnaBridge	167:e84263d55307	2401	*/
AnnaBridge	167:e84263d55307	2402	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
AnnaBridge	167:e84263d55307	2403	{
AnnaBridge	167:e84263d55307	2404	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2405	uint32_t ccsidr;
AnnaBridge	167:e84263d55307	2406	uint32_t sets;
AnnaBridge	167:e84263d55307	2407	uint32_t ways;
AnnaBridge	167:e84263d55307	2408
AnnaBridge	167:e84263d55307	2409	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	167:e84263d55307	2410	__DSB();
AnnaBridge	167:e84263d55307	2411
AnnaBridge	167:e84263d55307	2412	ccsidr = SCB->CCSIDR;
AnnaBridge	167:e84263d55307	2413
AnnaBridge	167:e84263d55307	2414	/* clean & invalidate D-Cache */
AnnaBridge	167:e84263d55307	2415	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	167:e84263d55307	2416	do {
AnnaBridge	167:e84263d55307	2417	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	167:e84263d55307	2418	do {
AnnaBridge	167:e84263d55307	2419	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
AnnaBridge	167:e84263d55307	2420	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge	167:e84263d55307	2421	#if defined ( __CC_ARM )
AnnaBridge	167:e84263d55307	2422	__schedule_barrier();
AnnaBridge	167:e84263d55307	2423	#endif
AnnaBridge	167:e84263d55307	2424	} while (ways-- != 0U);
AnnaBridge	167:e84263d55307	2425	} while(sets-- != 0U);
AnnaBridge	167:e84263d55307	2426
AnnaBridge	167:e84263d55307	2427	__DSB();
AnnaBridge	167:e84263d55307	2428	__ISB();
AnnaBridge	167:e84263d55307	2429	#endif
AnnaBridge	167:e84263d55307	2430	}
AnnaBridge	167:e84263d55307	2431
AnnaBridge	167:e84263d55307	2432
AnnaBridge	167:e84263d55307	2433	/**
AnnaBridge	167:e84263d55307	2434	\brief D-Cache Invalidate by address
AnnaBridge	167:e84263d55307	2435	\details Invalidates D-Cache for the given address
<>	144:ef7eb2e8f9f7	2436	\param[in] addr address (aligned to 32-byte boundary)
<>	144:ef7eb2e8f9f7	2437	\param[in] dsize size of memory block (in number of bytes)
<>	144:ef7eb2e8f9f7	2438	*/
<>	144:ef7eb2e8f9f7	2439	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
<>	144:ef7eb2e8f9f7	2440	{
AnnaBridge	167:e84263d55307	2441	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2442	int32_t op_size = dsize;
<>	144:ef7eb2e8f9f7	2443	uint32_t op_addr = (uint32_t)addr;
AnnaBridge	167:e84263d55307	2444	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
<>	144:ef7eb2e8f9f7	2445
<>	144:ef7eb2e8f9f7	2446	__DSB();
<>	144:ef7eb2e8f9f7	2447
<>	144:ef7eb2e8f9f7	2448	while (op_size > 0) {
<>	144:ef7eb2e8f9f7	2449	SCB->DCIMVAC = op_addr;
AnnaBridge	167:e84263d55307	2450	op_addr += (uint32_t)linesize;
AnnaBridge	167:e84263d55307	2451	op_size -= linesize;
<>	144:ef7eb2e8f9f7	2452	}
<>	144:ef7eb2e8f9f7	2453
<>	144:ef7eb2e8f9f7	2454	__DSB();
<>	144:ef7eb2e8f9f7	2455	__ISB();
<>	144:ef7eb2e8f9f7	2456	#endif
<>	144:ef7eb2e8f9f7	2457	}
<>	144:ef7eb2e8f9f7	2458
<>	144:ef7eb2e8f9f7	2459
<>	144:ef7eb2e8f9f7	2460	/**
AnnaBridge	167:e84263d55307	2461	\brief D-Cache Clean by address
AnnaBridge	167:e84263d55307	2462	\details Cleans D-Cache for the given address
<>	144:ef7eb2e8f9f7	2463	\param[in] addr address (aligned to 32-byte boundary)
<>	144:ef7eb2e8f9f7	2464	\param[in] dsize size of memory block (in number of bytes)
<>	144:ef7eb2e8f9f7	2465	*/
<>	144:ef7eb2e8f9f7	2466	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
<>	144:ef7eb2e8f9f7	2467	{
AnnaBridge	167:e84263d55307	2468	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2469	int32_t op_size = dsize;
<>	144:ef7eb2e8f9f7	2470	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	167:e84263d55307	2471	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
<>	144:ef7eb2e8f9f7	2472
<>	144:ef7eb2e8f9f7	2473	__DSB();
<>	144:ef7eb2e8f9f7	2474
<>	144:ef7eb2e8f9f7	2475	while (op_size > 0) {
<>	144:ef7eb2e8f9f7	2476	SCB->DCCMVAC = op_addr;
AnnaBridge	167:e84263d55307	2477	op_addr += (uint32_t)linesize;
AnnaBridge	167:e84263d55307	2478	op_size -= linesize;
<>	144:ef7eb2e8f9f7	2479	}
<>	144:ef7eb2e8f9f7	2480
<>	144:ef7eb2e8f9f7	2481	__DSB();
<>	144:ef7eb2e8f9f7	2482	__ISB();
<>	144:ef7eb2e8f9f7	2483	#endif
<>	144:ef7eb2e8f9f7	2484	}
<>	144:ef7eb2e8f9f7	2485
<>	144:ef7eb2e8f9f7	2486
<>	144:ef7eb2e8f9f7	2487	/**
AnnaBridge	167:e84263d55307	2488	\brief D-Cache Clean and Invalidate by address
AnnaBridge	167:e84263d55307	2489	\details Cleans and invalidates D_Cache for the given address
<>	144:ef7eb2e8f9f7	2490	\param[in] addr address (aligned to 32-byte boundary)
<>	144:ef7eb2e8f9f7	2491	\param[in] dsize size of memory block (in number of bytes)
<>	144:ef7eb2e8f9f7	2492	*/
<>	144:ef7eb2e8f9f7	2493	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
<>	144:ef7eb2e8f9f7	2494	{
AnnaBridge	167:e84263d55307	2495	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	167:e84263d55307	2496	int32_t op_size = dsize;
<>	144:ef7eb2e8f9f7	2497	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	167:e84263d55307	2498	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
<>	144:ef7eb2e8f9f7	2499
<>	144:ef7eb2e8f9f7	2500	__DSB();
<>	144:ef7eb2e8f9f7	2501
<>	144:ef7eb2e8f9f7	2502	while (op_size > 0) {
<>	144:ef7eb2e8f9f7	2503	SCB->DCCIMVAC = op_addr;
AnnaBridge	167:e84263d55307	2504	op_addr += (uint32_t)linesize;
AnnaBridge	167:e84263d55307	2505	op_size -= linesize;
<>	144:ef7eb2e8f9f7	2506	}
<>	144:ef7eb2e8f9f7	2507
<>	144:ef7eb2e8f9f7	2508	__DSB();
<>	144:ef7eb2e8f9f7	2509	__ISB();
<>	144:ef7eb2e8f9f7	2510	#endif
<>	144:ef7eb2e8f9f7	2511	}
<>	144:ef7eb2e8f9f7	2512
<>	144:ef7eb2e8f9f7	2513
<>	144:ef7eb2e8f9f7	2514	/@} end of CMSIS_Core_CacheFunctions /
<>	144:ef7eb2e8f9f7	2515
<>	144:ef7eb2e8f9f7	2516
<>	144:ef7eb2e8f9f7	2517
<>	144:ef7eb2e8f9f7	2518	/* ################################## SysTick function ############################################ */
AnnaBridge	167:e84263d55307	2519	/**
AnnaBridge	167:e84263d55307	2520	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2521	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	167:e84263d55307	2522	\brief Functions that configure the System.
<>	144:ef7eb2e8f9f7	2523	@{
<>	144:ef7eb2e8f9f7	2524	*/
<>	144:ef7eb2e8f9f7	2525
AnnaBridge	167:e84263d55307	2526	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	167:e84263d55307	2527
AnnaBridge	167:e84263d55307	2528	/**
AnnaBridge	167:e84263d55307	2529	\brief System Tick Configuration
AnnaBridge	167:e84263d55307	2530	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	167:e84263d55307	2531	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:e84263d55307	2532	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:e84263d55307	2533	\return 0 Function succeeded.
AnnaBridge	167:e84263d55307	2534	\return 1 Function failed.
AnnaBridge	167:e84263d55307	2535	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:e84263d55307	2536	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:e84263d55307	2537	must contain a vendor-specific implementation of this function.
<>	144:ef7eb2e8f9f7	2538	*/
<>	144:ef7eb2e8f9f7	2539	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<>	144:ef7eb2e8f9f7	2540	{
AnnaBridge	167:e84263d55307	2541	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:e84263d55307	2542	{
AnnaBridge	167:e84263d55307	2543	return (1UL); /* Reload value impossible */
AnnaBridge	167:e84263d55307	2544	}
<>	144:ef7eb2e8f9f7	2545
<>	144:ef7eb2e8f9f7	2546	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<>	144:ef7eb2e8f9f7	2547	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<>	144:ef7eb2e8f9f7	2548	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<>	144:ef7eb2e8f9f7	2549	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
<>	144:ef7eb2e8f9f7	2550	SysTick_CTRL_TICKINT_Msk \|
<>	144:ef7eb2e8f9f7	2551	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<>	144:ef7eb2e8f9f7	2552	return (0UL); /* Function successful */
<>	144:ef7eb2e8f9f7	2553	}
<>	144:ef7eb2e8f9f7	2554
<>	144:ef7eb2e8f9f7	2555	#endif
<>	144:ef7eb2e8f9f7	2556
<>	144:ef7eb2e8f9f7	2557	/@} end of CMSIS_Core_SysTickFunctions /
<>	144:ef7eb2e8f9f7	2558
<>	144:ef7eb2e8f9f7	2559
<>	144:ef7eb2e8f9f7	2560
<>	144:ef7eb2e8f9f7	2561	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	167:e84263d55307	2562	/**
AnnaBridge	167:e84263d55307	2563	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	2564	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	167:e84263d55307	2565	\brief Functions that access the ITM debug interface.
<>	144:ef7eb2e8f9f7	2566	@{
<>	144:ef7eb2e8f9f7	2567	*/
<>	144:ef7eb2e8f9f7	2568
AnnaBridge	167:e84263d55307	2569	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	167:e84263d55307	2570	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	167:e84263d55307	2571
AnnaBridge	167:e84263d55307	2572
AnnaBridge	167:e84263d55307	2573	/**
AnnaBridge	167:e84263d55307	2574	\brief ITM Send Character
AnnaBridge	167:e84263d55307	2575	\details Transmits a character via the ITM channel 0, and
AnnaBridge	167:e84263d55307	2576	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	167:e84263d55307	2577	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	167:e84263d55307	2578	\param [in] ch Character to transmit.
AnnaBridge	167:e84263d55307	2579	\returns Character to transmit.
<>	144:ef7eb2e8f9f7	2580	*/
<>	144:ef7eb2e8f9f7	2581	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<>	144:ef7eb2e8f9f7	2582	{
<>	144:ef7eb2e8f9f7	2583	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<>	144:ef7eb2e8f9f7	2584	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<>	144:ef7eb2e8f9f7	2585	{
AnnaBridge	167:e84263d55307	2586	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	167:e84263d55307	2587	{
AnnaBridge	167:e84263d55307	2588	__NOP();
AnnaBridge	167:e84263d55307	2589	}
AnnaBridge	167:e84263d55307	2590	ITM->PORT[0U].u8 = (uint8_t)ch;
<>	144:ef7eb2e8f9f7	2591	}
<>	144:ef7eb2e8f9f7	2592	return (ch);
<>	144:ef7eb2e8f9f7	2593	}
<>	144:ef7eb2e8f9f7	2594
<>	144:ef7eb2e8f9f7	2595
AnnaBridge	167:e84263d55307	2596	/**
AnnaBridge	167:e84263d55307	2597	\brief ITM Receive Character
AnnaBridge	167:e84263d55307	2598	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	167:e84263d55307	2599	\return Received character.
AnnaBridge	167:e84263d55307	2600	\return -1 No character pending.
<>	144:ef7eb2e8f9f7	2601	*/
AnnaBridge	167:e84263d55307	2602	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	167:e84263d55307	2603	{
<>	144:ef7eb2e8f9f7	2604	int32_t ch = -1; /* no character available */
<>	144:ef7eb2e8f9f7	2605
AnnaBridge	167:e84263d55307	2606	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	167:e84263d55307	2607	{
<>	144:ef7eb2e8f9f7	2608	ch = ITM_RxBuffer;
<>	144:ef7eb2e8f9f7	2609	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<>	144:ef7eb2e8f9f7	2610	}
<>	144:ef7eb2e8f9f7	2611
<>	144:ef7eb2e8f9f7	2612	return (ch);
<>	144:ef7eb2e8f9f7	2613	}
<>	144:ef7eb2e8f9f7	2614
<>	144:ef7eb2e8f9f7	2615
AnnaBridge	167:e84263d55307	2616	/**
AnnaBridge	167:e84263d55307	2617	\brief ITM Check Character
AnnaBridge	167:e84263d55307	2618	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	167:e84263d55307	2619	\return 0 No character available.
AnnaBridge	167:e84263d55307	2620	\return 1 Character available.
<>	144:ef7eb2e8f9f7	2621	*/
AnnaBridge	167:e84263d55307	2622	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	167:e84263d55307	2623	{
AnnaBridge	167:e84263d55307	2624
AnnaBridge	167:e84263d55307	2625	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	167:e84263d55307	2626	{
AnnaBridge	167:e84263d55307	2627	return (0); /* no character available */
AnnaBridge	167:e84263d55307	2628	}
AnnaBridge	167:e84263d55307	2629	else
AnnaBridge	167:e84263d55307	2630	{
AnnaBridge	167:e84263d55307	2631	return (1); /* character available */
<>	144:ef7eb2e8f9f7	2632	}
<>	144:ef7eb2e8f9f7	2633	}
<>	144:ef7eb2e8f9f7	2634
<>	144:ef7eb2e8f9f7	2635	/@} end of CMSIS_core_DebugFunctions /
<>	144:ef7eb2e8f9f7	2636
<>	144:ef7eb2e8f9f7	2637
<>	144:ef7eb2e8f9f7	2638
<>	144:ef7eb2e8f9f7	2639
<>	144:ef7eb2e8f9f7	2640	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	2641	}
<>	144:ef7eb2e8f9f7	2642	#endif
<>	144:ef7eb2e8f9f7	2643
<>	144:ef7eb2e8f9f7	2644	#endif /* __CORE_CM7_H_DEPENDANT */
<>	144:ef7eb2e8f9f7	2645
<>	144:ef7eb2e8f9f7	2646	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	07 Nov 2017
Imports:	14
Forks:	0
Commits:	178
Dependents:	1
Dependencies:	0
Followers:	1

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cmsis/core_cm7.h@167:e84263d55307, 2017-06-21 (annotated)

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