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mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents: Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

targets/TARGET_ublox/TARGET_HI2110/device/hi2110.h@177:619788de047e, 2017-11-07 (annotated)

Committer:: maxxir
Date:: Tue Nov 07 16:46:29 2017 +0000
Revision:: 177:619788de047e
Parent:: 170:19eb464bc2be

To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	150:02e0a0aed4ec	1	/* mbed Microcontroller Library
<>	150:02e0a0aed4ec	2	* Copyright (c) 2016 u-blox
<>	150:02e0a0aed4ec	3	*
<>	150:02e0a0aed4ec	4	* Licensed under the Apache License, Version 2.0 (the "License");
<>	150:02e0a0aed4ec	5	* you may not use this file except in compliance with the License.
<>	150:02e0a0aed4ec	6	* You may obtain a copy of the License at
<>	150:02e0a0aed4ec	7	*
<>	150:02e0a0aed4ec	8	* http://www.apache.org/licenses/LICENSE-2.0
<>	150:02e0a0aed4ec	9	*
<>	150:02e0a0aed4ec	10	* Unless required by applicable law or agreed to in writing, software
<>	150:02e0a0aed4ec	11	* distributed under the License is distributed on an "AS IS" BASIS,
<>	150:02e0a0aed4ec	12	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<>	150:02e0a0aed4ec	13	* See the License for the specific language governing permissions and
<>	150:02e0a0aed4ec	14	* limitations under the License.
<>	150:02e0a0aed4ec	15	*/
<>	150:02e0a0aed4ec	16
<>	150:02e0a0aed4ec	17	#ifndef HI2110_H
<>	150:02e0a0aed4ec	18	#define HI2110_H
<>	150:02e0a0aed4ec	19
<>	150:02e0a0aed4ec	20	#ifdef __cplusplus
<>	150:02e0a0aed4ec	21	extern "C" {
<>	150:02e0a0aed4ec	22	#endif
<>	150:02e0a0aed4ec	23
Kojto	170:19eb464bc2be	24	#include "system_hi2110.h"
Kojto	170:19eb464bc2be	25
<>	150:02e0a0aed4ec	26	/******************************************************************************/
<>	150:02e0a0aed4ec	27	/* Processor and Core Peripherals */
<>	150:02e0a0aed4ec	28	/******************************************************************************/
<>	150:02e0a0aed4ec	29
<>	150:02e0a0aed4ec	30	/*
<>	150:02e0a0aed4ec	31	* ==========================================================================
<>	150:02e0a0aed4ec	32	* ---------- Interrupt Number Definition -----------------------------------
<>	150:02e0a0aed4ec	33	* ==========================================================================
<>	150:02e0a0aed4ec	34	*/
<>	150:02e0a0aed4ec	35
<>	150:02e0a0aed4ec	36	typedef enum IRQn
<>	150:02e0a0aed4ec	37	{
<>	150:02e0a0aed4ec	38	/**** Cortex-M0 Processor Exceptions Numbers *************************************************/
<>	150:02e0a0aed4ec	39	Thread_mode = -16, /!< 0 Thread mode /
<>	150:02e0a0aed4ec	40	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
<>	150:02e0a0aed4ec	41	HardFault_IRQn = -13, /!< 3 Hard Fault Interrupt /
<>	150:02e0a0aed4ec	42	SVCall_IRQn = -5, /!< 11 SV Call Interrupt /
<>	150:02e0a0aed4ec	43	PendSV_IRQn = -2, /!< 14 Pend SV Interrupt /
<>	150:02e0a0aed4ec	44	SysTick_IRQn = -1, /!< 15 System Tick Interrupt /
<>	150:02e0a0aed4ec	45
<>	150:02e0a0aed4ec	46	/**** Device Specific Interrupt Numbers ******************************************************/
<>	150:02e0a0aed4ec	47	RTC_IRQn = 0, /!< RTC Interrupt /
<>	150:02e0a0aed4ec	48	Timer_IRQn = 1, /!< Timer Interrupt /
<>	150:02e0a0aed4ec	49	Security_IRQn = 2, /!< From Security Interrupt /
<>	150:02e0a0aed4ec	50	Protocol_IRQn = 3, /!< From Protocol Interrupt /
<>	150:02e0a0aed4ec	51	Apps_IRQn = 4, /!< Core Self Interrupt /
<>	150:02e0a0aed4ec	52	GPIO_IRQn = 5, /!< GPIO Interrupt /
<>	150:02e0a0aed4ec	53	DMA_IRQn = 6, /!< DMA Interrupt /
<>	150:02e0a0aed4ec	54	UART0_IRQn = 7, /!< UART0 Interrupt /
<>	150:02e0a0aed4ec	55	UART1_IRQn = 8, /!< UART1 Interrupt /
<>	150:02e0a0aed4ec	56	SSP0_IRQn = 9, /!< SPI0 Interrupt /
<>	150:02e0a0aed4ec	57	SSP1_IRQn = 10, /!< SPI1 Interrupt /
<>	150:02e0a0aed4ec	58	PWM0_Inner_IRQn = 11, /!< PW0 Inner Interrupt /
<>	150:02e0a0aed4ec	59	PWM0_Outer_IRQn = 12, /!< PW0 Outer Interrupt /
<>	150:02e0a0aed4ec	60	PWM1_Inner_IRQn = 13, /!< PW1 Inner Interrupt /
<>	150:02e0a0aed4ec	61	PWM1_Outer_IRQn = 14, /!< PW1 Outer Interrupt /
<>	150:02e0a0aed4ec	62	I2C_IRQn = 15, /!< I2C Interrupt /
<>	150:02e0a0aed4ec	63	LPUART_IRQn = 16, /!< Low Power UART Interrupt /
<>	150:02e0a0aed4ec	64	CAP_IRQn = 17, /!< CAP Interrupt /
<>	150:02e0a0aed4ec	65	COMP_IRQn = 18, /!< COMP Interrupt /
<>	150:02e0a0aed4ec	66	EDGE_IRQn = 19, /!< EDGE Interrupt /
<>	150:02e0a0aed4ec	67	Pulse_SWD_IRQn = 23, /!< SWD Pulse Interrupt /
<>	150:02e0a0aed4ec	68
<>	150:02e0a0aed4ec	69	} IRQn_Type;
<>	150:02e0a0aed4ec	70
<>	150:02e0a0aed4ec	71	/*
<>	150:02e0a0aed4ec	72	* ==========================================================================
<>	150:02e0a0aed4ec	73	* ----------- Processor and Core Peripheral Section ------------------------
<>	150:02e0a0aed4ec	74	* ==========================================================================
<>	150:02e0a0aed4ec	75	*/
<>	150:02e0a0aed4ec	76
<>	150:02e0a0aed4ec	77	/* Configuration of the Cortex-M# Processor and Core Peripherals */
<>	150:02e0a0aed4ec	78	#define __CM0_REV 0x0000 /!< Core Revision r2p1 /
<>	150:02e0a0aed4ec	79	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
<>	150:02e0a0aed4ec	80	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
<>	150:02e0a0aed4ec	81	#define __MPU_PRESENT 0 /!< MPU present or not /
<>	150:02e0a0aed4ec	82	#define __FPU_PRESENT 0 /!< FPU present or not /
<>	150:02e0a0aed4ec	83
<>	150:02e0a0aed4ec	84	#include <core_cm0.h> /* Cortex-M# processor and core peripherals */
<>	150:02e0a0aed4ec	85
<>	150:02e0a0aed4ec	86	/******************************************************************************/
<>	150:02e0a0aed4ec	87	/* Device Specific Peripheral registers structures */
<>	150:02e0a0aed4ec	88	/******************************************************************************/
<>	150:02e0a0aed4ec	89
<>	150:02e0a0aed4ec	90	/* UART */
<>	150:02e0a0aed4ec	91	typedef struct {
<>	150:02e0a0aed4ec	92	uint32_t UARTDR;
<>	150:02e0a0aed4ec	93	uint32_t UARTRSR;
<>	150:02e0a0aed4ec	94	uint32_t res0;
<>	150:02e0a0aed4ec	95	uint32_t res1;
<>	150:02e0a0aed4ec	96	uint32_t res2;
<>	150:02e0a0aed4ec	97	uint32_t res3;
<>	150:02e0a0aed4ec	98	uint32_t UARTFR;
<>	150:02e0a0aed4ec	99	uint32_t res4;
<>	150:02e0a0aed4ec	100	uint32_t UARTILPR;
<>	150:02e0a0aed4ec	101	uint32_t UARTIBRD; // Integer baud divider
<>	150:02e0a0aed4ec	102	uint32_t UARTFBRD; // Fractional Baud divider
<>	150:02e0a0aed4ec	103	uint32_t UARTLCR_H;
<>	150:02e0a0aed4ec	104	uint32_t UARTCR;
<>	150:02e0a0aed4ec	105	uint32_t UARTIFLS;
<>	150:02e0a0aed4ec	106	uint32_t UARTIMSC;
<>	150:02e0a0aed4ec	107	uint32_t UARTRIS;
<>	150:02e0a0aed4ec	108	uint32_t UARTMIS;
<>	150:02e0a0aed4ec	109	uint32_t UARTICR;
<>	150:02e0a0aed4ec	110	uint32_t UARTDMACR;
<>	150:02e0a0aed4ec	111	} uart_ctrl_t;
<>	150:02e0a0aed4ec	112
<>	150:02e0a0aed4ec	113	/******************************************************************************/
<>	150:02e0a0aed4ec	114	/* Peripheral memory map */
<>	150:02e0a0aed4ec	115	/******************************************************************************/
<>	150:02e0a0aed4ec	116
<>	150:02e0a0aed4ec	117	#define RTC_IRQ_TIME_LSBS ((volatile uint32_t )(0x40002000))
<>	150:02e0a0aed4ec	118	#define RTC_IRQ_TIME_LSBS_BITSET ((volatile uint32_t )(0x40002400))
<>	150:02e0a0aed4ec	119	#define RTC_IRQ_TIME_LSBS_BITCLR ((volatile uint32_t )(0x40002800))
<>	150:02e0a0aed4ec	120	#define RTC_IRQ_TIME_LSBS_BITTOG ((volatile uint32_t )(0x40002C00))
<>	150:02e0a0aed4ec	121	#define RTC_IRQ_TIME_MSBS ((volatile uint32_t )(0x40002004))
<>	150:02e0a0aed4ec	122	#define RTC_IRQ_TIME_MSBS_BITSET ((volatile uint32_t )(0x40002404))
<>	150:02e0a0aed4ec	123	#define RTC_IRQ_TIME_MSBS_BITCLR ((volatile uint32_t )(0x40002804))
<>	150:02e0a0aed4ec	124	#define RTC_IRQ_TIME_MSBS_BITTOG ((volatile uint32_t )(0x40002C04))
<>	150:02e0a0aed4ec	125	#define RTC_IRQ_CLR ((volatile uint32_t )(0x40002008))
<>	150:02e0a0aed4ec	126	#define RTC_IRQ_CLR_BITSET ((volatile uint32_t )(0x40002408))
<>	150:02e0a0aed4ec	127	#define RTC_IRQ_CLR_BITCLR ((volatile uint32_t )(0x40002808))
<>	150:02e0a0aed4ec	128	#define RTC_IRQ_CLR_BITTOG ((volatile uint32_t )(0x40002C08))
<>	150:02e0a0aed4ec	129	#define TIMER0_LOAD ((volatile uint32_t )(0x4000200C))
<>	150:02e0a0aed4ec	130	#define TIMER0_LOAD_BITSET ((volatile uint32_t )(0x4000240C))
<>	150:02e0a0aed4ec	131	#define TIMER0_LOAD_BITCLR ((volatile uint32_t )(0x4000280C))
<>	150:02e0a0aed4ec	132	#define TIMER0_LOAD_BITTOG ((volatile uint32_t )(0x40002C0C))
<>	150:02e0a0aed4ec	133	#define TIMER0_CTRL ((volatile uint32_t )(0x40002010))
<>	150:02e0a0aed4ec	134	#define TIMER0_CTRL_BITSET ((volatile uint32_t )(0x40002410))
<>	150:02e0a0aed4ec	135	#define TIMER0_CTRL_BITCLR ((volatile uint32_t )(0x40002810))
<>	150:02e0a0aed4ec	136	#define TIMER0_CTRL_BITTOG ((volatile uint32_t )(0x40002C10))
<>	150:02e0a0aed4ec	137	#define TIMER0_TIME ((volatile uint32_t )(0x40002014))
<>	150:02e0a0aed4ec	138	#define ARM_IRQ_REG ((volatile uint32_t )(0x40002018))
<>	150:02e0a0aed4ec	139	#define ARM_IRQ_REG_BITSET ((volatile uint32_t )(0x40002418))
<>	150:02e0a0aed4ec	140	#define ARM_IRQ_REG_BITCLR ((volatile uint32_t )(0x40002818))
<>	150:02e0a0aed4ec	141	#define ARM_IRQ_REG_BITTOG ((volatile uint32_t )(0x40002C18))
<>	150:02e0a0aed4ec	142	#define PIO_FUNC0 ((volatile uint32_t )(0x4000201C))
<>	150:02e0a0aed4ec	143	#define PIO_FUNC0_BITSET ((volatile uint32_t )(0x4000241C))
<>	150:02e0a0aed4ec	144	#define PIO_FUNC0_BITCLR ((volatile uint32_t )(0x4000281C))
<>	150:02e0a0aed4ec	145	#define PIO_FUNC0_BITTOG ((volatile uint32_t )(0x40002C1C))
<>	150:02e0a0aed4ec	146	#define PIO_FUNC1 ((volatile uint32_t )(0x40002020))
<>	150:02e0a0aed4ec	147	#define PIO_FUNC1_BITSET ((volatile uint32_t )(0x40002420))
<>	150:02e0a0aed4ec	148	#define PIO_FUNC1_BITCLR ((volatile uint32_t )(0x40002820))
<>	150:02e0a0aed4ec	149	#define PIO_FUNC1_BITTOG ((volatile uint32_t )(0x40002C20))
<>	150:02e0a0aed4ec	150	#define PIO_FUNC2 ((volatile uint32_t )(0x40002024))
<>	150:02e0a0aed4ec	151	#define PIO_FUNC2_BITSET ((volatile uint32_t )(0x40002424))
<>	150:02e0a0aed4ec	152	#define PIO_FUNC2_BITCLR ((volatile uint32_t )(0x40002824))
<>	150:02e0a0aed4ec	153	#define PIO_FUNC2_BITTOG ((volatile uint32_t )(0x40002C24))
<>	150:02e0a0aed4ec	154	#define PIO_FUNC3 ((volatile uint32_t )(0x40002028))
<>	150:02e0a0aed4ec	155	#define PIO_FUNC3_BITSET ((volatile uint32_t )(0x40002428))
<>	150:02e0a0aed4ec	156	#define PIO_FUNC3_BITCLR ((volatile uint32_t )(0x40002828))
<>	150:02e0a0aed4ec	157	#define PIO_FUNC3_BITTOG ((volatile uint32_t )(0x40002C28))
<>	150:02e0a0aed4ec	158	#define PIO_FUNC4 ((volatile uint32_t )(0x4000202C))
<>	150:02e0a0aed4ec	159	#define PIO_FUNC4_BITSET ((volatile uint32_t )(0x4000242C))
<>	150:02e0a0aed4ec	160	#define PIO_FUNC4_BITCLR ((volatile uint32_t )(0x4000282C))
<>	150:02e0a0aed4ec	161	#define PIO_FUNC4_BITTOG ((volatile uint32_t )(0x40002C2C))
<>	150:02e0a0aed4ec	162	#define GPIO_DIR ((volatile uint32_t )(0x40002030))
<>	150:02e0a0aed4ec	163	#define GPIO_DIR_BITSET ((volatile uint32_t )(0x40002430))
<>	150:02e0a0aed4ec	164	#define GPIO_DIR_BITCLR ((volatile uint32_t )(0x40002830))
<>	150:02e0a0aed4ec	165	#define GPIO_DIR_BITTOG ((volatile uint32_t )(0x40002C30))
<>	150:02e0a0aed4ec	166	#define GPIO_OUT ((volatile uint32_t )(0x40002034))
<>	150:02e0a0aed4ec	167	#define GPIO_OUT_BITSET ((volatile uint32_t )(0x40002434))
<>	150:02e0a0aed4ec	168	#define GPIO_OUT_BITCLR ((volatile uint32_t )(0x40002834))
<>	150:02e0a0aed4ec	169	#define GPIO_OUT_BITTOG ((volatile uint32_t )(0x40002C34))
<>	150:02e0a0aed4ec	170	#define GPIO_DRIVE ((volatile uint32_t )(0x40002038))
<>	150:02e0a0aed4ec	171	#define GPIO_DRIVE_BITSET ((volatile uint32_t )(0x40002438))
<>	150:02e0a0aed4ec	172	#define GPIO_DRIVE_BITCLR ((volatile uint32_t )(0x40002838))
<>	150:02e0a0aed4ec	173	#define GPIO_DRIVE_BITTOG ((volatile uint32_t )(0x40002C38))
<>	150:02e0a0aed4ec	174	#define GPIO_PULLEN ((volatile uint32_t )(0x4000203C))
<>	150:02e0a0aed4ec	175	#define GPIO_PULLEN_BITSET ((volatile uint32_t )(0x4000243C))
<>	150:02e0a0aed4ec	176	#define GPIO_PULLEN_BITCLR ((volatile uint32_t )(0x4000283C))
<>	150:02e0a0aed4ec	177	#define GPIO_PULLEN_BITTOG ((volatile uint32_t )(0x40002C3C))
<>	150:02e0a0aed4ec	178	#define GPIO_INT_RISE ((volatile uint32_t )(0x40002040))
<>	150:02e0a0aed4ec	179	#define GPIO_INT_RISE_BITSET ((volatile uint32_t )(0x40002440))
<>	150:02e0a0aed4ec	180	#define GPIO_INT_RISE_BITCLR ((volatile uint32_t )(0x40002840))
<>	150:02e0a0aed4ec	181	#define GPIO_INT_RISE_BITTOG ((volatile uint32_t )(0x40002C40))
<>	150:02e0a0aed4ec	182	#define GPIO_INT_FALL ((volatile uint32_t )(0x40002044))
<>	150:02e0a0aed4ec	183	#define GPIO_INT_FALL_BITSET ((volatile uint32_t )(0x40002444))
<>	150:02e0a0aed4ec	184	#define GPIO_INT_FALL_BITCLR ((volatile uint32_t )(0x40002844))
<>	150:02e0a0aed4ec	185	#define GPIO_INT_FALL_BITTOG ((volatile uint32_t )(0x40002C44))
<>	150:02e0a0aed4ec	186	#define GPIO_INT_HIGH ((volatile uint32_t )(0x40002048))
<>	150:02e0a0aed4ec	187	#define GPIO_INT_HIGH_BITSET ((volatile uint32_t )(0x40002448))
<>	150:02e0a0aed4ec	188	#define GPIO_INT_HIGH_BITCLR ((volatile uint32_t )(0x40002848))
<>	150:02e0a0aed4ec	189	#define GPIO_INT_HIGH_BITTOG ((volatile uint32_t )(0x40002C48))
<>	150:02e0a0aed4ec	190	#define GPIO_INT_LOW ((volatile uint32_t )(0x4000204C))
<>	150:02e0a0aed4ec	191	#define GPIO_INT_LOW_BITSET ((volatile uint32_t )(0x4000244C))
<>	150:02e0a0aed4ec	192	#define GPIO_INT_LOW_BITCLR ((volatile uint32_t )(0x4000284C))
<>	150:02e0a0aed4ec	193	#define GPIO_INT_LOW_BITTOG ((volatile uint32_t )(0x40002C4C))
<>	150:02e0a0aed4ec	194	#define GPIO_INT_CLR ((volatile uint32_t )(0x40002050))
<>	150:02e0a0aed4ec	195	#define GPIO_INT_CLR_BITSET ((volatile uint32_t )(0x40002450))
<>	150:02e0a0aed4ec	196	#define GPIO_INT_CLR_BITCLR ((volatile uint32_t )(0x40002850))
<>	150:02e0a0aed4ec	197	#define GPIO_INT_CLR_BITTOG ((volatile uint32_t )(0x40002C50))
<>	150:02e0a0aed4ec	198	#define GPIO_VALUE ((volatile uint32_t )(0x40002054))
<>	150:02e0a0aed4ec	199	#define GPIO_IRQ ((volatile uint32_t )(0x40002058))
<>	150:02e0a0aed4ec	200	#define WDT_INTERVAL ((volatile uint32_t )(0x4000205C))
<>	150:02e0a0aed4ec	201	#define WDT_INTERVAL_BITSET ((volatile uint32_t )(0x4000245C))
<>	150:02e0a0aed4ec	202	#define WDT_INTERVAL_BITCLR ((volatile uint32_t )(0x4000285C))
<>	150:02e0a0aed4ec	203	#define WDT_INTERVAL_BITTOG ((volatile uint32_t )(0x40002C5C))
<>	150:02e0a0aed4ec	204	#define WDT_CTRL ((volatile uint32_t )(0x40002060))
<>	150:02e0a0aed4ec	205	#define WDT_CTRL_BITSET ((volatile uint32_t )(0x40002460))
<>	150:02e0a0aed4ec	206	#define WDT_CTRL_BITCLR ((volatile uint32_t )(0x40002860))
<>	150:02e0a0aed4ec	207	#define WDT_CTRL_BITTOG ((volatile uint32_t )(0x40002C60))
<>	150:02e0a0aed4ec	208	#define WDT_TIME ((volatile uint32_t )(0x40002064))
<>	150:02e0a0aed4ec	209	#define RESET_CAUSE ((volatile uint32_t )(0x40002134))
<>	150:02e0a0aed4ec	210	#define PWM0_CTRL ((volatile uint32_t )(0x40002068))
<>	150:02e0a0aed4ec	211	#define PWM0_CTRL_BITSET ((volatile uint32_t )(0x40002468))
<>	150:02e0a0aed4ec	212	#define PWM0_CTRL_BITCLR ((volatile uint32_t )(0x40002868))
<>	150:02e0a0aed4ec	213	#define PWM0_CTRL_BITTOG ((volatile uint32_t )(0x40002C68))
<>	150:02e0a0aed4ec	214	#define PWM0_COUNT ((volatile uint32_t )(0x4000206C))
<>	150:02e0a0aed4ec	215	#define PWM0_COUNT_BITSET ((volatile uint32_t )(0x4000246C))
<>	150:02e0a0aed4ec	216	#define PWM0_COUNT_BITCLR ((volatile uint32_t )(0x4000286C))
<>	150:02e0a0aed4ec	217	#define PWM0_COUNT_BITTOG ((volatile uint32_t )(0x40002C6C))
<>	150:02e0a0aed4ec	218	#define PWM1_CTRL ((volatile uint32_t )(0x40002070))
<>	150:02e0a0aed4ec	219	#define PWM1_CTRL_BITSET ((volatile uint32_t )(0x40002470))
<>	150:02e0a0aed4ec	220	#define PWM1_CTRL_BITCLR ((volatile uint32_t )(0x40002870))
<>	150:02e0a0aed4ec	221	#define PWM1_CTRL_BITTOG ((volatile uint32_t )(0x40002C70))
<>	150:02e0a0aed4ec	222	#define PWM1_COUNT ((volatile uint32_t )(0x40002074))
<>	150:02e0a0aed4ec	223	#define PWM1_COUNT_BITSET ((volatile uint32_t )(0x40002474))
<>	150:02e0a0aed4ec	224	#define PWM1_COUNT_BITCLR ((volatile uint32_t )(0x40002874))
<>	150:02e0a0aed4ec	225	#define PWM1_COUNT_BITTOG ((volatile uint32_t )(0x40002C74))
<>	150:02e0a0aed4ec	226	#define PWM_STATUS ((volatile uint32_t )(0x40002078))
<>	150:02e0a0aed4ec	227	#define CLKEN_REG ((volatile uint32_t )(0x4000207C))
<>	150:02e0a0aed4ec	228	#define CLKEN_REG_BITSET ((volatile uint32_t )(0x4000247C))
<>	150:02e0a0aed4ec	229	#define CLKEN_REG_BITCLR ((volatile uint32_t )(0x4000287C))
<>	150:02e0a0aed4ec	230	#define CLKEN_REG_BITTOG ((volatile uint32_t )(0x40002C7C))
<>	150:02e0a0aed4ec	231	#define I2C_INTERRUPT_STATUS ((volatile uint32_t )(0x40002080))
<>	150:02e0a0aed4ec	232	#define I2C_INTERRUPT_CLEAR ((volatile uint32_t )(0x40002084))
<>	150:02e0a0aed4ec	233	#define I2C_INTERRUPT_CLEAR_BITSET ((volatile uint32_t )(0x40002484))
<>	150:02e0a0aed4ec	234	#define I2C_INTERRUPT_CLEAR_BITCLR ((volatile uint32_t )(0x40002884))
<>	150:02e0a0aed4ec	235	#define I2C_INTERRUPT_CLEAR_BITTOG ((volatile uint32_t )(0x40002C84))
<>	150:02e0a0aed4ec	236	#define I2C_INTERRUPT_ENABLE ((volatile uint32_t )(0x40002088))
<>	150:02e0a0aed4ec	237	#define I2C_INTERRUPT_ENABLE_BITSET ((volatile uint32_t )(0x40002488))
<>	150:02e0a0aed4ec	238	#define I2C_INTERRUPT_ENABLE_BITCLR ((volatile uint32_t )(0x40002888))
<>	150:02e0a0aed4ec	239	#define I2C_INTERRUPT_ENABLE_BITTOG ((volatile uint32_t )(0x40002C88))
<>	150:02e0a0aed4ec	240	#define I2C_MODE ((volatile uint32_t )(0x4000208C))
<>	150:02e0a0aed4ec	241	#define I2C_MODE_BITSET ((volatile uint32_t )(0x4000248C))
<>	150:02e0a0aed4ec	242	#define I2C_MODE_BITCLR ((volatile uint32_t )(0x4000288C))
<>	150:02e0a0aed4ec	243	#define I2C_MODE_BITTOG ((volatile uint32_t )(0x40002C8C))
<>	150:02e0a0aed4ec	244	#define I2C_TX_DATA ((volatile uint32_t )(0x40002090))
<>	150:02e0a0aed4ec	245	#define I2C_TX_DATA_BITSET ((volatile uint32_t )(0x40002490))
<>	150:02e0a0aed4ec	246	#define I2C_TX_DATA_BITCLR ((volatile uint32_t )(0x40002890))
<>	150:02e0a0aed4ec	247	#define I2C_TX_DATA_BITTOG ((volatile uint32_t )(0x40002C90))
<>	150:02e0a0aed4ec	248	#define I2C_RX_DATA ((volatile uint32_t )(0x40002144))
<>	150:02e0a0aed4ec	249	#define I2C_TX_RD_WRB ((volatile uint32_t )(0x40002094))
<>	150:02e0a0aed4ec	250	#define I2C_TX_RD_WRB_BITSET ((volatile uint32_t )(0x40002494))
<>	150:02e0a0aed4ec	251	#define I2C_TX_RD_WRB_BITCLR ((volatile uint32_t )(0x40002894))
<>	150:02e0a0aed4ec	252	#define I2C_TX_RD_WRB_BITTOG ((volatile uint32_t )(0x40002C94))
<>	150:02e0a0aed4ec	253	#define I2C_TX_NO_BYTES ((volatile uint32_t )(0x40002098))
<>	150:02e0a0aed4ec	254	#define I2C_TX_NO_BYTES_BITSET ((volatile uint32_t )(0x40002498))
<>	150:02e0a0aed4ec	255	#define I2C_TX_NO_BYTES_BITCLR ((volatile uint32_t )(0x40002898))
<>	150:02e0a0aed4ec	256	#define I2C_TX_NO_BYTES_BITTOG ((volatile uint32_t )(0x40002C98))
<>	150:02e0a0aed4ec	257	#define I2C_RX_NO_BYTES ((volatile uint32_t )(0x4000209C))
<>	150:02e0a0aed4ec	258	#define I2C_RX_NO_BYTES_MASTER ((volatile uint32_t )(0x400020A0))
<>	150:02e0a0aed4ec	259	#define I2C_RX_NO_BYTES_MASTER_BITSET ((volatile uint32_t )(0x400024A0))
<>	150:02e0a0aed4ec	260	#define I2C_RX_NO_BYTES_MASTER_BITCLR ((volatile uint32_t )(0x400028A0))
<>	150:02e0a0aed4ec	261	#define I2C_RX_NO_BYTES_MASTER_BITTOG ((volatile uint32_t )(0x40002CA0))
<>	150:02e0a0aed4ec	262	#define I2C_GO ((volatile uint32_t )(0x400020A4))
<>	150:02e0a0aed4ec	263	#define I2C_GO_BITSET ((volatile uint32_t )(0x400024A4))
<>	150:02e0a0aed4ec	264	#define I2C_GO_BITCLR ((volatile uint32_t )(0x400028A4))
<>	150:02e0a0aed4ec	265	#define I2C_GO_BITTOG ((volatile uint32_t )(0x40002CA4))
<>	150:02e0a0aed4ec	266	#define I2C_RX_EARLY_THRESHOLD ((volatile uint32_t )(0x400020A8))
<>	150:02e0a0aed4ec	267	#define I2C_RX_EARLY_THRESHOLD_BITSET ((volatile uint32_t )(0x400024A8))
<>	150:02e0a0aed4ec	268	#define I2C_RX_EARLY_THRESHOLD_BITCLR ((volatile uint32_t )(0x400028A8))
<>	150:02e0a0aed4ec	269	#define I2C_RX_EARLY_THRESHOLD_BITTOG ((volatile uint32_t )(0x40002CA8))
<>	150:02e0a0aed4ec	270	#define I2C_RX_AUTO_NAG_BYTE_CNT ((volatile uint32_t )(0x400020AC))
<>	150:02e0a0aed4ec	271	#define I2C_RX_AUTO_NAG_BYTE_CNT_BITSET ((volatile uint32_t )(0x400024AC))
<>	150:02e0a0aed4ec	272	#define I2C_RX_AUTO_NAG_BYTE_CNT_BITCLR ((volatile uint32_t )(0x400028AC))
<>	150:02e0a0aed4ec	273	#define I2C_RX_AUTO_NAG_BYTE_CNT_BITTOG ((volatile uint32_t )(0x40002CAC))
<>	150:02e0a0aed4ec	274	#define I2C_HALF_TIME ((volatile uint32_t )(0x400020B0))
<>	150:02e0a0aed4ec	275	#define I2C_HALF_TIME_BITSET ((volatile uint32_t )(0x400024B0))
<>	150:02e0a0aed4ec	276	#define I2C_HALF_TIME_BITCLR ((volatile uint32_t )(0x400028B0))
<>	150:02e0a0aed4ec	277	#define I2C_HALF_TIME_BITTOG ((volatile uint32_t )(0x40002CB0))
<>	150:02e0a0aed4ec	278	#define I2C_ADDRESS ((volatile uint32_t )(0x400020B4))
<>	150:02e0a0aed4ec	279	#define I2C_ADDRESS_BITSET ((volatile uint32_t )(0x400024B4))
<>	150:02e0a0aed4ec	280	#define I2C_ADDRESS_BITCLR ((volatile uint32_t )(0x400028B4))
<>	150:02e0a0aed4ec	281	#define I2C_ADDRESS_BITTOG ((volatile uint32_t )(0x40002CB4))
<>	150:02e0a0aed4ec	282	#define I2C_ADDR_TYPE ((volatile uint32_t )(0x400020B8))
<>	150:02e0a0aed4ec	283	#define I2C_ADDR_TYPE_BITSET ((volatile uint32_t )(0x400024B8))
<>	150:02e0a0aed4ec	284	#define I2C_ADDR_TYPE_BITCLR ((volatile uint32_t )(0x400028B8))
<>	150:02e0a0aed4ec	285	#define I2C_ADDR_TYPE_BITTOG ((volatile uint32_t )(0x40002CB8))
<>	150:02e0a0aed4ec	286	#define I2C_SOFT_RESET ((volatile uint32_t )(0x400020BC))
<>	150:02e0a0aed4ec	287	#define I2C_SOFT_RESET_BITSET ((volatile uint32_t )(0x400024BC))
<>	150:02e0a0aed4ec	288	#define I2C_SOFT_RESET_BITCLR ((volatile uint32_t )(0x400028BC))
<>	150:02e0a0aed4ec	289	#define I2C_SOFT_RESET_BITTOG ((volatile uint32_t )(0x40002CBC))
<>	150:02e0a0aed4ec	290	#define I2C_SLAVE_RWB ((volatile uint32_t )(0x400020C0))
<>	150:02e0a0aed4ec	291	#define I2C_MASTER_SM ((volatile uint32_t )(0x400020C4))
<>	150:02e0a0aed4ec	292	#define I2C_SLAVE_SM ((volatile uint32_t )(0x400020C8))
<>	150:02e0a0aed4ec	293	#define I2C_SLAVE_ENABLE ((volatile uint32_t )(0x400020CC))
<>	150:02e0a0aed4ec	294	#define I2C_SLAVE_ENABLE_BITSET ((volatile uint32_t )(0x400024CC))
<>	150:02e0a0aed4ec	295	#define I2C_SLAVE_ENABLE_BITCLR ((volatile uint32_t )(0x400028CC))
<>	150:02e0a0aed4ec	296	#define I2C_SLAVE_ENABLE_BITTOG ((volatile uint32_t )(0x40002CCC))
<>	150:02e0a0aed4ec	297	#define I2C_MASTER_SEND_RESTART ((volatile uint32_t )(0x400020D0))
<>	150:02e0a0aed4ec	298	#define I2C_MASTER_SEND_RESTART_BITSET ((volatile uint32_t )(0x400024D0))
<>	150:02e0a0aed4ec	299	#define I2C_MASTER_SEND_RESTART_BITCLR ((volatile uint32_t )(0x400028D0))
<>	150:02e0a0aed4ec	300	#define I2C_MASTER_SEND_RESTART_BITTOG ((volatile uint32_t )(0x40002CD0))
<>	150:02e0a0aed4ec	301	#define DMA_MUX ((volatile uint32_t )(0x400020D4))
<>	150:02e0a0aed4ec	302	#define DMA_MUX_BITSET ((volatile uint32_t )(0x400024D4))
<>	150:02e0a0aed4ec	303	#define DMA_MUX_BITCLR ((volatile uint32_t )(0x400028D4))
<>	150:02e0a0aed4ec	304	#define DMA_MUX_BITTOG ((volatile uint32_t )(0x40002CD4))
<>	150:02e0a0aed4ec	305	#define DMA_CTRL_STAT ((volatile uint32_t )(0x400020D8))
<>	150:02e0a0aed4ec	306	#define COMP_CTRL ((volatile uint32_t )(0x400020DC))
<>	150:02e0a0aed4ec	307	#define COMP_CTRL_BITSET ((volatile uint32_t )(0x400024DC))
<>	150:02e0a0aed4ec	308	#define COMP_CTRL_BITCLR ((volatile uint32_t )(0x400028DC))
<>	150:02e0a0aed4ec	309	#define COMP_CTRL_BITTOG ((volatile uint32_t )(0x40002CDC))
<>	150:02e0a0aed4ec	310	#define COMP_STAT ((volatile uint32_t )(0x400020E0))
<>	150:02e0a0aed4ec	311	#define LP_UART_CTRL ((volatile uint32_t )(0x400020E4))
<>	150:02e0a0aed4ec	312	#define LP_UART_CTRL_BITSET ((volatile uint32_t )(0x400024E4))
<>	150:02e0a0aed4ec	313	#define LP_UART_CTRL_BITCLR ((volatile uint32_t )(0x400028E4))
<>	150:02e0a0aed4ec	314	#define LP_UART_CTRL_BITTOG ((volatile uint32_t )(0x40002CE4))
<>	150:02e0a0aed4ec	315	#define LP_UART_STATUS ((volatile uint32_t )(0x400020E8))
<>	150:02e0a0aed4ec	316	#define LP_UART_DATA ((volatile uint32_t )(0x40002154))
<>	150:02e0a0aed4ec	317	#define CAP_FILT_CONF ((volatile uint32_t )(0x400020EC))
<>	150:02e0a0aed4ec	318	#define CAP_FILT_CONF_BITSET ((volatile uint32_t )(0x400024EC))
<>	150:02e0a0aed4ec	319	#define CAP_FILT_CONF_BITCLR ((volatile uint32_t )(0x400028EC))
<>	150:02e0a0aed4ec	320	#define CAP_FILT_CONF_BITTOG ((volatile uint32_t )(0x40002CEC))
<>	150:02e0a0aed4ec	321	#define CAP_IRQ_CONF ((volatile uint32_t )(0x400020F0))
<>	150:02e0a0aed4ec	322	#define CAP_IRQ_CONF_BITSET ((volatile uint32_t )(0x400024F0))
<>	150:02e0a0aed4ec	323	#define CAP_IRQ_CONF_BITCLR ((volatile uint32_t )(0x400028F0))
<>	150:02e0a0aed4ec	324	#define CAP_IRQ_CONF_BITTOG ((volatile uint32_t )(0x40002CF0))
<>	150:02e0a0aed4ec	325	#define CAP_STATUS ((volatile uint32_t )(0x400020F4))
<>	150:02e0a0aed4ec	326	#define CORE_ENABLE_SWD_ACCESS_APPS ((volatile uint32_t )(0x400020F8))
<>	150:02e0a0aed4ec	327	#define CORE_ENABLE_SWD_ACCESS_APPS_BITSET ((volatile uint32_t )(0x400024F8))
<>	150:02e0a0aed4ec	328	#define CORE_ENABLE_SWD_ACCESS_APPS_BITCLR ((volatile uint32_t )(0x400028F8))
<>	150:02e0a0aed4ec	329	#define CORE_ENABLE_SWD_ACCESS_APPS_BITTOG ((volatile uint32_t )(0x40002CF8))
<>	150:02e0a0aed4ec	330	#define APPS_DEBUGGER_TO_CORE_DATA ((volatile uint32_t )(0x400020FC))
<>	150:02e0a0aed4ec	331	#define APPS_CORE_TO_DEBUGGER_DATA ((volatile uint32_t )(0x40002100))
<>	150:02e0a0aed4ec	332	#define APPS_CORE_TO_DEBUGGER_DATA_BITSET ((volatile uint32_t )(0x40002500))
<>	150:02e0a0aed4ec	333	#define APPS_CORE_TO_DEBUGGER_DATA_BITCLR ((volatile uint32_t )(0x40002900))
<>	150:02e0a0aed4ec	334	#define APPS_CORE_TO_DEBUGGER_DATA_BITTOG ((volatile uint32_t )(0x40002D00))
<>	150:02e0a0aed4ec	335	#define APPS_DEBUG_DATA_TO_CORE_AVAILABLE ((volatile uint32_t )(0x40002104))
<>	150:02e0a0aed4ec	336	#define APPS_DEBUG_DATA_TO_CORE_ACCEPTED ((volatile uint32_t )(0x40002108))
<>	150:02e0a0aed4ec	337	#define APPS_DEBUG_DATA_TO_CORE_ACCEPTED_BITSET ((volatile uint32_t )(0x40002508))
<>	150:02e0a0aed4ec	338	#define APPS_DEBUG_DATA_TO_CORE_ACCEPTED_BITCLR ((volatile uint32_t )(0x40002908))
<>	150:02e0a0aed4ec	339	#define APPS_DEBUG_DATA_TO_CORE_ACCEPTED_BITTOG ((volatile uint32_t )(0x40002D08))
<>	150:02e0a0aed4ec	340	#define APPS_CORE_DATA_TO_DEBUGGER_AVAILABLE ((volatile uint32_t )(0x4000210C))
<>	150:02e0a0aed4ec	341	#define APPS_CORE_DATA_TO_DEBUGGER_AVAILABLE_BITSET ((volatile uint32_t )(0x4000250C))
<>	150:02e0a0aed4ec	342	#define APPS_CORE_DATA_TO_DEBUGGER_AVAILABLE_BITCLR ((volatile uint32_t )(0x4000290C))
<>	150:02e0a0aed4ec	343	#define APPS_CORE_DATA_TO_DEBUGGER_AVAILABLE_BITTOG ((volatile uint32_t )(0x40002D0C))
<>	150:02e0a0aed4ec	344	#define APPS_CORE_DATA_TO_DEBUGGER_ACCEPTED ((volatile uint32_t )(0x40002110))
<>	150:02e0a0aed4ec	345	#define SWD_REQUEST ((volatile uint32_t )(0x40002114))
<>	150:02e0a0aed4ec	346	#define EDGE_CTRL0 ((volatile uint32_t )(0x40002118))
<>	150:02e0a0aed4ec	347	#define EDGE_CTRL0_BITSET ((volatile uint32_t )(0x40002518))
<>	150:02e0a0aed4ec	348	#define EDGE_CTRL0_BITCLR ((volatile uint32_t )(0x40002918))
<>	150:02e0a0aed4ec	349	#define EDGE_CTRL0_BITTOG ((volatile uint32_t )(0x40002D18))
<>	150:02e0a0aed4ec	350	#define EDGE_CTRL1 ((volatile uint32_t )(0x4000211C))
<>	150:02e0a0aed4ec	351	#define EDGE_CTRL1_BITSET ((volatile uint32_t )(0x4000251C))
<>	150:02e0a0aed4ec	352	#define EDGE_CTRL1_BITCLR ((volatile uint32_t )(0x4000291C))
<>	150:02e0a0aed4ec	353	#define EDGE_CTRL1_BITTOG ((volatile uint32_t )(0x40002D1C))
<>	150:02e0a0aed4ec	354	#define EDGE_COUNT ((volatile uint32_t )(0x40002120))
<>	150:02e0a0aed4ec	355	#define RESET_REG ((volatile uint32_t )(0x40002124))
<>	150:02e0a0aed4ec	356	#define RESET_REG_BITSET ((volatile uint32_t )(0x40002524))
<>	150:02e0a0aed4ec	357	#define RESET_REG_BITCLR ((volatile uint32_t )(0x40002924))
<>	150:02e0a0aed4ec	358	#define RESET_REG_BITTOG ((volatile uint32_t )(0x40002D24))
<>	150:02e0a0aed4ec	359	#define DIGITAL_VERSION ((volatile uint32_t )(0x40000000))
<>	150:02e0a0aed4ec	360	#define CLK_FREQ_DAC ((volatile uint32_t )(0x40000004))
<>	150:02e0a0aed4ec	361	#define CLK_FREQ_SET ((volatile uint32_t )(0x40000008))
<>	150:02e0a0aed4ec	362	#define CLK_FREQ_SET_BITSET ((volatile uint32_t )(0x40000408))
<>	150:02e0a0aed4ec	363	#define CLK_FREQ_SET_BITCLR ((volatile uint32_t )(0x40000808))
<>	150:02e0a0aed4ec	364	#define CLK_FREQ_SET_BITTOG ((volatile uint32_t )(0x40000C08))
<>	150:02e0a0aed4ec	365	#define CLK_FREQ_NREFCLKS ((volatile uint32_t )(0x4000000C))
<>	150:02e0a0aed4ec	366	#define CLK_FREQ_NREFCLKS_BITSET ((volatile uint32_t )(0x4000040C))
<>	150:02e0a0aed4ec	367	#define CLK_FREQ_NREFCLKS_BITCLR ((volatile uint32_t )(0x4000080C))
<>	150:02e0a0aed4ec	368	#define CLK_FREQ_NREFCLKS_BITTOG ((volatile uint32_t )(0x40000C0C))
<>	150:02e0a0aed4ec	369	#define CLK_FREQ_REF_SEL ((volatile uint32_t )(0x40000010))
<>	150:02e0a0aed4ec	370	#define CLK_FREQ_REF_SEL_BITSET ((volatile uint32_t )(0x40000410))
<>	150:02e0a0aed4ec	371	#define CLK_FREQ_REF_SEL_BITCLR ((volatile uint32_t )(0x40000810))
<>	150:02e0a0aed4ec	372	#define CLK_FREQ_REF_SEL_BITTOG ((volatile uint32_t )(0x40000C10))
<>	150:02e0a0aed4ec	373	#define CLK_FREQ_DIG_CLKS ((volatile uint32_t )(0x40000014))
<>	150:02e0a0aed4ec	374	#define CLK_FREQ_HIGHTARGET ((volatile uint32_t )(0x40000018))
<>	150:02e0a0aed4ec	375	#define CLK_FREQ_HIGHTARGET_BITSET ((volatile uint32_t )(0x40000418))
<>	150:02e0a0aed4ec	376	#define CLK_FREQ_HIGHTARGET_BITCLR ((volatile uint32_t )(0x40000818))
<>	150:02e0a0aed4ec	377	#define CLK_FREQ_HIGHTARGET_BITTOG ((volatile uint32_t )(0x40000C18))
<>	150:02e0a0aed4ec	378	#define CLK_FREQ_LOWTARGET ((volatile uint32_t )(0x4000001C))
<>	150:02e0a0aed4ec	379	#define CLK_FREQ_LOWTARGET_BITSET ((volatile uint32_t )(0x4000041C))
<>	150:02e0a0aed4ec	380	#define CLK_FREQ_LOWTARGET_BITCLR ((volatile uint32_t )(0x4000081C))
<>	150:02e0a0aed4ec	381	#define CLK_FREQ_LOWTARGET_BITTOG ((volatile uint32_t )(0x40000C1C))
<>	150:02e0a0aed4ec	382	#define CLK_FREQ_LP_BACKOFF ((volatile uint32_t )(0x40000020))
<>	150:02e0a0aed4ec	383	#define CLK_FREQ_LP_BACKOFF_BITSET ((volatile uint32_t )(0x40000420))
<>	150:02e0a0aed4ec	384	#define CLK_FREQ_LP_BACKOFF_BITCLR ((volatile uint32_t )(0x40000820))
<>	150:02e0a0aed4ec	385	#define CLK_FREQ_LP_BACKOFF_BITTOG ((volatile uint32_t )(0x40000C20))
<>	150:02e0a0aed4ec	386	#define CLK_FREQ_ENABLE ((volatile uint32_t )(0x40000024))
<>	150:02e0a0aed4ec	387	#define CLK_FREQ_ENABLE_BITSET ((volatile uint32_t )(0x40000424))
<>	150:02e0a0aed4ec	388	#define CLK_FREQ_ENABLE_BITCLR ((volatile uint32_t )(0x40000824))
<>	150:02e0a0aed4ec	389	#define CLK_FREQ_ENABLE_BITTOG ((volatile uint32_t )(0x40000C24))
<>	150:02e0a0aed4ec	390	#define CLK_GATE_SYS ((volatile uint32_t )(0x40000028))
<>	150:02e0a0aed4ec	391	#define CLK_GATE_SYS_BITSET ((volatile uint32_t )(0x40000428))
<>	150:02e0a0aed4ec	392	#define CLK_GATE_SYS_BITCLR ((volatile uint32_t )(0x40000828))
<>	150:02e0a0aed4ec	393	#define CLK_GATE_SYS_BITTOG ((volatile uint32_t )(0x40000C28))
<>	150:02e0a0aed4ec	394	#define CLK_GATE_MODEM ((volatile uint32_t )(0x4000002C))
<>	150:02e0a0aed4ec	395	#define CLK_GATE_MODEM_BITSET ((volatile uint32_t )(0x4000042C))
<>	150:02e0a0aed4ec	396	#define CLK_GATE_MODEM_BITCLR ((volatile uint32_t )(0x4000082C))
<>	150:02e0a0aed4ec	397	#define CLK_GATE_MODEM_BITTOG ((volatile uint32_t )(0x40000C2C))
<>	150:02e0a0aed4ec	398	#define CLK_GATE_RADIO ((volatile uint32_t )(0x40000030))
<>	150:02e0a0aed4ec	399	#define CLK_GATE_RADIO_BITSET ((volatile uint32_t )(0x40000430))
<>	150:02e0a0aed4ec	400	#define CLK_GATE_RADIO_BITCLR ((volatile uint32_t )(0x40000830))
<>	150:02e0a0aed4ec	401	#define CLK_GATE_RADIO_BITTOG ((volatile uint32_t )(0x40000C30))
<>	150:02e0a0aed4ec	402	#define CLK_GATE_DEBUG ((volatile uint32_t )(0x40000034))
<>	150:02e0a0aed4ec	403	#define CLK_GATE_DEBUG_BITSET ((volatile uint32_t )(0x40000434))
<>	150:02e0a0aed4ec	404	#define CLK_GATE_DEBUG_BITCLR ((volatile uint32_t )(0x40000834))
<>	150:02e0a0aed4ec	405	#define CLK_GATE_DEBUG_BITTOG ((volatile uint32_t )(0x40000C34))
<>	150:02e0a0aed4ec	406	#define CLK_GATE_RBIST ((volatile uint32_t )(0x40000038))
<>	150:02e0a0aed4ec	407	#define CLK_GATE_RBIST_BITSET ((volatile uint32_t )(0x40000438))
<>	150:02e0a0aed4ec	408	#define CLK_GATE_RBIST_BITCLR ((volatile uint32_t )(0x40000838))
<>	150:02e0a0aed4ec	409	#define CLK_GATE_RBIST_BITTOG ((volatile uint32_t )(0x40000C38))
<>	150:02e0a0aed4ec	410	#define LPC_CTRL ((volatile uint32_t )(0x4000003C))
<>	150:02e0a0aed4ec	411	#define LPC_CTRL_BITSET ((volatile uint32_t )(0x4000043C))
<>	150:02e0a0aed4ec	412	#define LPC_CTRL_BITCLR ((volatile uint32_t )(0x4000083C))
<>	150:02e0a0aed4ec	413	#define LPC_CTRL_BITTOG ((volatile uint32_t )(0x40000C3C))
<>	150:02e0a0aed4ec	414	#define LPC_TEST ((volatile uint32_t )(0x40000040))
<>	150:02e0a0aed4ec	415	#define LPC_TEST_BITSET ((volatile uint32_t )(0x40000440))
<>	150:02e0a0aed4ec	416	#define LPC_TEST_BITCLR ((volatile uint32_t )(0x40000840))
<>	150:02e0a0aed4ec	417	#define LPC_TEST_BITTOG ((volatile uint32_t )(0x40000C40))
<>	150:02e0a0aed4ec	418	#define FPGA_FLASH_WR ((volatile uint32_t )(0x40000044))
<>	150:02e0a0aed4ec	419	#define FPGA_FLASH_WR_BITSET ((volatile uint32_t )(0x40000444))
<>	150:02e0a0aed4ec	420	#define FPGA_FLASH_WR_BITCLR ((volatile uint32_t )(0x40000844))
<>	150:02e0a0aed4ec	421	#define FPGA_FLASH_WR_BITTOG ((volatile uint32_t )(0x40000C44))
<>	150:02e0a0aed4ec	422	#define FPGA_FLASH_RD ((volatile uint32_t )(0x40000048))
<>	150:02e0a0aed4ec	423	#define PMU_CTRL ((volatile uint32_t )(0x4000004C))
<>	150:02e0a0aed4ec	424	#define PMU_CTRL_BITSET ((volatile uint32_t )(0x4000044C))
<>	150:02e0a0aed4ec	425	#define PMU_CTRL_BITCLR ((volatile uint32_t )(0x4000084C))
<>	150:02e0a0aed4ec	426	#define PMU_CTRL_BITTOG ((volatile uint32_t )(0x40000C4C))
<>	150:02e0a0aed4ec	427	#define APP_CTRL0 ((volatile uint32_t )(0x40000050))
<>	150:02e0a0aed4ec	428	#define APP_CTRL0_BITSET ((volatile uint32_t )(0x40000450))
<>	150:02e0a0aed4ec	429	#define APP_CTRL0_BITCLR ((volatile uint32_t )(0x40000850))
<>	150:02e0a0aed4ec	430	#define APP_CTRL0_BITTOG ((volatile uint32_t )(0x40000C50))
<>	150:02e0a0aed4ec	431	#define APP_CTRL1 ((volatile uint32_t )(0x40000054))
<>	150:02e0a0aed4ec	432	#define APP_CTRL1_BITSET ((volatile uint32_t )(0x40000454))
<>	150:02e0a0aed4ec	433	#define APP_CTRL1_BITCLR ((volatile uint32_t )(0x40000854))
<>	150:02e0a0aed4ec	434	#define APP_CTRL1_BITTOG ((volatile uint32_t )(0x40000C54))
<>	150:02e0a0aed4ec	435	#define APP_CTRL2 ((volatile uint32_t )(0x40000058))
<>	150:02e0a0aed4ec	436	#define APP_CTRL2_BITSET ((volatile uint32_t )(0x40000458))
<>	150:02e0a0aed4ec	437	#define APP_CTRL2_BITCLR ((volatile uint32_t )(0x40000858))
<>	150:02e0a0aed4ec	438	#define APP_CTRL2_BITTOG ((volatile uint32_t )(0x40000C58))
<>	150:02e0a0aed4ec	439	#define APP_CTRL3 ((volatile uint32_t )(0x4000005C))
<>	150:02e0a0aed4ec	440	#define APP_CTRL3_BITSET ((volatile uint32_t )(0x4000045C))
<>	150:02e0a0aed4ec	441	#define APP_CTRL3_BITCLR ((volatile uint32_t )(0x4000085C))
<>	150:02e0a0aed4ec	442	#define APP_CTRL3_BITTOG ((volatile uint32_t )(0x40000C5C))
<>	150:02e0a0aed4ec	443	#define PMU_STAT ((volatile uint32_t )(0x40000060))
<>	150:02e0a0aed4ec	444	#define PMUBIST_ADC_CONF ((volatile uint32_t )(0x40000064))
<>	150:02e0a0aed4ec	445	#define PMUBIST_ADC_CONF_BITSET ((volatile uint32_t )(0x40000464))
<>	150:02e0a0aed4ec	446	#define PMUBIST_ADC_CONF_BITCLR ((volatile uint32_t )(0x40000864))
<>	150:02e0a0aed4ec	447	#define PMUBIST_ADC_CONF_BITTOG ((volatile uint32_t )(0x40000C64))
<>	150:02e0a0aed4ec	448	#define PMUBIST_ADC_DATA ((volatile uint32_t )(0x40000068))
<>	150:02e0a0aed4ec	449	#define STATUS ((volatile uint32_t )(0x4000006C))
<>	150:02e0a0aed4ec	450	#define LPC_STATUS ((volatile uint32_t )(0x40000070))
<>	150:02e0a0aed4ec	451	#define LPC_PDTIMER ((volatile uint32_t )(0x40000074))
<>	150:02e0a0aed4ec	452	#define LPC_PDTIMER_BITSET ((volatile uint32_t )(0x40000474))
<>	150:02e0a0aed4ec	453	#define LPC_PDTIMER_BITCLR ((volatile uint32_t )(0x40000874))
<>	150:02e0a0aed4ec	454	#define LPC_PDTIMER_BITTOG ((volatile uint32_t )(0x40000C74))
<>	150:02e0a0aed4ec	455	#define PIO_OWNER0 ((volatile uint32_t )(0x40000078))
<>	150:02e0a0aed4ec	456	#define PIO_OWNER1 ((volatile uint32_t )(0x4000007C))
<>	150:02e0a0aed4ec	457	#define RTC_TIME_LSBS ((volatile uint32_t )(0x40000080))
<>	150:02e0a0aed4ec	458	#define RTC_TIME_MSBS ((volatile uint32_t )(0x40000084))
<>	150:02e0a0aed4ec	459	#define DEBUG_SEL ((volatile uint32_t )(0x40000088))
<>	150:02e0a0aed4ec	460	#define DEBUG_SEL_BITSET ((volatile uint32_t )(0x40000488))
<>	150:02e0a0aed4ec	461	#define DEBUG_SEL_BITCLR ((volatile uint32_t )(0x40000888))
<>	150:02e0a0aed4ec	462	#define DEBUG_SEL_BITTOG ((volatile uint32_t )(0x40000C88))
<>	150:02e0a0aed4ec	463	#define FLASH_STATUS ((volatile uint32_t )(0x4000008C))
<>	150:02e0a0aed4ec	464	#define CHIP_WDT_INTERVAL ((volatile uint32_t )(0x40000090))
<>	150:02e0a0aed4ec	465	#define CHIP_WDT_INTERVAL_BITSET ((volatile uint32_t )(0x40000490))
<>	150:02e0a0aed4ec	466	#define CHIP_WDT_INTERVAL_BITCLR ((volatile uint32_t )(0x40000890))
<>	150:02e0a0aed4ec	467	#define CHIP_WDT_INTERVAL_BITTOG ((volatile uint32_t )(0x40000C90))
<>	150:02e0a0aed4ec	468	#define CHIP_WDT_CTRL ((volatile uint32_t )(0x40000094))
<>	150:02e0a0aed4ec	469	#define CHIP_WDT_CTRL_BITSET ((volatile uint32_t )(0x40000494))
<>	150:02e0a0aed4ec	470	#define CHIP_WDT_CTRL_BITCLR ((volatile uint32_t )(0x40000894))
<>	150:02e0a0aed4ec	471	#define CHIP_WDT_CTRL_BITTOG ((volatile uint32_t )(0x40000C94))
<>	150:02e0a0aed4ec	472	#define CHIP_WDT_TIME ((volatile uint32_t )(0x40000098))
<>	150:02e0a0aed4ec	473	#define CHIP_RESET ((volatile uint32_t )(0x4000009C))
<>	150:02e0a0aed4ec	474	#define CHIP_RESET_BITSET ((volatile uint32_t )(0x4000049C))
<>	150:02e0a0aed4ec	475	#define CHIP_RESET_BITCLR ((volatile uint32_t )(0x4000089C))
<>	150:02e0a0aed4ec	476	#define CHIP_RESET_BITTOG ((volatile uint32_t )(0x40000C9C))
<>	150:02e0a0aed4ec	477	#define SWD_PIN_CFG ((volatile uint32_t )(0x400000A0))
<>	150:02e0a0aed4ec	478	#define SWD_PIN_CFG_BITSET ((volatile uint32_t )(0x400004A0))
<>	150:02e0a0aed4ec	479	#define SWD_PIN_CFG_BITCLR ((volatile uint32_t )(0x400008A0))
<>	150:02e0a0aed4ec	480	#define SWD_PIN_CFG_BITTOG ((volatile uint32_t )(0x40000CA0))
<>	150:02e0a0aed4ec	481
<>	150:02e0a0aed4ec	482	/******************************************************************************/
<>	150:02e0a0aed4ec	483	/* Peripheral declaration */
<>	150:02e0a0aed4ec	484	/******************************************************************************/
<>	150:02e0a0aed4ec	485
<>	150:02e0a0aed4ec	486	/* UART Defines */
<>	150:02e0a0aed4ec	487	#define UART0_BASE 0x50003000
<>	150:02e0a0aed4ec	488	#define UART1_BASE 0x50004000
<>	150:02e0a0aed4ec	489
<>	150:02e0a0aed4ec	490	#ifdef __cplusplus
<>	150:02e0a0aed4ec	491	}
<>	150:02e0a0aed4ec	492	#endif
<>	150:02e0a0aed4ec	493
<>	150:02e0a0aed4ec	494	#endif /* HI2110_H */

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Type:	Library
Created:	07 Nov 2017
Imports:	14
Forks:	0
Commits:	178
Dependents:	1
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targets/TARGET_ublox/TARGET_HI2110/device/hi2110.h@177:619788de047e, 2017-11-07 (annotated)

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