Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
172:7d866c31b3c5 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /* mbed Microcontroller Library
AnnaBridge 172:7d866c31b3c5 2 * Copyright (c) 2015-2016 Nuvoton
AnnaBridge 172:7d866c31b3c5 3 *
AnnaBridge 172:7d866c31b3c5 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 172:7d866c31b3c5 5 * you may not use this file except in compliance with the License.
AnnaBridge 172:7d866c31b3c5 6 * You may obtain a copy of the License at
AnnaBridge 172:7d866c31b3c5 7 *
AnnaBridge 172:7d866c31b3c5 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 172:7d866c31b3c5 9 *
AnnaBridge 172:7d866c31b3c5 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 172:7d866c31b3c5 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 172:7d866c31b3c5 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 172:7d866c31b3c5 13 * See the License for the specific language governing permissions and
AnnaBridge 172:7d866c31b3c5 14 * limitations under the License.
AnnaBridge 172:7d866c31b3c5 15 */
AnnaBridge 172:7d866c31b3c5 16
AnnaBridge 172:7d866c31b3c5 17 #include "us_ticker_api.h"
AnnaBridge 172:7d866c31b3c5 18 #include "sleep_api.h"
AnnaBridge 172:7d866c31b3c5 19 #include "mbed_assert.h"
AnnaBridge 172:7d866c31b3c5 20 #include "nu_modutil.h"
AnnaBridge 172:7d866c31b3c5 21 #include "nu_miscutil.h"
AnnaBridge 172:7d866c31b3c5 22 #include "mbed_critical.h"
AnnaBridge 172:7d866c31b3c5 23
AnnaBridge 172:7d866c31b3c5 24 // us_ticker tick = us = timestamp
AnnaBridge 172:7d866c31b3c5 25 #define US_PER_TICK 1
AnnaBridge 172:7d866c31b3c5 26 #define US_PER_SEC (1000 * 1000)
AnnaBridge 172:7d866c31b3c5 27
AnnaBridge 172:7d866c31b3c5 28 #define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
AnnaBridge 172:7d866c31b3c5 29 #define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
AnnaBridge 172:7d866c31b3c5 30
AnnaBridge 172:7d866c31b3c5 31 #define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
AnnaBridge 172:7d866c31b3c5 32 #define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
AnnaBridge 172:7d866c31b3c5 33
AnnaBridge 172:7d866c31b3c5 34 #define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
AnnaBridge 172:7d866c31b3c5 35 #define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
AnnaBridge 172:7d866c31b3c5 36
AnnaBridge 172:7d866c31b3c5 37
AnnaBridge 172:7d866c31b3c5 38 static void tmr0_vec(void);
AnnaBridge 172:7d866c31b3c5 39 static void tmr1_vec(void);
AnnaBridge 172:7d866c31b3c5 40 static void us_ticker_arm_cd(void);
AnnaBridge 172:7d866c31b3c5 41
AnnaBridge 172:7d866c31b3c5 42 static int us_ticker_inited = 0;
AnnaBridge 172:7d866c31b3c5 43 static volatile uint32_t counter_major = 0;
AnnaBridge 172:7d866c31b3c5 44 static volatile uint32_t cd_major_minor_us = 0;
AnnaBridge 172:7d866c31b3c5 45 static volatile uint32_t cd_minor_us = 0;
AnnaBridge 172:7d866c31b3c5 46
AnnaBridge 172:7d866c31b3c5 47 // NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
AnnaBridge 172:7d866c31b3c5 48 // NOTE: Choose clock source of timer:
AnnaBridge 172:7d866c31b3c5 49 // 1. HIRC: Be the most accurate but might cause unknown HardFault.
AnnaBridge 172:7d866c31b3c5 50 // 2. HXT: Less accurate and cannot pass mbed-drivers test.
AnnaBridge 172:7d866c31b3c5 51 // 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
AnnaBridge 172:7d866c31b3c5 52 // NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
AnnaBridge 172:7d866c31b3c5 53 static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
AnnaBridge 172:7d866c31b3c5 54 static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
AnnaBridge 172:7d866c31b3c5 55
AnnaBridge 172:7d866c31b3c5 56 #define TMR_CMP_MIN 2
AnnaBridge 172:7d866c31b3c5 57 #define TMR_CMP_MAX 0xFFFFFFu
AnnaBridge 172:7d866c31b3c5 58
AnnaBridge 172:7d866c31b3c5 59 void us_ticker_init(void)
AnnaBridge 172:7d866c31b3c5 60 {
AnnaBridge 172:7d866c31b3c5 61 if (us_ticker_inited) {
AnnaBridge 172:7d866c31b3c5 62 return;
AnnaBridge 172:7d866c31b3c5 63 }
AnnaBridge 172:7d866c31b3c5 64
AnnaBridge 172:7d866c31b3c5 65 counter_major = 0;
AnnaBridge 172:7d866c31b3c5 66 cd_major_minor_us = 0;
AnnaBridge 172:7d866c31b3c5 67 cd_minor_us = 0;
AnnaBridge 172:7d866c31b3c5 68 us_ticker_inited = 1;
AnnaBridge 172:7d866c31b3c5 69
AnnaBridge 172:7d866c31b3c5 70 // Reset IP
AnnaBridge 172:7d866c31b3c5 71 SYS_ResetModule(timer0hires_modinit.rsetidx);
AnnaBridge 172:7d866c31b3c5 72 SYS_ResetModule(timer1hires_modinit.rsetidx);
AnnaBridge 172:7d866c31b3c5 73
AnnaBridge 172:7d866c31b3c5 74 // Select IP clock source
AnnaBridge 172:7d866c31b3c5 75 CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
AnnaBridge 172:7d866c31b3c5 76 CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
AnnaBridge 172:7d866c31b3c5 77 // Enable IP clock
AnnaBridge 172:7d866c31b3c5 78 CLK_EnableModuleClock(timer0hires_modinit.clkidx);
AnnaBridge 172:7d866c31b3c5 79 CLK_EnableModuleClock(timer1hires_modinit.clkidx);
AnnaBridge 172:7d866c31b3c5 80
AnnaBridge 172:7d866c31b3c5 81 // Timer for normal counter
AnnaBridge 172:7d866c31b3c5 82 uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 83 uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
AnnaBridge 172:7d866c31b3c5 84 MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
AnnaBridge 172:7d866c31b3c5 85 MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
AnnaBridge 172:7d866c31b3c5 86 uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
AnnaBridge 172:7d866c31b3c5 87 MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
AnnaBridge 172:7d866c31b3c5 88 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
AnnaBridge 172:7d866c31b3c5 89 ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
AnnaBridge 172:7d866c31b3c5 90 ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
AnnaBridge 172:7d866c31b3c5 91
AnnaBridge 172:7d866c31b3c5 92 NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
AnnaBridge 172:7d866c31b3c5 93 NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var);
AnnaBridge 172:7d866c31b3c5 94
AnnaBridge 172:7d866c31b3c5 95 NVIC_EnableIRQ(timer0hires_modinit.irq_n);
AnnaBridge 172:7d866c31b3c5 96 NVIC_EnableIRQ(timer1hires_modinit.irq_n);
AnnaBridge 172:7d866c31b3c5 97
AnnaBridge 172:7d866c31b3c5 98 TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 99 TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 100 }
AnnaBridge 172:7d866c31b3c5 101
AnnaBridge 172:7d866c31b3c5 102 uint32_t us_ticker_read()
AnnaBridge 172:7d866c31b3c5 103 {
AnnaBridge 172:7d866c31b3c5 104 if (! us_ticker_inited) {
AnnaBridge 172:7d866c31b3c5 105 us_ticker_init();
AnnaBridge 172:7d866c31b3c5 106 }
AnnaBridge 172:7d866c31b3c5 107
AnnaBridge 172:7d866c31b3c5 108 TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
AnnaBridge 172:7d866c31b3c5 109
AnnaBridge 172:7d866c31b3c5 110 do {
AnnaBridge 172:7d866c31b3c5 111 uint32_t major_minor_us;
AnnaBridge 172:7d866c31b3c5 112 uint32_t minor_us;
AnnaBridge 172:7d866c31b3c5 113
AnnaBridge 172:7d866c31b3c5 114 // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
AnnaBridge 172:7d866c31b3c5 115 // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
AnnaBridge 172:7d866c31b3c5 116 do {
AnnaBridge 172:7d866c31b3c5 117 core_util_critical_section_enter();
AnnaBridge 172:7d866c31b3c5 118
AnnaBridge 172:7d866c31b3c5 119 // NOTE: Order of reading minor_us/carry here is significant.
AnnaBridge 172:7d866c31b3c5 120 minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
AnnaBridge 172:7d866c31b3c5 121 uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
AnnaBridge 172:7d866c31b3c5 122 // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
AnnaBridge 172:7d866c31b3c5 123 if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
AnnaBridge 172:7d866c31b3c5 124 major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
AnnaBridge 172:7d866c31b3c5 125 } else {
AnnaBridge 172:7d866c31b3c5 126 major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
AnnaBridge 172:7d866c31b3c5 127 }
AnnaBridge 172:7d866c31b3c5 128
AnnaBridge 172:7d866c31b3c5 129 core_util_critical_section_exit();
AnnaBridge 172:7d866c31b3c5 130 } while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
AnnaBridge 172:7d866c31b3c5 131
AnnaBridge 172:7d866c31b3c5 132 return (major_minor_us / US_PER_TICK);
AnnaBridge 172:7d866c31b3c5 133 } while (0);
AnnaBridge 172:7d866c31b3c5 134 }
AnnaBridge 172:7d866c31b3c5 135
AnnaBridge 172:7d866c31b3c5 136 void us_ticker_disable_interrupt(void)
AnnaBridge 172:7d866c31b3c5 137 {
AnnaBridge 172:7d866c31b3c5 138 TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 139 }
AnnaBridge 172:7d866c31b3c5 140
AnnaBridge 172:7d866c31b3c5 141 void us_ticker_clear_interrupt(void)
AnnaBridge 172:7d866c31b3c5 142 {
AnnaBridge 172:7d866c31b3c5 143 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 144 }
AnnaBridge 172:7d866c31b3c5 145
AnnaBridge 172:7d866c31b3c5 146 void us_ticker_set_interrupt(timestamp_t timestamp)
AnnaBridge 172:7d866c31b3c5 147 {
AnnaBridge 172:7d866c31b3c5 148 TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 149
AnnaBridge 172:7d866c31b3c5 150 int delta = (int) (timestamp - us_ticker_read());
AnnaBridge 172:7d866c31b3c5 151 if (delta > 0) {
AnnaBridge 172:7d866c31b3c5 152 cd_major_minor_us = delta * US_PER_TICK;
AnnaBridge 172:7d866c31b3c5 153 us_ticker_arm_cd();
AnnaBridge 172:7d866c31b3c5 154 } else {
AnnaBridge 172:7d866c31b3c5 155 // NOTE: With us_ticker_fire_interrupt() introduced, upper layer would handle past event case.
AnnaBridge 172:7d866c31b3c5 156 // This code fragment gets redundant, but it is still kept here for backward-compatible.
AnnaBridge 172:7d866c31b3c5 157 void us_ticker_fire_interrupt(void);
AnnaBridge 172:7d866c31b3c5 158 us_ticker_fire_interrupt();
AnnaBridge 172:7d866c31b3c5 159 }
AnnaBridge 172:7d866c31b3c5 160 }
AnnaBridge 172:7d866c31b3c5 161
AnnaBridge 172:7d866c31b3c5 162 void us_ticker_fire_interrupt(void)
AnnaBridge 172:7d866c31b3c5 163 {
AnnaBridge 172:7d866c31b3c5 164 // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
AnnaBridge 172:7d866c31b3c5 165 // This prevents a recursive loop under heavy load which can lead to a stack overflow.
AnnaBridge 172:7d866c31b3c5 166 cd_major_minor_us = cd_minor_us = 0;
AnnaBridge 172:7d866c31b3c5 167 NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
AnnaBridge 172:7d866c31b3c5 168 }
AnnaBridge 172:7d866c31b3c5 169
AnnaBridge 172:7d866c31b3c5 170 static void tmr0_vec(void)
AnnaBridge 172:7d866c31b3c5 171 {
AnnaBridge 172:7d866c31b3c5 172 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 173 counter_major ++;
AnnaBridge 172:7d866c31b3c5 174 }
AnnaBridge 172:7d866c31b3c5 175
AnnaBridge 172:7d866c31b3c5 176 static void tmr1_vec(void)
AnnaBridge 172:7d866c31b3c5 177 {
AnnaBridge 172:7d866c31b3c5 178 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 179 cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
AnnaBridge 172:7d866c31b3c5 180 if (cd_major_minor_us == 0) {
AnnaBridge 172:7d866c31b3c5 181 // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
AnnaBridge 172:7d866c31b3c5 182 us_ticker_irq_handler();
AnnaBridge 172:7d866c31b3c5 183 } else {
AnnaBridge 172:7d866c31b3c5 184 us_ticker_arm_cd();
AnnaBridge 172:7d866c31b3c5 185 }
AnnaBridge 172:7d866c31b3c5 186 }
AnnaBridge 172:7d866c31b3c5 187
AnnaBridge 172:7d866c31b3c5 188 static void us_ticker_arm_cd(void)
AnnaBridge 172:7d866c31b3c5 189 {
AnnaBridge 172:7d866c31b3c5 190 TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname);
AnnaBridge 172:7d866c31b3c5 191
AnnaBridge 172:7d866c31b3c5 192 cd_minor_us = cd_major_minor_us;
AnnaBridge 172:7d866c31b3c5 193
AnnaBridge 172:7d866c31b3c5 194 // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
AnnaBridge 172:7d866c31b3c5 195 // NUC472/M451: See TIMER_CTL_RSTCNT_Msk
AnnaBridge 172:7d866c31b3c5 196 // M480
AnnaBridge 172:7d866c31b3c5 197 timer1_base->CNT = 0;
AnnaBridge 172:7d866c31b3c5 198 while (timer1_base->CNT & TIMER_CNT_RSTACT_Msk);
AnnaBridge 172:7d866c31b3c5 199 // One-shot mode, Clock = 1 MHz
AnnaBridge 172:7d866c31b3c5 200 uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
AnnaBridge 172:7d866c31b3c5 201 uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1;
AnnaBridge 172:7d866c31b3c5 202 MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
AnnaBridge 172:7d866c31b3c5 203 MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0);
AnnaBridge 172:7d866c31b3c5 204 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
AnnaBridge 172:7d866c31b3c5 205 timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
AnnaBridge 172:7d866c31b3c5 206 timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/;
AnnaBridge 172:7d866c31b3c5 207
AnnaBridge 172:7d866c31b3c5 208 uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK;
AnnaBridge 172:7d866c31b3c5 209 cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
AnnaBridge 172:7d866c31b3c5 210 timer1_base->CMP = cmp_timer1;
AnnaBridge 172:7d866c31b3c5 211
AnnaBridge 172:7d866c31b3c5 212 TIMER_EnableInt(timer1_base);
AnnaBridge 172:7d866c31b3c5 213 TIMER_Start(timer1_base);
AnnaBridge 172:7d866c31b3c5 214 }