Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.c@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Watchdog Timer 2 Function Implementations.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5 /* *****************************************************************************
<> 157:ff67d9f36b67 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 7 *
<> 157:ff67d9f36b67 8 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 9 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 10 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 12 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 13 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 14 *
<> 157:ff67d9f36b67 15 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 16 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 17 *
<> 157:ff67d9f36b67 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 24 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 29 *
<> 157:ff67d9f36b67 30 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 31 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 32 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 34 * ownership rights.
<> 157:ff67d9f36b67 35 *
<> 157:ff67d9f36b67 36 * $Date: 2016-09-08 17:06:34 -0500 (Thu, 08 Sep 2016) $
<> 157:ff67d9f36b67 37 * $Revision: 24320 $
<> 157:ff67d9f36b67 38 *
<> 157:ff67d9f36b67 39 **************************************************************************** */
<> 157:ff67d9f36b67 40
<> 157:ff67d9f36b67 41 /* **** Includes **** */
<> 157:ff67d9f36b67 42 #include <stddef.h>
<> 157:ff67d9f36b67 43 #include "wdt2.h"
<> 157:ff67d9f36b67 44 #include "pwrseq_regs.h"
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /**
<> 157:ff67d9f36b67 47 * @ingroup wdt2
<> 157:ff67d9f36b67 48 * @{
<> 157:ff67d9f36b67 49 */
<> 157:ff67d9f36b67 50 static uint32_t interruptEnable = 0; //keeps track to interrupts to enable in start function
<> 157:ff67d9f36b67 51
<> 157:ff67d9f36b67 52 /* ************************************************************************* */
<> 157:ff67d9f36b67 53 int WDT2_Init(uint8_t runInSleep, uint8_t unlock_key)
<> 157:ff67d9f36b67 54 {
<> 157:ff67d9f36b67 55 //enable nanoring in run and sleep mode
<> 157:ff67d9f36b67 56 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN);
<> 157:ff67d9f36b67 57
<> 157:ff67d9f36b67 58 //unlock ctrl to be writable
<> 157:ff67d9f36b67 59 MXC_WDT2->lock_ctrl = unlock_key;
<> 157:ff67d9f36b67 60
<> 157:ff67d9f36b67 61 //check to make sure it unlocked
<> 157:ff67d9f36b67 62 if (MXC_WDT2->lock_ctrl & 0x01)
<> 157:ff67d9f36b67 63 return E_BAD_STATE;
<> 157:ff67d9f36b67 64
<> 157:ff67d9f36b67 65 //disable all interrupts
<> 157:ff67d9f36b67 66 interruptEnable = 0;
<> 157:ff67d9f36b67 67 MXC_WDT2->enable = interruptEnable;
<> 157:ff67d9f36b67 68
<> 157:ff67d9f36b67 69 //enable the watchdog clock and clear all other settings
<> 157:ff67d9f36b67 70 MXC_WDT2->ctrl = (MXC_F_WDT2_CTRL_EN_CLOCK);
<> 157:ff67d9f36b67 71
<> 157:ff67d9f36b67 72 //clear all interrupt flags
<> 157:ff67d9f36b67 73 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
<> 157:ff67d9f36b67 74
<> 157:ff67d9f36b67 75 if(runInSleep) {
<> 157:ff67d9f36b67 76 // turn on nanoring during sleep
<> 157:ff67d9f36b67 77 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_SLP);
<> 157:ff67d9f36b67 78 //turn on timer during sleep
<> 157:ff67d9f36b67 79 MXC_WDT2->ctrl |= MXC_F_WDT2_CTRL_EN_TIMER_SLP;
<> 157:ff67d9f36b67 80 } else {
<> 157:ff67d9f36b67 81 // turn off nanoring during sleep
<> 157:ff67d9f36b67 82 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_NREN_SLP);
<> 157:ff67d9f36b67 83 //turn off timer during sleep
<> 157:ff67d9f36b67 84 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER_SLP);
<> 157:ff67d9f36b67 85 }
<> 157:ff67d9f36b67 86
<> 157:ff67d9f36b67 87 //lock ctrl to read-only
<> 157:ff67d9f36b67 88 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90 return E_NO_ERROR;
<> 157:ff67d9f36b67 91 }
<> 157:ff67d9f36b67 92
<> 157:ff67d9f36b67 93 /* ************************************************************************* */
<> 157:ff67d9f36b67 94 int WDT2_EnableWakeUp(wdt2_period_t int_period, uint8_t unlock_key)
<> 157:ff67d9f36b67 95 {
<> 157:ff67d9f36b67 96 // Make sure interrupt period is valid
<> 157:ff67d9f36b67 97 if (int_period >= WDT2_PERIOD_MAX)
<> 157:ff67d9f36b67 98 return E_INVALID;
<> 157:ff67d9f36b67 99
<> 157:ff67d9f36b67 100 //unlock ctrl to be writable
<> 157:ff67d9f36b67 101 MXC_WDT2->lock_ctrl = unlock_key;
<> 157:ff67d9f36b67 102
<> 157:ff67d9f36b67 103 //check to make sure it unlocked
<> 157:ff67d9f36b67 104 if (MXC_WDT2->lock_ctrl & 0x01)
<> 157:ff67d9f36b67 105 return E_BAD_STATE;
<> 157:ff67d9f36b67 106
<> 157:ff67d9f36b67 107 //stop timer and clear interval period
<> 157:ff67d9f36b67 108 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_INT_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER);
<> 157:ff67d9f36b67 109
<> 157:ff67d9f36b67 110 //set interval period
<> 157:ff67d9f36b67 111 MXC_WDT2->ctrl |= (int_period << MXC_F_WDT2_CTRL_INT_PERIOD_POS);
<> 157:ff67d9f36b67 112
<> 157:ff67d9f36b67 113 //enable timeout wake-up
<> 157:ff67d9f36b67 114 interruptEnable |= MXC_F_WDT2_ENABLE_TIMEOUT;
<> 157:ff67d9f36b67 115
<> 157:ff67d9f36b67 116 //lock ctrl to read-only
<> 157:ff67d9f36b67 117 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 157:ff67d9f36b67 118
<> 157:ff67d9f36b67 119 // Enable wake-up
<> 157:ff67d9f36b67 120 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG;
<> 157:ff67d9f36b67 121
<> 157:ff67d9f36b67 122 return E_NO_ERROR;
<> 157:ff67d9f36b67 123 }
<> 157:ff67d9f36b67 124
<> 157:ff67d9f36b67 125 /* ************************************************************************* */
<> 157:ff67d9f36b67 126 int WDT2_DisableWakeUp(uint8_t unlock_key)
<> 157:ff67d9f36b67 127 {
<> 157:ff67d9f36b67 128 //unlock register to be writable
<> 157:ff67d9f36b67 129 MXC_WDT2->lock_ctrl = unlock_key;
<> 157:ff67d9f36b67 130
<> 157:ff67d9f36b67 131 //check to make sure it unlocked
<> 157:ff67d9f36b67 132 if (MXC_WDT2->lock_ctrl & 0x01)
<> 157:ff67d9f36b67 133 return E_BAD_STATE;
<> 157:ff67d9f36b67 134
<> 157:ff67d9f36b67 135 //disable timeout wake-up
<> 157:ff67d9f36b67 136 interruptEnable &= ~MXC_F_WDT2_ENABLE_TIMEOUT;
<> 157:ff67d9f36b67 137 MXC_WDT2->enable = interruptEnable;
<> 157:ff67d9f36b67 138
<> 157:ff67d9f36b67 139 //lock register to read-only
<> 157:ff67d9f36b67 140 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 157:ff67d9f36b67 141
<> 157:ff67d9f36b67 142 // disable wake-up
<> 157:ff67d9f36b67 143 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG;
<> 157:ff67d9f36b67 144
<> 157:ff67d9f36b67 145 return E_NO_ERROR;
<> 157:ff67d9f36b67 146 }
<> 157:ff67d9f36b67 147
<> 157:ff67d9f36b67 148 /* ************************************************************************* */
<> 157:ff67d9f36b67 149 int WDT2_EnableReset(wdt2_period_t rst_period, uint8_t unlock_key)
<> 157:ff67d9f36b67 150 {
<> 157:ff67d9f36b67 151 // Make sure reset period is valid
<> 157:ff67d9f36b67 152 if (rst_period >= WDT2_PERIOD_MAX)
<> 157:ff67d9f36b67 153 return E_INVALID;
<> 157:ff67d9f36b67 154
<> 157:ff67d9f36b67 155 //unlock ctrl to be writable
<> 157:ff67d9f36b67 156 MXC_WDT2->lock_ctrl = unlock_key;
<> 157:ff67d9f36b67 157
<> 157:ff67d9f36b67 158 //check to make sure it unlocked
<> 157:ff67d9f36b67 159 if (MXC_WDT2->lock_ctrl & 0x01)
<> 157:ff67d9f36b67 160 return E_BAD_STATE;
<> 157:ff67d9f36b67 161
<> 157:ff67d9f36b67 162 //stop timer and clear reset period
<> 157:ff67d9f36b67 163 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_RST_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER);
<> 157:ff67d9f36b67 164
<> 157:ff67d9f36b67 165 //set reset period
<> 157:ff67d9f36b67 166 MXC_WDT2->ctrl |= (rst_period << MXC_F_WDT2_CTRL_RST_PERIOD_POS);
<> 157:ff67d9f36b67 167
<> 157:ff67d9f36b67 168 //int flag has to be clear before interrupt enable can be written
<> 157:ff67d9f36b67 169 MXC_WDT2->flags = MXC_F_WDT2_FLAGS_RESET_OUT;
<> 157:ff67d9f36b67 170
<> 157:ff67d9f36b67 171 //enable reset0
<> 157:ff67d9f36b67 172 interruptEnable |= MXC_F_WDT2_ENABLE_RESET_OUT;
<> 157:ff67d9f36b67 173
<> 157:ff67d9f36b67 174 //lock ctrl to read-only
<> 157:ff67d9f36b67 175 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 157:ff67d9f36b67 176
<> 157:ff67d9f36b67 177 //enable RSTN on WDT2 reset
<> 157:ff67d9f36b67 178 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG;
<> 157:ff67d9f36b67 179
<> 157:ff67d9f36b67 180 return E_NO_ERROR;
<> 157:ff67d9f36b67 181 }
<> 157:ff67d9f36b67 182
<> 157:ff67d9f36b67 183 /* ************************************************************************* */
<> 157:ff67d9f36b67 184 int WDT2_DisableReset(uint8_t unlock_key)
<> 157:ff67d9f36b67 185 {
<> 157:ff67d9f36b67 186 //unlock register to be writable
<> 157:ff67d9f36b67 187 MXC_WDT2->lock_ctrl = unlock_key;
<> 157:ff67d9f36b67 188
<> 157:ff67d9f36b67 189 //check to make sure it unlocked
<> 157:ff67d9f36b67 190 if (MXC_WDT2->lock_ctrl & 0x01)
<> 157:ff67d9f36b67 191 return E_BAD_STATE;
<> 157:ff67d9f36b67 192
<> 157:ff67d9f36b67 193 //disable reset
<> 157:ff67d9f36b67 194 interruptEnable &= ~MXC_F_WDT2_ENABLE_RESET_OUT;
<> 157:ff67d9f36b67 195 MXC_WDT2->enable = interruptEnable;
<> 157:ff67d9f36b67 196
<> 157:ff67d9f36b67 197 //lock register to read-only
<> 157:ff67d9f36b67 198 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 157:ff67d9f36b67 199
<> 157:ff67d9f36b67 200 //disable RSTN on WDT2 reset
<> 157:ff67d9f36b67 201 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG;
<> 157:ff67d9f36b67 202
<> 157:ff67d9f36b67 203 return E_NO_ERROR;
<> 157:ff67d9f36b67 204 }
<> 157:ff67d9f36b67 205
<> 157:ff67d9f36b67 206 /* ************************************************************************* */
<> 157:ff67d9f36b67 207 int WDT2_Start(uint8_t unlock_key)
<> 157:ff67d9f36b67 208 {
<> 157:ff67d9f36b67 209 //check if watchdog is already running
<> 157:ff67d9f36b67 210 if(WDT2_IsActive())
<> 157:ff67d9f36b67 211 return E_BAD_STATE;
<> 157:ff67d9f36b67 212
<> 157:ff67d9f36b67 213 //unlock ctrl to be writable
<> 157:ff67d9f36b67 214 MXC_WDT2->lock_ctrl = unlock_key;
<> 157:ff67d9f36b67 215
<> 157:ff67d9f36b67 216 //check to make sure it unlocked
<> 157:ff67d9f36b67 217 if (MXC_WDT2->lock_ctrl & 0x01)
<> 157:ff67d9f36b67 218 return E_BAD_STATE;
<> 157:ff67d9f36b67 219
<> 157:ff67d9f36b67 220 WDT2_Reset();
<> 157:ff67d9f36b67 221
<> 157:ff67d9f36b67 222 //enable interrupts
<> 157:ff67d9f36b67 223 MXC_WDT2->enable = interruptEnable;
<> 157:ff67d9f36b67 224
<> 157:ff67d9f36b67 225 //start timer
<> 157:ff67d9f36b67 226 MXC_WDT2->ctrl |= (MXC_F_WDT2_CTRL_EN_TIMER);
<> 157:ff67d9f36b67 227
<> 157:ff67d9f36b67 228 //lock ctrl to read-only
<> 157:ff67d9f36b67 229 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 157:ff67d9f36b67 230
<> 157:ff67d9f36b67 231 return E_NO_ERROR;
<> 157:ff67d9f36b67 232 }
<> 157:ff67d9f36b67 233
<> 157:ff67d9f36b67 234 /* ************************************************************************* */
<> 157:ff67d9f36b67 235 void WDT2_Reset(void)
<> 157:ff67d9f36b67 236 {
<> 157:ff67d9f36b67 237 //reset the watchdog counter
<> 157:ff67d9f36b67 238 MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_0;
<> 157:ff67d9f36b67 239 MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_1;
<> 157:ff67d9f36b67 240
<> 157:ff67d9f36b67 241 //clear all interrupt flags
<> 157:ff67d9f36b67 242 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
<> 157:ff67d9f36b67 243
<> 157:ff67d9f36b67 244 //wait for all interrupts to clear
<> 157:ff67d9f36b67 245 while(MXC_WDT2->flags != 0) {
<> 157:ff67d9f36b67 246 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
<> 157:ff67d9f36b67 247 }
<> 157:ff67d9f36b67 248
<> 157:ff67d9f36b67 249 return;
<> 157:ff67d9f36b67 250 }
<> 157:ff67d9f36b67 251
<> 157:ff67d9f36b67 252 /* ************************************************************************* */
<> 157:ff67d9f36b67 253 int WDT2_Stop(uint8_t unlock_key)
<> 157:ff67d9f36b67 254 {
<> 157:ff67d9f36b67 255 //check if watchdog is not running
<> 157:ff67d9f36b67 256 if(!WDT2_IsActive())
<> 157:ff67d9f36b67 257 return E_BAD_STATE;
<> 157:ff67d9f36b67 258
<> 157:ff67d9f36b67 259 //unlock ctrl to be writable
<> 157:ff67d9f36b67 260 MXC_WDT2->lock_ctrl = unlock_key;
<> 157:ff67d9f36b67 261
<> 157:ff67d9f36b67 262 //check to make sure it unlocked
<> 157:ff67d9f36b67 263 if (MXC_WDT2->lock_ctrl & 0x01)
<> 157:ff67d9f36b67 264 return E_BAD_STATE;
<> 157:ff67d9f36b67 265
<> 157:ff67d9f36b67 266 //disabled the timer and interrupts
<> 157:ff67d9f36b67 267 MXC_WDT2->enable = 0;
<> 157:ff67d9f36b67 268 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER);
<> 157:ff67d9f36b67 269
<> 157:ff67d9f36b67 270 //lock ctrl to read-only
<> 157:ff67d9f36b67 271 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 157:ff67d9f36b67 272
<> 157:ff67d9f36b67 273 return E_NO_ERROR;
<> 157:ff67d9f36b67 274 }
<> 157:ff67d9f36b67 275 /**@} end of group wdt2*/