Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

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<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the SPI Master module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5 /* ****************************************************************************
<> 157:ff67d9f36b67 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 7 *
<> 157:ff67d9f36b67 8 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 9 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 10 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 12 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 13 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 14 *
<> 157:ff67d9f36b67 15 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 16 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 17 *
<> 157:ff67d9f36b67 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 24 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 29 *
<> 157:ff67d9f36b67 30 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 31 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 32 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 34 * ownership rights.
<> 157:ff67d9f36b67 35 *
<> 157:ff67d9f36b67 36 * $Date: 2016-10-10 19:42:44 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 37 * $Revision: 24672 $
<> 157:ff67d9f36b67 38 *
<> 157:ff67d9f36b67 39 **************************************************************************** */
<> 157:ff67d9f36b67 40
<> 157:ff67d9f36b67 41 /* **** Includes **** */
<> 157:ff67d9f36b67 42 #include "mxc_config.h"
<> 157:ff67d9f36b67 43 #include "mxc_sys.h"
<> 157:ff67d9f36b67 44 #include "spim_regs.h"
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 47 #ifndef _SPIM_H_
<> 157:ff67d9f36b67 48 #define _SPIM_H_
<> 157:ff67d9f36b67 49
<> 157:ff67d9f36b67 50 #ifdef __cplusplus
<> 157:ff67d9f36b67 51 extern "C" {
<> 157:ff67d9f36b67 52 #endif
<> 157:ff67d9f36b67 53 /**
<> 157:ff67d9f36b67 54 * @ingroup commperipherals
<> 157:ff67d9f36b67 55 * @defgroup spi_comm SPI
<> 157:ff67d9f36b67 56 * @brief SPI Master and Slave Communication Peripherals
<> 157:ff67d9f36b67 57 */
<> 157:ff67d9f36b67 58
<> 157:ff67d9f36b67 59 /**
<> 157:ff67d9f36b67 60 * @ingroup spi_comm
<> 157:ff67d9f36b67 61 * @defgroup spim SPI Master
<> 157:ff67d9f36b67 62 * @brief Serial Peripheral Interface Master (SPIM) Communications
<> 157:ff67d9f36b67 63 * Interface.
<> 157:ff67d9f36b67 64 * @{
<> 157:ff67d9f36b67 65 */
<> 157:ff67d9f36b67 66
<> 157:ff67d9f36b67 67 /* **** Definitions **** */
<> 157:ff67d9f36b67 68
<> 157:ff67d9f36b67 69 /**
<> 157:ff67d9f36b67 70 * Enumeration type for selecting the active levels for the SPI Master Slave Select (SS) lines.
<> 157:ff67d9f36b67 71 */
<> 157:ff67d9f36b67 72 typedef enum {
<> 157:ff67d9f36b67 73 SPIM_SSEL0_HIGH = (0x1 << 0), /**< Slave Select 0 High. */
<> 157:ff67d9f36b67 74 SPIM_SSEL0_LOW = 0, /**< Slave Select 0 Low. */
<> 157:ff67d9f36b67 75 SPIM_SSEL1_HIGH = (0x1 << 1), /**< Slave Select 1 High. */
<> 157:ff67d9f36b67 76 SPIM_SSEL1_LOW = 0, /**< Slave Select 1 Low. */
<> 157:ff67d9f36b67 77 SPIM_SSEL2_HIGH = (0x1 << 2), /**< Slave Select 2 High. */
<> 157:ff67d9f36b67 78 SPIM_SSEL2_LOW = 0, /**< Slave Select 2 Low. */
<> 157:ff67d9f36b67 79 SPIM_SSEL3_HIGH = (0x1 << 3), /**< Slave Select 3 High. */
<> 157:ff67d9f36b67 80 SPIM_SSEL3_LOW = 0, /**< Slave Select 3 Low. */
<> 157:ff67d9f36b67 81 SPIM_SSEL4_HIGH = (0x1 << 4), /**< Slave Select 4 High. */
<> 157:ff67d9f36b67 82 SPIM_SSEL4_LOW = 0 /**< Slave Select 4 Low. */
<> 157:ff67d9f36b67 83 }
<> 157:ff67d9f36b67 84 spim_ssel_t;
<> 157:ff67d9f36b67 85
<> 157:ff67d9f36b67 86 /**
<> 157:ff67d9f36b67 87 * Enumeration type for setting the number data lines to use for communication.
<> 157:ff67d9f36b67 88 */
<> 157:ff67d9f36b67 89 typedef enum {
<> 157:ff67d9f36b67 90 SPIM_WIDTH_1 = 0, /**< 1 Data Line. */
<> 157:ff67d9f36b67 91 SPIM_WIDTH_2 = 1, /**< 2 Data Lines (x2). */
<> 157:ff67d9f36b67 92 SPIM_WIDTH_4 = 2 /**< 4 Data Lines (x4). */
<> 157:ff67d9f36b67 93 } spim_width_t;
<> 157:ff67d9f36b67 94
<> 157:ff67d9f36b67 95 /**
<> 157:ff67d9f36b67 96 * Structure type for configuring a SPIM port.
<> 157:ff67d9f36b67 97 */
<> 157:ff67d9f36b67 98 typedef struct {
<> 157:ff67d9f36b67 99 uint8_t mode; /**< SPIM mode selection, 0 to 3. */
<> 157:ff67d9f36b67 100 uint32_t ssel_pol; /**< Mask of active levels for the slave select signals, see #spim_ssel_t. */
<> 157:ff67d9f36b67 101 uint32_t baud; /**< Baud rate in Hz. */
<> 157:ff67d9f36b67 102 } spim_cfg_t;
<> 157:ff67d9f36b67 103
<> 157:ff67d9f36b67 104 /**
<> 157:ff67d9f36b67 105 * Structure type representing a SPI Master Transaction request.
<> 157:ff67d9f36b67 106 */
<> 157:ff67d9f36b67 107 typedef struct spim_req spim_req_t;
<> 157:ff67d9f36b67 108
<> 157:ff67d9f36b67 109 /**
<> 157:ff67d9f36b67 110 * @brief Callback function type used in asynchromous SPIM communications requests.
<> 157:ff67d9f36b67 111 * @details The function declaration for the SPIM callback is:
<> 157:ff67d9f36b67 112 * @code
<> 157:ff67d9f36b67 113 * void callback(spim_req_t * req, int error_code);
<> 157:ff67d9f36b67 114 * @endcode
<> 157:ff67d9f36b67 115 * | | |
<> 157:ff67d9f36b67 116 * | -----: | :----------------------------------------- |
<> 157:ff67d9f36b67 117 * | \p req | Pointer to a #spim_req object representing the active SPIM active transaction. |
<> 157:ff67d9f36b67 118 * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
<> 157:ff67d9f36b67 119 * @addtogroup spim_async
<> 157:ff67d9f36b67 120 */
<> 157:ff67d9f36b67 121 typedef void (*spim_callback_fn)(spim_req_t * req, int error_code);
<> 157:ff67d9f36b67 122
<> 157:ff67d9f36b67 123 /**
<> 157:ff67d9f36b67 124 * @brief Structure definition for an SPI Master Transaction request.
<> 157:ff67d9f36b67 125 * @note When using this structure for an asynchronous operation, the
<> 157:ff67d9f36b67 126 * structure must remain allocated until the callback is completed.
<> 157:ff67d9f36b67 127 * @addtogroup spim_async
<> 157:ff67d9f36b67 128 */
<> 157:ff67d9f36b67 129 struct spim_req {
<> 157:ff67d9f36b67 130 uint8_t ssel; /**< Number of the Slave Select to use. */
<> 157:ff67d9f36b67 131 uint8_t deass; /**< Set to de-assert slave select at the completions of the transaction.*/
<> 157:ff67d9f36b67 132 const uint8_t *tx_data; /**< Pointer to a buffer to transmit data from. */
<> 157:ff67d9f36b67 133 uint8_t *rx_data; /**< Pointer to a buffer to store data received. */
<> 157:ff67d9f36b67 134 spim_width_t width; /**< Number of data lines to use, see #spim_width_t. */
<> 157:ff67d9f36b67 135 unsigned len; /**< Number of bytes to send from the \p tx_data buffer. */
<> 157:ff67d9f36b67 136 unsigned read_num; /**< Number of bytes read and stored in \p rx_data buffer. */
<> 157:ff67d9f36b67 137 unsigned write_num; /**< Number of bytes sent from the \p tx_data buffer, this will be filled by the driver after up to \p len bytes have been transmitted. */
<> 157:ff67d9f36b67 138 spim_callback_fn callback; /**< Function pointer to a callback function if desired, NULL otherwise */
<> 157:ff67d9f36b67 139 };
<> 157:ff67d9f36b67 140
<> 157:ff67d9f36b67 141 /* **** Globals **** */
<> 157:ff67d9f36b67 142
<> 157:ff67d9f36b67 143 /* **** Function Prototypes **** */
<> 157:ff67d9f36b67 144
<> 157:ff67d9f36b67 145 /**
<> 157:ff67d9f36b67 146 * @brief Initialize the SPIM peripheral module.
<> 157:ff67d9f36b67 147 *
<> 157:ff67d9f36b67 148 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 149 * @param cfg Pointer to an SPIM configuration object.
<> 157:ff67d9f36b67 150 * @param sys_cfg Pointer to a system configuration object to select the
<> 157:ff67d9f36b67 151 * peripheral clock rate and assign the requested GPIO.
<> 157:ff67d9f36b67 152 *
<> 157:ff67d9f36b67 153 * @return #E_NO_ERROR if the SPIM port is initialized successfully, @ref MXC_Error_Codes
<> 157:ff67d9f36b67 154 * "error" if unsuccessful.
<> 157:ff67d9f36b67 155 */
<> 157:ff67d9f36b67 156 int SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *cfg, const sys_cfg_spim_t *sys_cfg);
<> 157:ff67d9f36b67 157
<> 157:ff67d9f36b67 158 /**
<> 157:ff67d9f36b67 159 * @brief Shutdown the SPIM peripheral module instance represented by the
<> 157:ff67d9f36b67 160 * @p spim parameter.
<> 157:ff67d9f36b67 161 *
<> 157:ff67d9f36b67 162 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 163 *
<> 157:ff67d9f36b67 164 * @return #E_NO_ERROR if the SPIM is shutdown successfully, @ref
<> 157:ff67d9f36b67 165 * MXC_Error_Codes "error" if unsuccessful.
<> 157:ff67d9f36b67 166 */
<> 157:ff67d9f36b67 167 int SPIM_Shutdown(mxc_spim_regs_t *spim);
<> 157:ff67d9f36b67 168
<> 157:ff67d9f36b67 169 /**
<> 157:ff67d9f36b67 170 * @brief Send Clock cycles on SCK without reading or writing.
<> 157:ff67d9f36b67 171 *
<> 157:ff67d9f36b67 172 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 173 * @param len Number of clock cycles to send.
<> 157:ff67d9f36b67 174 * @param ssel Slave select number.
<> 157:ff67d9f36b67 175 * @param deass De-assert slave select at the end of the transaction.
<> 157:ff67d9f36b67 176 *
<> 157:ff67d9f36b67 177 * @return Cycles transacted if everything is successful, @ref
<> 157:ff67d9f36b67 178 * MXC_Error_Codes "error" if unsuccessful.
<> 157:ff67d9f36b67 179 */
<> 157:ff67d9f36b67 180 int SPIM_Clocks(mxc_spim_regs_t *spim, uint32_t len, uint8_t ssel, uint8_t deass);
<> 157:ff67d9f36b67 181
<> 157:ff67d9f36b67 182 /**
<> 157:ff67d9f36b67 183 * @brief Read/write SPIM data. This function will block until the
<> 157:ff67d9f36b67 184 * transaction is complete.
<> 157:ff67d9f36b67 185 *
<> 157:ff67d9f36b67 186 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 187 * @param req Request for a SPIM transaction.
<> 157:ff67d9f36b67 188 * @note If a callback function is registered it will not be called when using a blocking function.
<> 157:ff67d9f36b67 189 *
<> 157:ff67d9f36b67 190 * @return Bytes transacted if everything is successful, error if
<> 157:ff67d9f36b67 191 * unsuccessful.
<> 157:ff67d9f36b67 192 */
<> 157:ff67d9f36b67 193 int SPIM_Trans(mxc_spim_regs_t *spim, spim_req_t *req);
<> 157:ff67d9f36b67 194 /**
<> 157:ff67d9f36b67 195 * @defgroup spim_async SPIM Asynchrous Functions
<> 157:ff67d9f36b67 196 * @{
<> 157:ff67d9f36b67 197 */
<> 157:ff67d9f36b67 198 /**
<> 157:ff67d9f36b67 199 * @brief Asynchronously read/write SPIM data.
<> 157:ff67d9f36b67 200 *
<> 157:ff67d9f36b67 201 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 202 * @param req Request for a SPIM transaction.
<> 157:ff67d9f36b67 203 * @note Request struct must remain allocated until callback.
<> 157:ff67d9f36b67 204 *
<> 157:ff67d9f36b67 205 * @return #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes
<> 157:ff67d9f36b67 206 * "error" if unsuccessful.
<> 157:ff67d9f36b67 207 */
<> 157:ff67d9f36b67 208 int SPIM_TransAsync(mxc_spim_regs_t *spim, spim_req_t *req);
<> 157:ff67d9f36b67 209
<> 157:ff67d9f36b67 210 /**
<> 157:ff67d9f36b67 211 * @brief Abort asynchronous request.
<> 157:ff67d9f36b67 212 *
<> 157:ff67d9f36b67 213 * @param req Pointer to a request structure for a SPIM transaction.
<> 157:ff67d9f36b67 214 *
<> 157:ff67d9f36b67 215 * @return #E_NO_ERROR if request aborted, , @ref MXC_Error_Codes "error" if
<> 157:ff67d9f36b67 216 * unsuccessful.
<> 157:ff67d9f36b67 217 */
<> 157:ff67d9f36b67 218 int SPIM_AbortAsync(spim_req_t *req);
<> 157:ff67d9f36b67 219
<> 157:ff67d9f36b67 220 /**
<> 157:ff67d9f36b67 221 * @brief SPIM interrupt handler.
<> 157:ff67d9f36b67 222 * @details This function should be called by the application from the
<> 157:ff67d9f36b67 223 * interrupt handler if SPIM interrupts are enabled. Alternately,
<> 157:ff67d9f36b67 224 * this function can be periodically polled by the application if
<> 157:ff67d9f36b67 225 * SPIM interrupts are disabled.
<> 157:ff67d9f36b67 226 *
<> 157:ff67d9f36b67 227 * @param spim Base address of the SPIM module.
<> 157:ff67d9f36b67 228 */
<> 157:ff67d9f36b67 229 void SPIM_Handler(mxc_spim_regs_t *spim);
<> 157:ff67d9f36b67 230
<> 157:ff67d9f36b67 231 /**
<> 157:ff67d9f36b67 232 * @brief Check the SPIM to see if it's busy.
<> 157:ff67d9f36b67 233 *
<> 157:ff67d9f36b67 234 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 235 *
<> 157:ff67d9f36b67 236 * @retval #E_NO_ERROR if idle.
<> 157:ff67d9f36b67 237 * @retval #E_BUSY if in use.
<> 157:ff67d9f36b67 238 */
<> 157:ff67d9f36b67 239 int SPIM_Busy(mxc_spim_regs_t *spim);
<> 157:ff67d9f36b67 240 /**@} end of spim_async define group */
<> 157:ff67d9f36b67 241
<> 157:ff67d9f36b67 242 /**
<> 157:ff67d9f36b67 243 * @brief Attempts to prepare the SPIM for Low Power Sleep Modes.
<> 157:ff67d9f36b67 244 * @details Checks for any ongoing transactions. Disables interrupts if the
<> 157:ff67d9f36b67 245 * SPIM is idle.
<> 157:ff67d9f36b67 246 *
<> 157:ff67d9f36b67 247 * @param spim The spim
<> 157:ff67d9f36b67 248 *
<> 157:ff67d9f36b67 249 * @return #E_NO_ERROR if ready to sleep.
<> 157:ff67d9f36b67 250 * @return #E_BUSY if not able to sleep at this time.
<> 157:ff67d9f36b67 251 */
<> 157:ff67d9f36b67 252 int SPIM_PrepForSleep(mxc_spim_regs_t *spim);
<> 157:ff67d9f36b67 253
<> 157:ff67d9f36b67 254 /**
<> 157:ff67d9f36b67 255 * @brief Enables the SPIM without overwriting the existing configuration.
<> 157:ff67d9f36b67 256 *
<> 157:ff67d9f36b67 257 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 258 */
<> 157:ff67d9f36b67 259 __STATIC_INLINE void SPIM_Enable(mxc_spim_regs_t *spim)
<> 157:ff67d9f36b67 260 {
<> 157:ff67d9f36b67 261 spim->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN |
<> 157:ff67d9f36b67 262 MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN);
<> 157:ff67d9f36b67 263 }
<> 157:ff67d9f36b67 264
<> 157:ff67d9f36b67 265 /**
<> 157:ff67d9f36b67 266 * @brief Drains/empties the data in the RX FIFO.
<> 157:ff67d9f36b67 267 *
<> 157:ff67d9f36b67 268 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 269 */
<> 157:ff67d9f36b67 270 __STATIC_INLINE void SPIM_DrainRX(mxc_spim_regs_t *spim)
<> 157:ff67d9f36b67 271 {
<> 157:ff67d9f36b67 272 uint32_t ctrl_save = spim->gen_ctrl;
<> 157:ff67d9f36b67 273 spim->gen_ctrl = (ctrl_save & ~MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN);
<> 157:ff67d9f36b67 274 spim->gen_ctrl = ctrl_save;
<> 157:ff67d9f36b67 275 }
<> 157:ff67d9f36b67 276
<> 157:ff67d9f36b67 277 /**
<> 157:ff67d9f36b67 278 * @brief Drains/empties the data in the TX FIFO.
<> 157:ff67d9f36b67 279 *
<> 157:ff67d9f36b67 280 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 281 */
<> 157:ff67d9f36b67 282 __STATIC_INLINE void SPIM_DrainTX(mxc_spim_regs_t *spim)
<> 157:ff67d9f36b67 283 {
<> 157:ff67d9f36b67 284 uint32_t ctrl_save = spim->gen_ctrl;
<> 157:ff67d9f36b67 285 spim->gen_ctrl = (ctrl_save & ~MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN);
<> 157:ff67d9f36b67 286 spim->gen_ctrl = ctrl_save;
<> 157:ff67d9f36b67 287 }
<> 157:ff67d9f36b67 288
<> 157:ff67d9f36b67 289 /**
<> 157:ff67d9f36b67 290 * @brief Returns the number of bytes free in the TX FIFO.
<> 157:ff67d9f36b67 291 *
<> 157:ff67d9f36b67 292 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 293 *
<> 157:ff67d9f36b67 294 * @return Number of bytes free in Transmit FIFO.
<> 157:ff67d9f36b67 295 */
<> 157:ff67d9f36b67 296 __STATIC_INLINE unsigned SPIM_NumWriteAvail(mxc_spim_regs_t *spim)
<> 157:ff67d9f36b67 297 {
<> 157:ff67d9f36b67 298 return (MXC_CFG_SPIM_FIFO_DEPTH - ((spim->fifo_ctrl &
<> 157:ff67d9f36b67 299 MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS));
<> 157:ff67d9f36b67 300 }
<> 157:ff67d9f36b67 301
<> 157:ff67d9f36b67 302 /**
<> 157:ff67d9f36b67 303 * @brief Returns the number of bytes available to read in the RX FIFO.
<> 157:ff67d9f36b67 304 *
<> 157:ff67d9f36b67 305 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 306 *
<> 157:ff67d9f36b67 307 * @return Number of bytes in RX FIFO.
<> 157:ff67d9f36b67 308 */
<> 157:ff67d9f36b67 309 __STATIC_INLINE unsigned SPIM_NumReadAvail(mxc_spim_regs_t *spim)
<> 157:ff67d9f36b67 310 {
<> 157:ff67d9f36b67 311 return ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >>
<> 157:ff67d9f36b67 312 MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
<> 157:ff67d9f36b67 313 }
<> 157:ff67d9f36b67 314
<> 157:ff67d9f36b67 315 /**
<> 157:ff67d9f36b67 316 * @brief Clear the SPIM interrupt flags.
<> 157:ff67d9f36b67 317 *
<> 157:ff67d9f36b67 318 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 319 * @param mask Mask of the SPIM interrupt flags to clear, see @ref
<> 157:ff67d9f36b67 320 * SPIM_INTFL_Register Register for the SPIM interrupt flag
<> 157:ff67d9f36b67 321 * bit masks.
<> 157:ff67d9f36b67 322 */
<> 157:ff67d9f36b67 323 __STATIC_INLINE void SPIM_ClearFlags(mxc_spim_regs_t *spim, uint32_t mask)
<> 157:ff67d9f36b67 324 {
<> 157:ff67d9f36b67 325 spim->intfl = mask;
<> 157:ff67d9f36b67 326 }
<> 157:ff67d9f36b67 327
<> 157:ff67d9f36b67 328 /**
<> 157:ff67d9f36b67 329 * @brief Read the current SPIM interrupt flags.
<> 157:ff67d9f36b67 330 *
<> 157:ff67d9f36b67 331 * @param spim Pointer to the SPIM register structure.
<> 157:ff67d9f36b67 332 *
<> 157:ff67d9f36b67 333 * @return Mask of currently set SPIM interrupt flags, see @ref
<> 157:ff67d9f36b67 334 * SPIM_INTFL_Register Register for the SPIM interrupt flag bit
<> 157:ff67d9f36b67 335 * masks.
<> 157:ff67d9f36b67 336 */
<> 157:ff67d9f36b67 337 __STATIC_INLINE unsigned SPIM_GetFlags(mxc_spim_regs_t *spim)
<> 157:ff67d9f36b67 338 {
<> 157:ff67d9f36b67 339 return (spim->intfl);
<> 157:ff67d9f36b67 340 }
<> 157:ff67d9f36b67 341
<> 157:ff67d9f36b67 342 /**@} end of group spim_comm */
<> 157:ff67d9f36b67 343 #ifdef __cplusplus
<> 157:ff67d9f36b67 344 }
<> 157:ff67d9f36b67 345 #endif
<> 157:ff67d9f36b67 346
<> 157:ff67d9f36b67 347 #endif /* _SPIM_H_ */