Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M451/serial_api.c@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Parent:
151:5eaa88a5bcc7
Child:
161:2cc1468da177
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "serial_api.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_SERIAL
<> 149:156823d33999 20
<> 149:156823d33999 21 #include "cmsis.h"
<> 149:156823d33999 22 #include "mbed_error.h"
<> 149:156823d33999 23 #include "mbed_assert.h"
<> 149:156823d33999 24 #include "PeripheralPins.h"
<> 149:156823d33999 25 #include "nu_modutil.h"
<> 149:156823d33999 26 #include "nu_bitutil.h"
<> 149:156823d33999 27
<> 149:156823d33999 28 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 29 #include "dma_api.h"
<> 149:156823d33999 30 #include "dma.h"
<> 149:156823d33999 31 #endif
<> 149:156823d33999 32
<> 149:156823d33999 33 struct nu_uart_var {
<> 151:5eaa88a5bcc7 34 uint32_t ref_cnt; // Reference count of the H/W module
<> 149:156823d33999 35 serial_t * obj;
<> 149:156823d33999 36 uint32_t fifo_size_tx;
<> 149:156823d33999 37 uint32_t fifo_size_rx;
<> 149:156823d33999 38 void (*vec)(void);
<> 149:156823d33999 39 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 40 void (*vec_async)(void);
<> 149:156823d33999 41 uint8_t pdma_perp_tx;
<> 149:156823d33999 42 uint8_t pdma_perp_rx;
<> 149:156823d33999 43 #endif
<> 149:156823d33999 44 };
<> 149:156823d33999 45
<> 149:156823d33999 46 static void uart0_vec(void);
<> 149:156823d33999 47 static void uart1_vec(void);
<> 149:156823d33999 48 static void uart2_vec(void);
<> 149:156823d33999 49 static void uart3_vec(void);
<> 149:156823d33999 50 static void uart_irq(serial_t *obj);
<> 149:156823d33999 51
<> 149:156823d33999 52 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 53 static void uart0_vec_async(void);
<> 149:156823d33999 54 static void uart1_vec_async(void);
<> 149:156823d33999 55 static void uart2_vec_async(void);
<> 149:156823d33999 56 static void uart3_vec_async(void);
<> 149:156823d33999 57 static void uart_irq_async(serial_t *obj);
<> 149:156823d33999 58
<> 149:156823d33999 59 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
<> 149:156823d33999 60 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
<> 149:156823d33999 61
<> 149:156823d33999 62 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
<> 149:156823d33999 63 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
<> 149:156823d33999 64 static int serial_write_async(serial_t *obj);
<> 149:156823d33999 65 static int serial_read_async(serial_t *obj);
<> 149:156823d33999 66
<> 149:156823d33999 67 static uint32_t serial_rx_event_check(serial_t *obj);
<> 149:156823d33999 68 static uint32_t serial_tx_event_check(serial_t *obj);
<> 149:156823d33999 69
<> 149:156823d33999 70 static int serial_is_tx_complete(serial_t *obj);
<> 149:156823d33999 71 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 149:156823d33999 72
<> 149:156823d33999 73 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
<> 149:156823d33999 74 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
<> 149:156823d33999 75 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
<> 149:156823d33999 76 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 149:156823d33999 77 static int serial_is_rx_complete(serial_t *obj);
<> 149:156823d33999 78
<> 149:156823d33999 79 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
<> 149:156823d33999 80 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
<> 149:156823d33999 81 #endif
<> 149:156823d33999 82
<> 149:156823d33999 83 static struct nu_uart_var uart0_var = {
<> 151:5eaa88a5bcc7 84 .ref_cnt = 0,
<> 149:156823d33999 85 .obj = NULL,
<> 149:156823d33999 86 .fifo_size_tx = 16,
<> 149:156823d33999 87 .fifo_size_rx = 16,
<> 149:156823d33999 88 .vec = uart0_vec,
<> 149:156823d33999 89 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 90 .vec_async = uart0_vec_async,
<> 149:156823d33999 91 .pdma_perp_tx = PDMA_UART0_TX,
<> 149:156823d33999 92 .pdma_perp_rx = PDMA_UART0_RX
<> 149:156823d33999 93 #endif
<> 149:156823d33999 94 };
<> 149:156823d33999 95 static struct nu_uart_var uart1_var = {
<> 151:5eaa88a5bcc7 96 .ref_cnt = 0,
<> 149:156823d33999 97 .obj = NULL,
<> 149:156823d33999 98 .fifo_size_tx = 16,
<> 149:156823d33999 99 .fifo_size_rx = 16,
<> 149:156823d33999 100 .vec = uart1_vec,
<> 149:156823d33999 101 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 102 .vec_async = uart1_vec_async,
<> 149:156823d33999 103 .pdma_perp_tx = PDMA_UART1_TX,
<> 149:156823d33999 104 .pdma_perp_rx = PDMA_UART1_RX
<> 149:156823d33999 105 #endif
<> 149:156823d33999 106 };
<> 149:156823d33999 107 static struct nu_uart_var uart2_var = {
<> 151:5eaa88a5bcc7 108 .ref_cnt = 0,
<> 149:156823d33999 109 .obj = NULL,
<> 149:156823d33999 110 .fifo_size_tx = 16,
<> 149:156823d33999 111 .fifo_size_rx = 16,
<> 149:156823d33999 112 .vec = uart2_vec,
<> 149:156823d33999 113 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 114 .vec_async = uart2_vec_async,
<> 149:156823d33999 115 .pdma_perp_tx = PDMA_UART2_TX,
<> 149:156823d33999 116 .pdma_perp_rx = PDMA_UART2_RX
<> 149:156823d33999 117 #endif
<> 149:156823d33999 118 };
<> 149:156823d33999 119 static struct nu_uart_var uart3_var = {
<> 151:5eaa88a5bcc7 120 .ref_cnt = 0,
<> 149:156823d33999 121 .obj = NULL,
<> 149:156823d33999 122 .fifo_size_tx = 16,
<> 149:156823d33999 123 .fifo_size_rx = 16,
<> 149:156823d33999 124 .vec = uart3_vec,
<> 149:156823d33999 125 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 126 .vec_async = uart3_vec_async,
<> 149:156823d33999 127 .pdma_perp_tx = PDMA_UART3_TX,
<> 149:156823d33999 128 .pdma_perp_rx = PDMA_UART3_RX
<> 149:156823d33999 129 #endif
<> 149:156823d33999 130 };
<> 149:156823d33999 131
<> 149:156823d33999 132
<> 149:156823d33999 133 int stdio_uart_inited = 0;
<> 149:156823d33999 134 serial_t stdio_uart;
<> 149:156823d33999 135 static uint32_t uart_modinit_mask = 0;
<> 149:156823d33999 136
<> 149:156823d33999 137 static const struct nu_modinit_s uart_modinit_tab[] = {
<> 149:156823d33999 138 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
<> 149:156823d33999 139 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
<> 149:156823d33999 140 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
<> 149:156823d33999 141 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
<> 149:156823d33999 142
<> 149:156823d33999 143 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
<> 149:156823d33999 144 };
<> 149:156823d33999 145
<> 149:156823d33999 146 extern void mbed_sdk_init(void);
<> 149:156823d33999 147
<> 149:156823d33999 148 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 149:156823d33999 149 {
<> 151:5eaa88a5bcc7 150 // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
<> 149:156823d33999 151 mbed_sdk_init();
<> 149:156823d33999 152
<> 149:156823d33999 153 // Determine which UART_x the pins are used for
<> 149:156823d33999 154 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
<> 149:156823d33999 155 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
<> 149:156823d33999 156 // Get the peripheral name (UART_x) from the pins and assign it to the object
<> 149:156823d33999 157 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
<> 149:156823d33999 158 MBED_ASSERT((int)obj->serial.uart != NC);
<> 149:156823d33999 159
<> 149:156823d33999 160 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 161 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 162 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 163
<> 151:5eaa88a5bcc7 164 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 165
<> 151:5eaa88a5bcc7 166 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 167 // Reset this module
<> 151:5eaa88a5bcc7 168 SYS_ResetModule(modinit->rsetidx);
<> 151:5eaa88a5bcc7 169
<> 151:5eaa88a5bcc7 170 // Select IP clock source
<> 151:5eaa88a5bcc7 171 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
<> 151:5eaa88a5bcc7 172 // Enable IP clock
<> 151:5eaa88a5bcc7 173 CLK_EnableModuleClock(modinit->clkidx);
<> 149:156823d33999 174
<> 151:5eaa88a5bcc7 175 pinmap_pinout(tx, PinMap_UART_TX);
<> 151:5eaa88a5bcc7 176 pinmap_pinout(rx, PinMap_UART_RX);
<> 151:5eaa88a5bcc7 177
<> 151:5eaa88a5bcc7 178 obj->serial.pin_tx = tx;
<> 151:5eaa88a5bcc7 179 obj->serial.pin_rx = rx;
<> 151:5eaa88a5bcc7 180 }
<> 151:5eaa88a5bcc7 181 var->ref_cnt ++;
<> 149:156823d33999 182
<> 149:156823d33999 183 // Configure the UART module and set its baudrate
<> 149:156823d33999 184 serial_baud(obj, 9600);
<> 149:156823d33999 185 // Configure data bits, parity, and stop bits
<> 149:156823d33999 186 serial_format(obj, 8, ParityNone, 1);
<> 149:156823d33999 187
<> 151:5eaa88a5bcc7 188 obj->serial.vec = var->vec;
<> 149:156823d33999 189
<> 149:156823d33999 190 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 191 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
<> 149:156823d33999 192 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 149:156823d33999 193 obj->serial.event = 0;
<> 149:156823d33999 194 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 195 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 196 #endif
<> 149:156823d33999 197
<> 149:156823d33999 198 // For stdio management
<> 151:5eaa88a5bcc7 199 if (obj->serial.uart == STDIO_UART) {
<> 149:156823d33999 200 stdio_uart_inited = 1;
<> 151:5eaa88a5bcc7 201 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 149:156823d33999 202 }
<> 149:156823d33999 203
<> 151:5eaa88a5bcc7 204 if (var->ref_cnt) {
<> 151:5eaa88a5bcc7 205 // Mark this module to be inited.
<> 151:5eaa88a5bcc7 206 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 207 uart_modinit_mask |= 1 << i;
<> 151:5eaa88a5bcc7 208 }
<> 149:156823d33999 209 }
<> 149:156823d33999 210
<> 149:156823d33999 211 void serial_free(serial_t *obj)
<> 149:156823d33999 212 {
<> 149:156823d33999 213 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 214 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 215 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 216
<> 151:5eaa88a5bcc7 217 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 218
<> 151:5eaa88a5bcc7 219 var->ref_cnt --;
<> 151:5eaa88a5bcc7 220 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 221 #if DEVICE_SERIAL_ASYNCH
<> 151:5eaa88a5bcc7 222 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 223 dma_channel_free(obj->serial.dma_chn_id_tx);
<> 151:5eaa88a5bcc7 224 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 225 }
<> 151:5eaa88a5bcc7 226 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 227 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 151:5eaa88a5bcc7 228 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 229 }
<> 151:5eaa88a5bcc7 230 #endif
<> 151:5eaa88a5bcc7 231
<> 151:5eaa88a5bcc7 232 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
<> 149:156823d33999 233
<> 151:5eaa88a5bcc7 234 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 151:5eaa88a5bcc7 235 NVIC_DisableIRQ(modinit->irq_n);
<> 149:156823d33999 236
<> 151:5eaa88a5bcc7 237 // Disable IP clock
<> 151:5eaa88a5bcc7 238 CLK_DisableModuleClock(modinit->clkidx);
<> 151:5eaa88a5bcc7 239 }
<> 151:5eaa88a5bcc7 240
<> 151:5eaa88a5bcc7 241 if (var->obj == obj) {
<> 151:5eaa88a5bcc7 242 var->obj = NULL;
<> 151:5eaa88a5bcc7 243 }
<> 151:5eaa88a5bcc7 244
<> 151:5eaa88a5bcc7 245 if (obj->serial.uart == STDIO_UART) {
<> 149:156823d33999 246 stdio_uart_inited = 0;
<> 149:156823d33999 247 }
<> 149:156823d33999 248
<> 151:5eaa88a5bcc7 249 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 250 // Mark this module to be deinited.
<> 151:5eaa88a5bcc7 251 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 252 uart_modinit_mask &= ~(1 << i);
<> 151:5eaa88a5bcc7 253 }
<> 149:156823d33999 254 }
<> 149:156823d33999 255
<> 149:156823d33999 256 void serial_baud(serial_t *obj, int baudrate) {
<> 149:156823d33999 257 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 149:156823d33999 258 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
<> 149:156823d33999 259
<> 149:156823d33999 260 obj->serial.baudrate = baudrate;
<> 149:156823d33999 261 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
<> 149:156823d33999 262 }
<> 149:156823d33999 263
<> 149:156823d33999 264 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
<> 149:156823d33999 265 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 149:156823d33999 266 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
<> 149:156823d33999 267
<> 149:156823d33999 268 // TODO: Assert for not supported parity and data bits
<> 149:156823d33999 269 obj->serial.databits = data_bits;
<> 149:156823d33999 270 obj->serial.parity = parity;
<> 149:156823d33999 271 obj->serial.stopbits = stop_bits;
<> 149:156823d33999 272
<> 149:156823d33999 273 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
<> 149:156823d33999 274 (data_bits == 6) ? UART_WORD_LEN_6 :
<> 149:156823d33999 275 (data_bits == 7) ? UART_WORD_LEN_7 :
<> 149:156823d33999 276 UART_WORD_LEN_8;
<> 149:156823d33999 277 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
<> 149:156823d33999 278 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
<> 149:156823d33999 279 UART_PARITY_NONE;
<> 149:156823d33999 280 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
<> 149:156823d33999 281 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
<> 149:156823d33999 282 0, // Don't change baudrate
<> 149:156823d33999 283 databits_intern,
<> 149:156823d33999 284 parity_intern,
<> 149:156823d33999 285 stopbits_intern);
<> 149:156823d33999 286 }
<> 149:156823d33999 287
<> 149:156823d33999 288 #if DEVICE_SERIAL_FC
<> 149:156823d33999 289
<> 149:156823d33999 290 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 149:156823d33999 291 {
<> 149:156823d33999 292 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 293
<> 149:156823d33999 294 // First, disable flow control completely.
<> 149:156823d33999 295 uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
<> 149:156823d33999 296
<> 149:156823d33999 297 if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
<> 149:156823d33999 298 // Check if RTS pin matches.
<> 149:156823d33999 299 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
<> 149:156823d33999 300 MBED_ASSERT(uart_rts == obj->serial.uart);
<> 149:156823d33999 301 // Enable the pin for RTS function
<> 149:156823d33999 302 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 153:fa9ff456f731 303 // nRTS pin output is low level active
<> 153:fa9ff456f731 304 uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
<> 149:156823d33999 305 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
<> 149:156823d33999 306 // Enable RTS
<> 149:156823d33999 307 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
<> 149:156823d33999 308 }
<> 149:156823d33999 309
<> 149:156823d33999 310 if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
<> 149:156823d33999 311 // Check if CTS pin matches.
<> 149:156823d33999 312 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
<> 149:156823d33999 313 MBED_ASSERT(uart_cts == obj->serial.uart);
<> 149:156823d33999 314 // Enable the pin for CTS function
<> 149:156823d33999 315 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 153:fa9ff456f731 316 // nCTS pin input is low level active
<> 153:fa9ff456f731 317 uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
<> 149:156823d33999 318 // Enable CTS
<> 149:156823d33999 319 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
<> 149:156823d33999 320 }
<> 149:156823d33999 321 }
<> 149:156823d33999 322
<> 149:156823d33999 323 #endif //DEVICE_SERIAL_FC
<> 149:156823d33999 324
<> 149:156823d33999 325 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 149:156823d33999 326 {
<> 149:156823d33999 327 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 149:156823d33999 328 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
<> 149:156823d33999 329
<> 149:156823d33999 330 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 331 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 332 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 333
<> 149:156823d33999 334 obj->serial.irq_handler = (uint32_t) handler;
<> 149:156823d33999 335 obj->serial.irq_id = id;
<> 149:156823d33999 336
<> 149:156823d33999 337 // Restore sync-mode vector
<> 149:156823d33999 338 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
<> 149:156823d33999 339 }
<> 149:156823d33999 340
<> 149:156823d33999 341 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 149:156823d33999 342 {
<> 149:156823d33999 343 if (enable) {
<> 149:156823d33999 344 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 345 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 346 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 347
<> 149:156823d33999 348 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
<> 149:156823d33999 349 NVIC_EnableIRQ(modinit->irq_n);
<> 149:156823d33999 350
<> 151:5eaa88a5bcc7 351 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 151:5eaa88a5bcc7 352 // Multiple serial S/W objects for single UART H/W module possibly.
<> 151:5eaa88a5bcc7 353 // Bind serial S/W object to UART H/W module as interrupt is enabled.
<> 151:5eaa88a5bcc7 354 var->obj = obj;
<> 151:5eaa88a5bcc7 355
<> 149:156823d33999 356 switch (irq) {
<> 149:156823d33999 357 // NOTE: Setting inten_msk first to avoid race condition
<> 149:156823d33999 358 case RxIrq:
<> 149:156823d33999 359 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
<> 149:156823d33999 360 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 361 break;
<> 149:156823d33999 362 case TxIrq:
<> 149:156823d33999 363 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
<> 149:156823d33999 364 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 365 break;
<> 149:156823d33999 366 }
<> 149:156823d33999 367 } else { // disable
<> 149:156823d33999 368 switch (irq) {
<> 149:156823d33999 369 case RxIrq:
<> 149:156823d33999 370 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 371 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
<> 149:156823d33999 372 break;
<> 149:156823d33999 373 case TxIrq:
<> 149:156823d33999 374 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 375 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
<> 149:156823d33999 376 break;
<> 149:156823d33999 377 }
<> 149:156823d33999 378 }
<> 149:156823d33999 379 }
<> 149:156823d33999 380
<> 149:156823d33999 381 int serial_getc(serial_t *obj)
<> 149:156823d33999 382 {
<> 149:156823d33999 383 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
<> 149:156823d33999 384 while (! serial_readable(obj));
<> 149:156823d33999 385 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 386
<> 149:156823d33999 387 // Simulate clear of the interrupt flag
<> 149:156823d33999 388 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 149:156823d33999 389 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 390 }
<> 149:156823d33999 391
<> 149:156823d33999 392 return c;
<> 149:156823d33999 393 }
<> 149:156823d33999 394
<> 149:156823d33999 395 void serial_putc(serial_t *obj, int c)
<> 149:156823d33999 396 {
<> 149:156823d33999 397 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
<> 149:156823d33999 398 while (! serial_writable(obj));
<> 149:156823d33999 399 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
<> 149:156823d33999 400
<> 149:156823d33999 401 // Simulate clear of the interrupt flag
<> 149:156823d33999 402 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 403 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 404 }
<> 149:156823d33999 405 }
<> 149:156823d33999 406
<> 149:156823d33999 407 int serial_readable(serial_t *obj)
<> 149:156823d33999 408 {
<> 149:156823d33999 409 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 410 return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 411 }
<> 149:156823d33999 412
<> 149:156823d33999 413 int serial_writable(serial_t *obj)
<> 149:156823d33999 414 {
<> 149:156823d33999 415 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 416 }
<> 149:156823d33999 417
<> 149:156823d33999 418 void serial_pinout_tx(PinName tx)
<> 149:156823d33999 419 {
<> 149:156823d33999 420 pinmap_pinout(tx, PinMap_UART_TX);
<> 149:156823d33999 421 }
<> 149:156823d33999 422
<> 149:156823d33999 423 void serial_break_set(serial_t *obj)
<> 149:156823d33999 424 {
<> 149:156823d33999 425 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
<> 149:156823d33999 426 }
<> 149:156823d33999 427
<> 149:156823d33999 428 void serial_break_clear(serial_t *obj)
<> 149:156823d33999 429 {
<> 149:156823d33999 430 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
<> 149:156823d33999 431 }
<> 149:156823d33999 432
<> 149:156823d33999 433 static void uart0_vec(void)
<> 149:156823d33999 434 {
<> 149:156823d33999 435 uart_irq(uart0_var.obj);
<> 149:156823d33999 436 }
<> 149:156823d33999 437
<> 149:156823d33999 438 static void uart1_vec(void)
<> 149:156823d33999 439 {
<> 149:156823d33999 440 uart_irq(uart1_var.obj);
<> 149:156823d33999 441 }
<> 149:156823d33999 442
<> 149:156823d33999 443 static void uart2_vec(void)
<> 149:156823d33999 444 {
<> 149:156823d33999 445 uart_irq(uart2_var.obj);
<> 149:156823d33999 446 }
<> 149:156823d33999 447
<> 149:156823d33999 448 static void uart3_vec(void)
<> 149:156823d33999 449 {
<> 149:156823d33999 450 uart_irq(uart3_var.obj);
<> 149:156823d33999 451 }
<> 149:156823d33999 452
<> 149:156823d33999 453 static void uart_irq(serial_t *obj)
<> 149:156823d33999 454 {
<> 149:156823d33999 455 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 456
<> 149:156823d33999 457 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 149:156823d33999 458 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 149:156823d33999 459 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 460 if (obj->serial.irq_handler) {
<> 149:156823d33999 461 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
<> 149:156823d33999 462 }
<> 149:156823d33999 463 }
<> 149:156823d33999 464
<> 149:156823d33999 465 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 149:156823d33999 466 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 149:156823d33999 467 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 468 if (obj->serial.irq_handler) {
<> 149:156823d33999 469 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
<> 149:156823d33999 470 }
<> 149:156823d33999 471 }
<> 149:156823d33999 472
<> 149:156823d33999 473 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
<> 149:156823d33999 474 uart_base->INTSTS = uart_base->INTSTS;
<> 149:156823d33999 475 uart_base->FIFOSTS = uart_base->FIFOSTS;
<> 149:156823d33999 476 }
<> 149:156823d33999 477
<> 149:156823d33999 478
<> 149:156823d33999 479 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 480 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 481 {
<> 149:156823d33999 482 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
<> 149:156823d33999 483
<> 149:156823d33999 484 obj->serial.dma_usage_tx = hint;
<> 149:156823d33999 485 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
<> 149:156823d33999 486
<> 149:156823d33999 487 // UART IRQ is necessary for both interrupt way and DMA way
<> 149:156823d33999 488 serial_tx_enable_event(obj, event, 1);
<> 149:156823d33999 489 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
<> 149:156823d33999 490 //UART_HAL_DisableTransmitter(obj->serial.address);
<> 149:156823d33999 491 //UART_HAL_FlushTxFifo(obj->serial.address);
<> 149:156823d33999 492 //UART_HAL_EnableTransmitter(obj->serial.address);
<> 149:156823d33999 493
<> 149:156823d33999 494 int n_word = 0;
<> 149:156823d33999 495 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 149:156823d33999 496 // Interrupt way
<> 149:156823d33999 497 n_word = serial_write_async(obj);
<> 149:156823d33999 498 serial_tx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 499 } else {
<> 149:156823d33999 500 // DMA way
<> 149:156823d33999 501 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 502 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 503 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 504
<> 149:156823d33999 505 PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
<> 149:156823d33999 506 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 507 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
<> 149:156823d33999 508 0, // Scatter-gather disabled
<> 149:156823d33999 509 0); // Scatter-gather descriptor address
<> 149:156823d33999 510 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 511 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 149:156823d33999 512 tx_length);
<> 149:156823d33999 513 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 514 (uint32_t) tx, // NOTE:
<> 149:156823d33999 515 // NUC472: End of source address
<> 149:156823d33999 516 // M451: Start of source address
<> 149:156823d33999 517 PDMA_SAR_INC, // Source address incremental
<> 149:156823d33999 518 (uint32_t) obj->serial.uart, // Destination address
<> 149:156823d33999 519 PDMA_DAR_FIX); // Destination address fixed
<> 149:156823d33999 520 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 521 PDMA_REQ_SINGLE, // Single mode
<> 149:156823d33999 522 0); // Burst size
<> 149:156823d33999 523 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 524 PDMA_INT_TRANS_DONE); // Interrupt type
<> 149:156823d33999 525 // Register DMA event handler
<> 149:156823d33999 526 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
<> 149:156823d33999 527 serial_tx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 528 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
<> 149:156823d33999 529 }
<> 149:156823d33999 530
<> 149:156823d33999 531 return n_word;
<> 149:156823d33999 532 }
<> 149:156823d33999 533
<> 149:156823d33999 534 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
<> 149:156823d33999 535 {
<> 149:156823d33999 536 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
<> 149:156823d33999 537
<> 149:156823d33999 538 obj->serial.dma_usage_rx = hint;
<> 149:156823d33999 539 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
<> 149:156823d33999 540 // DMA doesn't support char match, so fall back to IRQ if it is requested.
<> 149:156823d33999 541 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
<> 149:156823d33999 542 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 149:156823d33999 543 char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 149:156823d33999 544 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 149:156823d33999 545 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 149:156823d33999 546 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 547 }
<> 149:156823d33999 548
<> 149:156823d33999 549 // UART IRQ is necessary for both interrupt way and DMA way
<> 149:156823d33999 550 serial_rx_enable_event(obj, event, 1);
<> 149:156823d33999 551 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
<> 149:156823d33999 552 serial_rx_set_char_match(obj, char_match);
<> 149:156823d33999 553 //UART_HAL_DisableReceiver(obj->serial.address);
<> 149:156823d33999 554 //UART_HAL_FlushRxFifo(obj->serial.address);
<> 149:156823d33999 555 //UART_HAL_EnableReceiver(obj->serial.address);
<> 149:156823d33999 556
<> 149:156823d33999 557 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 149:156823d33999 558 // Interrupt way
<> 149:156823d33999 559 serial_rx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 560 } else {
<> 149:156823d33999 561 // DMA way
<> 149:156823d33999 562 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 563 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 564 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 565
<> 149:156823d33999 566 PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
<> 149:156823d33999 567 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 568 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
<> 149:156823d33999 569 0, // Scatter-gather disabled
<> 149:156823d33999 570 0); // Scatter-gather descriptor address
<> 149:156823d33999 571 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 572 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 149:156823d33999 573 rx_length);
<> 149:156823d33999 574 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 575 (uint32_t) obj->serial.uart, // Source address
<> 149:156823d33999 576 PDMA_SAR_FIX, // Source address fixed
<> 149:156823d33999 577 (uint32_t) rx, // NOTE:
<> 149:156823d33999 578 // NUC472: End of destination address
<> 149:156823d33999 579 // M451: Start of destination address
<> 149:156823d33999 580 PDMA_DAR_INC); // Destination address incremental
<> 149:156823d33999 581 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 582 PDMA_REQ_SINGLE, // Single mode
<> 149:156823d33999 583 0); // Burst size
<> 149:156823d33999 584 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 585 PDMA_INT_TRANS_DONE); // Interrupt type
<> 149:156823d33999 586 // Register DMA event handler
<> 149:156823d33999 587 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
<> 149:156823d33999 588 serial_rx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 589 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
<> 149:156823d33999 590 }
<> 149:156823d33999 591 }
<> 149:156823d33999 592
<> 149:156823d33999 593 void serial_tx_abort_asynch(serial_t *obj)
<> 149:156823d33999 594 {
<> 149:156823d33999 595 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 149:156823d33999 596 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
<> 149:156823d33999 597
<> 149:156823d33999 598 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
<> 149:156823d33999 599 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 600 PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
<> 149:156823d33999 601 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 149:156823d33999 602 //PDMA_STOP(obj->serial.dma_chn_id_tx);
<> 149:156823d33999 603 PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
<> 149:156823d33999 604 }
<> 149:156823d33999 605 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
<> 149:156823d33999 606 }
<> 149:156823d33999 607
<> 149:156823d33999 608 // Necessary for both interrupt way and DMA way
<> 149:156823d33999 609 serial_irq_set(obj, TxIrq, 0);
<> 149:156823d33999 610 // FIXME: more complete abort operation
<> 149:156823d33999 611 //UART_HAL_DisableTransmitter(obj->serial.serial.address);
<> 149:156823d33999 612 //UART_HAL_FlushTxFifo(obj->serial.serial.address);
<> 149:156823d33999 613 }
<> 149:156823d33999 614
<> 149:156823d33999 615 void serial_rx_abort_asynch(serial_t *obj)
<> 149:156823d33999 616 {
<> 149:156823d33999 617 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
<> 149:156823d33999 618 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 619 PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
<> 149:156823d33999 620 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 149:156823d33999 621 //PDMA_STOP(obj->serial.dma_chn_id_rx);
<> 149:156823d33999 622 PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
<> 149:156823d33999 623 }
<> 149:156823d33999 624 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
<> 149:156823d33999 625 }
<> 149:156823d33999 626
<> 149:156823d33999 627 // Necessary for both interrupt way and DMA way
<> 149:156823d33999 628 serial_irq_set(obj, RxIrq, 0);
<> 149:156823d33999 629 // FIXME: more complete abort operation
<> 149:156823d33999 630 //UART_HAL_DisableReceiver(obj->serial.serial.address);
<> 149:156823d33999 631 //UART_HAL_FlushRxFifo(obj->serial.serial.address);
<> 149:156823d33999 632 }
<> 149:156823d33999 633
<> 149:156823d33999 634 uint8_t serial_tx_active(serial_t *obj)
<> 149:156823d33999 635 {
<> 149:156823d33999 636 return serial_is_irq_en(obj, TxIrq);
<> 149:156823d33999 637 }
<> 149:156823d33999 638
<> 149:156823d33999 639 uint8_t serial_rx_active(serial_t *obj)
<> 149:156823d33999 640 {
<> 149:156823d33999 641 return serial_is_irq_en(obj, RxIrq);
<> 149:156823d33999 642 }
<> 149:156823d33999 643
<> 149:156823d33999 644 int serial_irq_handler_asynch(serial_t *obj)
<> 149:156823d33999 645 {
<> 149:156823d33999 646 int event_rx = 0;
<> 149:156823d33999 647 int event_tx = 0;
<> 149:156823d33999 648
<> 151:5eaa88a5bcc7 649 // Necessary for both interrupt way and DMA way
<> 149:156823d33999 650 if (serial_is_irq_en(obj, RxIrq)) {
<> 149:156823d33999 651 event_rx = serial_rx_event_check(obj);
<> 149:156823d33999 652 if (event_rx) {
<> 149:156823d33999 653 serial_rx_abort_asynch(obj);
<> 149:156823d33999 654 }
<> 149:156823d33999 655 }
<> 149:156823d33999 656
<> 149:156823d33999 657 if (serial_is_irq_en(obj, TxIrq)) {
<> 149:156823d33999 658 event_tx = serial_tx_event_check(obj);
<> 149:156823d33999 659 if (event_tx) {
<> 149:156823d33999 660 serial_tx_abort_asynch(obj);
<> 149:156823d33999 661 }
<> 149:156823d33999 662 }
<> 149:156823d33999 663
<> 149:156823d33999 664 return (obj->serial.event & (event_rx | event_tx));
<> 149:156823d33999 665 }
<> 149:156823d33999 666
<> 149:156823d33999 667 int serial_allow_powerdown(void)
<> 149:156823d33999 668 {
<> 149:156823d33999 669 uint32_t modinit_mask = uart_modinit_mask;
<> 149:156823d33999 670 while (modinit_mask) {
<> 149:156823d33999 671 int uart_idx = nu_ctz(modinit_mask);
<> 149:156823d33999 672 const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
<> 149:156823d33999 673 if (modinit->modname != NC) {
<> 149:156823d33999 674 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
<> 149:156823d33999 675 // Disallow entering power-down mode if Tx FIFO has data to flush
<> 149:156823d33999 676 if (! UART_IS_TX_EMPTY((uart_base))) {
<> 149:156823d33999 677 return 0;
<> 149:156823d33999 678 }
<> 149:156823d33999 679 // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
<> 149:156823d33999 680 if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 149:156823d33999 681 return 0;
<> 149:156823d33999 682 }
<> 149:156823d33999 683 // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
<> 149:156823d33999 684 if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
<> 149:156823d33999 685 return 0;
<> 149:156823d33999 686 }
<> 149:156823d33999 687 }
<> 149:156823d33999 688 modinit_mask &= ~(1 << uart_idx);
<> 149:156823d33999 689 }
<> 149:156823d33999 690
<> 149:156823d33999 691 return 1;
<> 149:156823d33999 692 }
<> 149:156823d33999 693
<> 149:156823d33999 694 static void uart0_vec_async(void)
<> 149:156823d33999 695 {
<> 149:156823d33999 696 uart_irq_async(uart0_var.obj);
<> 149:156823d33999 697 }
<> 149:156823d33999 698
<> 149:156823d33999 699 static void uart1_vec_async(void)
<> 149:156823d33999 700 {
<> 149:156823d33999 701 uart_irq_async(uart1_var.obj);
<> 149:156823d33999 702 }
<> 149:156823d33999 703
<> 149:156823d33999 704 static void uart2_vec_async(void)
<> 149:156823d33999 705 {
<> 149:156823d33999 706 uart_irq_async(uart2_var.obj);
<> 149:156823d33999 707 }
<> 149:156823d33999 708
<> 149:156823d33999 709 static void uart3_vec_async(void)
<> 149:156823d33999 710 {
<> 149:156823d33999 711 uart_irq_async(uart3_var.obj);
<> 149:156823d33999 712 }
<> 149:156823d33999 713
<> 149:156823d33999 714 static void uart_irq_async(serial_t *obj)
<> 149:156823d33999 715 {
<> 149:156823d33999 716 if (serial_is_irq_en(obj, RxIrq)) {
<> 149:156823d33999 717 (*obj->serial.irq_handler_rx_async)();
<> 149:156823d33999 718 }
<> 149:156823d33999 719 if (serial_is_irq_en(obj, TxIrq)) {
<> 149:156823d33999 720 (*obj->serial.irq_handler_tx_async)();
<> 149:156823d33999 721 }
<> 149:156823d33999 722 }
<> 149:156823d33999 723
<> 149:156823d33999 724 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
<> 149:156823d33999 725 {
<> 149:156823d33999 726 obj->char_match = char_match;
<> 149:156823d33999 727 obj->char_found = 0;
<> 149:156823d33999 728 }
<> 149:156823d33999 729
<> 149:156823d33999 730 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 149:156823d33999 731 {
<> 149:156823d33999 732 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
<> 149:156823d33999 733 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
<> 149:156823d33999 734
<> 149:156823d33999 735 //if (event & SERIAL_EVENT_TX_COMPLETE) {
<> 149:156823d33999 736 //}
<> 149:156823d33999 737 }
<> 149:156823d33999 738
<> 149:156823d33999 739 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 149:156823d33999 740 {
<> 149:156823d33999 741 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
<> 149:156823d33999 742 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
<> 149:156823d33999 743
<> 149:156823d33999 744 //if (event & SERIAL_EVENT_RX_COMPLETE) {
<> 149:156823d33999 745 //}
<> 149:156823d33999 746 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
<> 149:156823d33999 747 //}
<> 149:156823d33999 748 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
<> 149:156823d33999 749 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 149:156823d33999 750 }
<> 149:156823d33999 751 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
<> 149:156823d33999 752 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 149:156823d33999 753 }
<> 149:156823d33999 754 if (event & SERIAL_EVENT_RX_OVERFLOW) {
<> 149:156823d33999 755 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
<> 149:156823d33999 756 }
<> 149:156823d33999 757 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
<> 149:156823d33999 758 //}
<> 149:156823d33999 759 }
<> 149:156823d33999 760
<> 149:156823d33999 761 static int serial_is_tx_complete(serial_t *obj)
<> 149:156823d33999 762 {
<> 149:156823d33999 763 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
<> 149:156823d33999 764 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 765 // FIXME: Premature abort???
<> 149:156823d33999 766 return (obj->tx_buff.pos == obj->tx_buff.length);
<> 149:156823d33999 767 }
<> 149:156823d33999 768
<> 149:156823d33999 769 static int serial_is_rx_complete(serial_t *obj)
<> 149:156823d33999 770 {
<> 149:156823d33999 771 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 772 return (obj->rx_buff.pos == obj->rx_buff.length);
<> 149:156823d33999 773 }
<> 149:156823d33999 774
<> 149:156823d33999 775 static uint32_t serial_tx_event_check(serial_t *obj)
<> 149:156823d33999 776 {
<> 149:156823d33999 777 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 778
<> 149:156823d33999 779 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 149:156823d33999 780 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 149:156823d33999 781 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 782 }
<> 149:156823d33999 783
<> 149:156823d33999 784 uint32_t event = 0;
<> 149:156823d33999 785
<> 149:156823d33999 786 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 149:156823d33999 787 serial_write_async(obj);
<> 149:156823d33999 788 }
<> 149:156823d33999 789
<> 149:156823d33999 790 if (serial_is_tx_complete(obj)) {
<> 149:156823d33999 791 event |= SERIAL_EVENT_TX_COMPLETE;
<> 149:156823d33999 792 }
<> 149:156823d33999 793
<> 149:156823d33999 794 return event;
<> 149:156823d33999 795 }
<> 149:156823d33999 796
<> 149:156823d33999 797 static uint32_t serial_rx_event_check(serial_t *obj)
<> 149:156823d33999 798 {
<> 149:156823d33999 799 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 800
<> 149:156823d33999 801 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 149:156823d33999 802 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 149:156823d33999 803 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 804 }
<> 149:156823d33999 805
<> 149:156823d33999 806 uint32_t event = 0;
<> 149:156823d33999 807
<> 149:156823d33999 808 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
<> 149:156823d33999 809 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
<> 149:156823d33999 810 }
<> 149:156823d33999 811 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
<> 149:156823d33999 812 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
<> 149:156823d33999 813 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
<> 149:156823d33999 814 }
<> 149:156823d33999 815 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
<> 149:156823d33999 816 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
<> 149:156823d33999 817 event |= SERIAL_EVENT_RX_PARITY_ERROR;
<> 149:156823d33999 818 }
<> 149:156823d33999 819
<> 149:156823d33999 820 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
<> 149:156823d33999 821 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
<> 149:156823d33999 822 event |= SERIAL_EVENT_RX_OVERFLOW;
<> 149:156823d33999 823 }
<> 149:156823d33999 824
<> 149:156823d33999 825 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 149:156823d33999 826 serial_read_async(obj);
<> 149:156823d33999 827 }
<> 149:156823d33999 828
<> 149:156823d33999 829 if (serial_is_rx_complete(obj)) {
<> 149:156823d33999 830 event |= SERIAL_EVENT_RX_COMPLETE;
<> 149:156823d33999 831 }
<> 149:156823d33999 832 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
<> 149:156823d33999 833 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
<> 149:156823d33999 834 // FIXME: Timing to reset char_found?
<> 149:156823d33999 835 //obj->char_found = 0;
<> 149:156823d33999 836 }
<> 149:156823d33999 837
<> 149:156823d33999 838 return event;
<> 149:156823d33999 839 }
<> 149:156823d33999 840
<> 149:156823d33999 841 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
<> 149:156823d33999 842 {
<> 149:156823d33999 843 serial_t *obj = (serial_t *) id;
<> 149:156823d33999 844
<> 149:156823d33999 845 // FIXME: Pass this error to caller
<> 149:156823d33999 846 if (event_dma & DMA_EVENT_ABORT) {
<> 149:156823d33999 847 }
<> 149:156823d33999 848 // Expect UART IRQ will catch this transfer done event
<> 149:156823d33999 849 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 149:156823d33999 850 obj->tx_buff.pos = obj->tx_buff.length;
<> 149:156823d33999 851 }
<> 149:156823d33999 852 // FIXME: Pass this error to caller
<> 149:156823d33999 853 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 149:156823d33999 854 }
<> 149:156823d33999 855
<> 149:156823d33999 856 uart_irq_async(obj);
<> 149:156823d33999 857 }
<> 149:156823d33999 858
<> 149:156823d33999 859 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
<> 149:156823d33999 860 {
<> 149:156823d33999 861 serial_t *obj = (serial_t *) id;
<> 149:156823d33999 862
<> 149:156823d33999 863 // FIXME: Pass this error to caller
<> 149:156823d33999 864 if (event_dma & DMA_EVENT_ABORT) {
<> 149:156823d33999 865 }
<> 149:156823d33999 866 // Expect UART IRQ will catch this transfer done event
<> 149:156823d33999 867 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 149:156823d33999 868 obj->rx_buff.pos = obj->rx_buff.length;
<> 149:156823d33999 869 }
<> 149:156823d33999 870 // FIXME: Pass this error to caller
<> 149:156823d33999 871 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 149:156823d33999 872 }
<> 149:156823d33999 873
<> 149:156823d33999 874 uart_irq_async(obj);
<> 149:156823d33999 875 }
<> 149:156823d33999 876
<> 149:156823d33999 877 static int serial_write_async(serial_t *obj)
<> 149:156823d33999 878 {
<> 149:156823d33999 879 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 880 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 881 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 882
<> 149:156823d33999 883 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 884
<> 149:156823d33999 885 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
<> 149:156823d33999 886 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
<> 149:156823d33999 887 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
<> 149:156823d33999 888 tx_fifo_busy = tx_fifo_max;
<> 149:156823d33999 889 }
<> 149:156823d33999 890 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
<> 149:156823d33999 891 if (tx_fifo_free == 0) {
<> 149:156823d33999 892 // Simulate clear of the interrupt flag
<> 149:156823d33999 893 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 894 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 895 }
<> 149:156823d33999 896 return 0;
<> 149:156823d33999 897 }
<> 149:156823d33999 898
<> 149:156823d33999 899 uint32_t bytes_per_word = obj->tx_buff.width / 8;
<> 149:156823d33999 900
<> 149:156823d33999 901 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
<> 149:156823d33999 902 int n_words = 0;
<> 149:156823d33999 903 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
<> 149:156823d33999 904 switch (bytes_per_word) {
<> 149:156823d33999 905 case 4:
<> 149:156823d33999 906 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 907 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 908 case 2:
<> 149:156823d33999 909 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 910 case 1:
<> 149:156823d33999 911 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 912 }
<> 149:156823d33999 913
<> 149:156823d33999 914 n_words ++;
<> 149:156823d33999 915 tx_fifo_free -= bytes_per_word;
<> 149:156823d33999 916 obj->tx_buff.pos ++;
<> 149:156823d33999 917 }
<> 149:156823d33999 918
<> 149:156823d33999 919 if (n_words) {
<> 149:156823d33999 920 // Simulate clear of the interrupt flag
<> 149:156823d33999 921 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 922 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 923 }
<> 149:156823d33999 924 }
<> 149:156823d33999 925
<> 149:156823d33999 926 return n_words;
<> 149:156823d33999 927 }
<> 149:156823d33999 928
<> 149:156823d33999 929 static int serial_read_async(serial_t *obj)
<> 149:156823d33999 930 {
<> 149:156823d33999 931 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 932 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 933 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 934
<> 149:156823d33999 935 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
<> 149:156823d33999 936 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
<> 149:156823d33999 937 //if (rx_fifo_free == 0) {
<> 149:156823d33999 938 // return 0;
<> 149:156823d33999 939 //}
<> 149:156823d33999 940
<> 149:156823d33999 941 uint32_t bytes_per_word = obj->rx_buff.width / 8;
<> 149:156823d33999 942
<> 149:156823d33999 943 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
<> 149:156823d33999 944 int n_words = 0;
<> 149:156823d33999 945 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
<> 149:156823d33999 946 switch (bytes_per_word) {
<> 149:156823d33999 947 case 4:
<> 149:156823d33999 948 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 949 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 950 case 2:
<> 149:156823d33999 951 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 952 case 1:
<> 149:156823d33999 953 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 954 }
<> 149:156823d33999 955
<> 149:156823d33999 956 n_words ++;
<> 149:156823d33999 957 rx_fifo_busy -= bytes_per_word;
<> 149:156823d33999 958 obj->rx_buff.pos ++;
<> 149:156823d33999 959
<> 149:156823d33999 960 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 149:156823d33999 961 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 149:156823d33999 962 uint8_t *rx_cmp = rx;
<> 149:156823d33999 963 switch (bytes_per_word) {
<> 149:156823d33999 964 case 4:
<> 149:156823d33999 965 rx_cmp -= 2;
<> 149:156823d33999 966 case 2:
<> 149:156823d33999 967 rx_cmp --;
<> 149:156823d33999 968 case 1:
<> 149:156823d33999 969 rx_cmp --;
<> 149:156823d33999 970 }
<> 149:156823d33999 971 if (*rx_cmp == obj->char_match) {
<> 149:156823d33999 972 obj->char_found = 1;
<> 149:156823d33999 973 break;
<> 149:156823d33999 974 }
<> 149:156823d33999 975 }
<> 149:156823d33999 976 }
<> 149:156823d33999 977
<> 149:156823d33999 978 if (n_words) {
<> 149:156823d33999 979 // Simulate clear of the interrupt flag
<> 149:156823d33999 980 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 149:156823d33999 981 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 982 }
<> 149:156823d33999 983 }
<> 149:156823d33999 984
<> 149:156823d33999 985 return n_words;
<> 149:156823d33999 986 }
<> 149:156823d33999 987
<> 149:156823d33999 988 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
<> 149:156823d33999 989 {
<> 149:156823d33999 990 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 991 obj->tx_buff.length = length;
<> 149:156823d33999 992 obj->tx_buff.pos = 0;
<> 149:156823d33999 993 obj->tx_buff.width = width;
<> 149:156823d33999 994 }
<> 149:156823d33999 995
<> 149:156823d33999 996 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
<> 149:156823d33999 997 {
<> 149:156823d33999 998 obj->rx_buff.buffer = rx;
<> 149:156823d33999 999 obj->rx_buff.length = length;
<> 149:156823d33999 1000 obj->rx_buff.pos = 0;
<> 149:156823d33999 1001 obj->rx_buff.width = width;
<> 149:156823d33999 1002 }
<> 149:156823d33999 1003
<> 149:156823d33999 1004 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 149:156823d33999 1005 {
<> 149:156823d33999 1006 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 1007 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 1008 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 1009
<> 149:156823d33999 1010 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1011 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 1012 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1013 obj->serial.vec = var->vec_async;
<> 149:156823d33999 1014 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
<> 149:156823d33999 1015 serial_irq_set(obj, TxIrq, enable);
<> 149:156823d33999 1016 }
<> 149:156823d33999 1017
<> 149:156823d33999 1018 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 149:156823d33999 1019 {
<> 149:156823d33999 1020 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 1021 MBED_ASSERT(modinit != NULL);
<> 149:156823d33999 1022 MBED_ASSERT(modinit->modname == obj->serial.uart);
<> 149:156823d33999 1023
<> 149:156823d33999 1024 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1025 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 1026 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1027 obj->serial.vec = var->vec_async;
<> 149:156823d33999 1028 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
<> 149:156823d33999 1029 serial_irq_set(obj, RxIrq, enable);
<> 149:156823d33999 1030 }
<> 149:156823d33999 1031
<> 149:156823d33999 1032 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
<> 149:156823d33999 1033 {
<> 149:156823d33999 1034 if (*dma_usage != DMA_USAGE_NEVER) {
<> 149:156823d33999 1035 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 1036 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
<> 149:156823d33999 1037 }
<> 149:156823d33999 1038 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 1039 *dma_usage = DMA_USAGE_NEVER;
<> 149:156823d33999 1040 }
<> 149:156823d33999 1041 }
<> 149:156823d33999 1042 else {
<> 149:156823d33999 1043 dma_channel_free(*dma_ch);
<> 149:156823d33999 1044 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 1045 }
<> 149:156823d33999 1046 }
<> 149:156823d33999 1047
<> 149:156823d33999 1048 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
<> 149:156823d33999 1049 {
<> 149:156823d33999 1050 int inten_msk = 0;
<> 149:156823d33999 1051
<> 149:156823d33999 1052 switch (irq) {
<> 149:156823d33999 1053 case RxIrq:
<> 149:156823d33999 1054 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
<> 149:156823d33999 1055 break;
<> 149:156823d33999 1056 case TxIrq:
<> 149:156823d33999 1057 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
<> 149:156823d33999 1058 break;
<> 149:156823d33999 1059 }
<> 149:156823d33999 1060
<> 149:156823d33999 1061 return !! inten_msk;
<> 149:156823d33999 1062 }
<> 149:156823d33999 1063
<> 149:156823d33999 1064 #endif // #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 1065 #endif // #if DEVICE_SERIAL