Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC15XX/spi_api.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999
Child:
170:19eb464bc2be
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include <math.h>
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 22 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 static const SWM_Map SWM_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 25 {4, 0},
<> 144:ef7eb2e8f9f7 26 {5, 24},
<> 144:ef7eb2e8f9f7 27 };
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 static const SWM_Map SWM_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 30 {3, 8},
<> 144:ef7eb2e8f9f7 31 {5, 0},
<> 144:ef7eb2e8f9f7 32 };
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 static const SWM_Map SWM_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 35 {3, 16},
<> 144:ef7eb2e8f9f7 36 {5, 8},
<> 144:ef7eb2e8f9f7 37 };
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 static const SWM_Map SWM_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 40 {3, 24},
<> 144:ef7eb2e8f9f7 41 {5, 16},
<> 144:ef7eb2e8f9f7 42 };
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 // bit flags for used SPIs
<> 144:ef7eb2e8f9f7 45 static unsigned char spi_used = 0;
<> 144:ef7eb2e8f9f7 46 static int get_available_spi(PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 144:ef7eb2e8f9f7 47 {
<> 144:ef7eb2e8f9f7 48 if (spi_used == 0) {
<> 144:ef7eb2e8f9f7 49 return 0; // The first user
<> 144:ef7eb2e8f9f7 50 }
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 const SWM_Map *swm;
<> 144:ef7eb2e8f9f7 53 uint32_t regVal;
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 // Investigate if same pins as the used SPI0/1 - to be able to reuse it
<> 144:ef7eb2e8f9f7 56 for (int spi_n = 0; spi_n < 2; spi_n++) {
<> 144:ef7eb2e8f9f7 57 if (spi_used & (1<<spi_n)) {
<> 144:ef7eb2e8f9f7 58 if (sclk != NC) {
<> 144:ef7eb2e8f9f7 59 swm = &SWM_SPI_SCLK[spi_n];
<> 144:ef7eb2e8f9f7 60 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 61 if (regVal != (sclk << swm->offset)) {
<> 144:ef7eb2e8f9f7 62 // Existing pin is not the same as the one we want
<> 144:ef7eb2e8f9f7 63 continue;
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 if (mosi != NC) {
<> 144:ef7eb2e8f9f7 68 swm = &SWM_SPI_MOSI[spi_n];
<> 144:ef7eb2e8f9f7 69 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 70 if (regVal != (mosi << swm->offset)) {
<> 144:ef7eb2e8f9f7 71 // Existing pin is not the same as the one we want
<> 144:ef7eb2e8f9f7 72 continue;
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74 }
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 if (miso != NC) {
<> 144:ef7eb2e8f9f7 77 swm = &SWM_SPI_MISO[spi_n];
<> 144:ef7eb2e8f9f7 78 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 79 if (regVal != (miso << swm->offset)) {
<> 144:ef7eb2e8f9f7 80 // Existing pin is not the same as the one we want
<> 144:ef7eb2e8f9f7 81 continue;
<> 144:ef7eb2e8f9f7 82 }
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 86 swm = &SWM_SPI_SSEL[spi_n];
<> 144:ef7eb2e8f9f7 87 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 88 if (regVal != (ssel << swm->offset)) {
<> 144:ef7eb2e8f9f7 89 // Existing pin is not the same as the one we want
<> 144:ef7eb2e8f9f7 90 continue;
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 // The pins for the currently used SPIx are the same as the
<> 144:ef7eb2e8f9f7 95 // ones we want so we will reuse it
<> 144:ef7eb2e8f9f7 96 return spi_n;
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 // None of the existing SPIx pin setups match the pins we want
<> 144:ef7eb2e8f9f7 101 // so the last hope is to select one unused SPIx
<> 144:ef7eb2e8f9f7 102 if ((spi_used & 1) == 0) {
<> 144:ef7eb2e8f9f7 103 return 0;
<> 144:ef7eb2e8f9f7 104 } else if ((spi_used & 2) == 0) {
<> 144:ef7eb2e8f9f7 105 return 1;
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 // No matching setup and no free SPIx
<> 144:ef7eb2e8f9f7 109 return -1;
<> 144:ef7eb2e8f9f7 110 }
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 static inline void spi_disable(spi_t *obj);
<> 144:ef7eb2e8f9f7 113 static inline void spi_enable(spi_t *obj);
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 144:ef7eb2e8f9f7 116 {
<> 144:ef7eb2e8f9f7 117 int spi_n = get_available_spi(mosi, miso, sclk, ssel);
<> 144:ef7eb2e8f9f7 118 if (spi_n == -1) {
<> 144:ef7eb2e8f9f7 119 error("No available SPI");
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 obj->spi_n = spi_n;
<> 144:ef7eb2e8f9f7 123 spi_used |= (1 << spi_n);
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE);
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 const SWM_Map *swm;
<> 144:ef7eb2e8f9f7 128 uint32_t regVal;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 if (sclk != NC) {
<> 144:ef7eb2e8f9f7 131 swm = &SWM_SPI_SCLK[obj->spi_n];
<> 144:ef7eb2e8f9f7 132 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 133 LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 if (mosi != NC) {
<> 144:ef7eb2e8f9f7 137 swm = &SWM_SPI_MOSI[obj->spi_n];
<> 144:ef7eb2e8f9f7 138 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 139 LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 if (miso != NC) {
<> 144:ef7eb2e8f9f7 143 swm = &SWM_SPI_MISO[obj->spi_n];
<> 144:ef7eb2e8f9f7 144 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 145 LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 149 swm = &SWM_SPI_SSEL[obj->spi_n];
<> 144:ef7eb2e8f9f7 150 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 151 LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 // clear interrupts
<> 144:ef7eb2e8f9f7 155 obj->spi->INTENCLR = 0x3f;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 // enable power and clocking
<> 144:ef7eb2e8f9f7 158 LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1 << (obj->spi_n + 9));
<> 144:ef7eb2e8f9f7 159 LPC_SYSCON->PRESETCTRL1 |= (0x1 << (obj->spi_n + 9));
<> 144:ef7eb2e8f9f7 160 LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (obj->spi_n + 9));
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 void spi_free(spi_t *obj)
<> 144:ef7eb2e8f9f7 164 {
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 spi_disable(obj);
<> 144:ef7eb2e8f9f7 170 MBED_ASSERT((bits >= 1 && bits <= 16) && (mode >= 0 && mode <= 3));
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 int polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 173 int phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 // set it up
<> 144:ef7eb2e8f9f7 176 int LEN = bits - 1; // LEN - Data Length
<> 144:ef7eb2e8f9f7 177 int CPOL = (polarity) ? 1 : 0; // CPOL - Clock Polarity select
<> 144:ef7eb2e8f9f7 178 int CPHA = (phase) ? 1 : 0; // CPHA - Clock Phase select
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 uint32_t tmp = obj->spi->CFG;
<> 144:ef7eb2e8f9f7 181 tmp &= ~((1 << 5) | (1 << 4) | (1 << 2));
<> 144:ef7eb2e8f9f7 182 tmp |= (CPOL << 5) | (CPHA << 4) | ((slave ? 0 : 1) << 2);
<> 144:ef7eb2e8f9f7 183 obj->spi->CFG = tmp;
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 // select frame length
<> 144:ef7eb2e8f9f7 186 tmp = obj->spi->TXCTL;
<> 144:ef7eb2e8f9f7 187 tmp &= ~(0xf << 24);
<> 144:ef7eb2e8f9f7 188 tmp |= (LEN << 24);
<> 144:ef7eb2e8f9f7 189 obj->spi->TXCTL = tmp;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 spi_enable(obj);
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 void spi_frequency(spi_t *obj, int hz)
<> 144:ef7eb2e8f9f7 195 {
<> 144:ef7eb2e8f9f7 196 spi_disable(obj);
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 // rise DIV value if it cannot be divided
<> 144:ef7eb2e8f9f7 199 obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
<> 144:ef7eb2e8f9f7 200 obj->spi->DLY = 0;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 spi_enable(obj);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 static inline void spi_disable(spi_t *obj)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 obj->spi->CFG &= ~(1 << 0);
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 static inline void spi_enable(spi_t *obj)
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 obj->spi->CFG |= (1 << 0);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 static inline int spi_readable(spi_t *obj)
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 return obj->spi->STAT & (1 << 0);
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 static inline int spi_writeable(spi_t *obj)
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 return obj->spi->STAT & (1 << 1);
<> 144:ef7eb2e8f9f7 223 }
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 static inline void spi_write(spi_t *obj, int value)
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 while (!spi_writeable(obj));
<> 144:ef7eb2e8f9f7 228 // end of transfer
<> 144:ef7eb2e8f9f7 229 obj->spi->TXCTL |= (1 << 20);
<> 144:ef7eb2e8f9f7 230 obj->spi->TXDAT = (value & 0xffff);
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 static inline int spi_read(spi_t *obj)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 while (!spi_readable(obj));
<> 144:ef7eb2e8f9f7 236 return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 int spi_busy(spi_t *obj)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 // checking RXOV(Receiver Overrun interrupt flag)
<> 144:ef7eb2e8f9f7 242 return obj->spi->STAT & (1 << 2);
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 int spi_master_write(spi_t *obj, int value)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 spi_write(obj, value);
<> 144:ef7eb2e8f9f7 248 return spi_read(obj);
<> 144:ef7eb2e8f9f7 249 }
<> 144:ef7eb2e8f9f7 250
AnnaBridge 167:e84263d55307 251 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
AnnaBridge 167:e84263d55307 252 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 167:e84263d55307 253
AnnaBridge 167:e84263d55307 254 for (int i = 0; i < total; i++) {
AnnaBridge 167:e84263d55307 255 char out = (i < tx_length) ? tx_buffer[i] : 0xff;
AnnaBridge 167:e84263d55307 256 char in = spi_master_write(obj, out);
AnnaBridge 167:e84263d55307 257 if (i < rx_length) {
AnnaBridge 167:e84263d55307 258 rx_buffer[i] = in;
AnnaBridge 167:e84263d55307 259 }
AnnaBridge 167:e84263d55307 260 }
AnnaBridge 167:e84263d55307 261
AnnaBridge 167:e84263d55307 262 return total;
AnnaBridge 167:e84263d55307 263 }
AnnaBridge 167:e84263d55307 264
<> 144:ef7eb2e8f9f7 265 int spi_slave_receive(spi_t *obj)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 int spi_slave_read(spi_t *obj)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 void spi_slave_write(spi_t *obj, int value)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 while (spi_writeable(obj) == 0) ;
<> 144:ef7eb2e8f9f7 278 obj->spi->TXDAT = value;
<> 144:ef7eb2e8f9f7 279 }