Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_STM/mbed_rtx.h@168:9672193075cf, 2017-07-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Jul 06 15:42:05 2017 +0100
Revision:
168:9672193075cf
Parent:
167:e84263d55307
Child:
170:19eb464bc2be
This updates the lib to the mbed lib v 146

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2016 ARM Limited
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #ifndef MBED_MBED_RTX_H
<> 149:156823d33999 18 #define MBED_MBED_RTX_H
<> 149:156823d33999 19
<> 149:156823d33999 20 #if defined(TARGET_STM32F051R8)
<> 149:156823d33999 21
<> 149:156823d33999 22 #ifndef INITIAL_SP
<> 149:156823d33999 23 #define INITIAL_SP (0x20002000UL)
<> 149:156823d33999 24 #endif
<> 149:156823d33999 25
<> 149:156823d33999 26 #elif defined(TARGET_STM32L031K6)
<> 149:156823d33999 27
<> 149:156823d33999 28 #ifndef INITIAL_SP
<> 149:156823d33999 29 #define INITIAL_SP (0x20002000UL)
<> 149:156823d33999 30 #endif
<> 149:156823d33999 31
<> 149:156823d33999 32 #elif defined(TARGET_STM32F070RB)
<> 149:156823d33999 33
<> 149:156823d33999 34 #ifndef INITIAL_SP
<> 149:156823d33999 35 #define INITIAL_SP (0x20004000UL)
<> 149:156823d33999 36 #endif
<> 149:156823d33999 37
<> 149:156823d33999 38 #elif defined(TARGET_STM32F072RB)
<> 149:156823d33999 39
<> 149:156823d33999 40 #ifndef INITIAL_SP
<> 149:156823d33999 41 #define INITIAL_SP (0x20004000UL)
<> 149:156823d33999 42 #endif
<> 149:156823d33999 43
<> 149:156823d33999 44 #elif defined(TARGET_STM32F091RC)
<> 149:156823d33999 45
<> 149:156823d33999 46 #ifndef INITIAL_SP
<> 149:156823d33999 47 #define INITIAL_SP (0x20008000UL)
<> 149:156823d33999 48 #endif
<> 149:156823d33999 49
<> 149:156823d33999 50 #elif defined(TARGET_STM32F100RB)
<> 149:156823d33999 51
<> 149:156823d33999 52 #ifndef INITIAL_SP
<> 149:156823d33999 53 #define INITIAL_SP (0x20002000UL)
<> 149:156823d33999 54 #endif
<> 149:156823d33999 55
<> 149:156823d33999 56 #elif defined(TARGET_STM32F103RB)
<> 149:156823d33999 57
<> 149:156823d33999 58 #ifndef INITIAL_SP
<> 149:156823d33999 59 #define INITIAL_SP (0x20005000UL)
<> 149:156823d33999 60 #endif
<> 149:156823d33999 61
<> 149:156823d33999 62 #elif defined(TARGET_STM32F207ZG)
<> 149:156823d33999 63
<> 149:156823d33999 64 #ifndef INITIAL_SP
<> 149:156823d33999 65 #define INITIAL_SP (0x20020000UL)
<> 149:156823d33999 66 #endif
<> 149:156823d33999 67
<> 149:156823d33999 68 #elif defined(TARGET_STM32F303VC)
<> 149:156823d33999 69
<> 149:156823d33999 70 #ifndef INITIAL_SP
<> 149:156823d33999 71 #define INITIAL_SP (0x2000A000UL)
<> 149:156823d33999 72 #endif
<> 149:156823d33999 73
<> 149:156823d33999 74 #elif defined(TARGET_STM32F334C8)
<> 149:156823d33999 75
<> 149:156823d33999 76 #ifndef INITIAL_SP
<> 149:156823d33999 77 #define INITIAL_SP (0x20003000UL)
<> 149:156823d33999 78 #endif
<> 149:156823d33999 79
<> 149:156823d33999 80 #elif defined(TARGET_STM32F302R8)
<> 149:156823d33999 81
<> 149:156823d33999 82 #ifndef INITIAL_SP
<> 149:156823d33999 83 #define INITIAL_SP (0x20004000UL)
<> 149:156823d33999 84 #endif
<> 149:156823d33999 85
<> 149:156823d33999 86 #elif defined(TARGET_STM32F303K8)
<> 149:156823d33999 87
<> 149:156823d33999 88 #ifndef INITIAL_SP
<> 149:156823d33999 89 #define INITIAL_SP (0x20003000UL)
<> 149:156823d33999 90 #endif
<> 149:156823d33999 91
<> 149:156823d33999 92 #elif defined(TARGET_STM32F303RE)
<> 149:156823d33999 93
<> 149:156823d33999 94 #ifndef INITIAL_SP
<> 149:156823d33999 95 #define INITIAL_SP (0x20010000UL)
<> 149:156823d33999 96 #endif
<> 149:156823d33999 97
<> 149:156823d33999 98 #elif defined(TARGET_STM32F303ZE)
<> 149:156823d33999 99
<> 149:156823d33999 100 #ifndef INITIAL_SP
<> 149:156823d33999 101 #define INITIAL_SP (0x20010000UL)
<> 149:156823d33999 102 #endif
<> 149:156823d33999 103
<> 149:156823d33999 104 #elif defined(TARGET_STM32F334R8)
<> 149:156823d33999 105
<> 149:156823d33999 106 #ifndef INITIAL_SP
<> 149:156823d33999 107 #define INITIAL_SP (0x20003000UL)
<> 149:156823d33999 108 #endif
<> 149:156823d33999 109
<> 149:156823d33999 110 #elif defined(TARGET_STM32F446VE)
<> 149:156823d33999 111
<> 149:156823d33999 112 #ifndef INITIAL_SP
<> 149:156823d33999 113 #define INITIAL_SP (0x20020000UL)
<> 149:156823d33999 114 #endif
<> 149:156823d33999 115
<> 149:156823d33999 116 #elif defined(TARGET_STM32F401VC)
<> 149:156823d33999 117
<> 149:156823d33999 118 #ifndef INITIAL_SP
<> 149:156823d33999 119 #define INITIAL_SP (0x20010000UL)
<> 149:156823d33999 120 #endif
<> 149:156823d33999 121
<> 149:156823d33999 122 #elif (defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F439ZI))
<> 149:156823d33999 123
<> 149:156823d33999 124 #ifndef INITIAL_SP
<> 149:156823d33999 125 #define INITIAL_SP (0x20030000UL)
<> 149:156823d33999 126 #endif
<> 149:156823d33999 127
<> 149:156823d33999 128 #elif defined(TARGET_UBLOX_EVK_ODIN_W2)
<> 149:156823d33999 129
<> 149:156823d33999 130 #ifndef INITIAL_SP
<> 149:156823d33999 131 #define INITIAL_SP (0x20030000UL)
<> 149:156823d33999 132 #endif
<> 149:156823d33999 133
<> 162:e13f6fdb2ac4 134 #elif defined(TARGET_UBLOX_C030)
<> 162:e13f6fdb2ac4 135
<> 162:e13f6fdb2ac4 136 #ifndef INITIAL_SP
<> 162:e13f6fdb2ac4 137 #define INITIAL_SP (0x20030000UL)
<> 162:e13f6fdb2ac4 138 #endif
<> 162:e13f6fdb2ac4 139
<> 149:156823d33999 140 #elif defined(TARGET_STM32F469NI)
<> 149:156823d33999 141
<> 149:156823d33999 142 #ifndef INITIAL_SP
<> 149:156823d33999 143 #define INITIAL_SP (0x20050000UL)
<> 149:156823d33999 144 #endif
<> 149:156823d33999 145
<> 149:156823d33999 146 #elif defined(TARGET_STM32F405RG)
<> 149:156823d33999 147
<> 149:156823d33999 148 #ifndef INITIAL_SP
<> 149:156823d33999 149 #define INITIAL_SP (0x20020000UL)
<> 149:156823d33999 150 #endif
<> 149:156823d33999 151
<> 149:156823d33999 152 #elif defined(TARGET_STM32F401RE)
<> 149:156823d33999 153
<> 149:156823d33999 154 #ifndef INITIAL_SP
<> 149:156823d33999 155 #define INITIAL_SP (0x20018000UL)
<> 149:156823d33999 156 #endif
<> 149:156823d33999 157
<> 149:156823d33999 158 #elif defined(TARGET_STM32F410RB)
<> 149:156823d33999 159
<> 149:156823d33999 160 #ifndef INITIAL_SP
<> 149:156823d33999 161 #define INITIAL_SP (0x20008000UL)
<> 149:156823d33999 162 #endif
<> 149:156823d33999 163
<> 149:156823d33999 164 #elif defined(TARGET_MTS_MDOT_F411RE) || defined (TARGET_MTS_DRAGONFLY_F411RE)
<> 149:156823d33999 165
<> 149:156823d33999 166 #ifndef INITIAL_SP
<> 149:156823d33999 167 #define INITIAL_SP (0x20020000UL)
<> 149:156823d33999 168 #endif
<> 149:156823d33999 169
<> 149:156823d33999 170 #elif defined(TARGET_STM32F411RE)
<> 149:156823d33999 171
<> 149:156823d33999 172 #ifndef INITIAL_SP
<> 149:156823d33999 173 #define INITIAL_SP (0x20020000UL)
<> 149:156823d33999 174 #endif
<> 149:156823d33999 175
<> 153:fa9ff456f731 176 #elif defined(TARGET_STM32F412ZG)
<> 153:fa9ff456f731 177
<> 153:fa9ff456f731 178 #ifndef INITIAL_SP
<> 153:fa9ff456f731 179 #define INITIAL_SP (0x20040000UL)
<> 153:fa9ff456f731 180 #endif
<> 153:fa9ff456f731 181
AnnaBridge 168:9672193075cf 182 #elif defined(TARGET_STM32F413ZH)
AnnaBridge 168:9672193075cf 183
AnnaBridge 168:9672193075cf 184 #ifndef INITIAL_SP
AnnaBridge 168:9672193075cf 185 #define INITIAL_SP (0x20050000UL)
AnnaBridge 168:9672193075cf 186 #endif
AnnaBridge 168:9672193075cf 187 #ifndef OS_TASKCNT
AnnaBridge 168:9672193075cf 188 #define OS_TASKCNT 14
AnnaBridge 168:9672193075cf 189 #endif
AnnaBridge 168:9672193075cf 190 #ifndef OS_MAINSTKSIZE
AnnaBridge 168:9672193075cf 191 #define OS_MAINSTKSIZE 256
AnnaBridge 168:9672193075cf 192 #endif
AnnaBridge 168:9672193075cf 193 #ifndef OS_CLOCK
AnnaBridge 168:9672193075cf 194 #define OS_CLOCK 100000000
AnnaBridge 168:9672193075cf 195 #endif
AnnaBridge 168:9672193075cf 196
AnnaBridge 168:9672193075cf 197
<> 149:156823d33999 198 #elif defined(TARGET_STM32F446RE)
<> 149:156823d33999 199
<> 149:156823d33999 200 #ifndef INITIAL_SP
<> 149:156823d33999 201 #define INITIAL_SP (0x20020000UL)
<> 149:156823d33999 202 #endif
<> 149:156823d33999 203
<> 149:156823d33999 204 #elif defined(TARGET_STM32F446ZE)
<> 149:156823d33999 205
<> 149:156823d33999 206 #ifndef INITIAL_SP
<> 149:156823d33999 207 #define INITIAL_SP (0x20020000UL)
<> 149:156823d33999 208 #endif
<> 149:156823d33999 209
<> 149:156823d33999 210 #elif defined(TARGET_STM32F407VG)
<> 149:156823d33999 211
<> 149:156823d33999 212 #ifndef INITIAL_SP
<> 149:156823d33999 213 #define INITIAL_SP (0x20020000UL)
<> 149:156823d33999 214 #endif
<> 149:156823d33999 215
<> 149:156823d33999 216 #elif defined(TARGET_STM32F746NG)
<> 149:156823d33999 217
<> 149:156823d33999 218 #ifndef INITIAL_SP
<> 149:156823d33999 219 #define INITIAL_SP (0x20050000UL)
<> 149:156823d33999 220 #endif
<> 149:156823d33999 221
<> 149:156823d33999 222 #elif (defined(TARGET_STM32F746ZG) || defined(TARGET_STM32F756ZG))
<> 149:156823d33999 223
<> 149:156823d33999 224 #ifndef INITIAL_SP
<> 149:156823d33999 225 #define INITIAL_SP (0x20050000UL)
<> 149:156823d33999 226 #endif
<> 149:156823d33999 227
<> 149:156823d33999 228 #elif defined(TARGET_STM32F767ZI)
<> 149:156823d33999 229
<> 149:156823d33999 230 #ifndef INITIAL_SP
<> 149:156823d33999 231 #define INITIAL_SP (0x20080000UL)
<> 149:156823d33999 232 #endif
<> 149:156823d33999 233
<> 149:156823d33999 234 #elif defined(TARGET_STM32F769NI)
<> 149:156823d33999 235
<> 149:156823d33999 236 #ifndef INITIAL_SP
<> 149:156823d33999 237 #define INITIAL_SP (0x20080000UL)
<> 149:156823d33999 238 #endif
<> 149:156823d33999 239
<> 149:156823d33999 240 #elif defined(TARGET_STM32L053C8)
<> 149:156823d33999 241
<> 149:156823d33999 242 #ifndef INITIAL_SP
<> 149:156823d33999 243 #define INITIAL_SP (0x20002000UL)
<> 149:156823d33999 244 #endif
<> 149:156823d33999 245
<> 149:156823d33999 246 #elif defined(TARGET_STM32L031K6)
<> 149:156823d33999 247
<> 149:156823d33999 248 #ifndef INITIAL_SP
<> 149:156823d33999 249 #define INITIAL_SP (0x20002000UL)
<> 149:156823d33999 250 #endif
<> 149:156823d33999 251
<> 149:156823d33999 252 #elif defined(TARGET_STM32L053R8)
<> 149:156823d33999 253
<> 149:156823d33999 254 #ifndef INITIAL_SP
<> 149:156823d33999 255 #define INITIAL_SP (0x20002000UL)
<> 149:156823d33999 256 #endif
<> 149:156823d33999 257
AnnaBridge 165:e614a9f1c9e2 258 #elif defined(TARGET_STM32L072CZ)
AnnaBridge 165:e614a9f1c9e2 259
AnnaBridge 165:e614a9f1c9e2 260 #ifndef INITIAL_SP
AnnaBridge 165:e614a9f1c9e2 261 #define INITIAL_SP (0x20005000UL)
AnnaBridge 165:e614a9f1c9e2 262 #endif
AnnaBridge 165:e614a9f1c9e2 263
<> 149:156823d33999 264 #elif defined(TARGET_STM32L073RZ)
<> 149:156823d33999 265
<> 149:156823d33999 266 #ifndef INITIAL_SP
<> 149:156823d33999 267 #define INITIAL_SP (0x20005000UL)
<> 149:156823d33999 268 #endif
<> 149:156823d33999 269
<> 149:156823d33999 270 #elif defined(TARGET_STM32L152RC)
<> 149:156823d33999 271
<> 149:156823d33999 272 #ifndef INITIAL_SP
<> 149:156823d33999 273 #define INITIAL_SP (0x20008000UL)
<> 149:156823d33999 274 #endif
<> 149:156823d33999 275
<> 149:156823d33999 276 #elif defined(TARGET_STM32L152RE)
<> 149:156823d33999 277
<> 149:156823d33999 278 #ifndef INITIAL_SP
<> 149:156823d33999 279 #define INITIAL_SP (0x20014000UL)
<> 149:156823d33999 280 #endif
<> 149:156823d33999 281
<> 149:156823d33999 282 #elif defined(TARGET_NZ32_SC151)
<> 149:156823d33999 283
<> 149:156823d33999 284 #ifndef INITIAL_SP
<> 149:156823d33999 285 #define INITIAL_SP (0x20008000UL)
<> 149:156823d33999 286 #endif
<> 149:156823d33999 287
<> 149:156823d33999 288 #elif defined(TARGET_XDOT_L151CC)
<> 149:156823d33999 289
<> 149:156823d33999 290 #ifndef INITIAL_SP
<> 149:156823d33999 291 #define INITIAL_SP (0x20008000UL)
<> 149:156823d33999 292 #endif
<> 149:156823d33999 293
AnnaBridge 167:e84263d55307 294 #elif defined(TARGET_STM32L476VG) || defined(TARGET_STM32L475VG)
<> 149:156823d33999 295
<> 149:156823d33999 296 #ifndef INITIAL_SP
<> 149:156823d33999 297 #define INITIAL_SP (0x20018000UL)
<> 149:156823d33999 298 #endif
<> 149:156823d33999 299
<> 149:156823d33999 300 #elif defined(TARGET_STM32L432KC)
<> 149:156823d33999 301
<> 149:156823d33999 302 #ifndef INITIAL_SP
<> 149:156823d33999 303 #define INITIAL_SP (0x2000C000UL)
<> 149:156823d33999 304 #endif
<> 149:156823d33999 305
<> 149:156823d33999 306 #elif (defined(TARGET_STM32L476RG) || defined(TARGET_STM32L486RG))
<> 149:156823d33999 307
<> 149:156823d33999 308 #ifndef INITIAL_SP
<> 149:156823d33999 309 #define INITIAL_SP (0x20018000UL)
<> 149:156823d33999 310 #endif
<> 149:156823d33999 311
<> 149:156823d33999 312 #endif
<> 149:156823d33999 313
<> 149:156823d33999 314 #endif // MBED_MBED_RTX_H