Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
160:d5399cc887bb 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file i2c.c
<> 149:156823d33999 4 * @brief I2C driver
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: $
<> 149:156823d33999 8 * $Date: 2016-04-12 $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup i2c
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 *
<> 149:156823d33999 31 * <h1> Reference document(s) </h1>
<> 149:156823d33999 32 * <p>
<> 149:156823d33999 33 * IPC7208 APB I2C Master Design Specification v1.3
<> 149:156823d33999 34 * </p>
<> 149:156823d33999 35 * The I2C bus is an industry-standard two-wire (clock and data) serial communication bus between master(initiator) and slave device.
<> 149:156823d33999 36 * Within the procedure of the I2C-bus, unique situations arise which are defined as START and STOP conditions .A HIGH to LOW transition on
<> 149:156823d33999 37 * the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition.A LOW to HIGH transition on the
<> 149:156823d33999 38 * SDA line while SCL is HIGH defines a STOP condition.START and STOP conditions are always generated by the master. The bus is considered
<> 149:156823d33999 39 * to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition.
<> 149:156823d33999 40 * A master may start a transfer only if the bus is free. Two or more masters may generate a START condition.
<> 149:156823d33999 41 * Every byte put on the SDA line must be 8-bits long.Each byte has to be followed by an acknowledge bit.
<> 149:156823d33999 42 * This APB(Advanced peripheral bus) I2C Master is an APB Slave peripheral that can also serves as an I2C bus Master. The Command register
<> 149:156823d33999 43 * is the programming interface to the I2C Engine. The commands arrive at the I2C Engine via the Command FIFO,so the first valid command
<> 149:156823d33999 44 * that is written to the Command register is the first I2C instruction implemented on the I2C bus.Because the command interface provides
<> 149:156823d33999 45 * the basic building blocks for any I2C transaction, access to a wide range of I2C slave devices is supported.
<> 149:156823d33999 46 * I2C can be enabled by setting bit 7 of the control register .
<> 149:156823d33999 47 * There is a generated clock (a divided version of the APB clock) in this module that may be used as the I2C System Clock.
<> 149:156823d33999 48 * There are two FIFO in the I2C; Command FIFO and Read data FIFO
<> 149:156823d33999 49 * The commands(I2C instructions) and data arrive at the I2C Engine via the Command FIFO.
<> 149:156823d33999 50 * if the command FIFO is empty , up to 32 commands can be written to the command interface , it is programmer's responsibility to keep
<> 149:156823d33999 51 * the track of command FIFO's status either by interrupt or by polling method by reading status register, which represents Operational
<> 149:156823d33999 52 * Status of the I2C Module and its sub-modules.The action from the processor may be necessary after reading the status register.Reading
<> 149:156823d33999 53 * the Status register clears the blkInt Interrupt signal.Read data FIFO is where data read by the processor from I2C slave is placed .
<> 149:156823d33999 54 *
<> 149:156823d33999 55 *
<> 149:156823d33999 56 * <h1> Functional description (internal) </h1>
<> 149:156823d33999 57 * <p>
<> 149:156823d33999 58 *
<> 149:156823d33999 59 * </p>
<> 149:156823d33999 60 */
<> 149:156823d33999 61 #if DEVICE_I2C
<> 149:156823d33999 62 #include "i2c.h"
<> 160:d5399cc887bb 63 #include "mbed_wait_api.h"
<> 149:156823d33999 64
<> 149:156823d33999 65 /* See i2c.h for details */
<> 149:156823d33999 66 void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
<> 149:156823d33999 67 {
<> 149:156823d33999 68 uint32_t clockDivisor;
<> 149:156823d33999 69 /* determine the I2C to use */
<> 149:156823d33999 70 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
<> 149:156823d33999 71 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
<> 149:156823d33999 72 obj->membase = (I2cIpc7208Reg_pt)pinmap_merge(i2c_sda, i2c_scl);
<> 149:156823d33999 73 MBED_ASSERT((int)obj->membase != NC);
<> 149:156823d33999 74
<> 149:156823d33999 75 /* By default disbale interrupts */
<> 149:156823d33999 76 obj->membase->IER.WORD = False;
<> 149:156823d33999 77
<> 149:156823d33999 78 /* enable interrupt associated with the device */
<> 149:156823d33999 79 if(obj->membase == I2C1REG) {
<> 149:156823d33999 80 CLOCK_ENABLE(CLOCK_I2C); /* enable i2c peripheral */
<> 149:156823d33999 81 NVIC_ClearPendingIRQ(I2C_IRQn);
<> 149:156823d33999 82 NVIC_EnableIRQ(I2C_IRQn);
<> 149:156823d33999 83 } else {
<> 149:156823d33999 84 CLOCK_ENABLE(CLOCK_I2C2); /* enable i2c peripheral */
<> 149:156823d33999 85 NVIC_ClearPendingIRQ(I2C2_IRQn);
<> 149:156823d33999 86 NVIC_EnableIRQ(I2C2_IRQn);
<> 149:156823d33999 87 }
<> 149:156823d33999 88
<> 149:156823d33999 89 /*select I2C clock source */
<> 149:156823d33999 90 obj->membase->CR.BITS.I2C_CLK_SRC = True;
<> 149:156823d33999 91
<> 149:156823d33999 92 /* enable I2C clock divider */
<> 149:156823d33999 93 obj->membase->CR.BITS.I2C_APB_CD_EN = True;
<> 149:156823d33999 94
<> 149:156823d33999 95 /* set default baud rate at 100k */
<> 149:156823d33999 96 clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2;
<> 149:156823d33999 97 obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
<> 149:156823d33999 98 obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
<> 149:156823d33999 99
<> 149:156823d33999 100 /* Cross bar setting */
<> 149:156823d33999 101 pinmap_pinout(sda, PinMap_I2C_SDA);
<> 149:156823d33999 102 pinmap_pinout(scl, PinMap_I2C_SCL);
<> 149:156823d33999 103
<> 149:156823d33999 104 /*Enable open drain & pull up for sda & scl pin */
<> 149:156823d33999 105 pin_mode(sda, OpenDrainPullUp);
<> 149:156823d33999 106 pin_mode(scl, OpenDrainPullUp);
<> 149:156823d33999 107
<> 149:156823d33999 108 /* PAD drive strength */
<> 149:156823d33999 109 PadReg_t *padRegSda = (PadReg_t*)(PADREG_BASE + (sda * PAD_REG_ADRS_BYTE_SIZE));
<> 149:156823d33999 110 PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE));
<> 149:156823d33999 111
<> 149:156823d33999 112 CLOCK_ENABLE(CLOCK_PAD);
<> 149:156823d33999 113 padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */
<> 149:156823d33999 114 padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */
<> 149:156823d33999 115 CLOCK_DISABLE(CLOCK_PAD);
<> 149:156823d33999 116
<> 149:156823d33999 117 CLOCK_ENABLE(CLOCK_GPIO);
<> 149:156823d33999 118 GPIOREG->W_OUT |= ((True << sda) | (True << scl));
<> 149:156823d33999 119 CLOCK_DISABLE(CLOCK_GPIO);
<> 149:156823d33999 120
<> 149:156823d33999 121 /* Enable i2c module */
<> 149:156823d33999 122 obj->membase->CR.BITS.I2C_MODULE_EN = True;
<> 149:156823d33999 123 }
<> 149:156823d33999 124
<> 149:156823d33999 125 /* See i2c.h for details */
<> 149:156823d33999 126 void fI2cFrequency(i2c_t *obj, uint32_t hz)
<> 149:156823d33999 127 {
<> 149:156823d33999 128 /* Set user baud rate */
<> 149:156823d33999 129 uint32_t clockDivisor;
<> 149:156823d33999 130 clockDivisor = ((fClockGetPeriphClockfrequency() / hz) >> 2) - 2;
<> 149:156823d33999 131 obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
<> 149:156823d33999 132 obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
<> 149:156823d33999 133 }
<> 149:156823d33999 134
<> 149:156823d33999 135 /* See i2c.h for details */
<> 149:156823d33999 136 int32_t fI2cStart(i2c_t *obj)
<> 149:156823d33999 137 {
<> 149:156823d33999 138 /* Send start bit */
<> 159:612c381a210f 139 SEND_COMMAND(I2C_CMD_START);
<> 149:156823d33999 140 return I2C_API_STATUS_SUCCESS;
<> 149:156823d33999 141 }
<> 149:156823d33999 142
<> 149:156823d33999 143 /* See i2c.h for details */
<> 149:156823d33999 144 int32_t fI2cStop(i2c_t *obj)
<> 149:156823d33999 145 {
<> 149:156823d33999 146 /* Send stop bit */
<> 159:612c381a210f 147 SEND_COMMAND(I2C_CMD_STOP);
<> 149:156823d33999 148 if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT |
<> 149:156823d33999 149 I2C_STATUS_CMD_FIFO_OFL_BIT |
<> 149:156823d33999 150 I2C_STATUS_BUS_ERR_BIT)) {
<> 149:156823d33999 151 /* I2c error occured */
<> 149:156823d33999 152 return I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 153 }
<> 149:156823d33999 154 return I2C_API_STATUS_SUCCESS;
<> 149:156823d33999 155 }
<> 149:156823d33999 156
<> 149:156823d33999 157 /* See i2c.h for details */
<> 159:612c381a210f 158 int32_t fI2cReadB(i2c_t *obj, char *buf, int len)
<> 149:156823d33999 159 {
<> 149:156823d33999 160 int32_t read = 0;
<> 149:156823d33999 161
<> 149:156823d33999 162 while (read < len) {
<> 149:156823d33999 163 /* Send read command */
<> 159:612c381a210f 164 SEND_COMMAND(I2C_CMD_RDAT8);
<> 149:156823d33999 165 while(!RD_DATA_READY) {
<> 149:156823d33999 166 if (I2C_BUS_ERR_CHECK) {
<> 149:156823d33999 167 /* Bus error occured */
<> 149:156823d33999 168 return I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 169 }
<> 149:156823d33999 170 }
<> 159:612c381a210f 171 buf[read++] = obj->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */
<> 149:156823d33999 172
<> 149:156823d33999 173 if(!(read>=len)) { /* No ACK will be generated for the last read, upper level I2C protocol should generate */
<> 159:612c381a210f 174 SEND_COMMAND(I2C_CMD_WDAT0); /* TODO based on requirement generate ACK or NACK Based on the requirement. */
<> 159:612c381a210f 175 } else {
<> 159:612c381a210f 176 /* No ack */
<> 159:612c381a210f 177 SEND_COMMAND(I2C_CMD_WDAT1);
<> 149:156823d33999 178 }
<> 149:156823d33999 179
<> 149:156823d33999 180 /* check for FIFO underflow */
<> 149:156823d33999 181 if(I2C_UFL_CHECK) {
<> 149:156823d33999 182 return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */
<> 149:156823d33999 183 }
<> 149:156823d33999 184 if(I2C_BUS_ERR_CHECK) {
<> 149:156823d33999 185 /* Bus error */
<> 149:156823d33999 186 return I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 187 }
<> 149:156823d33999 188 }
<> 149:156823d33999 189
<> 149:156823d33999 190 return read;
<> 149:156823d33999 191 }
<> 149:156823d33999 192
<> 149:156823d33999 193 /* See i2c.h for details */
<> 159:612c381a210f 194 int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len)
<> 149:156823d33999 195 {
<> 149:156823d33999 196 int32_t write = 0;
<> 149:156823d33999 197
<> 149:156823d33999 198 while (write < len) {
<> 149:156823d33999 199 /* Send write command */
<> 159:612c381a210f 200 SEND_COMMAND(I2C_CMD_WDAT8);
<> 159:612c381a210f 201
<> 149:156823d33999 202 if(buf[write] == I2C_CMD_RDAT8) {
<> 149:156823d33999 203 /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13)
<> 149:156823d33999 204 then as the command is read out (i.e. the FIFO goes empty), the WDAT8 command will be misinterpreted as a
<> 149:156823d33999 205 RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */
<> 149:156823d33999 206 /* Send 0x13 bit wise */
<> 159:612c381a210f 207 SEND_COMMAND(I2C_CMD_WDAT0);
<> 159:612c381a210f 208
<> 159:612c381a210f 209 SEND_COMMAND(I2C_CMD_WDAT0);
<> 159:612c381a210f 210
<> 159:612c381a210f 211 SEND_COMMAND(I2C_CMD_WDAT0);
<> 159:612c381a210f 212
<> 159:612c381a210f 213 SEND_COMMAND(I2C_CMD_WDAT1);
<> 149:156823d33999 214
<> 159:612c381a210f 215 SEND_COMMAND(I2C_CMD_WDAT0);
<> 159:612c381a210f 216
<> 159:612c381a210f 217 SEND_COMMAND(I2C_CMD_WDAT0);
<> 159:612c381a210f 218
<> 159:612c381a210f 219 SEND_COMMAND(I2C_CMD_WDAT1);
<> 159:612c381a210f 220
<> 159:612c381a210f 221 SEND_COMMAND(I2C_CMD_WDAT1);
<> 149:156823d33999 222 } else {
<> 149:156823d33999 223 /* Send data */
<> 159:612c381a210f 224 SEND_COMMAND(buf[write++]);
<> 149:156823d33999 225 }
<> 159:612c381a210f 226 SEND_COMMAND(I2C_CMD_VRFY_ACK); /* TODO Verify ACK based on requirement, Do we need? */
<> 149:156823d33999 227
<> 149:156823d33999 228 if (I2C_BUS_ERR_CHECK) {
<> 149:156823d33999 229 /* Bus error */
<> 149:156823d33999 230 return I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 231 }
<> 159:612c381a210f 232
<> 159:612c381a210f 233 while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
<> 149:156823d33999 234 }
<> 149:156823d33999 235
<> 149:156823d33999 236 return write;
<> 149:156823d33999 237 }
<> 149:156823d33999 238
<> 159:612c381a210f 239 #endif /* DEVICE_I2C */