Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
156:95d6b41a828b 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include "pwmout_api.h"
<> 144:ef7eb2e8f9f7 18 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 19 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 20 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 static LPC_SCT0_Type *SCTs[4] = {
<> 144:ef7eb2e8f9f7 23 (LPC_SCT0_Type*)LPC_SCT0,
<> 144:ef7eb2e8f9f7 24 (LPC_SCT0_Type*)LPC_SCT1,
<> 144:ef7eb2e8f9f7 25 (LPC_SCT0_Type*)LPC_SCT2,
<> 144:ef7eb2e8f9f7 26 (LPC_SCT0_Type*)LPC_SCT3,
<> 144:ef7eb2e8f9f7 27 };
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 // bit flags for used SCTs
<> 144:ef7eb2e8f9f7 30 static unsigned char sct_used = (1 << 3);
<> 144:ef7eb2e8f9f7 31 static int get_available_sct(void) {
<> 144:ef7eb2e8f9f7 32 int i;
<> 144:ef7eb2e8f9f7 33 for (i=0; i<4; i++) {
<> 144:ef7eb2e8f9f7 34 if ((sct_used & (1 << i)) == 0)
<> 144:ef7eb2e8f9f7 35 return i;
<> 144:ef7eb2e8f9f7 36 }
<> 144:ef7eb2e8f9f7 37 return -1;
<> 144:ef7eb2e8f9f7 38 }
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 void pwmout_init(pwmout_t* obj, PinName pin) {
<> 144:ef7eb2e8f9f7 41 MBED_ASSERT(pin != (uint32_t)NC);
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 int sct_n = get_available_sct();
<> 144:ef7eb2e8f9f7 44 if (sct_n == -1) {
<> 144:ef7eb2e8f9f7 45 error("No available SCT");
<> 144:ef7eb2e8f9f7 46 }
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 sct_used |= (1 << sct_n);
<> 144:ef7eb2e8f9f7 49 obj->pwm = SCTs[sct_n];
<> 144:ef7eb2e8f9f7 50 obj->pwm_ch = sct_n;
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 LPC_SCT0_Type* pwm = obj->pwm;
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 // Enable the SCT clock
<> 144:ef7eb2e8f9f7 55 LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << (obj->pwm_ch + 2));
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 // Clear peripheral reset the SCT:
<> 144:ef7eb2e8f9f7 58 LPC_SYSCON->PRESETCTRL1 |= (1 << (obj->pwm_ch + 2));
<> 144:ef7eb2e8f9f7 59 LPC_SYSCON->PRESETCTRL1 &= ~(1 << (obj->pwm_ch + 2));
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 switch(obj->pwm_ch) {
<> 144:ef7eb2e8f9f7 62 case 0:
<> 144:ef7eb2e8f9f7 63 // SCT0_OUT0
<> 144:ef7eb2e8f9f7 64 LPC_SWM->PINASSIGN[7] &= ~0x0000FF00;
<> 144:ef7eb2e8f9f7 65 LPC_SWM->PINASSIGN[7] |= (pin << 8);
<> 144:ef7eb2e8f9f7 66 break;
<> 144:ef7eb2e8f9f7 67 case 1:
<> 144:ef7eb2e8f9f7 68 // SCT1_OUT0
<> 144:ef7eb2e8f9f7 69 LPC_SWM->PINASSIGN[8] &= ~0x000000FF;
<> 144:ef7eb2e8f9f7 70 LPC_SWM->PINASSIGN[8] |= (pin);
<> 144:ef7eb2e8f9f7 71 break;
<> 144:ef7eb2e8f9f7 72 case 2:
<> 144:ef7eb2e8f9f7 73 // SCT2_OUT0
<> 144:ef7eb2e8f9f7 74 LPC_SWM->PINASSIGN[8] &= ~0xFF000000;
<> 144:ef7eb2e8f9f7 75 LPC_SWM->PINASSIGN[8] |= (pin << 24);
<> 144:ef7eb2e8f9f7 76 break;
<> 144:ef7eb2e8f9f7 77 case 3:
<> 144:ef7eb2e8f9f7 78 // SCT3_OUT0
<> 144:ef7eb2e8f9f7 79 LPC_SWM->PINASSIGN[9] &= ~0x00FF0000;
<> 144:ef7eb2e8f9f7 80 LPC_SWM->PINASSIGN[9] |= (pin << 16);
<> 144:ef7eb2e8f9f7 81 break;
<> 144:ef7eb2e8f9f7 82 default:
<> 144:ef7eb2e8f9f7 83 break;
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 // Unified 32-bit counter, autolimit
<> 144:ef7eb2e8f9f7 87 pwm->CONFIG |= ((0x3 << 17) | 0x01);
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // halt and clear the counter
<> 144:ef7eb2e8f9f7 90 pwm->CTRL |= (1 << 2) | (1 << 3);
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 pwm->OUT0_SET = (1 << 0); // event 0
<> 144:ef7eb2e8f9f7 93 pwm->OUT0_CLR = (1 << 1); // event 1
<> 156:95d6b41a828b 94 // Resolve conflicts on output 0 to set output
<> 156:95d6b41a828b 95 // This allows duty cycle = 1.0 to work, where the MATCH registers for set and clear are equal
<> 156:95d6b41a828b 96 pwm->RES = 0x01;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 pwm->EV0_CTRL = (1 << 12);
<> 144:ef7eb2e8f9f7 99 pwm->EV0_STATE = 0xFFFFFFFF;
<> 144:ef7eb2e8f9f7 100 pwm->EV1_CTRL = (1 << 12) | (1 << 0);
<> 144:ef7eb2e8f9f7 101 pwm->EV1_STATE = 0xFFFFFFFF;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // default to 20ms: standard for servos, and fine for e.g. brightness control
<> 144:ef7eb2e8f9f7 104 pwmout_period_ms(obj, 20);
<> 144:ef7eb2e8f9f7 105 pwmout_write (obj, 0);
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 void pwmout_free(pwmout_t* obj) {
<> 144:ef7eb2e8f9f7 109 // Disable the SCT clock
<> 144:ef7eb2e8f9f7 110 LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1 << (obj->pwm_ch + 2));
<> 144:ef7eb2e8f9f7 111 sct_used &= ~(1 << obj->pwm_ch);
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 void pwmout_write(pwmout_t* obj, float value) {
<> 144:ef7eb2e8f9f7 115 LPC_SCT0_Type* pwm = obj->pwm;
<> 144:ef7eb2e8f9f7 116 if (value < 0.0f) {
<> 144:ef7eb2e8f9f7 117 value = 0.0;
<> 144:ef7eb2e8f9f7 118 } else if (value > 1.0f) {
<> 144:ef7eb2e8f9f7 119 value = 1.0;
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121 uint32_t t_on = (uint32_t)((float)(pwm->MATCHREL0 + 1) * value);
<> 144:ef7eb2e8f9f7 122 if (t_on > 0) {
<> 144:ef7eb2e8f9f7 123 pwm->MATCHREL1 = t_on - 1;
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 // Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
<> 144:ef7eb2e8f9f7 126 if (pwm->CTRL & (1 << 2)) {
<> 144:ef7eb2e8f9f7 127 pwm->MATCH1 = pwm->MATCHREL1;
<> 144:ef7eb2e8f9f7 128 pwm->CTRL &= ~(1 << 2);
<> 144:ef7eb2e8f9f7 129 }
<> 144:ef7eb2e8f9f7 130 } else {
<> 144:ef7eb2e8f9f7 131 // Halt the timer and force the output low
<> 144:ef7eb2e8f9f7 132 pwm->CTRL |= (1 << 2) | (1 << 3);
<> 144:ef7eb2e8f9f7 133 pwm->OUTPUT = 0x00000000;
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 float pwmout_read(pwmout_t* obj) {
<> 144:ef7eb2e8f9f7 138 LPC_SCT0_Type* pwm = obj->pwm;
<> 144:ef7eb2e8f9f7 139 uint32_t t_off = pwm->MATCHREL0 + 1;
<> 144:ef7eb2e8f9f7 140 uint32_t t_on = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
<> 144:ef7eb2e8f9f7 141 float v = (float)t_on/(float)t_off;
<> 144:ef7eb2e8f9f7 142 return (v > 1.0f) ? (1.0f) : (v);
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 void pwmout_period(pwmout_t* obj, float seconds) {
<> 144:ef7eb2e8f9f7 146 pwmout_period_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 void pwmout_period_ms(pwmout_t* obj, int ms) {
<> 144:ef7eb2e8f9f7 150 pwmout_period_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 // Set the PWM period, keeping the duty cycle the same.
<> 144:ef7eb2e8f9f7 154 void pwmout_period_us(pwmout_t* obj, int us) {
<> 144:ef7eb2e8f9f7 155 LPC_SCT0_Type* pwm = obj->pwm;
<> 144:ef7eb2e8f9f7 156 uint32_t t_off = pwm->MATCHREL0 + 1;
<> 144:ef7eb2e8f9f7 157 uint32_t t_on = (!(pwm->CTRL & (1 << 2))) ? pwm->MATCHREL1 + 1 : 0;
<> 144:ef7eb2e8f9f7 158 float v = (float)t_on/(float)t_off;
<> 144:ef7eb2e8f9f7 159 uint32_t period_ticks = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
<> 144:ef7eb2e8f9f7 160 uint32_t pulsewidth_ticks = period_ticks * v;
<> 144:ef7eb2e8f9f7 161 pwm->MATCHREL0 = period_ticks - 1;
<> 144:ef7eb2e8f9f7 162 if (pulsewidth_ticks > 0) {
<> 144:ef7eb2e8f9f7 163 pwm->MATCHREL1 = pulsewidth_ticks - 1;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 // Un-halt the timer and ensure the new period & pulse-width take immediate effect if necessary
<> 144:ef7eb2e8f9f7 166 if (pwm->CTRL & (1 << 2)) {
<> 144:ef7eb2e8f9f7 167 pwm->MATCH0 = pwm->MATCHREL0;
<> 144:ef7eb2e8f9f7 168 pwm->MATCH1 = pwm->MATCHREL1;
<> 144:ef7eb2e8f9f7 169 pwm->CTRL &= ~(1 << 2);
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171 } else {
<> 144:ef7eb2e8f9f7 172 // Halt the timer and force the output low
<> 144:ef7eb2e8f9f7 173 pwm->CTRL |= (1 << 2) | (1 << 3);
<> 144:ef7eb2e8f9f7 174 pwm->OUTPUT = 0x00000000;
<> 156:95d6b41a828b 175
<> 144:ef7eb2e8f9f7 176 // Ensure the new period will take immediate effect when the timer is un-halted
<> 144:ef7eb2e8f9f7 177 pwm->MATCH0 = pwm->MATCHREL0;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
<> 144:ef7eb2e8f9f7 182 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
<> 144:ef7eb2e8f9f7 186 pwmout_pulsewidth_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
<> 144:ef7eb2e8f9f7 190 LPC_SCT0_Type* pwm = obj->pwm;
<> 144:ef7eb2e8f9f7 191 if (us > 0) {
<> 144:ef7eb2e8f9f7 192 pwm->MATCHREL1 = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000) - 1;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 // Un-halt the timer and ensure the new pulse-width takes immediate effect if necessary
<> 144:ef7eb2e8f9f7 195 if (pwm->CTRL & (1 << 2)) {
<> 144:ef7eb2e8f9f7 196 pwm->MATCH1 = pwm->MATCHREL1;
<> 144:ef7eb2e8f9f7 197 pwm->CTRL &= ~(1 << 2);
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199 } else {
<> 144:ef7eb2e8f9f7 200 // Halt the timer and force the output low
<> 144:ef7eb2e8f9f7 201 pwm->CTRL |= (1 << 2) | (1 << 3);
<> 144:ef7eb2e8f9f7 202 pwm->OUTPUT = 0x00000000;
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205