Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
172:7d866c31b3c5 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include <math.h>
<> 144:ef7eb2e8f9f7 18 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 19 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 20 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 21 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 22 #include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 static inline int ssp_disable(spi_t *obj);
<> 144:ef7eb2e8f9f7 25 static inline int ssp_enable(spi_t *obj);
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 28 // determine the SPI to use
<> 144:ef7eb2e8f9f7 29 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 30 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 31 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 32 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 33 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 34 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 37 MBED_ASSERT((int)obj->spi != NC);
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 // enable power and clocking
<> 144:ef7eb2e8f9f7 40 switch ((int)obj->spi) {
<> 144:ef7eb2e8f9f7 41 case SPI_0:
<> 144:ef7eb2e8f9f7 42 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
<> 144:ef7eb2e8f9f7 43 LPC_SYSCON->SSP0CLKDIV = 0x01;
<> 144:ef7eb2e8f9f7 44 LPC_SYSCON->PRESETCTRL |= 1 << 0;
<> 144:ef7eb2e8f9f7 45 break;
<> 144:ef7eb2e8f9f7 46 case SPI_1:
<> 144:ef7eb2e8f9f7 47 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
<> 144:ef7eb2e8f9f7 48 LPC_SYSCON->SSP1CLKDIV = 0x01;
<> 144:ef7eb2e8f9f7 49 LPC_SYSCON->PRESETCTRL |= 1 << 2;
<> 144:ef7eb2e8f9f7 50 break;
<> 144:ef7eb2e8f9f7 51 }
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 // pin out the spi pins
<> 144:ef7eb2e8f9f7 54 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 55 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 56 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 57 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 58 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 59 }
<> 144:ef7eb2e8f9f7 60 }
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 void spi_free(spi_t *obj) {}
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 65 MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3));
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 int polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 70 int phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 // set it up
<> 144:ef7eb2e8f9f7 73 int DSS = bits - 1; // DSS (data select size)
<> 144:ef7eb2e8f9f7 74 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
<> 144:ef7eb2e8f9f7 75 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 int FRF = 0; // FRF (frame format) = SPI
<> 144:ef7eb2e8f9f7 78 uint32_t tmp = obj->spi->CR0;
AnnaBridge 172:7d866c31b3c5 79 tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
<> 144:ef7eb2e8f9f7 80 tmp |= DSS << 0
<> 144:ef7eb2e8f9f7 81 | FRF << 4
<> 144:ef7eb2e8f9f7 82 | SPO << 6
<> 144:ef7eb2e8f9f7 83 | SPH << 7;
<> 144:ef7eb2e8f9f7 84 obj->spi->CR0 = tmp;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 tmp = obj->spi->CR1;
<> 144:ef7eb2e8f9f7 87 tmp &= ~(0xD);
<> 144:ef7eb2e8f9f7 88 tmp |= 0 << 0 // LBM - loop back mode - off
<> 144:ef7eb2e8f9f7 89 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
<> 144:ef7eb2e8f9f7 90 | 0 << 3; // SOD - slave output disable - na
<> 144:ef7eb2e8f9f7 91 obj->spi->CR1 = tmp;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 94 }
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 97 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 uint32_t PCLK = SystemCoreClock;
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 int prescaler;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
<> 144:ef7eb2e8f9f7 104 int prescale_hz = PCLK / prescaler;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 // calculate the divider
<> 144:ef7eb2e8f9f7 107 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 // check we can support the divider
<> 144:ef7eb2e8f9f7 110 if (divider < 256) {
<> 144:ef7eb2e8f9f7 111 // prescaler
<> 144:ef7eb2e8f9f7 112 obj->spi->CPSR = prescaler;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 // divider
AnnaBridge 172:7d866c31b3c5 115 obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
<> 144:ef7eb2e8f9f7 116 obj->spi->CR0 |= (divider - 1) << 8;
<> 144:ef7eb2e8f9f7 117 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 118 return;
<> 144:ef7eb2e8f9f7 119 }
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121 error("Couldn't setup requested SPI frequency");
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 static inline int ssp_disable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 125 return obj->spi->CR1 &= ~(1 << 1);
<> 144:ef7eb2e8f9f7 126 }
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 static inline int ssp_enable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 129 return obj->spi->CR1 |= (1 << 1);
<> 144:ef7eb2e8f9f7 130 }
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 static inline int ssp_readable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 133 return obj->spi->SR & (1 << 2);
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 static inline int ssp_writeable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 137 return obj->spi->SR & (1 << 1);
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 static inline void ssp_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 141 while (!ssp_writeable(obj));
<> 144:ef7eb2e8f9f7 142 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 static inline int ssp_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 146 while (!ssp_readable(obj));
<> 144:ef7eb2e8f9f7 147 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 static inline int ssp_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 151 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 155 ssp_write(obj, value);
<> 144:ef7eb2e8f9f7 156 return ssp_read(obj);
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
Kojto 170:19eb464bc2be 159 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 170:19eb464bc2be 160 char *rx_buffer, int rx_length, char write_fill) {
AnnaBridge 167:e84263d55307 161 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 167:e84263d55307 162
AnnaBridge 167:e84263d55307 163 for (int i = 0; i < total; i++) {
Kojto 170:19eb464bc2be 164 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 167:e84263d55307 165 char in = spi_master_write(obj, out);
AnnaBridge 167:e84263d55307 166 if (i < rx_length) {
AnnaBridge 167:e84263d55307 167 rx_buffer[i] = in;
AnnaBridge 167:e84263d55307 168 }
AnnaBridge 167:e84263d55307 169 }
AnnaBridge 167:e84263d55307 170
AnnaBridge 167:e84263d55307 171 return total;
AnnaBridge 167:e84263d55307 172 }
AnnaBridge 167:e84263d55307 173
<> 144:ef7eb2e8f9f7 174 int spi_slave_receive(spi_t *obj) {
<> 144:ef7eb2e8f9f7 175 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 int spi_slave_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 179 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 void spi_slave_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 183 while (ssp_writeable(obj) == 0) ;
<> 144:ef7eb2e8f9f7 184 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 int spi_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 188 return ssp_busy(obj);
<> 144:ef7eb2e8f9f7 189 }