Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
176:447f873cad2f 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /* mbed Microcontroller Library
AnnaBridge 172:7d866c31b3c5 2 * Copyright (c) 2015-2016 Nuvoton
AnnaBridge 172:7d866c31b3c5 3 *
AnnaBridge 172:7d866c31b3c5 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 172:7d866c31b3c5 5 * you may not use this file except in compliance with the License.
AnnaBridge 172:7d866c31b3c5 6 * You may obtain a copy of the License at
AnnaBridge 172:7d866c31b3c5 7 *
AnnaBridge 172:7d866c31b3c5 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 172:7d866c31b3c5 9 *
AnnaBridge 172:7d866c31b3c5 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 172:7d866c31b3c5 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 172:7d866c31b3c5 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 172:7d866c31b3c5 13 * See the License for the specific language governing permissions and
AnnaBridge 172:7d866c31b3c5 14 * limitations under the License.
AnnaBridge 172:7d866c31b3c5 15 */
AnnaBridge 172:7d866c31b3c5 16
AnnaBridge 172:7d866c31b3c5 17 #include "pwmout_api.h"
AnnaBridge 172:7d866c31b3c5 18
AnnaBridge 172:7d866c31b3c5 19 #if DEVICE_PWMOUT
AnnaBridge 172:7d866c31b3c5 20
AnnaBridge 172:7d866c31b3c5 21 #include "cmsis.h"
AnnaBridge 172:7d866c31b3c5 22 #include "pinmap.h"
AnnaBridge 172:7d866c31b3c5 23 #include "PeripheralPins.h"
AnnaBridge 172:7d866c31b3c5 24 #include "nu_modutil.h"
AnnaBridge 172:7d866c31b3c5 25 #include "nu_miscutil.h"
AnnaBridge 172:7d866c31b3c5 26 #include "nu_bitutil.h"
AnnaBridge 172:7d866c31b3c5 27
AnnaBridge 172:7d866c31b3c5 28 struct nu_pwm_var {
AnnaBridge 172:7d866c31b3c5 29 uint32_t en_msk;
AnnaBridge 172:7d866c31b3c5 30 };
AnnaBridge 172:7d866c31b3c5 31
AnnaBridge 172:7d866c31b3c5 32 static struct nu_pwm_var pwm0_var = {
AnnaBridge 172:7d866c31b3c5 33 .en_msk = 0
AnnaBridge 172:7d866c31b3c5 34 };
AnnaBridge 172:7d866c31b3c5 35
AnnaBridge 172:7d866c31b3c5 36 static struct nu_pwm_var pwm1_var = {
AnnaBridge 172:7d866c31b3c5 37 .en_msk = 0
AnnaBridge 172:7d866c31b3c5 38 };
AnnaBridge 172:7d866c31b3c5 39
AnnaBridge 172:7d866c31b3c5 40 static uint32_t pwm_modinit_mask = 0;
AnnaBridge 172:7d866c31b3c5 41
AnnaBridge 172:7d866c31b3c5 42 static const struct nu_modinit_s pwm_modinit_tab[] = {
AnnaBridge 172:7d866c31b3c5 43 {PWM_0_0, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P0_IRQn, &pwm0_var},
AnnaBridge 172:7d866c31b3c5 44 {PWM_0_1, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P0_IRQn, &pwm0_var},
AnnaBridge 172:7d866c31b3c5 45 {PWM_0_2, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P1_IRQn, &pwm0_var},
AnnaBridge 172:7d866c31b3c5 46 {PWM_0_3, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P1_IRQn, &pwm0_var},
AnnaBridge 172:7d866c31b3c5 47 {PWM_0_4, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P2_IRQn, &pwm0_var},
AnnaBridge 172:7d866c31b3c5 48 {PWM_0_5, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P2_IRQn, &pwm0_var},
AnnaBridge 172:7d866c31b3c5 49
AnnaBridge 172:7d866c31b3c5 50 {PWM_1_0, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P0_IRQn, &pwm1_var},
AnnaBridge 172:7d866c31b3c5 51 {PWM_1_1, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P0_IRQn, &pwm1_var},
AnnaBridge 172:7d866c31b3c5 52 {PWM_1_2, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P1_IRQn, &pwm1_var},
AnnaBridge 172:7d866c31b3c5 53 {PWM_1_3, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P1_IRQn, &pwm1_var},
AnnaBridge 172:7d866c31b3c5 54 {PWM_1_4, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P2_IRQn, &pwm1_var},
AnnaBridge 172:7d866c31b3c5 55 {PWM_1_5, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P2_IRQn, &pwm1_var},
AnnaBridge 172:7d866c31b3c5 56
AnnaBridge 172:7d866c31b3c5 57 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
AnnaBridge 172:7d866c31b3c5 58 };
AnnaBridge 172:7d866c31b3c5 59
AnnaBridge 172:7d866c31b3c5 60 static void pwmout_config(pwmout_t* obj, int start);
AnnaBridge 172:7d866c31b3c5 61
AnnaBridge 172:7d866c31b3c5 62 void pwmout_init(pwmout_t* obj, PinName pin)
AnnaBridge 172:7d866c31b3c5 63 {
AnnaBridge 172:7d866c31b3c5 64 obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
AnnaBridge 172:7d866c31b3c5 65 MBED_ASSERT((int) obj->pwm != NC);
AnnaBridge 172:7d866c31b3c5 66
AnnaBridge 172:7d866c31b3c5 67 const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
AnnaBridge 172:7d866c31b3c5 68 MBED_ASSERT(modinit != NULL);
AnnaBridge 172:7d866c31b3c5 69 MBED_ASSERT(modinit->modname == (int) obj->pwm);
AnnaBridge 172:7d866c31b3c5 70
AnnaBridge 172:7d866c31b3c5 71 // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module.
AnnaBridge 172:7d866c31b3c5 72 if (! ((struct nu_pwm_var *) modinit->var)->en_msk) {
AnnaBridge 172:7d866c31b3c5 73 // Reset this module if no channel enabled
AnnaBridge 172:7d866c31b3c5 74 SYS_ResetModule(modinit->rsetidx);
AnnaBridge 172:7d866c31b3c5 75 }
AnnaBridge 172:7d866c31b3c5 76
AnnaBridge 172:7d866c31b3c5 77 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
AnnaBridge 172:7d866c31b3c5 78
AnnaBridge 172:7d866c31b3c5 79 // NOTE: Channels 0/1/2/3/4/5 share a clock source.
AnnaBridge 172:7d866c31b3c5 80 if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) {
AnnaBridge 172:7d866c31b3c5 81 // Select clock source of paired channels
AnnaBridge 172:7d866c31b3c5 82 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
AnnaBridge 172:7d866c31b3c5 83 // Enable clock of paired channels
AnnaBridge 172:7d866c31b3c5 84 CLK_EnableModuleClock(modinit->clkidx);
AnnaBridge 172:7d866c31b3c5 85 }
AnnaBridge 172:7d866c31b3c5 86
AnnaBridge 172:7d866c31b3c5 87 // Wire pinout
AnnaBridge 172:7d866c31b3c5 88 pinmap_pinout(pin, PinMap_PWM);
AnnaBridge 172:7d866c31b3c5 89
AnnaBridge 172:7d866c31b3c5 90 // Default: period = 10 ms, pulse width = 0 ms
AnnaBridge 172:7d866c31b3c5 91 obj->period_us = 1000 * 10;
AnnaBridge 172:7d866c31b3c5 92 obj->pulsewidth_us = 0;
AnnaBridge 172:7d866c31b3c5 93 pwmout_config(obj, 0);
AnnaBridge 172:7d866c31b3c5 94
AnnaBridge 172:7d866c31b3c5 95 ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
AnnaBridge 172:7d866c31b3c5 96
AnnaBridge 172:7d866c31b3c5 97 // Mark this module to be inited.
AnnaBridge 172:7d866c31b3c5 98 int i = modinit - pwm_modinit_tab;
AnnaBridge 172:7d866c31b3c5 99 pwm_modinit_mask |= 1 << i;
AnnaBridge 172:7d866c31b3c5 100 }
AnnaBridge 172:7d866c31b3c5 101
AnnaBridge 172:7d866c31b3c5 102 void pwmout_free(pwmout_t* obj)
AnnaBridge 172:7d866c31b3c5 103 {
AnnaBridge 172:7d866c31b3c5 104 EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm);
AnnaBridge 172:7d866c31b3c5 105 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
AnnaBridge 172:7d866c31b3c5 106 EPWM_ForceStop(pwm_base, 1 << chn);
AnnaBridge 172:7d866c31b3c5 107
AnnaBridge 172:7d866c31b3c5 108 const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
AnnaBridge 172:7d866c31b3c5 109 MBED_ASSERT(modinit != NULL);
AnnaBridge 172:7d866c31b3c5 110 MBED_ASSERT(modinit->modname == (int) obj->pwm);
AnnaBridge 172:7d866c31b3c5 111 ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn);
AnnaBridge 172:7d866c31b3c5 112
AnnaBridge 172:7d866c31b3c5 113
AnnaBridge 172:7d866c31b3c5 114 if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) {
AnnaBridge 172:7d866c31b3c5 115 CLK_DisableModuleClock(modinit->clkidx);
AnnaBridge 172:7d866c31b3c5 116 }
AnnaBridge 172:7d866c31b3c5 117
AnnaBridge 172:7d866c31b3c5 118 // Mark this module to be deinited.
AnnaBridge 172:7d866c31b3c5 119 int i = modinit - pwm_modinit_tab;
AnnaBridge 172:7d866c31b3c5 120 pwm_modinit_mask &= ~(1 << i);
AnnaBridge 172:7d866c31b3c5 121 }
AnnaBridge 172:7d866c31b3c5 122
AnnaBridge 172:7d866c31b3c5 123 void pwmout_write(pwmout_t* obj, float value)
AnnaBridge 172:7d866c31b3c5 124 {
AnnaBridge 172:7d866c31b3c5 125 obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us);
AnnaBridge 172:7d866c31b3c5 126 pwmout_config(obj, 1);
AnnaBridge 172:7d866c31b3c5 127 }
AnnaBridge 172:7d866c31b3c5 128
AnnaBridge 172:7d866c31b3c5 129 float pwmout_read(pwmout_t* obj)
AnnaBridge 172:7d866c31b3c5 130 {
AnnaBridge 172:7d866c31b3c5 131 return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f);
AnnaBridge 172:7d866c31b3c5 132 }
AnnaBridge 172:7d866c31b3c5 133
AnnaBridge 172:7d866c31b3c5 134 void pwmout_period(pwmout_t* obj, float seconds)
AnnaBridge 172:7d866c31b3c5 135 {
AnnaBridge 172:7d866c31b3c5 136 pwmout_period_us(obj, seconds * 1000000.0f);
AnnaBridge 172:7d866c31b3c5 137 }
AnnaBridge 172:7d866c31b3c5 138
AnnaBridge 172:7d866c31b3c5 139 void pwmout_period_ms(pwmout_t* obj, int ms)
AnnaBridge 172:7d866c31b3c5 140 {
AnnaBridge 172:7d866c31b3c5 141 pwmout_period_us(obj, ms * 1000);
AnnaBridge 172:7d866c31b3c5 142 }
AnnaBridge 172:7d866c31b3c5 143
AnnaBridge 172:7d866c31b3c5 144 // Set the PWM period, keeping the duty cycle the same.
AnnaBridge 172:7d866c31b3c5 145 void pwmout_period_us(pwmout_t* obj, int us)
AnnaBridge 172:7d866c31b3c5 146 {
AnnaBridge 172:7d866c31b3c5 147 uint32_t period_us_old = obj->period_us;
AnnaBridge 172:7d866c31b3c5 148 uint32_t pulsewidth_us_old = obj->pulsewidth_us;
AnnaBridge 172:7d866c31b3c5 149 obj->period_us = us;
AnnaBridge 172:7d866c31b3c5 150 obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us);
AnnaBridge 172:7d866c31b3c5 151 pwmout_config(obj, 1);
AnnaBridge 172:7d866c31b3c5 152 }
AnnaBridge 172:7d866c31b3c5 153
AnnaBridge 172:7d866c31b3c5 154 void pwmout_pulsewidth(pwmout_t* obj, float seconds)
AnnaBridge 172:7d866c31b3c5 155 {
AnnaBridge 172:7d866c31b3c5 156 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
AnnaBridge 172:7d866c31b3c5 157 }
AnnaBridge 172:7d866c31b3c5 158
AnnaBridge 172:7d866c31b3c5 159 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
AnnaBridge 172:7d866c31b3c5 160 {
AnnaBridge 172:7d866c31b3c5 161 pwmout_pulsewidth_us(obj, ms * 1000);
AnnaBridge 172:7d866c31b3c5 162 }
AnnaBridge 172:7d866c31b3c5 163
AnnaBridge 172:7d866c31b3c5 164 void pwmout_pulsewidth_us(pwmout_t* obj, int us)
AnnaBridge 172:7d866c31b3c5 165 {
AnnaBridge 172:7d866c31b3c5 166 obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us);
AnnaBridge 172:7d866c31b3c5 167 pwmout_config(obj, 1);
AnnaBridge 172:7d866c31b3c5 168 }
AnnaBridge 172:7d866c31b3c5 169
AnnaBridge 172:7d866c31b3c5 170 static void pwmout_config(pwmout_t* obj, int start)
AnnaBridge 172:7d866c31b3c5 171 {
AnnaBridge 172:7d866c31b3c5 172 EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm);
AnnaBridge 172:7d866c31b3c5 173 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
AnnaBridge 172:7d866c31b3c5 174
AnnaBridge 172:7d866c31b3c5 175 // To avoid abnormal pulse on (re-)configuration, follow the sequence: stop/configure(/re-start).
AnnaBridge 172:7d866c31b3c5 176 // NOTE: The issue is met in ARM mbed CI test tests-api-pwm on M487.
AnnaBridge 172:7d866c31b3c5 177 EPWM_ForceStop(pwm_base, 1 << chn);
AnnaBridge 172:7d866c31b3c5 178
AnnaBridge 172:7d866c31b3c5 179 // NOTE: Support period < 1s
AnnaBridge 172:7d866c31b3c5 180 // NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
AnnaBridge 172:7d866c31b3c5 181 // 1. Inverse duty cycle (100 - duty)
AnnaBridge 172:7d866c31b3c5 182 // 2. Inverse PWM output polarity
AnnaBridge 172:7d866c31b3c5 183 // This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
AnnaBridge 172:7d866c31b3c5 184 EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
AnnaBridge 172:7d866c31b3c5 185 pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn);
AnnaBridge 172:7d866c31b3c5 186
AnnaBridge 172:7d866c31b3c5 187 if (start) {
AnnaBridge 172:7d866c31b3c5 188 // Enable output of the specified PWM channel
AnnaBridge 172:7d866c31b3c5 189 EPWM_EnableOutput(pwm_base, 1 << chn);
AnnaBridge 172:7d866c31b3c5 190 EPWM_Start(pwm_base, 1 << chn);
AnnaBridge 172:7d866c31b3c5 191 }
AnnaBridge 172:7d866c31b3c5 192 }
AnnaBridge 172:7d866c31b3c5 193
AnnaBridge 172:7d866c31b3c5 194 #endif