Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.h@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
157:ff67d9f36b67 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief I2CM (Inter-Integrated Circuit Master) function prototypes and
<> 157:ff67d9f36b67 4 * data types.
<> 157:ff67d9f36b67 5 */
<> 157:ff67d9f36b67 6
<> 157:ff67d9f36b67 7 /* ****************************************************************************
<> 157:ff67d9f36b67 8 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 9 *
<> 157:ff67d9f36b67 10 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 11 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 12 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 14 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 15 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 16 *
<> 157:ff67d9f36b67 17 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 18 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 19 *
<> 157:ff67d9f36b67 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 23 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 24 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 26 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 27 *
<> 157:ff67d9f36b67 28 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 30 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 31 *
<> 157:ff67d9f36b67 32 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 33 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 34 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 35 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 36 * ownership rights.
<> 157:ff67d9f36b67 37 *
<> 157:ff67d9f36b67 38 * $Date: 2016-10-10 18:58:15 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 39 * $Revision: 24660 $
<> 157:ff67d9f36b67 40 *
<> 157:ff67d9f36b67 41 *************************************************************************** */
<> 157:ff67d9f36b67 42
<> 157:ff67d9f36b67 43 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 44 #ifndef _I2CM_H_
<> 157:ff67d9f36b67 45 #define _I2CM_H_
<> 157:ff67d9f36b67 46
<> 157:ff67d9f36b67 47 /***** Includes *****/
<> 157:ff67d9f36b67 48 #include "mxc_config.h"
<> 157:ff67d9f36b67 49 #include "mxc_sys.h"
<> 157:ff67d9f36b67 50 #include "i2cm_regs.h"
<> 157:ff67d9f36b67 51
<> 157:ff67d9f36b67 52 #ifdef __cplusplus
<> 157:ff67d9f36b67 53 extern "C" {
<> 157:ff67d9f36b67 54 #endif
<> 157:ff67d9f36b67 55 /**
<> 157:ff67d9f36b67 56 * @ingroup commperipherals
<> 157:ff67d9f36b67 57 * @defgroup i2c_master_slave I2C
<> 157:ff67d9f36b67 58 * @brief I2C Master and Slave Communications
<> 157:ff67d9f36b67 59 */
<> 157:ff67d9f36b67 60 /**
<> 157:ff67d9f36b67 61 * @ingroup i2c_master_slave
<> 157:ff67d9f36b67 62 * @defgroup i2cm I2C Master
<> 157:ff67d9f36b67 63 * @brief I2C Master
<> 157:ff67d9f36b67 64 * @{
<> 157:ff67d9f36b67 65 */
<> 157:ff67d9f36b67 66
<> 157:ff67d9f36b67 67 /* **** Definitions **** */
<> 157:ff67d9f36b67 68
<> 157:ff67d9f36b67 69 /**
<> 157:ff67d9f36b67 70 * Enumeration type to select supported I2CM frequencies.
<> 157:ff67d9f36b67 71 */
<> 157:ff67d9f36b67 72 typedef enum {
<> 157:ff67d9f36b67 73 I2CM_SPEED_100KHZ = 0, /**< Use to select a bus communication speed of 100 kHz. */
<> 157:ff67d9f36b67 74 I2CM_SPEED_400KHZ = 1 /**< Use to select a bus communication speed of 400 kHz. */
<> 157:ff67d9f36b67 75 } i2cm_speed_t;
<> 157:ff67d9f36b67 76
<> 157:ff67d9f36b67 77 /**
<> 157:ff67d9f36b67 78 * Structure type for an I2CM Transaction request.
<> 157:ff67d9f36b67 79 */
<> 157:ff67d9f36b67 80 typedef struct i2cm_req i2cm_req_t;
<> 157:ff67d9f36b67 81
<> 157:ff67d9f36b67 82 /**
<> 157:ff67d9f36b67 83 * Function type for the I2C Master callback. The function declaration for the
<> 157:ff67d9f36b67 84 * I2CM callback is:
<> 157:ff67d9f36b67 85 * @code
<> 157:ff67d9f36b67 86 * void callback(i2cm_req_t * req, int error_code);
<> 157:ff67d9f36b67 87 * @endcode | | | | -----: |
<> 157:ff67d9f36b67 88 * :----------------------------------------- | | @p req | Pointer to an
<> 157:ff67d9f36b67 89 * #i2cm_req object representing the I2CM active transaction. | | @p error_code
<> 157:ff67d9f36b67 90 * | An error code if the active transaction had a failure or #E_NO_ERROR if
<> 157:ff67d9f36b67 91 * successful. |
<> 157:ff67d9f36b67 92 *
<> 157:ff67d9f36b67 93 * @addtogroup i2cm_async
<> 157:ff67d9f36b67 94 * @{
<> 157:ff67d9f36b67 95 */
<> 157:ff67d9f36b67 96 typedef void (*i2cm_callback_fn)(i2cm_req_t * req, int error_code);
<> 157:ff67d9f36b67 97 /**@}*/
<> 157:ff67d9f36b67 98
<> 157:ff67d9f36b67 99
<> 157:ff67d9f36b67 100 /**
<> 157:ff67d9f36b67 101 * I2CM Transaction request structure.
<> 157:ff67d9f36b67 102 * @note Only supports 7-bit addressing. Driver will shift the address and
<> 157:ff67d9f36b67 103 * add the read bit when necessary.
<> 157:ff67d9f36b67 104 */
<> 157:ff67d9f36b67 105 struct i2cm_req {
<> 157:ff67d9f36b67 106 uint8_t addr; /**< 7-Bit unshifted address of the slave for communication. */
<> 157:ff67d9f36b67 107 const uint8_t *cmd_data; /**< Pointer to a command data buffer to send to the slave before either a read or write transaction. */
<> 157:ff67d9f36b67 108 uint32_t cmd_len; /**< Number of bytes in command. */
<> 157:ff67d9f36b67 109 uint8_t *data; /**< Data to write or read. */
<> 157:ff67d9f36b67 110 uint32_t data_len; /**< Length of data. */
<> 157:ff67d9f36b67 111 uint32_t cmd_num; /**< Number of command bytes sent. */
<> 157:ff67d9f36b67 112 uint32_t data_num; /**< Number of data bytes sent. */
<> 157:ff67d9f36b67 113 i2cm_callback_fn callback; /**< Function pointer to a callback function. */
<> 157:ff67d9f36b67 114 };
<> 157:ff67d9f36b67 115
<> 157:ff67d9f36b67 116 /* **** Globals **** */
<> 157:ff67d9f36b67 117
<> 157:ff67d9f36b67 118 /* **** Function Prototypes **** */
<> 157:ff67d9f36b67 119
<> 157:ff67d9f36b67 120 /**
<> 157:ff67d9f36b67 121 * @brief Initialize the I2CM peripheral module.
<> 157:ff67d9f36b67 122 *
<> 157:ff67d9f36b67 123 * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 124 * @param sys_cfg Pointer to an I2CM configuration structure of type
<> 157:ff67d9f36b67 125 * #sys_cfg_i2cm_t.
<> 157:ff67d9f36b67 126 * @param speed I2CM bus speed, see #i2cm_speed_t.
<> 157:ff67d9f36b67 127 *
<> 157:ff67d9f36b67 128 * @return #E_NO_ERROR if initialized successfully, error if unsuccessful.
<> 157:ff67d9f36b67 129 */
<> 157:ff67d9f36b67 130 int I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *sys_cfg, i2cm_speed_t speed);
<> 157:ff67d9f36b67 131
<> 157:ff67d9f36b67 132 /**
<> 157:ff67d9f36b67 133 * @brief Shutdown I2CM module.
<> 157:ff67d9f36b67 134 *
<> 157:ff67d9f36b67 135 * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 136 *
<> 157:ff67d9f36b67 137 * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
<> 157:ff67d9f36b67 138 *
<> 157:ff67d9f36b67 139 */
<> 157:ff67d9f36b67 140 int I2CM_Shutdown(mxc_i2cm_regs_t *i2cm);
<> 157:ff67d9f36b67 141
<> 157:ff67d9f36b67 142 /**
<> 157:ff67d9f36b67 143 * @defgroup i2cm_blocking I2CM Blocking Functions
<> 157:ff67d9f36b67 144 * @{
<> 157:ff67d9f36b67 145 */
<> 157:ff67d9f36b67 146
<> 157:ff67d9f36b67 147 /**
<> 157:ff67d9f36b67 148 * @brief Read I2CM data. Will block until transaction is complete.
<> 157:ff67d9f36b67 149 *
<> 157:ff67d9f36b67 150 * @note Command is an optional feature where the master will write the @c
<> 157:ff67d9f36b67 151 * cmd_data before reading from the slave. If command is undesired,
<> 157:ff67d9f36b67 152 * set the @c *cmd_data parameter to NULL and pass 0 for the @c
<> 157:ff67d9f36b67 153 * cmd_len parameter.
<> 157:ff67d9f36b67 154 * @note If there is a command, the master will send a repeated start
<> 157:ff67d9f36b67 155 * sequence before attempting to read from the slave.
<> 157:ff67d9f36b67 156 * @note This function blocks until the transaction has completed.
<> 157:ff67d9f36b67 157 *
<> 157:ff67d9f36b67 158 * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 159 * @param addr I2C address of the slave.
<> 157:ff67d9f36b67 160 * @param cmd_data Data to write before reading.
<> 157:ff67d9f36b67 161 * @param cmd_len Number of bytes to write before reading.
<> 157:ff67d9f36b67 162 * @param data Where to store the data read.
<> 157:ff67d9f36b67 163 * @param len Number of bytes to read.
<> 157:ff67d9f36b67 164 *
<> 157:ff67d9f36b67 165 * @return Number of bytes read if successful, error code if unsuccessful.
<> 157:ff67d9f36b67 166 */
<> 157:ff67d9f36b67 167 int I2CM_Read(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
<> 157:ff67d9f36b67 168 uint32_t cmd_len, uint8_t* data, uint32_t len);
<> 157:ff67d9f36b67 169
<> 157:ff67d9f36b67 170 /**
<> 157:ff67d9f36b67 171 * @brief Write data to a slave device.
<> 157:ff67d9f36b67 172 *
<> 157:ff67d9f36b67 173 * @note Command is an optional feature where the master will write the @c
<> 157:ff67d9f36b67 174 * cmd_data before writing the @c data to the slave. If command is
<> 157:ff67d9f36b67 175 * not needed, set the @c cmd_data to @c NULL and set @c cmd_len to
<> 157:ff67d9f36b67 176 * 0. If there is a command, the master will send a repeated start
<> 157:ff67d9f36b67 177 * sequence before attempting to read from the slave.
<> 157:ff67d9f36b67 178 * @note This function blocks until the transaction has completed.
<> 157:ff67d9f36b67 179 *
<> 157:ff67d9f36b67 180 * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 181 * @param addr I2C address of the slave.
<> 157:ff67d9f36b67 182 * @param cmd_data Data to write before writing data.
<> 157:ff67d9f36b67 183 * @param cmd_len Number of bytes to write before writing data.
<> 157:ff67d9f36b67 184 * @param data Data to be written.
<> 157:ff67d9f36b67 185 * @param len Number of bytes to Write.
<> 157:ff67d9f36b67 186 *
<> 157:ff67d9f36b67 187 * @return Number of bytes writen if successful or an @ref MXC_Error_Codes
<> 157:ff67d9f36b67 188 * "Error Code" if unsuccessful.
<> 157:ff67d9f36b67 189 */
<> 157:ff67d9f36b67 190 int I2CM_Write(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
<> 157:ff67d9f36b67 191 uint32_t cmd_len, uint8_t* data, uint32_t len);
<> 157:ff67d9f36b67 192 /**@} end of i2cm_blocking functions */
<> 157:ff67d9f36b67 193
<> 157:ff67d9f36b67 194 /**
<> 157:ff67d9f36b67 195 * @defgroup i2cm_async I2CM Asynchrous Functions
<> 157:ff67d9f36b67 196 * @{
<> 157:ff67d9f36b67 197 */
<> 157:ff67d9f36b67 198
<> 157:ff67d9f36b67 199 /**
<> 157:ff67d9f36b67 200 * @brief Asynchronously read I2CM data.
<> 157:ff67d9f36b67 201 *
<> 157:ff67d9f36b67 202 * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 203 * @param req Pointer to an I2CM transaction request structure, see
<> 157:ff67d9f36b67 204 * #i2cm_req.
<> 157:ff67d9f36b67 205 *
<> 157:ff67d9f36b67 206 * @return #E_NO_ERROR if everything is successful or an @ref
<> 157:ff67d9f36b67 207 * MXC_Error_Codes "Error Code" if unsuccessful.
<> 157:ff67d9f36b67 208 */
<> 157:ff67d9f36b67 209 int I2CM_ReadAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req);
<> 157:ff67d9f36b67 210
<> 157:ff67d9f36b67 211 /**
<> 157:ff67d9f36b67 212 * @brief Asynchronously write I2CM data.
<> 157:ff67d9f36b67 213 *
<> 157:ff67d9f36b67 214 * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 215 * @param req Pointer to an I2CM transaction request structure, see
<> 157:ff67d9f36b67 216 * #i2cm_req.
<> 157:ff67d9f36b67 217 *
<> 157:ff67d9f36b67 218 * @return #E_NO_ERROR if everything is successful, error if unsuccessful.
<> 157:ff67d9f36b67 219 */
<> 157:ff67d9f36b67 220 int I2CM_WriteAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req);
<> 157:ff67d9f36b67 221
<> 157:ff67d9f36b67 222 /**
<> 157:ff67d9f36b67 223 * @brief Abort asynchronous request.
<> 157:ff67d9f36b67 224 * @param req Pointer to request for an I2CM transaction.
<> 157:ff67d9f36b67 225 * @note Will call the callback for the request.
<> 157:ff67d9f36b67 226 *
<> 157:ff67d9f36b67 227 * @return #E_NO_ERROR if request aborted, error if unsuccessful.
<> 157:ff67d9f36b67 228 */
<> 157:ff67d9f36b67 229 int I2CM_AbortAsync(i2cm_req_t *req);
<> 157:ff67d9f36b67 230
<> 157:ff67d9f36b67 231 /**
<> 157:ff67d9f36b67 232 * @brief I2CM interrupt handler.
<> 157:ff67d9f36b67 233 *
<> 157:ff67d9f36b67 234 * @details This function is an IRQ handler and will be called by the core if
<> 157:ff67d9f36b67 235 * I2CM interrupts are enabled. Alternately, if the application is
<> 157:ff67d9f36b67 236 * using asynchronous methods, this function can be periodically
<> 157:ff67d9f36b67 237 * called by the application if the I2CM interrupts are disabled.
<> 157:ff67d9f36b67 238 *
<> 157:ff67d9f36b67 239 * @param i2cm Base address of the I2CM module.
<> 157:ff67d9f36b67 240 */
<> 157:ff67d9f36b67 241 void I2CM_Handler(mxc_i2cm_regs_t *i2cm);
<> 157:ff67d9f36b67 242 /**@} end of i2cm_async */
<> 157:ff67d9f36b67 243
<> 157:ff67d9f36b67 244 /**
<> 157:ff67d9f36b67 245 * @brief Returns the status of the I2CM peripheral module.
<> 157:ff67d9f36b67 246 *
<> 157:ff67d9f36b67 247 * @param i2cm Pointer to the I2CM register structure, see
<> 157:ff67d9f36b67 248 * #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 249 *
<> 157:ff67d9f36b67 250 * @return #E_NO_ERROR if idle.
<> 157:ff67d9f36b67 251 * @return #E_BUSY if in use.
<> 157:ff67d9f36b67 252 */
<> 157:ff67d9f36b67 253 int I2CM_Busy(mxc_i2cm_regs_t *i2cm);
<> 157:ff67d9f36b67 254
<> 157:ff67d9f36b67 255 /**
<> 157:ff67d9f36b67 256 * @brief Attempt to prepare the I2CM for sleep.
<> 157:ff67d9f36b67 257 * @details Checks for any ongoing transactions. Disables interrupts if the
<> 157:ff67d9f36b67 258 * I2CM is idle.
<> 157:ff67d9f36b67 259 *
<> 157:ff67d9f36b67 260 * @param i2cm Pointer to the I2CM register structure, see
<> 157:ff67d9f36b67 261 * #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 262 *
<> 157:ff67d9f36b67 263 * @return #E_NO_ERROR if ready to sleep.
<> 157:ff67d9f36b67 264 * @return #E_BUSY if the bus is not ready for sleep.
<> 157:ff67d9f36b67 265 */
<> 157:ff67d9f36b67 266 int I2CM_PrepForSleep(mxc_i2cm_regs_t *i2cm);
<> 157:ff67d9f36b67 267
<> 157:ff67d9f36b67 268 /**
<> 157:ff67d9f36b67 269 * @brief Check the I2C bus to determine if any other masters are using the
<> 157:ff67d9f36b67 270 * bus.
<> 157:ff67d9f36b67 271 *
<> 157:ff67d9f36b67 272 * @param i2cm Pointer to the I2CM register structure, see
<> 157:ff67d9f36b67 273 * #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 274 *
<> 157:ff67d9f36b67 275 * @return #E_NO_ERROR if SCL and SDA are high,
<> 157:ff67d9f36b67 276 * @return #E_BUSY otherwise.
<> 157:ff67d9f36b67 277 */
<> 157:ff67d9f36b67 278 int I2CM_BusCheck(mxc_i2cm_regs_t *i2cm);
<> 157:ff67d9f36b67 279
<> 157:ff67d9f36b67 280 /**
<> 157:ff67d9f36b67 281 * @brief Drain/Empty all of the data in the I2CM Receive FIFO.
<> 157:ff67d9f36b67 282 *
<> 157:ff67d9f36b67 283 * @param i2cm Pointer to the I2CM register structure, see
<> 157:ff67d9f36b67 284 * #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 285 */
<> 157:ff67d9f36b67 286 __STATIC_INLINE void I2CM_DrainRX(mxc_i2cm_regs_t *i2cm)
<> 157:ff67d9f36b67 287 {
<> 157:ff67d9f36b67 288 i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_RX_FIFO_EN);
<> 157:ff67d9f36b67 289 i2cm->ctrl |= MXC_F_I2CM_CTRL_RX_FIFO_EN;
<> 157:ff67d9f36b67 290 }
<> 157:ff67d9f36b67 291
<> 157:ff67d9f36b67 292 /**
<> 157:ff67d9f36b67 293 * @brief Drain/Empty any data in the I2CM Transmit FIFO.
<> 157:ff67d9f36b67 294 *
<> 157:ff67d9f36b67 295 * @param i2cm Pointer to the I2CM register structure, see
<> 157:ff67d9f36b67 296 * #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 297 */
<> 157:ff67d9f36b67 298 __STATIC_INLINE void I2CM_DrainTX(mxc_i2cm_regs_t *i2cm)
<> 157:ff67d9f36b67 299 {
<> 157:ff67d9f36b67 300 i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_TX_FIFO_EN);
<> 157:ff67d9f36b67 301 i2cm->ctrl |= MXC_F_I2CM_CTRL_TX_FIFO_EN;
<> 157:ff67d9f36b67 302 }
<> 157:ff67d9f36b67 303
<> 157:ff67d9f36b67 304 /**
<> 157:ff67d9f36b67 305 * @brief Clear interrupt flags.
<> 157:ff67d9f36b67 306 *
<> 157:ff67d9f36b67 307 * @param i2cm Pointer to the I2CM register structure, see
<> 157:ff67d9f36b67 308 * #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 309 * @param mask Mask of I2CM interrupts to clear (1 to clear),
<> 157:ff67d9f36b67 310 * @see I2CM_INTFL_Register for the interrupt flag masks.
<> 157:ff67d9f36b67 311 */
<> 157:ff67d9f36b67 312 __STATIC_INLINE void I2CM_ClearFlags(mxc_i2cm_regs_t *i2cm, uint32_t mask)
<> 157:ff67d9f36b67 313 {
<> 157:ff67d9f36b67 314 i2cm->intfl = mask;
<> 157:ff67d9f36b67 315 }
<> 157:ff67d9f36b67 316
<> 157:ff67d9f36b67 317 /**
<> 157:ff67d9f36b67 318 * @brief Gets the current I2CM interrupt flags.
<> 157:ff67d9f36b67 319 * @param i2cm Pointer to the I2CM register structure, see
<> 157:ff67d9f36b67 320 * #mxc_i2cm_regs_t.
<> 157:ff67d9f36b67 321 *
<> 157:ff67d9f36b67 322 * @return The currently set interrupt flags, @see I2CM_INTFL_Register
<> 157:ff67d9f36b67 323 * for the interrupt flag masks.
<> 157:ff67d9f36b67 324 */
<> 157:ff67d9f36b67 325 __STATIC_INLINE unsigned I2CM_GetFlags(mxc_i2cm_regs_t *i2cm)
<> 157:ff67d9f36b67 326 {
<> 157:ff67d9f36b67 327 return(i2cm->intfl);
<> 157:ff67d9f36b67 328 }
<> 157:ff67d9f36b67 329 /**@} end of group i2cm */
<> 157:ff67d9f36b67 330
<> 157:ff67d9f36b67 331 void I2CM_Recover(mxc_i2cm_regs_t *i2cm);
<> 157:ff67d9f36b67 332 int I2CM_WriteTxFifo(mxc_i2cm_regs_t *regs, mxc_i2cm_fifo_regs_t *fifo, const uint16_t data);
<> 157:ff67d9f36b67 333 int I2CM_TxInProgress(mxc_i2cm_regs_t *i2cm);
<> 157:ff67d9f36b67 334 int I2CM_Tx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, const uint8_t *data, uint32_t len, uint8_t stop);
<> 157:ff67d9f36b67 335
<> 157:ff67d9f36b67 336 #ifdef __cplusplus
<> 157:ff67d9f36b67 337 }
<> 157:ff67d9f36b67 338 #endif
<> 157:ff67d9f36b67 339
<> 157:ff67d9f36b67 340 #endif /* _I2CM_H_ */