Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
174:b96e65c34a4d 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*******************************************************************************
<> 149:156823d33999 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 149:156823d33999 5 * copy of this software and associated documentation files (the "Software"),
<> 149:156823d33999 6 * to deal in the Software without restriction, including without limitation
<> 149:156823d33999 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 149:156823d33999 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 149:156823d33999 9 * Software is furnished to do so, subject to the following conditions:
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * The above copyright notice and this permission notice shall be included
<> 149:156823d33999 12 * in all copies or substantial portions of the Software.
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 149:156823d33999 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 149:156823d33999 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 149:156823d33999 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 149:156823d33999 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 149:156823d33999 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 149:156823d33999 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * Except as contained in this notice, the name of Maxim Integrated
<> 149:156823d33999 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 149:156823d33999 24 * Products, Inc. Branding Policy.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * The mere transfer of this software does not imply any licenses
<> 149:156823d33999 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 149:156823d33999 28 * trademarks, maskwork rights, or any other form of intellectual
<> 149:156823d33999 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 149:156823d33999 30 * ownership rights.
<> 149:156823d33999 31 *******************************************************************************
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 #include "rtc_api.h"
<> 149:156823d33999 35 #include "lp_ticker_api.h"
<> 149:156823d33999 36 #include "cmsis.h"
<> 149:156823d33999 37 #include "rtc_regs.h"
<> 149:156823d33999 38 #include "pwrseq_regs.h"
<> 149:156823d33999 39 #include "clkman_regs.h"
<> 149:156823d33999 40
<> 149:156823d33999 41 /**
<> 149:156823d33999 42 * Defines clock divider for 4096Hz input clock.
<> 149:156823d33999 43 */
<> 149:156823d33999 44 typedef enum {
<> 149:156823d33999 45 /** (4kHz) divide input clock by 2^0 = 1 */
<> 149:156823d33999 46 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
<> 149:156823d33999 47 /** (2kHz) divide input clock by 2^1 = 2 */
<> 149:156823d33999 48 MXC_E_RTC_PRESCALE_DIV_2_1,
<> 149:156823d33999 49 /** (1kHz) divide input clock by 2^2 = 4 */
<> 149:156823d33999 50 MXC_E_RTC_PRESCALE_DIV_2_2,
<> 149:156823d33999 51 /** (512Hz) divide input clock by 2^3 = 8 */
<> 149:156823d33999 52 MXC_E_RTC_PRESCALE_DIV_2_3,
<> 149:156823d33999 53 /** (256Hz) divide input clock by 2^4 = 16 */
<> 149:156823d33999 54 MXC_E_RTC_PRESCALE_DIV_2_4,
<> 149:156823d33999 55 /** (128Hz) divide input clock by 2^5 = 32 */
<> 149:156823d33999 56 MXC_E_RTC_PRESCALE_DIV_2_5,
<> 149:156823d33999 57 /** (64Hz) divide input clock by 2^6 = 64 */
<> 149:156823d33999 58 MXC_E_RTC_PRESCALE_DIV_2_6,
<> 149:156823d33999 59 /** (32Hz) divide input clock by 2^7 = 128 */
<> 149:156823d33999 60 MXC_E_RTC_PRESCALE_DIV_2_7,
<> 149:156823d33999 61 /** (16Hz) divide input clock by 2^8 = 256 */
<> 149:156823d33999 62 MXC_E_RTC_PRESCALE_DIV_2_8,
<> 149:156823d33999 63 /** (8Hz) divide input clock by 2^9 = 512 */
<> 149:156823d33999 64 MXC_E_RTC_PRESCALE_DIV_2_9,
<> 149:156823d33999 65 /** (4Hz) divide input clock by 2^10 = 1024 */
<> 149:156823d33999 66 MXC_E_RTC_PRESCALE_DIV_2_10,
<> 149:156823d33999 67 /** (2Hz) divide input clock by 2^11 = 2048 */
<> 149:156823d33999 68 MXC_E_RTC_PRESCALE_DIV_2_11,
<> 149:156823d33999 69 /** (1Hz) divide input clock by 2^12 = 4096 */
<> 149:156823d33999 70 MXC_E_RTC_PRESCALE_DIV_2_12,
<> 149:156823d33999 71 } mxc_rtc_prescale_t;
<> 149:156823d33999 72
<> 149:156823d33999 73 #define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
<> 149:156823d33999 74 #define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
<> 149:156823d33999 75
<> 149:156823d33999 76 #define WINDOW 1000
<> 149:156823d33999 77
<> 149:156823d33999 78 static int rtc_inited = 0;
<> 149:156823d33999 79 static volatile uint32_t overflow_cnt = 0;
<> 149:156823d33999 80
<> 149:156823d33999 81 static uint64_t rtc_read64(void);
<> 149:156823d33999 82
<> 149:156823d33999 83 //******************************************************************************
<> 149:156823d33999 84 static void overflow_handler(void)
<> 149:156823d33999 85 {
<> 149:156823d33999 86 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
<> 149:156823d33999 87 overflow_cnt++;
<> 149:156823d33999 88
<> 149:156823d33999 89 // Wait for pending transactions
<> 149:156823d33999 90 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 149:156823d33999 91 }
<> 149:156823d33999 92
<> 149:156823d33999 93 //******************************************************************************
<> 149:156823d33999 94 void rtc_init(void)
<> 149:156823d33999 95 {
<> 149:156823d33999 96 if (rtc_inited) {
<> 149:156823d33999 97 return;
<> 149:156823d33999 98 }
<> 149:156823d33999 99 rtc_inited = 1;
<> 149:156823d33999 100
<> 149:156823d33999 101 overflow_cnt = 0;
<> 149:156823d33999 102
<> 149:156823d33999 103 // Enable the clock to the synchronizer
<> 149:156823d33999 104 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
<> 149:156823d33999 105
<> 149:156823d33999 106 // Enable the clock to the RTC
<> 149:156823d33999 107 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 149:156823d33999 108
<> 149:156823d33999 109 // Prepare interrupt handlers
<> 149:156823d33999 110 NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
<> 149:156823d33999 111 NVIC_EnableIRQ(RTC0_IRQn);
<> 149:156823d33999 112 NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
<> 149:156823d33999 113 NVIC_EnableIRQ(RTC3_IRQn);
<> 149:156823d33999 114
<> 149:156823d33999 115 // Enable wakeup on RTC rollover
<> 149:156823d33999 116 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
<> 149:156823d33999 117
<> 149:156823d33999 118 /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
<> 149:156823d33999 119 * if it is already running.
<> 149:156823d33999 120 */
<> 149:156823d33999 121 if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) {
<> 149:156823d33999 122 // Set the clock divider
<> 149:156823d33999 123 MXC_RTCTMR->prescale = PRESCALE_VAL;
<> 149:156823d33999 124
<> 149:156823d33999 125 // Enable the overflow interrupt
<> 149:156823d33999 126 MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
<> 149:156823d33999 127
<> 149:156823d33999 128 // Restart the timer from 0
<> 149:156823d33999 129 MXC_RTCTMR->timer = 0;
<> 149:156823d33999 130
<> 149:156823d33999 131 // Enable the RTC
<> 149:156823d33999 132 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
<> 149:156823d33999 133 }
<> 149:156823d33999 134 }
<> 149:156823d33999 135
<> 149:156823d33999 136 //******************************************************************************
<> 149:156823d33999 137 void lp_ticker_init(void)
<> 149:156823d33999 138 {
<> 149:156823d33999 139 rtc_init();
<> 149:156823d33999 140 }
<> 149:156823d33999 141
<> 149:156823d33999 142 //******************************************************************************
<> 149:156823d33999 143 void rtc_free(void)
<> 149:156823d33999 144 {
<> 149:156823d33999 145 if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
<> 149:156823d33999 146 // Clear and disable RTC
<> 149:156823d33999 147 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
<> 149:156823d33999 148 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
<> 149:156823d33999 149
<> 149:156823d33999 150 // Wait for pending transactions
<> 149:156823d33999 151 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 149:156823d33999 152 }
<> 149:156823d33999 153
<> 149:156823d33999 154 // Disable the clock to the RTC
<> 149:156823d33999 155 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
<> 149:156823d33999 156
<> 149:156823d33999 157 // Disable the clock to the synchronizer
<> 149:156823d33999 158 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DISABLED;
<> 149:156823d33999 159 }
<> 149:156823d33999 160
<> 149:156823d33999 161 //******************************************************************************
<> 149:156823d33999 162 int rtc_isenabled(void)
<> 149:156823d33999 163 {
<> 149:156823d33999 164 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
<> 149:156823d33999 165 }
<> 149:156823d33999 166
<> 149:156823d33999 167 //******************************************************************************
<> 149:156823d33999 168 time_t rtc_read(void)
<> 149:156823d33999 169 {
<> 149:156823d33999 170 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
<> 149:156823d33999 171 uint32_t ovf1, ovf2;
<> 149:156823d33999 172
<> 149:156823d33999 173 // Make sure RTC is setup before trying to read
<> 149:156823d33999 174 if (!rtc_inited) {
<> 149:156823d33999 175 rtc_init();
<> 149:156823d33999 176 }
<> 149:156823d33999 177
<> 149:156823d33999 178 // Ensure coherency between overflow_cnt and timer
<> 149:156823d33999 179 do {
<> 149:156823d33999 180 ovf_cnt_1 = overflow_cnt;
<> 149:156823d33999 181 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 149:156823d33999 182 timer_cnt = MXC_RTCTMR->timer;
<> 149:156823d33999 183 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 149:156823d33999 184 ovf_cnt_2 = overflow_cnt;
<> 149:156823d33999 185 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
<> 149:156823d33999 186
<> 149:156823d33999 187 // Account for an unserviced interrupt
<> 149:156823d33999 188 if (ovf1) {
<> 149:156823d33999 189 ovf_cnt_1++;
<> 149:156823d33999 190 }
<> 149:156823d33999 191
<> 149:156823d33999 192 return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
<> 149:156823d33999 193 }
<> 149:156823d33999 194
<> 149:156823d33999 195 //******************************************************************************
<> 149:156823d33999 196 static uint64_t rtc_read64(void)
<> 149:156823d33999 197 {
<> 149:156823d33999 198 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
<> 149:156823d33999 199 uint32_t ovf1, ovf2;
<> 149:156823d33999 200 uint64_t current_us;
<> 149:156823d33999 201
<> 149:156823d33999 202 // Make sure RTC is setup before trying to read
<> 149:156823d33999 203 if (!rtc_inited) {
<> 149:156823d33999 204 rtc_init();
<> 149:156823d33999 205 }
<> 149:156823d33999 206
<> 149:156823d33999 207 // Ensure coherency between overflow_cnt and timer
<> 149:156823d33999 208 do {
<> 149:156823d33999 209 ovf_cnt_1 = overflow_cnt;
<> 149:156823d33999 210 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 149:156823d33999 211 timer_cnt = MXC_RTCTMR->timer;
<> 149:156823d33999 212 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 149:156823d33999 213 ovf_cnt_2 = overflow_cnt;
<> 149:156823d33999 214 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
<> 149:156823d33999 215
<> 149:156823d33999 216 // Account for an unserviced interrupt
<> 149:156823d33999 217 if (ovf1) {
<> 149:156823d33999 218 ovf_cnt_1++;
<> 149:156823d33999 219 }
<> 149:156823d33999 220
<> 149:156823d33999 221 current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
<> 149:156823d33999 222
<> 149:156823d33999 223 return current_us;
<> 149:156823d33999 224 }
<> 149:156823d33999 225
<> 149:156823d33999 226 //******************************************************************************
<> 149:156823d33999 227 void rtc_write(time_t t)
<> 149:156823d33999 228 {
<> 149:156823d33999 229 // Make sure RTC is setup before accessing
<> 149:156823d33999 230 if (!rtc_inited) {
<> 149:156823d33999 231 rtc_init();
<> 149:156823d33999 232 }
<> 149:156823d33999 233
<> 149:156823d33999 234 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
<> 149:156823d33999 235 MXC_RTCTMR->timer = t << SHIFT_AMT;
<> 149:156823d33999 236 overflow_cnt = t >> (32 - SHIFT_AMT);
<> 149:156823d33999 237 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating
<> 149:156823d33999 238 }
<> 149:156823d33999 239
<> 149:156823d33999 240 //******************************************************************************
<> 149:156823d33999 241 void lp_ticker_set_interrupt(timestamp_t timestamp)
<> 149:156823d33999 242 {
<> 149:156823d33999 243 uint32_t comp_value;
<> 149:156823d33999 244 uint64_t curr_ts64;
<> 149:156823d33999 245 uint64_t ts64;
<> 149:156823d33999 246
<> 149:156823d33999 247 // Note: interrupts are disabled before this function is called.
<> 149:156823d33999 248
<> 149:156823d33999 249 // Disable the alarm while it is prepared
<> 149:156823d33999 250 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
<> 149:156823d33999 251
<> 149:156823d33999 252 curr_ts64 = rtc_read64();
<> 149:156823d33999 253 ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
<> 149:156823d33999 254
<> 149:156823d33999 255 // If this event is older than a recent window, it must be in the future
<> 149:156823d33999 256 if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
<> 149:156823d33999 257 ts64 += 0x100000000ULL;
<> 149:156823d33999 258 }
<> 149:156823d33999 259
<> 149:156823d33999 260 uint32_t timer = MXC_RTCTMR->timer;
<> 149:156823d33999 261 if (ts64 <= curr_ts64) {
<> 149:156823d33999 262 // This event has already occurred. Set the alarm to expire immediately.
<> 149:156823d33999 263 comp_value = timer + 1;
<> 149:156823d33999 264 } else {
<> 149:156823d33999 265 comp_value = (ts64 << SHIFT_AMT) / 1000000;
<> 149:156823d33999 266 }
<> 149:156823d33999 267
<> 149:156823d33999 268 // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
<> 149:156823d33999 269 if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
<> 149:156823d33999 270 comp_value = timer + 2;
<> 149:156823d33999 271 }
<> 149:156823d33999 272
<> 149:156823d33999 273 MXC_RTCTMR->comp[0] = comp_value;
<> 149:156823d33999 274 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
<> 149:156823d33999 275 MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
<> 149:156823d33999 276
<> 149:156823d33999 277 // Enable wakeup from RTC
<> 149:156823d33999 278 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
<> 149:156823d33999 279
<> 149:156823d33999 280 // Wait for pending transactions
<> 149:156823d33999 281 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 149:156823d33999 282 }
<> 149:156823d33999 283
AnnaBridge 174:b96e65c34a4d 284 void lp_ticker_fire_interrupt(void)
AnnaBridge 174:b96e65c34a4d 285 {
AnnaBridge 174:b96e65c34a4d 286 NVIC_SetPendingIRQ(RTC0_IRQn);
AnnaBridge 174:b96e65c34a4d 287 }
AnnaBridge 174:b96e65c34a4d 288
<> 149:156823d33999 289 //******************************************************************************
<> 149:156823d33999 290 inline void lp_ticker_disable_interrupt(void)
<> 149:156823d33999 291 {
<> 149:156823d33999 292 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
<> 149:156823d33999 293 }
<> 149:156823d33999 294
<> 149:156823d33999 295 //******************************************************************************
<> 149:156823d33999 296 inline void lp_ticker_clear_interrupt(void)
<> 149:156823d33999 297 {
<> 149:156823d33999 298 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
<> 149:156823d33999 299
<> 149:156823d33999 300 // Wait for pending transactions
<> 149:156823d33999 301 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 149:156823d33999 302 }
<> 149:156823d33999 303
<> 149:156823d33999 304 //******************************************************************************
<> 149:156823d33999 305 inline uint32_t lp_ticker_read(void)
<> 149:156823d33999 306 {
<> 149:156823d33999 307 return rtc_read64();
<> 149:156823d33999 308 }