Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
149:156823d33999 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "device.h"
<> 144:ef7eb2e8f9f7 35 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 36 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /*
<> 144:ef7eb2e8f9f7 39 * To select a peripheral function on Maxim microcontrollers, multiple
<> 144:ef7eb2e8f9f7 40 * configurations must be made. The mbed PinMap structure only includes one
<> 144:ef7eb2e8f9f7 41 * data member to hold this information. To extend the configuration storage,
<> 144:ef7eb2e8f9f7 42 * the "function" data member is used as a pointer to a pin_function_t
<> 144:ef7eb2e8f9f7 43 * structure. This structure is defined in objects.h. The definitions below
<> 144:ef7eb2e8f9f7 44 * include the creation of the pin_function_t structures and the assignment of
<> 144:ef7eb2e8f9f7 45 * the pointers to the "function" data members.
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #ifdef TOOLCHAIN_ARM_STD
<> 144:ef7eb2e8f9f7 49 #pragma diag_suppress 1296
<> 144:ef7eb2e8f9f7 50 #endif
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /************I2C***************/
<> 144:ef7eb2e8f9f7 53 const PinMap PinMap_I2C_SDA[] = {
<> 144:ef7eb2e8f9f7 54 { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 55 { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 56 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 57 };
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 const PinMap PinMap_I2C_SCL[] = {
<> 144:ef7eb2e8f9f7 60 { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 61 { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 62 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 63 };
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /************UART***************/
<> 144:ef7eb2e8f9f7 66 const PinMap PinMap_UART_TX[] = {
<> 144:ef7eb2e8f9f7 67 { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 68 { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 69 { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 70 { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 71 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 72 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 73 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 74 };
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 const PinMap PinMap_UART_RX[] = {
<> 144:ef7eb2e8f9f7 77 { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 78 { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 79 { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 80 { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 81 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 82 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 83 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 84 };
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 const PinMap PinMap_UART_CTS[] = {
<> 144:ef7eb2e8f9f7 87 { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 88 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 89 { P2_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 90 { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 91 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
<> 144:ef7eb2e8f9f7 92 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 93 };
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 const PinMap PinMap_UART_RTS[] = {
<> 144:ef7eb2e8f9f7 96 { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 97 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 98 { P2_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 99 { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 100 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
<> 144:ef7eb2e8f9f7 101 { NC, NC, 0 }
<> 144:ef7eb2e8f9f7 102 };
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /************SPI***************/
<> 144:ef7eb2e8f9f7 105 const PinMap PinMap_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 106 { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 107 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 108 { NC, NC, 0}
<> 144:ef7eb2e8f9f7 109 };
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 const PinMap PinMap_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 112 { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 113 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 114 { NC, NC, 0}
<> 144:ef7eb2e8f9f7 115 };
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 const PinMap PinMap_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 118 { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 119 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
<> 144:ef7eb2e8f9f7 120 { NC, NC, 0}
<> 144:ef7eb2e8f9f7 121 };
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 const PinMap PinMap_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 124 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
<> 144:ef7eb2e8f9f7 125 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
<> 144:ef7eb2e8f9f7 126 { NC, NC, 0}
<> 144:ef7eb2e8f9f7 127 };
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /************PWM***************/
<> 144:ef7eb2e8f9f7 130 const PinMap PinMap_PWM[] = {
<> 144:ef7eb2e8f9f7 131 {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
<> 144:ef7eb2e8f9f7 132 {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, {P0_1, PWM_0, 3},
<> 144:ef7eb2e8f9f7 133 {P0_2, PWM_2, 1}, {P0_2, PWM_1, 2}, {P0_2, PWM_5, 3},
<> 144:ef7eb2e8f9f7 134 {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, {P0_3, PWM_1, 3},
<> 144:ef7eb2e8f9f7 135 {P0_4, PWM_4, 1}, {P0_4, PWM_2, 2}, {P0_4, PWM_6, 3},
<> 144:ef7eb2e8f9f7 136 {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, {P0_5, PWM_2, 3},
<> 144:ef7eb2e8f9f7 137 {P0_6, PWM_6, 1}, {P0_6, PWM_3, 2}, {P0_6, PWM_7, 3},
<> 144:ef7eb2e8f9f7 138 {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, {P0_7, PWM_3, 3},
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
<> 144:ef7eb2e8f9f7 141 {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, {P1_1, PWM_0, 3},
<> 144:ef7eb2e8f9f7 142 {P1_2, PWM_2, 1}, {P1_2, PWM_1, 2}, {P1_2, PWM_5, 3},
<> 144:ef7eb2e8f9f7 143 {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, {P1_3, PWM_1, 3},
<> 144:ef7eb2e8f9f7 144 {P1_4, PWM_4, 1}, {P1_4, PWM_2, 2}, {P1_4, PWM_6, 3},
<> 144:ef7eb2e8f9f7 145 {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, {P1_5, PWM_2, 3},
<> 144:ef7eb2e8f9f7 146 {P1_6, PWM_6, 1}, {P1_6, PWM_3, 2}, {P1_6, PWM_7, 3},
<> 144:ef7eb2e8f9f7 147 {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, {P1_7, PWM_3, 3},
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
<> 144:ef7eb2e8f9f7 150 {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, {P2_1, PWM_0, 3},
<> 144:ef7eb2e8f9f7 151 {P2_2, PWM_2, 1}, {P2_2, PWM_1, 2}, {P2_2, PWM_5, 3},
<> 144:ef7eb2e8f9f7 152 {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, {P2_3, PWM_1, 3},
<> 144:ef7eb2e8f9f7 153 {P2_4, PWM_4, 1}, {P2_4, PWM_2, 2}, {P2_4, PWM_6, 3},
<> 144:ef7eb2e8f9f7 154 {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, {P2_5, PWM_2, 3},
<> 144:ef7eb2e8f9f7 155 {P2_6, PWM_6, 1}, {P2_6, PWM_3, 2}, {P2_6, PWM_7, 3},
<> 144:ef7eb2e8f9f7 156 {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, {P2_7, PWM_3, 3},
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 159 };
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /************ADC***************/
<> 144:ef7eb2e8f9f7 162 const PinMap PinMap_ADC[] = {
<> 144:ef7eb2e8f9f7 163 {AIN_0P, ADC, 0},
<> 144:ef7eb2e8f9f7 164 {AIN_1P, ADC, 0},
<> 144:ef7eb2e8f9f7 165 {AIN_2P, ADC, 0},
<> 144:ef7eb2e8f9f7 166 {AIN_3P, ADC, 0},
<> 144:ef7eb2e8f9f7 167 {AIN_4P, ADC, 0},
<> 144:ef7eb2e8f9f7 168 {AIN_5P, ADC, 0},
<> 144:ef7eb2e8f9f7 169 {AIN_0N, ADC, 0},
<> 144:ef7eb2e8f9f7 170 {AIN_1N, ADC, 0},
<> 144:ef7eb2e8f9f7 171 {AIN_2N, ADC, 0},
<> 144:ef7eb2e8f9f7 172 {AIN_3N, ADC, 0},
<> 144:ef7eb2e8f9f7 173 {AIN_4N, ADC, 0},
<> 144:ef7eb2e8f9f7 174 {AIN_5N, ADC, 0},
<> 144:ef7eb2e8f9f7 175 {AIN_0D, ADC, 1},
<> 144:ef7eb2e8f9f7 176 {AIN_1D, ADC, 1},
<> 144:ef7eb2e8f9f7 177 {AIN_2D, ADC, 1},
<> 144:ef7eb2e8f9f7 178 {AIN_3D, ADC, 1},
<> 144:ef7eb2e8f9f7 179 {AIN_4D, ADC, 1},
<> 144:ef7eb2e8f9f7 180 {AIN_5D, ADC, 1},
<> 144:ef7eb2e8f9f7 181 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 182 };
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /************DAC***************/
<> 144:ef7eb2e8f9f7 185 const PinMap PinMap_DAC[] = {
<> 144:ef7eb2e8f9f7 186 {AOUT_AO, DAC0, 0},
<> 144:ef7eb2e8f9f7 187 {AOUT_BO, DAC1, 0},
<> 144:ef7eb2e8f9f7 188 {AOUT_CO, DAC2, 0},
<> 144:ef7eb2e8f9f7 189 {AOUT_DO, DAC3, 0},
<> 144:ef7eb2e8f9f7 190 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 191 };