Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_NXP/TARGET_LPC43XX/i2c_api.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 #include "i2c_api.h"
<> 144:ef7eb2e8f9f7 19 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 20 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 21 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 // SCU mode for I2C SCL/SDA pins
<> 144:ef7eb2e8f9f7 24 #define SCU_PINIO_I2C SCU_PINIO_PULLNONE
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 static const PinMap PinMap_I2C_SDA[] = {
<> 144:ef7eb2e8f9f7 27 {P_DED, I2C_0, 0},
<> 144:ef7eb2e8f9f7 28 {P2_3, I2C_1, (SCU_PINIO_I2C | 1)},
<> 144:ef7eb2e8f9f7 29 {PE_13, I2C_1, (SCU_PINIO_I2C | 2)},
<> 144:ef7eb2e8f9f7 30 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 31 };
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 static const PinMap PinMap_I2C_SCL[] = {
<> 144:ef7eb2e8f9f7 34 {P_DED, I2C_0, 0},
<> 144:ef7eb2e8f9f7 35 {P2_4, I2C_1, (SCU_PINIO_I2C | 1)},
<> 144:ef7eb2e8f9f7 36 {PE_14, I2C_1, (SCU_PINIO_I2C | 2)},
<> 144:ef7eb2e8f9f7 37 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 38 };
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #define I2C_CONSET(x) (x->i2c->CONSET)
<> 144:ef7eb2e8f9f7 41 #define I2C_CONCLR(x) (x->i2c->CONCLR)
<> 144:ef7eb2e8f9f7 42 #define I2C_STAT(x) (x->i2c->STAT)
<> 144:ef7eb2e8f9f7 43 #define I2C_DAT(x) (x->i2c->DAT)
<> 144:ef7eb2e8f9f7 44 #define I2C_SCLL(x, val) (x->i2c->SCLL = val)
<> 144:ef7eb2e8f9f7 45 #define I2C_SCLH(x, val) (x->i2c->SCLH = val)
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 static const uint32_t I2C_addr_offset[2][4] = {
<> 144:ef7eb2e8f9f7 48 {0x0C, 0x20, 0x24, 0x28},
<> 144:ef7eb2e8f9f7 49 {0x30, 0x34, 0x38, 0x3C}
<> 144:ef7eb2e8f9f7 50 };
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
<> 144:ef7eb2e8f9f7 53 I2C_CONCLR(obj) = (start << 5)
<> 144:ef7eb2e8f9f7 54 | (stop << 4)
<> 144:ef7eb2e8f9f7 55 | (interrupt << 3)
<> 144:ef7eb2e8f9f7 56 | (acknowledge << 2);
<> 144:ef7eb2e8f9f7 57 }
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
<> 144:ef7eb2e8f9f7 60 I2C_CONSET(obj) = (start << 5)
<> 144:ef7eb2e8f9f7 61 | (stop << 4)
<> 144:ef7eb2e8f9f7 62 | (interrupt << 3)
<> 144:ef7eb2e8f9f7 63 | (acknowledge << 2);
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 // Clear the Serial Interrupt (SI)
<> 144:ef7eb2e8f9f7 67 static inline void i2c_clear_SI(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 68 i2c_conclr(obj, 0, 0, 1, 0);
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 static inline int i2c_status(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 72 return I2C_STAT(obj);
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 // Wait until the Serial Interrupt (SI) is set
<> 144:ef7eb2e8f9f7 76 static int i2c_wait_SI(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 77 int timeout = 0;
<> 144:ef7eb2e8f9f7 78 while (!(I2C_CONSET(obj) & (1 << 3))) {
<> 144:ef7eb2e8f9f7 79 timeout++;
<> 144:ef7eb2e8f9f7 80 if (timeout > 100000) return -1;
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82 return 0;
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 static inline void i2c_interface_enable(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 86 I2C_CONSET(obj) = 0x40;
<> 144:ef7eb2e8f9f7 87 }
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
<> 144:ef7eb2e8f9f7 90 // determine the SPI to use
<> 144:ef7eb2e8f9f7 91 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
<> 144:ef7eb2e8f9f7 92 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
<> 144:ef7eb2e8f9f7 93 obj->i2c = (LPC_I2C_T *)pinmap_merge(i2c_sda, i2c_scl);
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 if ((int)obj->i2c == NC) {
<> 144:ef7eb2e8f9f7 96 error("I2C pin mapping failed");
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 // set default frequency at 100k
<> 144:ef7eb2e8f9f7 100 i2c_frequency(obj, 100000);
<> 144:ef7eb2e8f9f7 101 i2c_conclr(obj, 1, 1, 1, 1);
<> 144:ef7eb2e8f9f7 102 i2c_interface_enable(obj);
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 // Set SCU functions
<> 144:ef7eb2e8f9f7 105 if (scl == P_DED) {
<> 144:ef7eb2e8f9f7 106 // Enable dedicated I2C0 SDA and SCL pins (open drain)
<> 144:ef7eb2e8f9f7 107 LPC_SCU->SFSI2C0 = (1 << 11) | (1 << 3);
<> 144:ef7eb2e8f9f7 108 } else {
<> 144:ef7eb2e8f9f7 109 pinmap_pinout(sda, PinMap_I2C_SDA);
<> 144:ef7eb2e8f9f7 110 pinmap_pinout(scl, PinMap_I2C_SCL);
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 inline int i2c_start(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 115 int status = 0;
<> 144:ef7eb2e8f9f7 116 int isInterrupted = I2C_CONSET(obj) & (1 << 3);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 // 8.1 Before master mode can be entered, I2CON must be initialised to:
<> 144:ef7eb2e8f9f7 119 // - I2EN STA STO SI AA - -
<> 144:ef7eb2e8f9f7 120 // - 1 0 0 x x - -
<> 144:ef7eb2e8f9f7 121 // if AA = 0, it can't enter slave mode
<> 144:ef7eb2e8f9f7 122 i2c_conclr(obj, 1, 1, 0, 1);
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 // The master mode may now be entered by setting the STA bit
<> 144:ef7eb2e8f9f7 125 // this will generate a start condition when the bus becomes free
<> 144:ef7eb2e8f9f7 126 i2c_conset(obj, 1, 0, 0, 1);
<> 144:ef7eb2e8f9f7 127 // Clearing SI bit when it wasn't set on entry can jump past state
<> 144:ef7eb2e8f9f7 128 // 0x10 or 0x08 and erroneously send uninitialized slave address.
<> 144:ef7eb2e8f9f7 129 if (isInterrupted)
<> 144:ef7eb2e8f9f7 130 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 133 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 // Clear start bit now that it's transmitted
<> 144:ef7eb2e8f9f7 136 i2c_conclr(obj, 1, 0, 0, 0);
<> 144:ef7eb2e8f9f7 137 return status;
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 inline int i2c_stop(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 141 int timeout = 0;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 // write the stop bit
<> 144:ef7eb2e8f9f7 144 i2c_conset(obj, 0, 1, 0, 0);
<> 144:ef7eb2e8f9f7 145 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 // wait for STO bit to reset
<> 144:ef7eb2e8f9f7 148 while(I2C_CONSET(obj) & (1 << 4)) {
<> 144:ef7eb2e8f9f7 149 timeout ++;
<> 144:ef7eb2e8f9f7 150 if (timeout > 100000) return 1;
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 return 0;
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
<> 144:ef7eb2e8f9f7 157 // write the data
<> 144:ef7eb2e8f9f7 158 I2C_DAT(obj) = value;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 // clear SI to init a send
<> 144:ef7eb2e8f9f7 161 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 // wait and return status
<> 144:ef7eb2e8f9f7 164 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 165 return i2c_status(obj);
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 static inline int i2c_do_read(i2c_t *obj, int last) {
<> 144:ef7eb2e8f9f7 169 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
<> 144:ef7eb2e8f9f7 170 if(last) {
<> 144:ef7eb2e8f9f7 171 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
<> 144:ef7eb2e8f9f7 172 } else {
<> 144:ef7eb2e8f9f7 173 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 // accept byte
<> 144:ef7eb2e8f9f7 177 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 // wait for it to arrive
<> 144:ef7eb2e8f9f7 180 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 // return the data
<> 144:ef7eb2e8f9f7 183 return (I2C_DAT(obj) & 0xFF);
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 void i2c_frequency(i2c_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 187 // [TODO] set pclk to /4
<> 144:ef7eb2e8f9f7 188 uint32_t PCLK = SystemCoreClock / 4;
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 uint32_t pulse = PCLK / (hz * 2);
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 // I2C Rate
<> 144:ef7eb2e8f9f7 193 I2C_SCLL(obj, pulse);
<> 144:ef7eb2e8f9f7 194 I2C_SCLH(obj, pulse);
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 // The I2C does a read or a write as a whole operation
<> 144:ef7eb2e8f9f7 198 // There are two types of error conditions it can encounter
<> 144:ef7eb2e8f9f7 199 // 1) it can not obtain the bus
<> 144:ef7eb2e8f9f7 200 // 2) it gets error responses at part of the transmission
<> 144:ef7eb2e8f9f7 201 //
<> 144:ef7eb2e8f9f7 202 // We tackle them as follows:
<> 144:ef7eb2e8f9f7 203 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
<> 144:ef7eb2e8f9f7 204 // which basically turns it in to a 2)
<> 144:ef7eb2e8f9f7 205 // 2) on error, we use the standard error mechanisms to report/debug
<> 144:ef7eb2e8f9f7 206 //
<> 144:ef7eb2e8f9f7 207 // Therefore an I2C transaction should always complete. If it doesn't it is usually
<> 144:ef7eb2e8f9f7 208 // because something is setup wrong (e.g. wiring), and we don't need to programatically
<> 144:ef7eb2e8f9f7 209 // check for that
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
<> 144:ef7eb2e8f9f7 212 int count, status;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 status = i2c_start(obj);
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 if ((status != 0x10) && (status != 0x08)) {
<> 144:ef7eb2e8f9f7 217 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 218 return I2C_ERROR_BUS_BUSY;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 status = i2c_do_write(obj, (address | 0x01), 1);
<> 144:ef7eb2e8f9f7 222 if (status != 0x40) {
<> 144:ef7eb2e8f9f7 223 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 224 return I2C_ERROR_NO_SLAVE;
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 // Read in all except last byte
<> 144:ef7eb2e8f9f7 228 for (count = 0; count < (length - 1); count++) {
<> 144:ef7eb2e8f9f7 229 int value = i2c_do_read(obj, 0);
<> 144:ef7eb2e8f9f7 230 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 231 if (status != 0x50) {
<> 144:ef7eb2e8f9f7 232 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 233 return count;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 data[count] = (char) value;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 // read in last byte
<> 144:ef7eb2e8f9f7 239 int value = i2c_do_read(obj, 1);
<> 144:ef7eb2e8f9f7 240 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 241 if (status != 0x58) {
<> 144:ef7eb2e8f9f7 242 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 243 return length - 1;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 data[count] = (char) value;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 // If not repeated start, send stop.
<> 144:ef7eb2e8f9f7 249 if (stop) {
<> 144:ef7eb2e8f9f7 250 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 return length;
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
<> 144:ef7eb2e8f9f7 257 int i, status;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 status = i2c_start(obj);
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 if ((status != 0x10) && (status != 0x08)) {
<> 144:ef7eb2e8f9f7 262 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 263 return I2C_ERROR_BUS_BUSY;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 status = i2c_do_write(obj, (address & 0xFE), 1);
<> 144:ef7eb2e8f9f7 267 if (status != 0x18) {
<> 144:ef7eb2e8f9f7 268 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 269 return I2C_ERROR_NO_SLAVE;
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 for (i=0; i<length; i++) {
<> 144:ef7eb2e8f9f7 273 status = i2c_do_write(obj, data[i], 0);
<> 144:ef7eb2e8f9f7 274 if(status != 0x28) {
<> 144:ef7eb2e8f9f7 275 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 276 return i;
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 // clearing the serial interrupt here might cause an unintended rewrite of the last byte
<> 144:ef7eb2e8f9f7 281 // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
<> 144:ef7eb2e8f9f7 282 // i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 // If not repeated start, send stop.
<> 144:ef7eb2e8f9f7 285 if (stop) {
<> 144:ef7eb2e8f9f7 286 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 return length;
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 void i2c_reset(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 293 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 int i2c_byte_read(i2c_t *obj, int last) {
<> 144:ef7eb2e8f9f7 297 return (i2c_do_read(obj, last) & 0xFF);
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 int i2c_byte_write(i2c_t *obj, int data) {
<> 144:ef7eb2e8f9f7 301 int ack;
<> 144:ef7eb2e8f9f7 302 int status = i2c_do_write(obj, (data & 0xFF), 0);
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 switch(status) {
<> 144:ef7eb2e8f9f7 305 case 0x18: case 0x28: // Master transmit ACKs
<> 144:ef7eb2e8f9f7 306 ack = 1;
<> 144:ef7eb2e8f9f7 307 break;
<> 144:ef7eb2e8f9f7 308 case 0x40: // Master receive address transmitted ACK
<> 144:ef7eb2e8f9f7 309 ack = 1;
<> 144:ef7eb2e8f9f7 310 break;
<> 144:ef7eb2e8f9f7 311 case 0xB8: // Slave transmit ACK
<> 144:ef7eb2e8f9f7 312 ack = 1;
<> 144:ef7eb2e8f9f7 313 break;
<> 144:ef7eb2e8f9f7 314 default:
<> 144:ef7eb2e8f9f7 315 ack = 0;
<> 144:ef7eb2e8f9f7 316 break;
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 return ack;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
<> 144:ef7eb2e8f9f7 323 if (enable_slave != 0) {
<> 144:ef7eb2e8f9f7 324 i2c_conclr(obj, 1, 1, 1, 0);
<> 144:ef7eb2e8f9f7 325 i2c_conset(obj, 0, 0, 0, 1);
<> 144:ef7eb2e8f9f7 326 } else {
<> 144:ef7eb2e8f9f7 327 i2c_conclr(obj, 1, 1, 1, 1);
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 int i2c_slave_receive(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 332 int status;
<> 144:ef7eb2e8f9f7 333 int retval;
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 336 switch(status) {
<> 144:ef7eb2e8f9f7 337 case 0x60: retval = 3; break;
<> 144:ef7eb2e8f9f7 338 case 0x70: retval = 2; break;
<> 144:ef7eb2e8f9f7 339 case 0xA8: retval = 1; break;
<> 144:ef7eb2e8f9f7 340 default : retval = 0; break;
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 return(retval);
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 int i2c_slave_read(i2c_t *obj, char *data, int length) {
<> 144:ef7eb2e8f9f7 347 int count = 0;
<> 144:ef7eb2e8f9f7 348 int status;
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 do {
<> 144:ef7eb2e8f9f7 351 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 352 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 353 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 354 if((status == 0x80) || (status == 0x90)) {
<> 144:ef7eb2e8f9f7 355 data[count] = I2C_DAT(obj) & 0xFF;
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357 count++;
<> 144:ef7eb2e8f9f7 358 } while (((status == 0x80) || (status == 0x90) ||
<> 144:ef7eb2e8f9f7 359 (status == 0x060) || (status == 0x70)) && (count < length));
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 if(status != 0xA0) {
<> 144:ef7eb2e8f9f7 362 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 return count;
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
<> 144:ef7eb2e8f9f7 371 int count = 0;
<> 144:ef7eb2e8f9f7 372 int status;
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 if(length <= 0) {
<> 144:ef7eb2e8f9f7 375 return(0);
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 do {
<> 144:ef7eb2e8f9f7 379 status = i2c_do_write(obj, data[count], 0);
<> 144:ef7eb2e8f9f7 380 count++;
<> 144:ef7eb2e8f9f7 381 } while ((count < length) && (status == 0xB8));
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 if ((status != 0xC0) && (status != 0xC8)) {
<> 144:ef7eb2e8f9f7 384 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 return(count);
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
<> 144:ef7eb2e8f9f7 393 uint32_t addr;
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 if ((idx >= 0) && (idx <= 3)) {
<> 144:ef7eb2e8f9f7 396 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
<> 144:ef7eb2e8f9f7 397 *((uint32_t *) addr) = address & 0xFF;
<> 144:ef7eb2e8f9f7 398 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
<> 144:ef7eb2e8f9f7 399 *((uint32_t *) addr) = mask & 0xFE;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 }