mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c
Dependents: Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay
Fork of mbed-dev by
targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Child:
- 150:02e0a0aed4ec
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /* |
<> | 149:156823d33999 | 2 | * Copyright (c) 2013 Nordic Semiconductor ASA |
<> | 149:156823d33999 | 3 | * All rights reserved. |
<> | 149:156823d33999 | 4 | * |
<> | 149:156823d33999 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 149:156823d33999 | 6 | * are permitted provided that the following conditions are met: |
<> | 149:156823d33999 | 7 | * |
<> | 149:156823d33999 | 8 | * 1. Redistributions of source code must retain the above copyright notice, this list |
<> | 149:156823d33999 | 9 | * of conditions and the following disclaimer. |
<> | 149:156823d33999 | 10 | * |
<> | 149:156823d33999 | 11 | * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA |
<> | 149:156823d33999 | 12 | * integrated circuit in a product or a software update for such product, must reproduce |
<> | 149:156823d33999 | 13 | * the above copyright notice, this list of conditions and the following disclaimer in |
<> | 149:156823d33999 | 14 | * the documentation and/or other materials provided with the distribution. |
<> | 149:156823d33999 | 15 | * |
<> | 149:156823d33999 | 16 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be |
<> | 149:156823d33999 | 17 | * used to endorse or promote products derived from this software without specific prior |
<> | 149:156823d33999 | 18 | * written permission. |
<> | 149:156823d33999 | 19 | * |
<> | 149:156823d33999 | 20 | * 4. This software, with or without modification, must only be used with a |
<> | 149:156823d33999 | 21 | * Nordic Semiconductor ASA integrated circuit. |
<> | 149:156823d33999 | 22 | * |
<> | 149:156823d33999 | 23 | * 5. Any software provided in binary or object form under this license must not be reverse |
<> | 149:156823d33999 | 24 | * engineered, decompiled, modified and/or disassembled. |
<> | 149:156823d33999 | 25 | * |
<> | 149:156823d33999 | 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 149:156823d33999 | 27 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 149:156823d33999 | 28 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 149:156823d33999 | 29 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 149:156823d33999 | 30 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 149:156823d33999 | 31 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 149:156823d33999 | 32 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 149:156823d33999 | 33 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 149:156823d33999 | 34 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 149:156823d33999 | 35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 149:156823d33999 | 36 | * |
<> | 149:156823d33999 | 37 | */ |
<> | 149:156823d33999 | 38 | |
<> | 149:156823d33999 | 39 | #include "us_ticker_api.h" |
<> | 149:156823d33999 | 40 | #include "common_rtc.h" |
<> | 149:156823d33999 | 41 | #include "app_util.h" |
<> | 149:156823d33999 | 42 | #include "nrf_drv_common.h" |
<> | 149:156823d33999 | 43 | #include "lp_ticker_api.h" |
<> | 149:156823d33999 | 44 | |
<> | 149:156823d33999 | 45 | |
<> | 149:156823d33999 | 46 | //------------------------------------------------------------------------------ |
<> | 149:156823d33999 | 47 | // Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h"). |
<> | 149:156823d33999 | 48 | // |
<> | 149:156823d33999 | 49 | #include "app_util_platform.h" |
<> | 149:156823d33999 | 50 | |
<> | 149:156823d33999 | 51 | bool m_common_rtc_enabled = false; |
<> | 149:156823d33999 | 52 | uint32_t volatile m_common_rtc_overflows = 0; |
<> | 149:156823d33999 | 53 | |
<> | 149:156823d33999 | 54 | #if defined(TARGET_MCU_NRF51822) |
<> | 149:156823d33999 | 55 | void common_rtc_irq_handler(void) |
<> | 149:156823d33999 | 56 | #else |
<> | 149:156823d33999 | 57 | void COMMON_RTC_IRQ_HANDLER(void) |
<> | 149:156823d33999 | 58 | #endif |
<> | 149:156823d33999 | 59 | { |
<> | 149:156823d33999 | 60 | if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) { |
<> | 149:156823d33999 | 61 | us_ticker_irq_handler(); |
<> | 149:156823d33999 | 62 | } |
<> | 149:156823d33999 | 63 | |
<> | 149:156823d33999 | 64 | #if DEVICE_LOWPOWERTIMER |
<> | 149:156823d33999 | 65 | if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) { |
<> | 149:156823d33999 | 66 | |
<> | 149:156823d33999 | 67 | lp_ticker_irq_handler(); |
<> | 149:156823d33999 | 68 | } |
<> | 149:156823d33999 | 69 | #endif |
<> | 149:156823d33999 | 70 | |
<> | 149:156823d33999 | 71 | if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) { |
<> | 149:156823d33999 | 72 | nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW); |
<> | 149:156823d33999 | 73 | // Don't disable this event. It shall occur periodically. |
<> | 149:156823d33999 | 74 | |
<> | 149:156823d33999 | 75 | ++m_common_rtc_overflows; |
<> | 149:156823d33999 | 76 | } |
<> | 149:156823d33999 | 77 | } |
<> | 149:156823d33999 | 78 | |
<> | 149:156823d33999 | 79 | void common_rtc_init(void) |
<> | 149:156823d33999 | 80 | { |
<> | 149:156823d33999 | 81 | if (m_common_rtc_enabled) { |
<> | 149:156823d33999 | 82 | return; |
<> | 149:156823d33999 | 83 | } |
<> | 149:156823d33999 | 84 | |
<> | 149:156823d33999 | 85 | // RTC is driven by the low frequency (32.768 kHz) clock, a proper request |
<> | 149:156823d33999 | 86 | // must be made to have it running. |
<> | 149:156823d33999 | 87 | // Currently this clock is started in 'SystemInit' (see "system_nrf51.c" |
<> | 149:156823d33999 | 88 | // or "system_nrf52.c", respectively). |
<> | 149:156823d33999 | 89 | |
<> | 149:156823d33999 | 90 | nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0); |
<> | 149:156823d33999 | 91 | |
<> | 149:156823d33999 | 92 | nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT); |
<> | 149:156823d33999 | 93 | #if defined(TARGET_MCU_NRF51822) |
<> | 149:156823d33999 | 94 | nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT); |
<> | 149:156823d33999 | 95 | #endif |
<> | 149:156823d33999 | 96 | #if DEVICE_LOWPOWERTIMER |
<> | 149:156823d33999 | 97 | nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT); |
<> | 149:156823d33999 | 98 | #endif |
<> | 149:156823d33999 | 99 | nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW); |
<> | 149:156823d33999 | 100 | |
<> | 149:156823d33999 | 101 | // Interrupts on all related events are enabled permanently. Particular |
<> | 149:156823d33999 | 102 | // events will be enabled or disabled as needed (such approach is more |
<> | 149:156823d33999 | 103 | // energy efficient). |
<> | 149:156823d33999 | 104 | nrf_rtc_int_enable(COMMON_RTC_INSTANCE, |
<> | 149:156823d33999 | 105 | #if defined(TARGET_MCU_NRF51822) |
<> | 149:156823d33999 | 106 | OS_TICK_INT_MASK | |
<> | 149:156823d33999 | 107 | #endif |
<> | 149:156823d33999 | 108 | #if DEVICE_LOWPOWERTIMER |
<> | 149:156823d33999 | 109 | LP_TICKER_INT_MASK | |
<> | 149:156823d33999 | 110 | #endif |
<> | 149:156823d33999 | 111 | US_TICKER_INT_MASK | |
<> | 149:156823d33999 | 112 | NRF_RTC_INT_OVERFLOW_MASK); |
<> | 149:156823d33999 | 113 | |
<> | 149:156823d33999 | 114 | // This event is enabled permanently, since overflow indications are needed |
<> | 149:156823d33999 | 115 | // continuously. |
<> | 149:156823d33999 | 116 | nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK); |
<> | 149:156823d33999 | 117 | // All other relevant events are initially disabled. |
<> | 149:156823d33999 | 118 | nrf_rtc_event_disable(COMMON_RTC_INSTANCE, |
<> | 149:156823d33999 | 119 | #if defined(TARGET_MCU_NRF51822) |
<> | 149:156823d33999 | 120 | OS_TICK_INT_MASK | |
<> | 149:156823d33999 | 121 | #endif |
<> | 149:156823d33999 | 122 | #if DEVICE_LOWPOWERTIMER |
<> | 149:156823d33999 | 123 | LP_TICKER_INT_MASK | |
<> | 149:156823d33999 | 124 | #endif |
<> | 149:156823d33999 | 125 | US_TICKER_INT_MASK); |
<> | 149:156823d33999 | 126 | |
<> | 149:156823d33999 | 127 | nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE), |
<> | 149:156823d33999 | 128 | APP_IRQ_PRIORITY_LOW); |
<> | 149:156823d33999 | 129 | |
<> | 149:156823d33999 | 130 | nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START); |
<> | 149:156823d33999 | 131 | |
<> | 149:156823d33999 | 132 | m_common_rtc_enabled = true; |
<> | 149:156823d33999 | 133 | } |
<> | 149:156823d33999 | 134 | |
<> | 149:156823d33999 | 135 | uint32_t common_rtc_32bit_ticks_get(void) |
<> | 149:156823d33999 | 136 | { |
<> | 149:156823d33999 | 137 | uint32_t ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); |
<> | 149:156823d33999 | 138 | // The counter used for time measurements is less than 32 bit wide, |
<> | 149:156823d33999 | 139 | // so its value is complemented with the number of registered overflows |
<> | 149:156823d33999 | 140 | // of the counter. |
<> | 149:156823d33999 | 141 | ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS); |
<> | 149:156823d33999 | 142 | return ticks; |
<> | 149:156823d33999 | 143 | } |
<> | 149:156823d33999 | 144 | |
<> | 149:156823d33999 | 145 | uint64_t common_rtc_64bit_us_get(void) |
<> | 149:156823d33999 | 146 | { |
<> | 149:156823d33999 | 147 | uint32_t ticks = common_rtc_32bit_ticks_get(); |
<> | 149:156823d33999 | 148 | // [ticks -> microseconds] |
<> | 149:156823d33999 | 149 | return ROUNDED_DIV(((uint64_t)ticks) * 1000000, RTC_INPUT_FREQ); |
<> | 149:156823d33999 | 150 | } |
<> | 149:156823d33999 | 151 | |
<> | 149:156823d33999 | 152 | void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel, |
<> | 149:156823d33999 | 153 | uint32_t int_mask) |
<> | 149:156823d33999 | 154 | { |
<> | 149:156823d33999 | 155 | // The internal counter is clocked with a frequency that cannot be easily |
<> | 149:156823d33999 | 156 | // multiplied to 1 MHz, therefore besides the translation of values |
<> | 149:156823d33999 | 157 | // (microsecond <-> ticks) a special care of overflows handling must be |
<> | 149:156823d33999 | 158 | // taken. Here the 32-bit timestamp value is complemented with information |
<> | 149:156823d33999 | 159 | // about current the system up time of (ticks + number of overflows of tick |
<> | 149:156823d33999 | 160 | // counter on upper bits, converted to microseconds), and such 64-bit value |
<> | 149:156823d33999 | 161 | // is then translated to counter ticks. Finally, the lower 24 bits of thus |
<> | 149:156823d33999 | 162 | // calculated value is written to the counter compare register to prepare |
<> | 149:156823d33999 | 163 | // the interrupt generation. |
<> | 149:156823d33999 | 164 | uint64_t current_time64 = common_rtc_64bit_us_get(); |
<> | 149:156823d33999 | 165 | // [add upper 32 bits from the current time to the timestamp value] |
<> | 149:156823d33999 | 166 | uint64_t timestamp64 = us_timestamp + |
<> | 149:156823d33999 | 167 | (current_time64 & ~(uint64_t)0xFFFFFFFF); |
<> | 149:156823d33999 | 168 | // [if the original timestamp value happens to be after the 32 bit counter |
<> | 149:156823d33999 | 169 | // of microsends overflows, correct the upper 32 bits accordingly] |
<> | 149:156823d33999 | 170 | if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) { |
<> | 149:156823d33999 | 171 | timestamp64 += ((uint64_t)1 << 32); |
<> | 149:156823d33999 | 172 | } |
<> | 149:156823d33999 | 173 | // [microseconds -> ticks, always round the result up to avoid too early |
<> | 149:156823d33999 | 174 | // interrupt generation] |
<> | 149:156823d33999 | 175 | uint32_t compare_value = |
<> | 149:156823d33999 | 176 | (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000); |
<> | 149:156823d33999 | 177 | |
<> | 149:156823d33999 | 178 | // The COMPARE event occurs when the value in compare register is N and |
<> | 149:156823d33999 | 179 | // the counter value changes from N-1 to N. Therefore, the minimal safe |
<> | 149:156823d33999 | 180 | // difference between the compare value to be set and the current counter |
<> | 149:156823d33999 | 181 | // value is 2 ticks. This guarantees that the compare trigger is properly |
<> | 149:156823d33999 | 182 | // setup before the compare condition occurs. |
<> | 149:156823d33999 | 183 | uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2; |
<> | 149:156823d33999 | 184 | if ((int)(compare_value - closest_safe_compare) <= 0) { |
<> | 149:156823d33999 | 185 | compare_value = closest_safe_compare; |
<> | 149:156823d33999 | 186 | } |
<> | 149:156823d33999 | 187 | |
<> | 149:156823d33999 | 188 | nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value)); |
<> | 149:156823d33999 | 189 | nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask); |
<> | 149:156823d33999 | 190 | } |
<> | 149:156823d33999 | 191 | //------------------------------------------------------------------------------ |
<> | 149:156823d33999 | 192 | |
<> | 149:156823d33999 | 193 | |
<> | 149:156823d33999 | 194 | void us_ticker_init(void) |
<> | 149:156823d33999 | 195 | { |
<> | 149:156823d33999 | 196 | common_rtc_init(); |
<> | 149:156823d33999 | 197 | } |
<> | 149:156823d33999 | 198 | |
<> | 149:156823d33999 | 199 | uint32_t us_ticker_read() |
<> | 149:156823d33999 | 200 | { |
<> | 149:156823d33999 | 201 | us_ticker_init(); |
<> | 149:156823d33999 | 202 | return (uint32_t)common_rtc_64bit_us_get(); |
<> | 149:156823d33999 | 203 | } |
<> | 149:156823d33999 | 204 | |
<> | 149:156823d33999 | 205 | void us_ticker_set_interrupt(timestamp_t timestamp) |
<> | 149:156823d33999 | 206 | { |
<> | 149:156823d33999 | 207 | common_rtc_set_interrupt(timestamp, |
<> | 149:156823d33999 | 208 | US_TICKER_CC_CHANNEL, US_TICKER_INT_MASK); |
<> | 149:156823d33999 | 209 | } |
<> | 149:156823d33999 | 210 | |
<> | 149:156823d33999 | 211 | void us_ticker_disable_interrupt(void) |
<> | 149:156823d33999 | 212 | { |
<> | 149:156823d33999 | 213 | nrf_rtc_event_disable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK); |
<> | 149:156823d33999 | 214 | } |
<> | 149:156823d33999 | 215 | |
<> | 149:156823d33999 | 216 | void us_ticker_clear_interrupt(void) |
<> | 149:156823d33999 | 217 | { |
<> | 149:156823d33999 | 218 | nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT); |
<> | 149:156823d33999 | 219 | } |
<> | 149:156823d33999 | 220 | |
<> | 149:156823d33999 | 221 | |
<> | 149:156823d33999 | 222 | // Since there is no SysTick on NRF51, the RTC1 channel 1 is used as an |
<> | 149:156823d33999 | 223 | // alternative source of RTOS ticks. |
<> | 149:156823d33999 | 224 | #if defined(TARGET_MCU_NRF51822) |
<> | 149:156823d33999 | 225 | |
<> | 149:156823d33999 | 226 | #include "toolchain.h" |
<> | 149:156823d33999 | 227 | |
<> | 149:156823d33999 | 228 | |
<> | 149:156823d33999 | 229 | #define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1) |
<> | 149:156823d33999 | 230 | |
<> | 149:156823d33999 | 231 | /** |
<> | 149:156823d33999 | 232 | * The value previously set in the capture compare register of channel 1 |
<> | 149:156823d33999 | 233 | */ |
<> | 149:156823d33999 | 234 | static uint32_t previous_tick_cc_value = 0; |
<> | 149:156823d33999 | 235 | |
<> | 149:156823d33999 | 236 | /* |
<> | 149:156823d33999 | 237 | RTX provide the following definitions which are used by the tick code: |
<> | 149:156823d33999 | 238 | * os_trv: The number (minus 1) of clock cycle between two tick. |
<> | 149:156823d33999 | 239 | * os_clockrate: Time duration between two ticks (in us). |
<> | 149:156823d33999 | 240 | * OS_Tick_Handler: The function which handle a tick event. |
<> | 149:156823d33999 | 241 | This function is special because it never returns. |
<> | 149:156823d33999 | 242 | Those definitions are used by the code which handle the os tick. |
<> | 149:156823d33999 | 243 | To allow compilation of us_ticker programs without RTOS, those symbols are |
<> | 149:156823d33999 | 244 | exported from this module as weak ones. |
<> | 149:156823d33999 | 245 | */ |
<> | 149:156823d33999 | 246 | MBED_WEAK uint32_t const os_trv; |
<> | 149:156823d33999 | 247 | MBED_WEAK uint32_t const os_clockrate; |
<> | 149:156823d33999 | 248 | MBED_WEAK void OS_Tick_Handler() { } |
<> | 149:156823d33999 | 249 | |
<> | 149:156823d33999 | 250 | |
<> | 149:156823d33999 | 251 | #if defined (__CC_ARM) /* ARMCC Compiler */ |
<> | 149:156823d33999 | 252 | |
<> | 149:156823d33999 | 253 | __asm void COMMON_RTC_IRQ_HANDLER(void) |
<> | 149:156823d33999 | 254 | { |
<> | 149:156823d33999 | 255 | IMPORT OS_Tick_Handler |
<> | 149:156823d33999 | 256 | IMPORT common_rtc_irq_handler |
<> | 149:156823d33999 | 257 | |
<> | 149:156823d33999 | 258 | /** |
<> | 149:156823d33999 | 259 | * Chanel 1 of RTC1 is used by RTX as a systick. |
<> | 149:156823d33999 | 260 | * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. |
<> | 149:156823d33999 | 261 | * Otherwise, just execute common_rtc_irq_handler. |
<> | 149:156823d33999 | 262 | * This function has to be written in assembly and tagged as naked because OS_Tick_Handler |
<> | 149:156823d33999 | 263 | * will never return. |
<> | 149:156823d33999 | 264 | * A c function would put lr on the stack before calling OS_Tick_Handler and this value |
<> | 149:156823d33999 | 265 | * would never been dequeued. |
<> | 149:156823d33999 | 266 | * |
<> | 149:156823d33999 | 267 | * \code |
<> | 149:156823d33999 | 268 | * void COMMON_RTC_IRQ_HANDLER(void) { |
<> | 149:156823d33999 | 269 | if(NRF_RTC1->EVENTS_COMPARE[1]) { |
<> | 149:156823d33999 | 270 | // never return... |
<> | 149:156823d33999 | 271 | OS_Tick_Handler(); |
<> | 149:156823d33999 | 272 | } else { |
<> | 149:156823d33999 | 273 | common_rtc_irq_handler(); |
<> | 149:156823d33999 | 274 | } |
<> | 149:156823d33999 | 275 | } |
<> | 149:156823d33999 | 276 | * \endcode |
<> | 149:156823d33999 | 277 | */ |
<> | 149:156823d33999 | 278 | ldr r0,=0x40011144 |
<> | 149:156823d33999 | 279 | ldr r1, [r0, #0] |
<> | 149:156823d33999 | 280 | cmp r1, #0 |
<> | 149:156823d33999 | 281 | beq US_TICKER_HANDLER |
<> | 149:156823d33999 | 282 | bl OS_Tick_Handler |
<> | 149:156823d33999 | 283 | US_TICKER_HANDLER |
<> | 149:156823d33999 | 284 | push {r3, lr} |
<> | 149:156823d33999 | 285 | bl common_rtc_irq_handler |
<> | 149:156823d33999 | 286 | pop {r3, pc} |
<> | 149:156823d33999 | 287 | ; ALIGN ; |
<> | 149:156823d33999 | 288 | } |
<> | 149:156823d33999 | 289 | |
<> | 149:156823d33999 | 290 | #elif defined (__GNUC__) /* GNU Compiler */ |
<> | 149:156823d33999 | 291 | |
<> | 149:156823d33999 | 292 | __attribute__((naked)) void COMMON_RTC_IRQ_HANDLER(void) |
<> | 149:156823d33999 | 293 | { |
<> | 149:156823d33999 | 294 | /** |
<> | 149:156823d33999 | 295 | * Chanel 1 of RTC1 is used by RTX as a systick. |
<> | 149:156823d33999 | 296 | * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. |
<> | 149:156823d33999 | 297 | * Otherwise, just execute common_rtc_irq_handler. |
<> | 149:156823d33999 | 298 | * This function has to be written in assembly and tagged as naked because OS_Tick_Handler |
<> | 149:156823d33999 | 299 | * will never return. |
<> | 149:156823d33999 | 300 | * A c function would put lr on the stack before calling OS_Tick_Handler and this value |
<> | 149:156823d33999 | 301 | * would never been dequeued. |
<> | 149:156823d33999 | 302 | * |
<> | 149:156823d33999 | 303 | * \code |
<> | 149:156823d33999 | 304 | * void COMMON_RTC_IRQ_HANDLER(void) { |
<> | 149:156823d33999 | 305 | if(NRF_RTC1->EVENTS_COMPARE[1]) { |
<> | 149:156823d33999 | 306 | // never return... |
<> | 149:156823d33999 | 307 | OS_Tick_Handler(); |
<> | 149:156823d33999 | 308 | } else { |
<> | 149:156823d33999 | 309 | common_rtc_irq_handler(); |
<> | 149:156823d33999 | 310 | } |
<> | 149:156823d33999 | 311 | } |
<> | 149:156823d33999 | 312 | * \endcode |
<> | 149:156823d33999 | 313 | */ |
<> | 149:156823d33999 | 314 | __asm__ ( |
<> | 149:156823d33999 | 315 | "ldr r0,=0x40011144\n" |
<> | 149:156823d33999 | 316 | "ldr r1, [r0, #0]\n" |
<> | 149:156823d33999 | 317 | "cmp r1, #0\n" |
<> | 149:156823d33999 | 318 | "beq US_TICKER_HANDLER\n" |
<> | 149:156823d33999 | 319 | "bl OS_Tick_Handler\n" |
<> | 149:156823d33999 | 320 | "US_TICKER_HANDLER:\n" |
<> | 149:156823d33999 | 321 | "push {r3, lr}\n" |
<> | 149:156823d33999 | 322 | "bl common_rtc_irq_handler\n" |
<> | 149:156823d33999 | 323 | "pop {r3, pc}\n" |
<> | 149:156823d33999 | 324 | "nop" |
<> | 149:156823d33999 | 325 | ); |
<> | 149:156823d33999 | 326 | } |
<> | 149:156823d33999 | 327 | |
<> | 149:156823d33999 | 328 | #elif defined (__ICCARM__)//IAR |
<> | 149:156823d33999 | 329 | void common_rtc_irq_handler(void); |
<> | 149:156823d33999 | 330 | |
<> | 149:156823d33999 | 331 | __stackless __task void COMMON_RTC_IRQ_HANDLER(void) |
<> | 149:156823d33999 | 332 | { |
<> | 149:156823d33999 | 333 | uint32_t temp; |
<> | 149:156823d33999 | 334 | |
<> | 149:156823d33999 | 335 | __asm volatile( |
<> | 149:156823d33999 | 336 | " ldr %[temp], [%[reg2check]] \n" |
<> | 149:156823d33999 | 337 | " cmp %[temp], #0 \n" |
<> | 149:156823d33999 | 338 | " beq 1f \n" |
<> | 149:156823d33999 | 339 | " bl.w OS_Tick_Handler \n" |
<> | 149:156823d33999 | 340 | "1: \n" |
<> | 149:156823d33999 | 341 | " push {r3, lr}\n" |
<> | 149:156823d33999 | 342 | " blx %[rtc_irq] \n" |
<> | 149:156823d33999 | 343 | " pop {r3, pc}\n" |
<> | 149:156823d33999 | 344 | |
<> | 149:156823d33999 | 345 | : /* Outputs */ |
<> | 149:156823d33999 | 346 | [temp] "=&r"(temp) |
<> | 149:156823d33999 | 347 | : /* Inputs */ |
<> | 149:156823d33999 | 348 | [reg2check] "r"(0x40011144), |
<> | 149:156823d33999 | 349 | [rtc_irq] "r"(common_rtc_irq_handler) |
<> | 149:156823d33999 | 350 | : /* Clobbers */ |
<> | 149:156823d33999 | 351 | "cc" |
<> | 149:156823d33999 | 352 | ); |
<> | 149:156823d33999 | 353 | (void)temp; |
<> | 149:156823d33999 | 354 | } |
<> | 149:156823d33999 | 355 | |
<> | 149:156823d33999 | 356 | |
<> | 149:156823d33999 | 357 | #else |
<> | 149:156823d33999 | 358 | |
<> | 149:156823d33999 | 359 | #error Compiler not supported. |
<> | 149:156823d33999 | 360 | #error Provide a definition of COMMON_RTC_IRQ_HANDLER. |
<> | 149:156823d33999 | 361 | |
<> | 149:156823d33999 | 362 | /* |
<> | 149:156823d33999 | 363 | * Chanel 1 of RTC1 is used by RTX as a systick. |
<> | 149:156823d33999 | 364 | * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. |
<> | 149:156823d33999 | 365 | * Otherwise, just execute common_rtc_irq_handler. |
<> | 149:156823d33999 | 366 | * This function has to be written in assembly and tagged as naked because OS_Tick_Handler |
<> | 149:156823d33999 | 367 | * will never return. |
<> | 149:156823d33999 | 368 | * A c function would put lr on the stack before calling OS_Tick_Handler and this value |
<> | 149:156823d33999 | 369 | * will never been dequeued. After a certain time a stack overflow will happen. |
<> | 149:156823d33999 | 370 | * |
<> | 149:156823d33999 | 371 | * \code |
<> | 149:156823d33999 | 372 | * void COMMON_RTC_IRQ_HANDLER(void) { |
<> | 149:156823d33999 | 373 | if(NRF_RTC1->EVENTS_COMPARE[1]) { |
<> | 149:156823d33999 | 374 | // never return... |
<> | 149:156823d33999 | 375 | OS_Tick_Handler(); |
<> | 149:156823d33999 | 376 | } else { |
<> | 149:156823d33999 | 377 | common_rtc_irq_handler(); |
<> | 149:156823d33999 | 378 | } |
<> | 149:156823d33999 | 379 | } |
<> | 149:156823d33999 | 380 | * \endcode |
<> | 149:156823d33999 | 381 | */ |
<> | 149:156823d33999 | 382 | |
<> | 149:156823d33999 | 383 | #endif |
<> | 149:156823d33999 | 384 | |
<> | 149:156823d33999 | 385 | /** |
<> | 149:156823d33999 | 386 | * Return the next number of clock cycle needed for the next tick. |
<> | 149:156823d33999 | 387 | * @note This function has been carrefuly optimized for a systick occuring every 1000us. |
<> | 149:156823d33999 | 388 | */ |
<> | 149:156823d33999 | 389 | static uint32_t get_next_tick_cc_delta() { |
<> | 149:156823d33999 | 390 | uint32_t delta = 0; |
<> | 149:156823d33999 | 391 | |
<> | 149:156823d33999 | 392 | if (os_clockrate != 1000) { |
<> | 149:156823d33999 | 393 | // In RTX, by default SYSTICK is is used. |
<> | 149:156823d33999 | 394 | // A tick event is generated every os_trv + 1 clock cycles of the system timer. |
<> | 149:156823d33999 | 395 | delta = os_trv + 1; |
<> | 149:156823d33999 | 396 | } else { |
<> | 149:156823d33999 | 397 | // If the clockrate is set to 1000us then 1000 tick should happen every second. |
<> | 149:156823d33999 | 398 | // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31. |
<> | 149:156823d33999 | 399 | // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be |
<> | 149:156823d33999 | 400 | // generated in 32000 clock cycle instead of 32768 clock cycles. |
<> | 149:156823d33999 | 401 | // As a result, if a user schedule an OS timer to start in 100s, the timer will start |
<> | 149:156823d33999 | 402 | // instead after 97.656s |
<> | 149:156823d33999 | 403 | // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768 |
<> | 149:156823d33999 | 404 | // clock cycles. |
<> | 149:156823d33999 | 405 | // The strategy is simple, for 1000 ticks: |
<> | 149:156823d33999 | 406 | // * 768 ticks will occur 33 clock cycles after the previous tick |
<> | 149:156823d33999 | 407 | // * 232 ticks will occur 32 clock cycles after the previous tick |
<> | 149:156823d33999 | 408 | // By default every delta is equal to 33. |
<> | 149:156823d33999 | 409 | // Every five ticks (20%, 200 delta in one second), the delta is equal to 32 |
<> | 149:156823d33999 | 410 | // The remaining (32) deltas equal to 32 are distributed using primes numbers. |
<> | 149:156823d33999 | 411 | static uint32_t counter = 0; |
<> | 149:156823d33999 | 412 | if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) { |
<> | 149:156823d33999 | 413 | delta = 32; |
<> | 149:156823d33999 | 414 | } else { |
<> | 149:156823d33999 | 415 | delta = 33; |
<> | 149:156823d33999 | 416 | } |
<> | 149:156823d33999 | 417 | ++counter; |
<> | 149:156823d33999 | 418 | if (counter == 1000) { |
<> | 149:156823d33999 | 419 | counter = 0; |
<> | 149:156823d33999 | 420 | } |
<> | 149:156823d33999 | 421 | } |
<> | 149:156823d33999 | 422 | return delta; |
<> | 149:156823d33999 | 423 | } |
<> | 149:156823d33999 | 424 | |
<> | 149:156823d33999 | 425 | static inline void clear_tick_interrupt() { |
<> | 149:156823d33999 | 426 | nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT); |
<> | 149:156823d33999 | 427 | nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK); |
<> | 149:156823d33999 | 428 | } |
<> | 149:156823d33999 | 429 | |
<> | 149:156823d33999 | 430 | /** |
<> | 149:156823d33999 | 431 | * Indicate if a value is included in a range which can be wrapped. |
<> | 149:156823d33999 | 432 | * @param begin start of the range |
<> | 149:156823d33999 | 433 | * @param end end of the range |
<> | 149:156823d33999 | 434 | * @param val value to check |
<> | 149:156823d33999 | 435 | * @return true if the value is included in the range and false otherwise. |
<> | 149:156823d33999 | 436 | */ |
<> | 149:156823d33999 | 437 | static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) { |
<> | 149:156823d33999 | 438 | // regular case, begin < end |
<> | 149:156823d33999 | 439 | // return true if begin <= val < end |
<> | 149:156823d33999 | 440 | if (begin < end) { |
<> | 149:156823d33999 | 441 | if (begin <= val && val < end) { |
<> | 149:156823d33999 | 442 | return true; |
<> | 149:156823d33999 | 443 | } else { |
<> | 149:156823d33999 | 444 | return false; |
<> | 149:156823d33999 | 445 | } |
<> | 149:156823d33999 | 446 | } else { |
<> | 149:156823d33999 | 447 | // In this case end < begin because it has wrap around the limits |
<> | 149:156823d33999 | 448 | // return false if end < val < begin |
<> | 149:156823d33999 | 449 | if (end < val && val < begin) { |
<> | 149:156823d33999 | 450 | return false; |
<> | 149:156823d33999 | 451 | } else { |
<> | 149:156823d33999 | 452 | return true; |
<> | 149:156823d33999 | 453 | } |
<> | 149:156823d33999 | 454 | } |
<> | 149:156823d33999 | 455 | |
<> | 149:156823d33999 | 456 | } |
<> | 149:156823d33999 | 457 | |
<> | 149:156823d33999 | 458 | /** |
<> | 149:156823d33999 | 459 | * Register the next tick. |
<> | 149:156823d33999 | 460 | */ |
<> | 149:156823d33999 | 461 | static void register_next_tick() { |
<> | 149:156823d33999 | 462 | previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); |
<> | 149:156823d33999 | 463 | uint32_t delta = get_next_tick_cc_delta(); |
<> | 149:156823d33999 | 464 | uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL; |
<> | 149:156823d33999 | 465 | |
<> | 149:156823d33999 | 466 | // Disable irq directly for few cycles, |
<> | 149:156823d33999 | 467 | // Validation of the new CC value against the COUNTER, |
<> | 149:156823d33999 | 468 | // Setting the new CC value and enabling CC IRQ should be an atomic operation |
<> | 149:156823d33999 | 469 | // Otherwise, there is a possibility to set an invalid CC value because |
<> | 149:156823d33999 | 470 | // the RTC1 keeps running. |
<> | 149:156823d33999 | 471 | // This code is very short 20-38 cycles in the worst case, it shouldn't |
<> | 149:156823d33999 | 472 | // disturb softdevice. |
<> | 149:156823d33999 | 473 | __disable_irq(); |
<> | 149:156823d33999 | 474 | uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); |
<> | 149:156823d33999 | 475 | |
<> | 149:156823d33999 | 476 | // If an overflow occur, set the next tick in COUNTER + delta clock cycles |
<> | 149:156823d33999 | 477 | if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false) { |
<> | 149:156823d33999 | 478 | new_compare_value = current_counter + delta; |
<> | 149:156823d33999 | 479 | } |
<> | 149:156823d33999 | 480 | nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value); |
<> | 149:156823d33999 | 481 | // Enable generation of the compare event for the value set above (this |
<> | 149:156823d33999 | 482 | // event will trigger the interrupt). |
<> | 149:156823d33999 | 483 | nrf_rtc_event_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK); |
<> | 149:156823d33999 | 484 | __enable_irq(); |
<> | 149:156823d33999 | 485 | } |
<> | 149:156823d33999 | 486 | |
<> | 149:156823d33999 | 487 | /** |
<> | 149:156823d33999 | 488 | * Initialize alternative hardware timer as RTX kernel timer |
<> | 149:156823d33999 | 489 | * This function is directly called by RTX. |
<> | 149:156823d33999 | 490 | * @note this function shouldn't be called directly. |
<> | 149:156823d33999 | 491 | * @return IRQ number of the alternative hardware timer |
<> | 149:156823d33999 | 492 | */ |
<> | 149:156823d33999 | 493 | int os_tick_init (void) |
<> | 149:156823d33999 | 494 | { |
<> | 149:156823d33999 | 495 | common_rtc_init(); |
<> | 149:156823d33999 | 496 | |
<> | 149:156823d33999 | 497 | nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, 0); |
<> | 149:156823d33999 | 498 | register_next_tick(); |
<> | 149:156823d33999 | 499 | |
<> | 149:156823d33999 | 500 | return nrf_drv_get_IRQn(COMMON_RTC_INSTANCE); |
<> | 149:156823d33999 | 501 | } |
<> | 149:156823d33999 | 502 | |
<> | 149:156823d33999 | 503 | /** |
<> | 149:156823d33999 | 504 | * Acknowledge the tick interrupt. |
<> | 149:156823d33999 | 505 | * This function is called by the function OS_Tick_Handler of RTX. |
<> | 149:156823d33999 | 506 | * @note this function shouldn't be called directly. |
<> | 149:156823d33999 | 507 | */ |
<> | 149:156823d33999 | 508 | void os_tick_irqack(void) |
<> | 149:156823d33999 | 509 | { |
<> | 149:156823d33999 | 510 | clear_tick_interrupt(); |
<> | 149:156823d33999 | 511 | register_next_tick(); |
<> | 149:156823d33999 | 512 | } |
<> | 149:156823d33999 | 513 | |
<> | 149:156823d33999 | 514 | /** |
<> | 149:156823d33999 | 515 | * Returns the overflow flag of the alternative hardware timer. |
<> | 149:156823d33999 | 516 | * @note This function is exposed by RTX kernel. |
<> | 149:156823d33999 | 517 | * @return 1 if the timer has overflowed and 0 otherwise. |
<> | 149:156823d33999 | 518 | */ |
<> | 149:156823d33999 | 519 | uint32_t os_tick_ovf(void) { |
<> | 149:156823d33999 | 520 | uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); |
<> | 149:156823d33999 | 521 | uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); |
<> | 149:156823d33999 | 522 | |
<> | 149:156823d33999 | 523 | return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1; |
<> | 149:156823d33999 | 524 | } |
<> | 149:156823d33999 | 525 | |
<> | 149:156823d33999 | 526 | /** |
<> | 149:156823d33999 | 527 | * Return the value of the alternative hardware timer. |
<> | 149:156823d33999 | 528 | * @note The documentation is not very clear about what is expected as a result, |
<> | 149:156823d33999 | 529 | * is it an ascending counter, a descending one ? |
<> | 149:156823d33999 | 530 | * None of this is specified. |
<> | 149:156823d33999 | 531 | * The default systick is a descending counter and this function return values in |
<> | 149:156823d33999 | 532 | * descending order, even if the internal counter used is an ascending one. |
<> | 149:156823d33999 | 533 | * @return the value of the alternative hardware timer. |
<> | 149:156823d33999 | 534 | */ |
<> | 149:156823d33999 | 535 | uint32_t os_tick_val(void) { |
<> | 149:156823d33999 | 536 | uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); |
<> | 149:156823d33999 | 537 | uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); |
<> | 149:156823d33999 | 538 | |
<> | 149:156823d33999 | 539 | // do not use os_tick_ovf because its counter value can be different |
<> | 149:156823d33999 | 540 | if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) { |
<> | 149:156823d33999 | 541 | if (next_tick_cc_value > previous_tick_cc_value) { |
<> | 149:156823d33999 | 542 | return next_tick_cc_value - current_counter; |
<> | 149:156823d33999 | 543 | } else if(current_counter <= next_tick_cc_value) { |
<> | 149:156823d33999 | 544 | return next_tick_cc_value - current_counter; |
<> | 149:156823d33999 | 545 | } else { |
<> | 149:156823d33999 | 546 | return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter); |
<> | 149:156823d33999 | 547 | } |
<> | 149:156823d33999 | 548 | } else { |
<> | 149:156823d33999 | 549 | // use (os_trv + 1) has the base step, can be totally inacurate ... |
<> | 149:156823d33999 | 550 | uint32_t clock_cycles_by_tick = os_trv + 1; |
<> | 149:156823d33999 | 551 | |
<> | 149:156823d33999 | 552 | // if current counter has wrap arround, add the limit to it. |
<> | 149:156823d33999 | 553 | if (current_counter < next_tick_cc_value) { |
<> | 149:156823d33999 | 554 | current_counter = current_counter + MAX_RTC_COUNTER_VAL; |
<> | 149:156823d33999 | 555 | } |
<> | 149:156823d33999 | 556 | |
<> | 149:156823d33999 | 557 | return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick); |
<> | 149:156823d33999 | 558 | } |
<> | 149:156823d33999 | 559 | |
<> | 149:156823d33999 | 560 | } |
<> | 149:156823d33999 | 561 | |
<> | 149:156823d33999 | 562 | #endif // defined(TARGET_MCU_NRF51822) |