Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
Parent:
149:156823d33999 
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file dma_map.h
<> 149:156823d33999 4 * @brief DMA hw module register map
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3415 $
<> 149:156823d33999 8 * $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup dma
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 */
<> 149:156823d33999 31
<> 149:156823d33999 32 #ifndef DMA_MAP_H_
<> 149:156823d33999 33 #define DMA_MAP_H_
<> 149:156823d33999 34
<> 149:156823d33999 35 /*************************************************************************************************
<> 149:156823d33999 36 * *
<> 149:156823d33999 37 * Header files *
<> 149:156823d33999 38 * *
<> 149:156823d33999 39 *************************************************************************************************/
<> 149:156823d33999 40
<> 149:156823d33999 41 #include "architecture.h"
<> 149:156823d33999 42
<> 149:156823d33999 43 /**************************************************************************************************
<> 149:156823d33999 44 * *
<> 149:156823d33999 45 * Type definitions *
<> 149:156823d33999 46 * *
<> 149:156823d33999 47 **************************************************************************************************/
<> 149:156823d33999 48
<> 149:156823d33999 49 /** DMA control HW registers structure overlay */
<> 149:156823d33999 50 typedef struct {
<> 149:156823d33999 51 union {
<> 149:156823d33999 52 struct {
<> 149:156823d33999 53 __IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
<> 149:156823d33999 54 __IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
<> 149:156823d33999 55 } BITS;
<> 149:156823d33999 56 __IO uint32_t WORD;
<> 149:156823d33999 57 } CONTROL; /**< Control register */
<> 149:156823d33999 58 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
<> 149:156823d33999 59 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
<> 149:156823d33999 60 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
<> 149:156823d33999 61 union {
<> 149:156823d33999 62 struct {
<> 149:156823d33999 63 __I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
<> 149:156823d33999 64 __I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
<> 149:156823d33999 65 __I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
<> 149:156823d33999 66 } BITS;
<> 149:156823d33999 67 __I uint32_t WORD;
<> 149:156823d33999 68 } STATUS; /**< Status register */
<> 149:156823d33999 69 union {
<> 149:156823d33999 70 struct {
<> 149:156823d33999 71 __IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
<> 149:156823d33999 72 __IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
<> 149:156823d33999 73 __IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
<> 149:156823d33999 74 } BITS;
<> 149:156823d33999 75 __IO uint32_t WORD;
<> 149:156823d33999 76 } INT_ENABLE; /**< Interrupt enable */
<> 149:156823d33999 77 union {
<> 149:156823d33999 78 struct {
<> 149:156823d33999 79 __IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
<> 149:156823d33999 80 __IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
<> 149:156823d33999 81 __IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
<> 149:156823d33999 82 } BITS;
<> 149:156823d33999 83 __IO uint32_t WORD;
<> 149:156823d33999 84 } INT_CLEAR; /**< Interrupt clear */
<> 149:156823d33999 85 union {
<> 149:156823d33999 86 struct {
<> 149:156823d33999 87 __I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
<> 149:156823d33999 88 __I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
<> 149:156823d33999 89 __I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
<> 149:156823d33999 90 } BITS;
<> 149:156823d33999 91 __I uint32_t WORD;
<> 149:156823d33999 92 } INT_STATUS; /**< Interrupt status */
<> 149:156823d33999 93 } DmaReg_t, *DmaReg_pt;
<> 149:156823d33999 94 #endif /* DMA_MAP_H_ */