Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32625/mxc/wdt2.c@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 * $Date: 2016-03-21 15:44:11 -0500 (Mon, 21 Mar 2016) $
<> 150:02e0a0aed4ec 33 * $Revision: 22024 $
<> 150:02e0a0aed4ec 34 *
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 /**
<> 150:02e0a0aed4ec 38 * @file wdt2.c
<> 150:02e0a0aed4ec 39 * @brief Watchdog 2 driver source.
<> 150:02e0a0aed4ec 40 */
<> 150:02e0a0aed4ec 41 #include <stddef.h>
<> 150:02e0a0aed4ec 42 #include "wdt2.h"
<> 150:02e0a0aed4ec 43 #include "pwrseq_regs.h"
<> 150:02e0a0aed4ec 44
<> 150:02e0a0aed4ec 45 static uint32_t interruptEnable = 0; //keeps track to interrupts to enable in start function
<> 150:02e0a0aed4ec 46
<> 150:02e0a0aed4ec 47 /******************************************************************************/
<> 150:02e0a0aed4ec 48 int WDT2_Init(uint8_t runInSleep, uint8_t unlock_key)
<> 150:02e0a0aed4ec 49 {
<> 150:02e0a0aed4ec 50 //enable nanoring in run and sleep mode
<> 150:02e0a0aed4ec 51 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN);
<> 150:02e0a0aed4ec 52
<> 150:02e0a0aed4ec 53 //unlock ctrl to be writable
<> 150:02e0a0aed4ec 54 MXC_WDT2->lock_ctrl = unlock_key;
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56 //check to make sure it unlocked
<> 150:02e0a0aed4ec 57 if (MXC_WDT2->lock_ctrl & 0x01)
<> 150:02e0a0aed4ec 58 return E_BAD_STATE;
<> 150:02e0a0aed4ec 59
<> 150:02e0a0aed4ec 60 //disable all interrupts
<> 150:02e0a0aed4ec 61 interruptEnable = 0;
<> 150:02e0a0aed4ec 62 MXC_WDT2->enable = interruptEnable;
<> 150:02e0a0aed4ec 63
<> 150:02e0a0aed4ec 64 //enable the watchdog clock and clear all other settings
<> 150:02e0a0aed4ec 65 MXC_WDT2->ctrl = (MXC_F_WDT2_CTRL_EN_CLOCK);
<> 150:02e0a0aed4ec 66
<> 150:02e0a0aed4ec 67 //clear all interrupt flags
<> 150:02e0a0aed4ec 68 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
<> 150:02e0a0aed4ec 69
<> 150:02e0a0aed4ec 70 if(runInSleep) {
<> 150:02e0a0aed4ec 71 // turn on nanoring during sleep
<> 150:02e0a0aed4ec 72 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_SLP);
<> 150:02e0a0aed4ec 73 //turn on timer during sleep
<> 150:02e0a0aed4ec 74 MXC_WDT2->ctrl |= MXC_F_WDT2_CTRL_EN_TIMER_SLP;
<> 150:02e0a0aed4ec 75 } else {
<> 150:02e0a0aed4ec 76 // turn off nanoring during sleep
<> 150:02e0a0aed4ec 77 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_NREN_SLP);
<> 150:02e0a0aed4ec 78 //turn off timer during sleep
<> 150:02e0a0aed4ec 79 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER_SLP);
<> 150:02e0a0aed4ec 80 }
<> 150:02e0a0aed4ec 81
<> 150:02e0a0aed4ec 82 //lock ctrl to read-only
<> 150:02e0a0aed4ec 83 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 150:02e0a0aed4ec 84
<> 150:02e0a0aed4ec 85 return E_NO_ERROR;
<> 150:02e0a0aed4ec 86 }
<> 150:02e0a0aed4ec 87
<> 150:02e0a0aed4ec 88 /******************************************************************************/
<> 150:02e0a0aed4ec 89 int WDT2_EnableWakeUp(wdt2_period_t int_period, uint8_t unlock_key)
<> 150:02e0a0aed4ec 90 {
<> 150:02e0a0aed4ec 91 // Make sure interrupt period is valid
<> 150:02e0a0aed4ec 92 if (int_period >= WDT2_PERIOD_MAX)
<> 150:02e0a0aed4ec 93 return E_INVALID;
<> 150:02e0a0aed4ec 94
<> 150:02e0a0aed4ec 95 //unlock ctrl to be writable
<> 150:02e0a0aed4ec 96 MXC_WDT2->lock_ctrl = unlock_key;
<> 150:02e0a0aed4ec 97
<> 150:02e0a0aed4ec 98 //check to make sure it unlocked
<> 150:02e0a0aed4ec 99 if (MXC_WDT2->lock_ctrl & 0x01)
<> 150:02e0a0aed4ec 100 return E_BAD_STATE;
<> 150:02e0a0aed4ec 101
<> 150:02e0a0aed4ec 102 //stop timer and clear interval period
<> 150:02e0a0aed4ec 103 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_INT_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER);
<> 150:02e0a0aed4ec 104
<> 150:02e0a0aed4ec 105 //set interval period
<> 150:02e0a0aed4ec 106 MXC_WDT2->ctrl |= (int_period << MXC_F_WDT2_CTRL_INT_PERIOD_POS);
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 //enable timeout wake-up
<> 150:02e0a0aed4ec 109 interruptEnable |= MXC_F_WDT2_ENABLE_TIMEOUT;
<> 150:02e0a0aed4ec 110
<> 150:02e0a0aed4ec 111 //lock ctrl to read-only
<> 150:02e0a0aed4ec 112 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 150:02e0a0aed4ec 113
<> 150:02e0a0aed4ec 114 // Enable wake-up
<> 150:02e0a0aed4ec 115 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG;
<> 150:02e0a0aed4ec 116
<> 150:02e0a0aed4ec 117 return E_NO_ERROR;
<> 150:02e0a0aed4ec 118 }
<> 150:02e0a0aed4ec 119
<> 150:02e0a0aed4ec 120 /******************************************************************************/
<> 150:02e0a0aed4ec 121 int WDT2_DisableWakeUp(uint8_t unlock_key)
<> 150:02e0a0aed4ec 122 {
<> 150:02e0a0aed4ec 123 //unlock register to be writable
<> 150:02e0a0aed4ec 124 MXC_WDT2->lock_ctrl = unlock_key;
<> 150:02e0a0aed4ec 125
<> 150:02e0a0aed4ec 126 //check to make sure it unlocked
<> 150:02e0a0aed4ec 127 if (MXC_WDT2->lock_ctrl & 0x01)
<> 150:02e0a0aed4ec 128 return E_BAD_STATE;
<> 150:02e0a0aed4ec 129
<> 150:02e0a0aed4ec 130 //disable timeout wake-up
<> 150:02e0a0aed4ec 131 interruptEnable &= ~MXC_F_WDT2_ENABLE_TIMEOUT;
<> 150:02e0a0aed4ec 132 MXC_WDT2->enable = interruptEnable;
<> 150:02e0a0aed4ec 133
<> 150:02e0a0aed4ec 134 //lock register to read-only
<> 150:02e0a0aed4ec 135 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 150:02e0a0aed4ec 136
<> 150:02e0a0aed4ec 137 // disable wake-up
<> 150:02e0a0aed4ec 138 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG;
<> 150:02e0a0aed4ec 139
<> 150:02e0a0aed4ec 140 return E_NO_ERROR;
<> 150:02e0a0aed4ec 141 }
<> 150:02e0a0aed4ec 142
<> 150:02e0a0aed4ec 143 /******************************************************************************/
<> 150:02e0a0aed4ec 144 int WDT2_EnableReset(wdt2_period_t rst_period, uint8_t unlock_key)
<> 150:02e0a0aed4ec 145 {
<> 150:02e0a0aed4ec 146 // Make sure reset period is valid
<> 150:02e0a0aed4ec 147 if (rst_period >= WDT2_PERIOD_MAX)
<> 150:02e0a0aed4ec 148 return E_INVALID;
<> 150:02e0a0aed4ec 149
<> 150:02e0a0aed4ec 150 //unlock ctrl to be writable
<> 150:02e0a0aed4ec 151 MXC_WDT2->lock_ctrl = unlock_key;
<> 150:02e0a0aed4ec 152
<> 150:02e0a0aed4ec 153 //check to make sure it unlocked
<> 150:02e0a0aed4ec 154 if (MXC_WDT2->lock_ctrl & 0x01)
<> 150:02e0a0aed4ec 155 return E_BAD_STATE;
<> 150:02e0a0aed4ec 156
<> 150:02e0a0aed4ec 157 //stop timer and clear reset period
<> 150:02e0a0aed4ec 158 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_RST_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER);
<> 150:02e0a0aed4ec 159
<> 150:02e0a0aed4ec 160 //set reset period
<> 150:02e0a0aed4ec 161 MXC_WDT2->ctrl |= (rst_period << MXC_F_WDT2_CTRL_RST_PERIOD_POS);
<> 150:02e0a0aed4ec 162
<> 150:02e0a0aed4ec 163 //int flag has to be clear before interrupt enable can be written
<> 150:02e0a0aed4ec 164 MXC_WDT2->flags = MXC_F_WDT2_FLAGS_RESET_OUT;
<> 150:02e0a0aed4ec 165
<> 150:02e0a0aed4ec 166 //enable reset0
<> 150:02e0a0aed4ec 167 interruptEnable |= MXC_F_WDT2_ENABLE_RESET_OUT;
<> 150:02e0a0aed4ec 168
<> 150:02e0a0aed4ec 169 //lock ctrl to read-only
<> 150:02e0a0aed4ec 170 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 150:02e0a0aed4ec 171
<> 150:02e0a0aed4ec 172 //enable RSTN on WDT2 reset
<> 150:02e0a0aed4ec 173 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG;
<> 150:02e0a0aed4ec 174
<> 150:02e0a0aed4ec 175 return E_NO_ERROR;
<> 150:02e0a0aed4ec 176 }
<> 150:02e0a0aed4ec 177
<> 150:02e0a0aed4ec 178 /******************************************************************************/
<> 150:02e0a0aed4ec 179 int WDT2_DisableReset(uint8_t unlock_key)
<> 150:02e0a0aed4ec 180 {
<> 150:02e0a0aed4ec 181 //unlock register to be writable
<> 150:02e0a0aed4ec 182 MXC_WDT2->lock_ctrl = unlock_key;
<> 150:02e0a0aed4ec 183
<> 150:02e0a0aed4ec 184 //check to make sure it unlocked
<> 150:02e0a0aed4ec 185 if (MXC_WDT2->lock_ctrl & 0x01)
<> 150:02e0a0aed4ec 186 return E_BAD_STATE;
<> 150:02e0a0aed4ec 187
<> 150:02e0a0aed4ec 188 //disable reset
<> 150:02e0a0aed4ec 189 interruptEnable &= ~MXC_F_WDT2_ENABLE_RESET_OUT;
<> 150:02e0a0aed4ec 190 MXC_WDT2->enable = interruptEnable;
<> 150:02e0a0aed4ec 191
<> 150:02e0a0aed4ec 192 //lock register to read-only
<> 150:02e0a0aed4ec 193 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 150:02e0a0aed4ec 194
<> 150:02e0a0aed4ec 195 //disable RSTN on WDT2 reset
<> 150:02e0a0aed4ec 196 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG;
<> 150:02e0a0aed4ec 197
<> 150:02e0a0aed4ec 198 return E_NO_ERROR;
<> 150:02e0a0aed4ec 199 }
<> 150:02e0a0aed4ec 200
<> 150:02e0a0aed4ec 201 /******************************************************************************/
<> 150:02e0a0aed4ec 202 int WDT2_Start(uint8_t unlock_key)
<> 150:02e0a0aed4ec 203 {
<> 150:02e0a0aed4ec 204 //check if watchdog is already running
<> 150:02e0a0aed4ec 205 if(WDT2_IsActive())
<> 150:02e0a0aed4ec 206 return E_BAD_STATE;
<> 150:02e0a0aed4ec 207
<> 150:02e0a0aed4ec 208 //unlock ctrl to be writable
<> 150:02e0a0aed4ec 209 MXC_WDT2->lock_ctrl = unlock_key;
<> 150:02e0a0aed4ec 210
<> 150:02e0a0aed4ec 211 //check to make sure it unlocked
<> 150:02e0a0aed4ec 212 if (MXC_WDT2->lock_ctrl & 0x01)
<> 150:02e0a0aed4ec 213 return E_BAD_STATE;
<> 150:02e0a0aed4ec 214
<> 150:02e0a0aed4ec 215 WDT2_Reset();
<> 150:02e0a0aed4ec 216
<> 150:02e0a0aed4ec 217 //enable interrupts
<> 150:02e0a0aed4ec 218 MXC_WDT2->enable = interruptEnable;
<> 150:02e0a0aed4ec 219
<> 150:02e0a0aed4ec 220 //start timer
<> 150:02e0a0aed4ec 221 MXC_WDT2->ctrl |= (MXC_F_WDT2_CTRL_EN_TIMER);
<> 150:02e0a0aed4ec 222
<> 150:02e0a0aed4ec 223 //lock ctrl to read-only
<> 150:02e0a0aed4ec 224 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 150:02e0a0aed4ec 225
<> 150:02e0a0aed4ec 226 return E_NO_ERROR;
<> 150:02e0a0aed4ec 227 }
<> 150:02e0a0aed4ec 228
<> 150:02e0a0aed4ec 229 /******************************************************************************/
<> 150:02e0a0aed4ec 230 void WDT2_Reset(void)
<> 150:02e0a0aed4ec 231 {
<> 150:02e0a0aed4ec 232 //reset the watchdog counter
<> 150:02e0a0aed4ec 233 MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_0;
<> 150:02e0a0aed4ec 234 MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_1;
<> 150:02e0a0aed4ec 235
<> 150:02e0a0aed4ec 236 //clear all interrupt flags
<> 150:02e0a0aed4ec 237 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
<> 150:02e0a0aed4ec 238
<> 150:02e0a0aed4ec 239 //wait for all interrupts to clear
<> 150:02e0a0aed4ec 240 while(MXC_WDT2->flags != 0) {
<> 150:02e0a0aed4ec 241 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
<> 150:02e0a0aed4ec 242 }
<> 150:02e0a0aed4ec 243
<> 150:02e0a0aed4ec 244 return;
<> 150:02e0a0aed4ec 245 }
<> 150:02e0a0aed4ec 246
<> 150:02e0a0aed4ec 247 /******************************************************************************/
<> 150:02e0a0aed4ec 248 int WDT2_Stop(uint8_t unlock_key)
<> 150:02e0a0aed4ec 249 {
<> 150:02e0a0aed4ec 250 //check if watchdog is not running
<> 150:02e0a0aed4ec 251 if(!WDT2_IsActive())
<> 150:02e0a0aed4ec 252 return E_BAD_STATE;
<> 150:02e0a0aed4ec 253
<> 150:02e0a0aed4ec 254 //unlock ctrl to be writable
<> 150:02e0a0aed4ec 255 MXC_WDT2->lock_ctrl = unlock_key;
<> 150:02e0a0aed4ec 256
<> 150:02e0a0aed4ec 257 //check to make sure it unlocked
<> 150:02e0a0aed4ec 258 if (MXC_WDT2->lock_ctrl & 0x01)
<> 150:02e0a0aed4ec 259 return E_BAD_STATE;
<> 150:02e0a0aed4ec 260
<> 150:02e0a0aed4ec 261 //disabled the timer and interrupts
<> 150:02e0a0aed4ec 262 MXC_WDT2->enable = 0;
<> 150:02e0a0aed4ec 263 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER);
<> 150:02e0a0aed4ec 264
<> 150:02e0a0aed4ec 265 //lock ctrl to read-only
<> 150:02e0a0aed4ec 266 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
<> 150:02e0a0aed4ec 267
<> 150:02e0a0aed4ec 268 return E_NO_ERROR;
<> 150:02e0a0aed4ec 269 }