Brahim KHARRAB / Mbed 2 deprecated test_rc522

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Dependencies:   mbed

MFRC522.h@0:161f7fa5a879, 2017-02-03 (annotated)

Committer:
mavix14
Date:
Fri Feb 03 14:38:55 2017 +0000
Revision:
0:161f7fa5a879
rrr

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UserRevisionLine numberNew contents of line
mavix14 0:161f7fa5a879 1 /**
mavix14 0:161f7fa5a879 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
mavix14 0:161f7fa5a879 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
mavix14 0:161f7fa5a879 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
mavix14 0:161f7fa5a879 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
mavix14 0:161f7fa5a879 6 * Ported to mbed by Martin Olejar, Dec, 2013
mavix14 0:161f7fa5a879 7 *
mavix14 0:161f7fa5a879 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
mavix14 0:161f7fa5a879 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
mavix14 0:161f7fa5a879 10 *
mavix14 0:161f7fa5a879 11 * There are three hardware components involved:
mavix14 0:161f7fa5a879 12 * 1) The micro controller: An Arduino
mavix14 0:161f7fa5a879 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
mavix14 0:161f7fa5a879 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
mavix14 0:161f7fa5a879 15 *
mavix14 0:161f7fa5a879 16 * The microcontroller and card reader uses SPI for communication.
mavix14 0:161f7fa5a879 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
mavix14 0:161f7fa5a879 18 *
mavix14 0:161f7fa5a879 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
mavix14 0:161f7fa5a879 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
mavix14 0:161f7fa5a879 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
mavix14 0:161f7fa5a879 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
mavix14 0:161f7fa5a879 23 *
mavix14 0:161f7fa5a879 24 * If only the PICC UID is wanted, the above documents has all the needed information.
mavix14 0:161f7fa5a879 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
mavix14 0:161f7fa5a879 26 * The MIFARE Classic chips and protocol is described in the datasheets:
mavix14 0:161f7fa5a879 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
mavix14 0:161f7fa5a879 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
mavix14 0:161f7fa5a879 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
mavix14 0:161f7fa5a879 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
mavix14 0:161f7fa5a879 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
mavix14 0:161f7fa5a879 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
mavix14 0:161f7fa5a879 33 *
mavix14 0:161f7fa5a879 34 * MIFARE Classic 1K (MF1S503x):
mavix14 0:161f7fa5a879 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
mavix14 0:161f7fa5a879 36 * The blocks are numbered 0-63.
mavix14 0:161f7fa5a879 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
mavix14 0:161f7fa5a879 38 * Bytes 0-5: Key A
mavix14 0:161f7fa5a879 39 * Bytes 6-8: Access Bits
mavix14 0:161f7fa5a879 40 * Bytes 9: User data
mavix14 0:161f7fa5a879 41 * Bytes 10-15: Key B (or user data)
mavix14 0:161f7fa5a879 42 * Block 0 is read only manufacturer data.
mavix14 0:161f7fa5a879 43 * To access a block, an authentication using a key from the block's sector must be performed first.
mavix14 0:161f7fa5a879 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
mavix14 0:161f7fa5a879 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
mavix14 0:161f7fa5a879 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
mavix14 0:161f7fa5a879 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
mavix14 0:161f7fa5a879 48 * MIFARE Classic 4K (MF1S703x):
mavix14 0:161f7fa5a879 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
mavix14 0:161f7fa5a879 50 * The blocks are numbered 0-255.
mavix14 0:161f7fa5a879 51 * The last block in each sector is the Sector Trailer like above.
mavix14 0:161f7fa5a879 52 * MIFARE Classic Mini (MF1 IC S20):
mavix14 0:161f7fa5a879 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
mavix14 0:161f7fa5a879 54 * The blocks are numbered 0-19.
mavix14 0:161f7fa5a879 55 * The last block in each sector is the Sector Trailer like above.
mavix14 0:161f7fa5a879 56 *
mavix14 0:161f7fa5a879 57 * MIFARE Ultralight (MF0ICU1):
mavix14 0:161f7fa5a879 58 * Has 16 pages of 4 bytes = 64 bytes.
mavix14 0:161f7fa5a879 59 * Pages 0 + 1 is used for the 7-byte UID.
mavix14 0:161f7fa5a879 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
mavix14 0:161f7fa5a879 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
mavix14 0:161f7fa5a879 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
mavix14 0:161f7fa5a879 63 * MIFARE Ultralight C (MF0ICU2):
mavix14 0:161f7fa5a879 64 * Has 48 pages of 4 bytes = 64 bytes.
mavix14 0:161f7fa5a879 65 * Pages 0 + 1 is used for the 7-byte UID.
mavix14 0:161f7fa5a879 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
mavix14 0:161f7fa5a879 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
mavix14 0:161f7fa5a879 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
mavix14 0:161f7fa5a879 69 * Page 40 Lock bytes
mavix14 0:161f7fa5a879 70 * Page 41 16 bit one way counter
mavix14 0:161f7fa5a879 71 * Pages 42-43 Authentication configuration
mavix14 0:161f7fa5a879 72 * Pages 44-47 Authentication key
mavix14 0:161f7fa5a879 73 */
mavix14 0:161f7fa5a879 74 #ifndef MFRC522_h
mavix14 0:161f7fa5a879 75 #define MFRC522_h
mavix14 0:161f7fa5a879 76
mavix14 0:161f7fa5a879 77 #include "mbed.h"
mavix14 0:161f7fa5a879 78
mavix14 0:161f7fa5a879 79 /**
mavix14 0:161f7fa5a879 80 * MFRC522 example
mavix14 0:161f7fa5a879 81 *
mavix14 0:161f7fa5a879 82 * @code
mavix14 0:161f7fa5a879 83 * #include "mbed.h"
mavix14 0:161f7fa5a879 84 * #include "MFRC522.h"
mavix14 0:161f7fa5a879 85 *
mavix14 0:161f7fa5a879 86 * //KL25Z Pins for MFRC522 SPI interface
mavix14 0:161f7fa5a879 87 * #define SPI_MOSI PTC6
mavix14 0:161f7fa5a879 88 * #define SPI_MISO PTC7
mavix14 0:161f7fa5a879 89 * #define SPI_SCLK PTC5
mavix14 0:161f7fa5a879 90 * #define SPI_CS PTC4
mavix14 0:161f7fa5a879 91 * // KL25Z Pin for MFRC522 reset
mavix14 0:161f7fa5a879 92 * #define MF_RESET PTC3
mavix14 0:161f7fa5a879 93 * // KL25Z Pins for Debug UART port
mavix14 0:161f7fa5a879 94 * #define UART_RX PTA1
mavix14 0:161f7fa5a879 95 * #define UART_TX PTA2
mavix14 0:161f7fa5a879 96 *
mavix14 0:161f7fa5a879 97 * DigitalOut LedRed (LED_RED);
mavix14 0:161f7fa5a879 98 * DigitalOut LedGreen (LED_GREEN);
mavix14 0:161f7fa5a879 99 *
mavix14 0:161f7fa5a879 100 * Serial DebugUART(UART_TX, UART_RX);
mavix14 0:161f7fa5a879 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
mavix14 0:161f7fa5a879 102 *
mavix14 0:161f7fa5a879 103 * int main(void) {
mavix14 0:161f7fa5a879 104 * // Set debug UART speed
mavix14 0:161f7fa5a879 105 * DebugUART.baud(115200);
mavix14 0:161f7fa5a879 106 *
mavix14 0:161f7fa5a879 107 * // Init. RC522 Chip
mavix14 0:161f7fa5a879 108 * RfChip.PCD_Init();
mavix14 0:161f7fa5a879 109 *
mavix14 0:161f7fa5a879 110 * while (true) {
mavix14 0:161f7fa5a879 111 * LedRed = 1;
mavix14 0:161f7fa5a879 112 * LedGreen = 1;
mavix14 0:161f7fa5a879 113 *
mavix14 0:161f7fa5a879 114 * // Look for new cards
mavix14 0:161f7fa5a879 115 * if ( ! RfChip.PICC_IsNewCardPresent())
mavix14 0:161f7fa5a879 116 * {
mavix14 0:161f7fa5a879 117 * wait_ms(500);
mavix14 0:161f7fa5a879 118 * continue;
mavix14 0:161f7fa5a879 119 * }
mavix14 0:161f7fa5a879 120 *
mavix14 0:161f7fa5a879 121 * LedRed = 0;
mavix14 0:161f7fa5a879 122 *
mavix14 0:161f7fa5a879 123 * // Select one of the cards
mavix14 0:161f7fa5a879 124 * if ( ! RfChip.PICC_ReadCardSerial())
mavix14 0:161f7fa5a879 125 * {
mavix14 0:161f7fa5a879 126 * wait_ms(500);
mavix14 0:161f7fa5a879 127 * continue;
mavix14 0:161f7fa5a879 128 * }
mavix14 0:161f7fa5a879 129 *
mavix14 0:161f7fa5a879 130 * LedRed = 1;
mavix14 0:161f7fa5a879 131 * LedGreen = 0;
mavix14 0:161f7fa5a879 132 *
mavix14 0:161f7fa5a879 133 * // Print Card UID
mavix14 0:161f7fa5a879 134 * printf("Card UID: ");
mavix14 0:161f7fa5a879 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
mavix14 0:161f7fa5a879 136 * {
mavix14 0:161f7fa5a879 137 * printf(" %X02", RfChip.uid.uidByte[i]);
mavix14 0:161f7fa5a879 138 * }
mavix14 0:161f7fa5a879 139 * printf("\n\r");
mavix14 0:161f7fa5a879 140 *
mavix14 0:161f7fa5a879 141 * // Print Card type
mavix14 0:161f7fa5a879 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
mavix14 0:161f7fa5a879 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
mavix14 0:161f7fa5a879 144 * wait_ms(1000);
mavix14 0:161f7fa5a879 145 * }
mavix14 0:161f7fa5a879 146 * }
mavix14 0:161f7fa5a879 147 * @endcode
mavix14 0:161f7fa5a879 148 */
mavix14 0:161f7fa5a879 149
mavix14 0:161f7fa5a879 150 class MFRC522 {
mavix14 0:161f7fa5a879 151 public:
mavix14 0:161f7fa5a879 152
mavix14 0:161f7fa5a879 153 /**
mavix14 0:161f7fa5a879 154 * MFRC522 registers (described in chapter 9 of the datasheet).
mavix14 0:161f7fa5a879 155 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
mavix14 0:161f7fa5a879 156 */
mavix14 0:161f7fa5a879 157 enum PCD_Register {
mavix14 0:161f7fa5a879 158 // Page 0: Command and status
mavix14 0:161f7fa5a879 159 // 0x00 // reserved for future use
mavix14 0:161f7fa5a879 160 CommandReg = 0x01 << 1, // starts and stops command execution
mavix14 0:161f7fa5a879 161 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
mavix14 0:161f7fa5a879 162 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
mavix14 0:161f7fa5a879 163 ComIrqReg = 0x04 << 1, // interrupt request bits
mavix14 0:161f7fa5a879 164 DivIrqReg = 0x05 << 1, // interrupt request bits
mavix14 0:161f7fa5a879 165 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
mavix14 0:161f7fa5a879 166 Status1Reg = 0x07 << 1, // communication status bits
mavix14 0:161f7fa5a879 167 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
mavix14 0:161f7fa5a879 168 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
mavix14 0:161f7fa5a879 169 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
mavix14 0:161f7fa5a879 170 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
mavix14 0:161f7fa5a879 171 ControlReg = 0x0C << 1, // miscellaneous control registers
mavix14 0:161f7fa5a879 172 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
mavix14 0:161f7fa5a879 173 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
mavix14 0:161f7fa5a879 174 // 0x0F // reserved for future use
mavix14 0:161f7fa5a879 175
mavix14 0:161f7fa5a879 176 // Page 1:Command
mavix14 0:161f7fa5a879 177 // 0x10 // reserved for future use
mavix14 0:161f7fa5a879 178 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
mavix14 0:161f7fa5a879 179 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
mavix14 0:161f7fa5a879 180 RxModeReg = 0x13 << 1, // defines reception data rate and framing
mavix14 0:161f7fa5a879 181 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
mavix14 0:161f7fa5a879 182 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
mavix14 0:161f7fa5a879 183 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
mavix14 0:161f7fa5a879 184 RxSelReg = 0x17 << 1, // selects internal receiver settings
mavix14 0:161f7fa5a879 185 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
mavix14 0:161f7fa5a879 186 DemodReg = 0x19 << 1, // defines demodulator settings
mavix14 0:161f7fa5a879 187 // 0x1A // reserved for future use
mavix14 0:161f7fa5a879 188 // 0x1B // reserved for future use
mavix14 0:161f7fa5a879 189 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
mavix14 0:161f7fa5a879 190 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
mavix14 0:161f7fa5a879 191 // 0x1E // reserved for future use
mavix14 0:161f7fa5a879 192 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
mavix14 0:161f7fa5a879 193
mavix14 0:161f7fa5a879 194 // Page 2: Configuration
mavix14 0:161f7fa5a879 195 // 0x20 // reserved for future use
mavix14 0:161f7fa5a879 196 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
mavix14 0:161f7fa5a879 197 CRCResultRegL = 0x22 << 1,
mavix14 0:161f7fa5a879 198 // 0x23 // reserved for future use
mavix14 0:161f7fa5a879 199 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
mavix14 0:161f7fa5a879 200 // 0x25 // reserved for future use
mavix14 0:161f7fa5a879 201 RFCfgReg = 0x26 << 1, // configures the receiver gain
mavix14 0:161f7fa5a879 202 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
mavix14 0:161f7fa5a879 203 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
mavix14 0:161f7fa5a879 204 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
mavix14 0:161f7fa5a879 205 TModeReg = 0x2A << 1, // defines settings for the internal timer
mavix14 0:161f7fa5a879 206 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
mavix14 0:161f7fa5a879 207 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
mavix14 0:161f7fa5a879 208 TReloadRegL = 0x2D << 1,
mavix14 0:161f7fa5a879 209 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
mavix14 0:161f7fa5a879 210 TCntValueRegL = 0x2F << 1,
mavix14 0:161f7fa5a879 211
mavix14 0:161f7fa5a879 212 // Page 3:Test Registers
mavix14 0:161f7fa5a879 213 // 0x30 // reserved for future use
mavix14 0:161f7fa5a879 214 TestSel1Reg = 0x31 << 1, // general test signal configuration
mavix14 0:161f7fa5a879 215 TestSel2Reg = 0x32 << 1, // general test signal configuration
mavix14 0:161f7fa5a879 216 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
mavix14 0:161f7fa5a879 217 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
mavix14 0:161f7fa5a879 218 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
mavix14 0:161f7fa5a879 219 AutoTestReg = 0x36 << 1, // controls the digital self test
mavix14 0:161f7fa5a879 220 VersionReg = 0x37 << 1, // shows the software version
mavix14 0:161f7fa5a879 221 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
mavix14 0:161f7fa5a879 222 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
mavix14 0:161f7fa5a879 223 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
mavix14 0:161f7fa5a879 224 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
mavix14 0:161f7fa5a879 225 // 0x3C // reserved for production tests
mavix14 0:161f7fa5a879 226 // 0x3D // reserved for production tests
mavix14 0:161f7fa5a879 227 // 0x3E // reserved for production tests
mavix14 0:161f7fa5a879 228 // 0x3F // reserved for production tests
mavix14 0:161f7fa5a879 229 };
mavix14 0:161f7fa5a879 230
mavix14 0:161f7fa5a879 231 // MFRC522 commands Described in chapter 10 of the datasheet.
mavix14 0:161f7fa5a879 232 enum PCD_Command {
mavix14 0:161f7fa5a879 233 PCD_Idle = 0x00, // no action, cancels current command execution
mavix14 0:161f7fa5a879 234 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
mavix14 0:161f7fa5a879 235 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
mavix14 0:161f7fa5a879 236 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
mavix14 0:161f7fa5a879 237 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
mavix14 0:161f7fa5a879 238 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
mavix14 0:161f7fa5a879 239 PCD_Receive = 0x08, // activates the receiver circuits
mavix14 0:161f7fa5a879 240 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
mavix14 0:161f7fa5a879 241 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
mavix14 0:161f7fa5a879 242 PCD_SoftReset = 0x0F // resets the MFRC522
mavix14 0:161f7fa5a879 243 };
mavix14 0:161f7fa5a879 244
mavix14 0:161f7fa5a879 245 // Commands sent to the PICC.
mavix14 0:161f7fa5a879 246 enum PICC_Command {
mavix14 0:161f7fa5a879 247 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
mavix14 0:161f7fa5a879 248 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
mavix14 0:161f7fa5a879 249 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
mavix14 0:161f7fa5a879 250 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
mavix14 0:161f7fa5a879 251 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
mavix14 0:161f7fa5a879 252 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
mavix14 0:161f7fa5a879 253 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
mavix14 0:161f7fa5a879 254 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
mavix14 0:161f7fa5a879 255
mavix14 0:161f7fa5a879 256 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
mavix14 0:161f7fa5a879 257 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
mavix14 0:161f7fa5a879 258 // The read/write commands can also be used for MIFARE Ultralight.
mavix14 0:161f7fa5a879 259 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
mavix14 0:161f7fa5a879 260 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
mavix14 0:161f7fa5a879 261 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
mavix14 0:161f7fa5a879 262 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
mavix14 0:161f7fa5a879 263 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
mavix14 0:161f7fa5a879 264 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
mavix14 0:161f7fa5a879 265 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
mavix14 0:161f7fa5a879 266 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
mavix14 0:161f7fa5a879 267
mavix14 0:161f7fa5a879 268 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
mavix14 0:161f7fa5a879 269 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
mavix14 0:161f7fa5a879 270 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
mavix14 0:161f7fa5a879 271 };
mavix14 0:161f7fa5a879 272
mavix14 0:161f7fa5a879 273 // MIFARE constants that does not fit anywhere else
mavix14 0:161f7fa5a879 274 enum MIFARE_Misc {
mavix14 0:161f7fa5a879 275 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
mavix14 0:161f7fa5a879 276 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
mavix14 0:161f7fa5a879 277 };
mavix14 0:161f7fa5a879 278
mavix14 0:161f7fa5a879 279 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
mavix14 0:161f7fa5a879 280 enum PICC_Type {
mavix14 0:161f7fa5a879 281 PICC_TYPE_UNKNOWN = 0,
mavix14 0:161f7fa5a879 282 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
mavix14 0:161f7fa5a879 283 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
mavix14 0:161f7fa5a879 284 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
mavix14 0:161f7fa5a879 285 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
mavix14 0:161f7fa5a879 286 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
mavix14 0:161f7fa5a879 287 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
mavix14 0:161f7fa5a879 288 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
mavix14 0:161f7fa5a879 289 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
mavix14 0:161f7fa5a879 290 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
mavix14 0:161f7fa5a879 291 };
mavix14 0:161f7fa5a879 292
mavix14 0:161f7fa5a879 293 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
mavix14 0:161f7fa5a879 294 enum StatusCode {
mavix14 0:161f7fa5a879 295 STATUS_OK = 1, // Success
mavix14 0:161f7fa5a879 296 STATUS_ERROR = 2, // Error in communication
mavix14 0:161f7fa5a879 297 STATUS_COLLISION = 3, // Collision detected
mavix14 0:161f7fa5a879 298 STATUS_TIMEOUT = 4, // Timeout in communication.
mavix14 0:161f7fa5a879 299 STATUS_NO_ROOM = 5, // A buffer is not big enough.
mavix14 0:161f7fa5a879 300 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
mavix14 0:161f7fa5a879 301 STATUS_INVALID = 7, // Invalid argument.
mavix14 0:161f7fa5a879 302 STATUS_CRC_WRONG = 8, // The CRC_A does not match
mavix14 0:161f7fa5a879 303 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
mavix14 0:161f7fa5a879 304 };
mavix14 0:161f7fa5a879 305
mavix14 0:161f7fa5a879 306 // A struct used for passing the UID of a PICC.
mavix14 0:161f7fa5a879 307 typedef struct {
mavix14 0:161f7fa5a879 308 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
mavix14 0:161f7fa5a879 309 uint8_t uidByte[10];
mavix14 0:161f7fa5a879 310 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
mavix14 0:161f7fa5a879 311 } Uid;
mavix14 0:161f7fa5a879 312
mavix14 0:161f7fa5a879 313 // A struct used for passing a MIFARE Crypto1 key
mavix14 0:161f7fa5a879 314 typedef struct {
mavix14 0:161f7fa5a879 315 uint8_t keyByte[MF_KEY_SIZE];
mavix14 0:161f7fa5a879 316 } MIFARE_Key;
mavix14 0:161f7fa5a879 317
mavix14 0:161f7fa5a879 318 // Member variables
mavix14 0:161f7fa5a879 319 Uid uid; // Used by PICC_ReadCardSerial().
mavix14 0:161f7fa5a879 320
mavix14 0:161f7fa5a879 321 // Size of the MFRC522 FIFO
mavix14 0:161f7fa5a879 322 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
mavix14 0:161f7fa5a879 323
mavix14 0:161f7fa5a879 324 /**
mavix14 0:161f7fa5a879 325 * MFRC522 constructor
mavix14 0:161f7fa5a879 326 *
mavix14 0:161f7fa5a879 327 * @param mosi SPI MOSI pin
mavix14 0:161f7fa5a879 328 * @param miso SPI MISO pin
mavix14 0:161f7fa5a879 329 * @param sclk SPI SCLK pin
mavix14 0:161f7fa5a879 330 * @param cs SPI CS pin
mavix14 0:161f7fa5a879 331 * @param reset Reset pin
mavix14 0:161f7fa5a879 332 */
mavix14 0:161f7fa5a879 333 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
mavix14 0:161f7fa5a879 334
mavix14 0:161f7fa5a879 335 /**
mavix14 0:161f7fa5a879 336 * MFRC522 destructor
mavix14 0:161f7fa5a879 337 */
mavix14 0:161f7fa5a879 338 ~MFRC522();
mavix14 0:161f7fa5a879 339
mavix14 0:161f7fa5a879 340
mavix14 0:161f7fa5a879 341 // ************************************************************************************
mavix14 0:161f7fa5a879 342 //! @name Functions for manipulating the MFRC522
mavix14 0:161f7fa5a879 343 // ************************************************************************************
mavix14 0:161f7fa5a879 344 //@{
mavix14 0:161f7fa5a879 345
mavix14 0:161f7fa5a879 346 /**
mavix14 0:161f7fa5a879 347 * Initializes the MFRC522 chip.
mavix14 0:161f7fa5a879 348 */
mavix14 0:161f7fa5a879 349 void PCD_Init (void);
mavix14 0:161f7fa5a879 350
mavix14 0:161f7fa5a879 351 /**
mavix14 0:161f7fa5a879 352 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
mavix14 0:161f7fa5a879 353 */
mavix14 0:161f7fa5a879 354 void PCD_Reset (void);
mavix14 0:161f7fa5a879 355
mavix14 0:161f7fa5a879 356 /**
mavix14 0:161f7fa5a879 357 * Turns the antenna on by enabling pins TX1 and TX2.
mavix14 0:161f7fa5a879 358 * After a reset these pins disabled.
mavix14 0:161f7fa5a879 359 */
mavix14 0:161f7fa5a879 360 void PCD_AntennaOn (void);
mavix14 0:161f7fa5a879 361
mavix14 0:161f7fa5a879 362 /**
mavix14 0:161f7fa5a879 363 * Writes a byte to the specified register in the MFRC522 chip.
mavix14 0:161f7fa5a879 364 * The interface is described in the datasheet section 8.1.2.
mavix14 0:161f7fa5a879 365 *
mavix14 0:161f7fa5a879 366 * @param reg The register to write to. One of the PCD_Register enums.
mavix14 0:161f7fa5a879 367 * @param value The value to write.
mavix14 0:161f7fa5a879 368 */
mavix14 0:161f7fa5a879 369 void PCD_WriteRegister (uint8_t reg, uint8_t value);
mavix14 0:161f7fa5a879 370
mavix14 0:161f7fa5a879 371 /**
mavix14 0:161f7fa5a879 372 * Writes a number of bytes to the specified register in the MFRC522 chip.
mavix14 0:161f7fa5a879 373 * The interface is described in the datasheet section 8.1.2.
mavix14 0:161f7fa5a879 374 *
mavix14 0:161f7fa5a879 375 * @param reg The register to write to. One of the PCD_Register enums.
mavix14 0:161f7fa5a879 376 * @param count The number of bytes to write to the register
mavix14 0:161f7fa5a879 377 * @param values The values to write. Byte array.
mavix14 0:161f7fa5a879 378 */
mavix14 0:161f7fa5a879 379 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
mavix14 0:161f7fa5a879 380
mavix14 0:161f7fa5a879 381 /**
mavix14 0:161f7fa5a879 382 * Reads a byte from the specified register in the MFRC522 chip.
mavix14 0:161f7fa5a879 383 * The interface is described in the datasheet section 8.1.2.
mavix14 0:161f7fa5a879 384 *
mavix14 0:161f7fa5a879 385 * @param reg The register to read from. One of the PCD_Register enums.
mavix14 0:161f7fa5a879 386 * @returns Register value
mavix14 0:161f7fa5a879 387 */
mavix14 0:161f7fa5a879 388 uint8_t PCD_ReadRegister (uint8_t reg);
mavix14 0:161f7fa5a879 389
mavix14 0:161f7fa5a879 390 /**
mavix14 0:161f7fa5a879 391 * Reads a number of bytes from the specified register in the MFRC522 chip.
mavix14 0:161f7fa5a879 392 * The interface is described in the datasheet section 8.1.2.
mavix14 0:161f7fa5a879 393 *
mavix14 0:161f7fa5a879 394 * @param reg The register to read from. One of the PCD_Register enums.
mavix14 0:161f7fa5a879 395 * @param count The number of bytes to read.
mavix14 0:161f7fa5a879 396 * @param values Byte array to store the values in.
mavix14 0:161f7fa5a879 397 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
mavix14 0:161f7fa5a879 398 */
mavix14 0:161f7fa5a879 399 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
mavix14 0:161f7fa5a879 400
mavix14 0:161f7fa5a879 401 /**
mavix14 0:161f7fa5a879 402 * Sets the bits given in mask in register reg.
mavix14 0:161f7fa5a879 403 *
mavix14 0:161f7fa5a879 404 * @param reg The register to update. One of the PCD_Register enums.
mavix14 0:161f7fa5a879 405 * @param mask The bits to set.
mavix14 0:161f7fa5a879 406 */
mavix14 0:161f7fa5a879 407 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
mavix14 0:161f7fa5a879 408
mavix14 0:161f7fa5a879 409 /**
mavix14 0:161f7fa5a879 410 * Clears the bits given in mask from register reg.
mavix14 0:161f7fa5a879 411 *
mavix14 0:161f7fa5a879 412 * @param reg The register to update. One of the PCD_Register enums.
mavix14 0:161f7fa5a879 413 * @param mask The bits to clear.
mavix14 0:161f7fa5a879 414 */
mavix14 0:161f7fa5a879 415 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
mavix14 0:161f7fa5a879 416
mavix14 0:161f7fa5a879 417 /**
mavix14 0:161f7fa5a879 418 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
mavix14 0:161f7fa5a879 419 *
mavix14 0:161f7fa5a879 420 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
mavix14 0:161f7fa5a879 421 * @param length The number of bytes to transfer.
mavix14 0:161f7fa5a879 422 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
mavix14 0:161f7fa5a879 423 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 424 */
mavix14 0:161f7fa5a879 425 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
mavix14 0:161f7fa5a879 426
mavix14 0:161f7fa5a879 427 /**
mavix14 0:161f7fa5a879 428 * Executes the Transceive command.
mavix14 0:161f7fa5a879 429 * CRC validation can only be done if backData and backLen are specified.
mavix14 0:161f7fa5a879 430 *
mavix14 0:161f7fa5a879 431 * @param sendData Pointer to the data to transfer to the FIFO.
mavix14 0:161f7fa5a879 432 * @param sendLen Number of bytes to transfer to the FIFO.
mavix14 0:161f7fa5a879 433 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
mavix14 0:161f7fa5a879 434 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
mavix14 0:161f7fa5a879 435 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
mavix14 0:161f7fa5a879 436 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
mavix14 0:161f7fa5a879 437 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
mavix14 0:161f7fa5a879 438 *
mavix14 0:161f7fa5a879 439 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 440 */
mavix14 0:161f7fa5a879 441 uint8_t PCD_TransceiveData (uint8_t *sendData,
mavix14 0:161f7fa5a879 442 uint8_t sendLen,
mavix14 0:161f7fa5a879 443 uint8_t *backData,
mavix14 0:161f7fa5a879 444 uint8_t *backLen,
mavix14 0:161f7fa5a879 445 uint8_t *validBits = NULL,
mavix14 0:161f7fa5a879 446 uint8_t rxAlign = 0,
mavix14 0:161f7fa5a879 447 bool checkCRC = false);
mavix14 0:161f7fa5a879 448
mavix14 0:161f7fa5a879 449
mavix14 0:161f7fa5a879 450 /**
mavix14 0:161f7fa5a879 451 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
mavix14 0:161f7fa5a879 452 * CRC validation can only be done if backData and backLen are specified.
mavix14 0:161f7fa5a879 453 *
mavix14 0:161f7fa5a879 454 * @param command The command to execute. One of the PCD_Command enums.
mavix14 0:161f7fa5a879 455 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
mavix14 0:161f7fa5a879 456 * @param sendData Pointer to the data to transfer to the FIFO.
mavix14 0:161f7fa5a879 457 * @param sendLen Number of bytes to transfer to the FIFO.
mavix14 0:161f7fa5a879 458 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
mavix14 0:161f7fa5a879 459 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
mavix14 0:161f7fa5a879 460 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
mavix14 0:161f7fa5a879 461 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
mavix14 0:161f7fa5a879 462 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
mavix14 0:161f7fa5a879 463 *
mavix14 0:161f7fa5a879 464 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 465 */
mavix14 0:161f7fa5a879 466 uint8_t PCD_CommunicateWithPICC(uint8_t command,
mavix14 0:161f7fa5a879 467 uint8_t waitIRq,
mavix14 0:161f7fa5a879 468 uint8_t *sendData,
mavix14 0:161f7fa5a879 469 uint8_t sendLen,
mavix14 0:161f7fa5a879 470 uint8_t *backData = NULL,
mavix14 0:161f7fa5a879 471 uint8_t *backLen = NULL,
mavix14 0:161f7fa5a879 472 uint8_t *validBits = NULL,
mavix14 0:161f7fa5a879 473 uint8_t rxAlign = 0,
mavix14 0:161f7fa5a879 474 bool checkCRC = false);
mavix14 0:161f7fa5a879 475
mavix14 0:161f7fa5a879 476 /**
mavix14 0:161f7fa5a879 477 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
mavix14 0:161f7fa5a879 478 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mavix14 0:161f7fa5a879 479 *
mavix14 0:161f7fa5a879 480 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mavix14 0:161f7fa5a879 481 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mavix14 0:161f7fa5a879 482 *
mavix14 0:161f7fa5a879 483 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 484 */
mavix14 0:161f7fa5a879 485 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
mavix14 0:161f7fa5a879 486
mavix14 0:161f7fa5a879 487 /**
mavix14 0:161f7fa5a879 488 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
mavix14 0:161f7fa5a879 489 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mavix14 0:161f7fa5a879 490 *
mavix14 0:161f7fa5a879 491 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mavix14 0:161f7fa5a879 492 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mavix14 0:161f7fa5a879 493 *
mavix14 0:161f7fa5a879 494 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 495 */
mavix14 0:161f7fa5a879 496 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
mavix14 0:161f7fa5a879 497
mavix14 0:161f7fa5a879 498 /**
mavix14 0:161f7fa5a879 499 * Transmits REQA or WUPA commands.
mavix14 0:161f7fa5a879 500 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mavix14 0:161f7fa5a879 501 *
mavix14 0:161f7fa5a879 502 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
mavix14 0:161f7fa5a879 503 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mavix14 0:161f7fa5a879 504 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mavix14 0:161f7fa5a879 505 *
mavix14 0:161f7fa5a879 506 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 507 */
mavix14 0:161f7fa5a879 508 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
mavix14 0:161f7fa5a879 509
mavix14 0:161f7fa5a879 510 /**
mavix14 0:161f7fa5a879 511 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
mavix14 0:161f7fa5a879 512 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
mavix14 0:161f7fa5a879 513 * On success:
mavix14 0:161f7fa5a879 514 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
mavix14 0:161f7fa5a879 515 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
mavix14 0:161f7fa5a879 516 *
mavix14 0:161f7fa5a879 517 * A PICC UID consists of 4, 7 or 10 bytes.
mavix14 0:161f7fa5a879 518 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
mavix14 0:161f7fa5a879 519 *
mavix14 0:161f7fa5a879 520 * UID size Number of UID bytes Cascade levels Example of PICC
mavix14 0:161f7fa5a879 521 * ======== =================== ============== ===============
mavix14 0:161f7fa5a879 522 * single 4 1 MIFARE Classic
mavix14 0:161f7fa5a879 523 * double 7 2 MIFARE Ultralight
mavix14 0:161f7fa5a879 524 * triple 10 3 Not currently in use?
mavix14 0:161f7fa5a879 525 *
mavix14 0:161f7fa5a879 526 *
mavix14 0:161f7fa5a879 527 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
mavix14 0:161f7fa5a879 528 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
mavix14 0:161f7fa5a879 529 *
mavix14 0:161f7fa5a879 530 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 531 */
mavix14 0:161f7fa5a879 532 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
mavix14 0:161f7fa5a879 533
mavix14 0:161f7fa5a879 534 /**
mavix14 0:161f7fa5a879 535 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
mavix14 0:161f7fa5a879 536 *
mavix14 0:161f7fa5a879 537 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 538 */
mavix14 0:161f7fa5a879 539 uint8_t PICC_HaltA (void);
mavix14 0:161f7fa5a879 540
mavix14 0:161f7fa5a879 541 // ************************************************************************************
mavix14 0:161f7fa5a879 542 //@}
mavix14 0:161f7fa5a879 543
mavix14 0:161f7fa5a879 544
mavix14 0:161f7fa5a879 545 // ************************************************************************************
mavix14 0:161f7fa5a879 546 //! @name Functions for communicating with MIFARE PICCs
mavix14 0:161f7fa5a879 547 // ************************************************************************************
mavix14 0:161f7fa5a879 548 //@{
mavix14 0:161f7fa5a879 549
mavix14 0:161f7fa5a879 550 /**
mavix14 0:161f7fa5a879 551 * Executes the MFRC522 MFAuthent command.
mavix14 0:161f7fa5a879 552 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
mavix14 0:161f7fa5a879 553 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
mavix14 0:161f7fa5a879 554 * For use with MIFARE Classic PICCs.
mavix14 0:161f7fa5a879 555 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
mavix14 0:161f7fa5a879 556 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
mavix14 0:161f7fa5a879 557 *
mavix14 0:161f7fa5a879 558 * All keys are set to FFFFFFFFFFFFh at chip delivery.
mavix14 0:161f7fa5a879 559 *
mavix14 0:161f7fa5a879 560 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
mavix14 0:161f7fa5a879 561 * @param blockAddr The block number. See numbering in the comments in the .h file.
mavix14 0:161f7fa5a879 562 * @param key Pointer to the Crypteo1 key to use (6 bytes)
mavix14 0:161f7fa5a879 563 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
mavix14 0:161f7fa5a879 564 *
mavix14 0:161f7fa5a879 565 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
mavix14 0:161f7fa5a879 566 */
mavix14 0:161f7fa5a879 567 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
mavix14 0:161f7fa5a879 568
mavix14 0:161f7fa5a879 569 /**
mavix14 0:161f7fa5a879 570 * Used to exit the PCD from its authenticated state.
mavix14 0:161f7fa5a879 571 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
mavix14 0:161f7fa5a879 572 */
mavix14 0:161f7fa5a879 573 void PCD_StopCrypto1 (void);
mavix14 0:161f7fa5a879 574
mavix14 0:161f7fa5a879 575 /**
mavix14 0:161f7fa5a879 576 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
mavix14 0:161f7fa5a879 577 *
mavix14 0:161f7fa5a879 578 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
mavix14 0:161f7fa5a879 579 *
mavix14 0:161f7fa5a879 580 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
mavix14 0:161f7fa5a879 581 * The MF0ICU1 returns a NAK for higher addresses.
mavix14 0:161f7fa5a879 582 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
mavix14 0:161f7fa5a879 583 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
mavix14 0:161f7fa5a879 584 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
mavix14 0:161f7fa5a879 585 *
mavix14 0:161f7fa5a879 586 * The buffer must be at least 18 bytes because a CRC_A is also returned.
mavix14 0:161f7fa5a879 587 * Checks the CRC_A before returning STATUS_OK.
mavix14 0:161f7fa5a879 588 *
mavix14 0:161f7fa5a879 589 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
mavix14 0:161f7fa5a879 590 * @param buffer The buffer to store the data in
mavix14 0:161f7fa5a879 591 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
mavix14 0:161f7fa5a879 592 *
mavix14 0:161f7fa5a879 593 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 594 */
mavix14 0:161f7fa5a879 595 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
mavix14 0:161f7fa5a879 596
mavix14 0:161f7fa5a879 597 /**
mavix14 0:161f7fa5a879 598 * Writes 16 bytes to the active PICC.
mavix14 0:161f7fa5a879 599 *
mavix14 0:161f7fa5a879 600 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
mavix14 0:161f7fa5a879 601 *
mavix14 0:161f7fa5a879 602 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
mavix14 0:161f7fa5a879 603 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
mavix14 0:161f7fa5a879 604 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
mavix14 0:161f7fa5a879 605 *
mavix14 0:161f7fa5a879 606 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
mavix14 0:161f7fa5a879 607 * @param buffer The 16 bytes to write to the PICC
mavix14 0:161f7fa5a879 608 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
mavix14 0:161f7fa5a879 609 *
mavix14 0:161f7fa5a879 610 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 611 */
mavix14 0:161f7fa5a879 612 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
mavix14 0:161f7fa5a879 613
mavix14 0:161f7fa5a879 614 /**
mavix14 0:161f7fa5a879 615 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
mavix14 0:161f7fa5a879 616 *
mavix14 0:161f7fa5a879 617 * @param page The page (2-15) to write to.
mavix14 0:161f7fa5a879 618 * @param buffer The 4 bytes to write to the PICC
mavix14 0:161f7fa5a879 619 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
mavix14 0:161f7fa5a879 620 *
mavix14 0:161f7fa5a879 621 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 622 */
mavix14 0:161f7fa5a879 623 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
mavix14 0:161f7fa5a879 624
mavix14 0:161f7fa5a879 625 /**
mavix14 0:161f7fa5a879 626 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
mavix14 0:161f7fa5a879 627 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mavix14 0:161f7fa5a879 628 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mavix14 0:161f7fa5a879 629 * Use MIFARE_Transfer() to store the result in a block.
mavix14 0:161f7fa5a879 630 *
mavix14 0:161f7fa5a879 631 * @param blockAddr The block (0-0xff) number.
mavix14 0:161f7fa5a879 632 * @param delta This number is subtracted from the value of block blockAddr.
mavix14 0:161f7fa5a879 633 *
mavix14 0:161f7fa5a879 634 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 635 */
mavix14 0:161f7fa5a879 636 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
mavix14 0:161f7fa5a879 637
mavix14 0:161f7fa5a879 638 /**
mavix14 0:161f7fa5a879 639 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
mavix14 0:161f7fa5a879 640 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mavix14 0:161f7fa5a879 641 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mavix14 0:161f7fa5a879 642 * Use MIFARE_Transfer() to store the result in a block.
mavix14 0:161f7fa5a879 643 *
mavix14 0:161f7fa5a879 644 * @param blockAddr The block (0-0xff) number.
mavix14 0:161f7fa5a879 645 * @param delta This number is added to the value of block blockAddr.
mavix14 0:161f7fa5a879 646 *
mavix14 0:161f7fa5a879 647 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 648 */
mavix14 0:161f7fa5a879 649 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
mavix14 0:161f7fa5a879 650
mavix14 0:161f7fa5a879 651 /**
mavix14 0:161f7fa5a879 652 * MIFARE Restore copies the value of the addressed block into a volatile memory.
mavix14 0:161f7fa5a879 653 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mavix14 0:161f7fa5a879 654 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mavix14 0:161f7fa5a879 655 * Use MIFARE_Transfer() to store the result in a block.
mavix14 0:161f7fa5a879 656 *
mavix14 0:161f7fa5a879 657 * @param blockAddr The block (0-0xff) number.
mavix14 0:161f7fa5a879 658 *
mavix14 0:161f7fa5a879 659 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 660 */
mavix14 0:161f7fa5a879 661 uint8_t MIFARE_Restore (uint8_t blockAddr);
mavix14 0:161f7fa5a879 662
mavix14 0:161f7fa5a879 663 /**
mavix14 0:161f7fa5a879 664 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
mavix14 0:161f7fa5a879 665 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mavix14 0:161f7fa5a879 666 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mavix14 0:161f7fa5a879 667 *
mavix14 0:161f7fa5a879 668 * @param blockAddr The block (0-0xff) number.
mavix14 0:161f7fa5a879 669 *
mavix14 0:161f7fa5a879 670 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 671 */
mavix14 0:161f7fa5a879 672 uint8_t MIFARE_Transfer (uint8_t blockAddr);
mavix14 0:161f7fa5a879 673
mavix14 0:161f7fa5a879 674 // ************************************************************************************
mavix14 0:161f7fa5a879 675 //@}
mavix14 0:161f7fa5a879 676
mavix14 0:161f7fa5a879 677
mavix14 0:161f7fa5a879 678 // ************************************************************************************
mavix14 0:161f7fa5a879 679 //! @name Support functions
mavix14 0:161f7fa5a879 680 // ************************************************************************************
mavix14 0:161f7fa5a879 681 //@{
mavix14 0:161f7fa5a879 682
mavix14 0:161f7fa5a879 683 /**
mavix14 0:161f7fa5a879 684 * Wrapper for MIFARE protocol communication.
mavix14 0:161f7fa5a879 685 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
mavix14 0:161f7fa5a879 686 *
mavix14 0:161f7fa5a879 687 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
mavix14 0:161f7fa5a879 688 * @param sendLen Number of bytes in sendData.
mavix14 0:161f7fa5a879 689 * @param acceptTimeout True => A timeout is also success
mavix14 0:161f7fa5a879 690 *
mavix14 0:161f7fa5a879 691 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 692 */
mavix14 0:161f7fa5a879 693 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
mavix14 0:161f7fa5a879 694
mavix14 0:161f7fa5a879 695 /**
mavix14 0:161f7fa5a879 696 * Translates the SAK (Select Acknowledge) to a PICC type.
mavix14 0:161f7fa5a879 697 *
mavix14 0:161f7fa5a879 698 * @param sak The SAK byte returned from PICC_Select().
mavix14 0:161f7fa5a879 699 *
mavix14 0:161f7fa5a879 700 * @return PICC_Type
mavix14 0:161f7fa5a879 701 */
mavix14 0:161f7fa5a879 702 uint8_t PICC_GetType (uint8_t sak);
mavix14 0:161f7fa5a879 703
mavix14 0:161f7fa5a879 704 /**
mavix14 0:161f7fa5a879 705 * Returns a string pointer to the PICC type name.
mavix14 0:161f7fa5a879 706 *
mavix14 0:161f7fa5a879 707 * @param type One of the PICC_Type enums.
mavix14 0:161f7fa5a879 708 *
mavix14 0:161f7fa5a879 709 * @return A string pointer to the PICC type name.
mavix14 0:161f7fa5a879 710 */
mavix14 0:161f7fa5a879 711 char* PICC_GetTypeName (uint8_t type);
mavix14 0:161f7fa5a879 712
mavix14 0:161f7fa5a879 713 /**
mavix14 0:161f7fa5a879 714 * Returns a string pointer to a status code name.
mavix14 0:161f7fa5a879 715 *
mavix14 0:161f7fa5a879 716 * @param code One of the StatusCode enums.
mavix14 0:161f7fa5a879 717 *
mavix14 0:161f7fa5a879 718 * @return A string pointer to a status code name.
mavix14 0:161f7fa5a879 719 */
mavix14 0:161f7fa5a879 720 char* GetStatusCodeName (uint8_t code);
mavix14 0:161f7fa5a879 721
mavix14 0:161f7fa5a879 722 /**
mavix14 0:161f7fa5a879 723 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
mavix14 0:161f7fa5a879 724 *
mavix14 0:161f7fa5a879 725 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
mavix14 0:161f7fa5a879 726 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
mavix14 0:161f7fa5a879 727 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
mavix14 0:161f7fa5a879 728 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
mavix14 0:161f7fa5a879 729 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
mavix14 0:161f7fa5a879 730 */
mavix14 0:161f7fa5a879 731 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
mavix14 0:161f7fa5a879 732 uint8_t g0,
mavix14 0:161f7fa5a879 733 uint8_t g1,
mavix14 0:161f7fa5a879 734 uint8_t g2,
mavix14 0:161f7fa5a879 735 uint8_t g3);
mavix14 0:161f7fa5a879 736
mavix14 0:161f7fa5a879 737 // ************************************************************************************
mavix14 0:161f7fa5a879 738 //@}
mavix14 0:161f7fa5a879 739
mavix14 0:161f7fa5a879 740
mavix14 0:161f7fa5a879 741 // ************************************************************************************
mavix14 0:161f7fa5a879 742 //! @name Convenience functions - does not add extra functionality
mavix14 0:161f7fa5a879 743 // ************************************************************************************
mavix14 0:161f7fa5a879 744 //@{
mavix14 0:161f7fa5a879 745
mavix14 0:161f7fa5a879 746 /**
mavix14 0:161f7fa5a879 747 * Returns true if a PICC responds to PICC_CMD_REQA.
mavix14 0:161f7fa5a879 748 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
mavix14 0:161f7fa5a879 749 *
mavix14 0:161f7fa5a879 750 * @return bool
mavix14 0:161f7fa5a879 751 */
mavix14 0:161f7fa5a879 752 bool PICC_IsNewCardPresent(void);
mavix14 0:161f7fa5a879 753
mavix14 0:161f7fa5a879 754 /**
mavix14 0:161f7fa5a879 755 * Simple wrapper around PICC_Select.
mavix14 0:161f7fa5a879 756 * Returns true if a UID could be read.
mavix14 0:161f7fa5a879 757 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
mavix14 0:161f7fa5a879 758 * The read UID is available in the class variable uid.
mavix14 0:161f7fa5a879 759 *
mavix14 0:161f7fa5a879 760 * @return bool
mavix14 0:161f7fa5a879 761 */
mavix14 0:161f7fa5a879 762 bool PICC_ReadCardSerial (void);
mavix14 0:161f7fa5a879 763
mavix14 0:161f7fa5a879 764 // ************************************************************************************
mavix14 0:161f7fa5a879 765 //@}
mavix14 0:161f7fa5a879 766
mavix14 0:161f7fa5a879 767
mavix14 0:161f7fa5a879 768 private:
mavix14 0:161f7fa5a879 769 SPI m_SPI;
mavix14 0:161f7fa5a879 770 DigitalOut m_CS;
mavix14 0:161f7fa5a879 771 DigitalOut m_RESET;
mavix14 0:161f7fa5a879 772
mavix14 0:161f7fa5a879 773 /**
mavix14 0:161f7fa5a879 774 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
mavix14 0:161f7fa5a879 775 *
mavix14 0:161f7fa5a879 776 * @param command The command to use
mavix14 0:161f7fa5a879 777 * @param blockAddr The block (0-0xff) number.
mavix14 0:161f7fa5a879 778 * @param data The data to transfer in step 2
mavix14 0:161f7fa5a879 779 *
mavix14 0:161f7fa5a879 780 * @return STATUS_OK on success, STATUS_??? otherwise.
mavix14 0:161f7fa5a879 781 */
mavix14 0:161f7fa5a879 782 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
mavix14 0:161f7fa5a879 783 };
mavix14 0:161f7fa5a879 784
mavix14 0:161f7fa5a879 785 #endif