Brahim KHARRAB / Mbed 2 deprecated test_rc522

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Dependencies:   mbed

MFRC522.cpp@0:161f7fa5a879, 2017-02-03 (annotated)

Committer:
mavix14
Date:
Fri Feb 03 14:38:55 2017 +0000
Revision:
0:161f7fa5a879
rrr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mavix14 0:161f7fa5a879 1 /*
mavix14 0:161f7fa5a879 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
mavix14 0:161f7fa5a879 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
mavix14 0:161f7fa5a879 4 * Released into the public domain.
mavix14 0:161f7fa5a879 5 */
mavix14 0:161f7fa5a879 6
mavix14 0:161f7fa5a879 7 #include "MFRC522.h"
mavix14 0:161f7fa5a879 8
mavix14 0:161f7fa5a879 9 static const char* const _TypeNamePICC[] =
mavix14 0:161f7fa5a879 10 {
mavix14 0:161f7fa5a879 11 "Unknown type",
mavix14 0:161f7fa5a879 12 "PICC compliant with ISO/IEC 14443-4",
mavix14 0:161f7fa5a879 13 "PICC compliant with ISO/IEC 18092 (NFC)",
mavix14 0:161f7fa5a879 14 "MIFARE Mini, 320 bytes",
mavix14 0:161f7fa5a879 15 "MIFARE 1KB",
mavix14 0:161f7fa5a879 16 "MIFARE 4KB",
mavix14 0:161f7fa5a879 17 "MIFARE Ultralight or Ultralight C",
mavix14 0:161f7fa5a879 18 "MIFARE Plus",
mavix14 0:161f7fa5a879 19 "MIFARE TNP3XXX",
mavix14 0:161f7fa5a879 20
mavix14 0:161f7fa5a879 21 /* not complete UID */
mavix14 0:161f7fa5a879 22 "SAK indicates UID is not complete"
mavix14 0:161f7fa5a879 23 };
mavix14 0:161f7fa5a879 24
mavix14 0:161f7fa5a879 25 static const char* const _ErrorMessage[] =
mavix14 0:161f7fa5a879 26 {
mavix14 0:161f7fa5a879 27 "Unknown error",
mavix14 0:161f7fa5a879 28 "Success",
mavix14 0:161f7fa5a879 29 "Error in communication",
mavix14 0:161f7fa5a879 30 "Collision detected",
mavix14 0:161f7fa5a879 31 "Timeout in communication",
mavix14 0:161f7fa5a879 32 "A buffer is not big enough",
mavix14 0:161f7fa5a879 33 "Internal error in the code, should not happen",
mavix14 0:161f7fa5a879 34 "Invalid argument",
mavix14 0:161f7fa5a879 35 "The CRC_A does not match",
mavix14 0:161f7fa5a879 36 "A MIFARE PICC responded with NAK"
mavix14 0:161f7fa5a879 37 };
mavix14 0:161f7fa5a879 38
mavix14 0:161f7fa5a879 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
mavix14 0:161f7fa5a879 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
mavix14 0:161f7fa5a879 41
mavix14 0:161f7fa5a879 42 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 43 // Functions for setting up the driver
mavix14 0:161f7fa5a879 44 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 45
mavix14 0:161f7fa5a879 46 /**
mavix14 0:161f7fa5a879 47 * Constructor.
mavix14 0:161f7fa5a879 48 * Prepares the output pins.
mavix14 0:161f7fa5a879 49 */
mavix14 0:161f7fa5a879 50 MFRC522::MFRC522(PinName mosi,
mavix14 0:161f7fa5a879 51 PinName miso,
mavix14 0:161f7fa5a879 52 PinName sclk,
mavix14 0:161f7fa5a879 53 PinName cs,
mavix14 0:161f7fa5a879 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
mavix14 0:161f7fa5a879 55 {
mavix14 0:161f7fa5a879 56 /* Configure SPI bus */
mavix14 0:161f7fa5a879 57 m_SPI.format(8, 0);
mavix14 0:161f7fa5a879 58 m_SPI.frequency(8000000);
mavix14 0:161f7fa5a879 59
mavix14 0:161f7fa5a879 60 /* Release SPI-CS pin */
mavix14 0:161f7fa5a879 61 m_CS = 1;
mavix14 0:161f7fa5a879 62
mavix14 0:161f7fa5a879 63 /* Release RESET pin */
mavix14 0:161f7fa5a879 64 m_RESET = 1;
mavix14 0:161f7fa5a879 65 } // End constructor
mavix14 0:161f7fa5a879 66
mavix14 0:161f7fa5a879 67
mavix14 0:161f7fa5a879 68 /**
mavix14 0:161f7fa5a879 69 * Destructor.
mavix14 0:161f7fa5a879 70 */
mavix14 0:161f7fa5a879 71 MFRC522::~MFRC522()
mavix14 0:161f7fa5a879 72 {
mavix14 0:161f7fa5a879 73
mavix14 0:161f7fa5a879 74 }
mavix14 0:161f7fa5a879 75
mavix14 0:161f7fa5a879 76
mavix14 0:161f7fa5a879 77 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 78 // Basic interface functions for communicating with the MFRC522
mavix14 0:161f7fa5a879 79 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 80
mavix14 0:161f7fa5a879 81 /**
mavix14 0:161f7fa5a879 82 * Writes a byte to the specified register in the MFRC522 chip.
mavix14 0:161f7fa5a879 83 * The interface is described in the datasheet section 8.1.2.
mavix14 0:161f7fa5a879 84 */
mavix14 0:161f7fa5a879 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
mavix14 0:161f7fa5a879 86 {
mavix14 0:161f7fa5a879 87 m_CS = 0; /* Select SPI Chip MFRC522 */
mavix14 0:161f7fa5a879 88
mavix14 0:161f7fa5a879 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
mavix14 0:161f7fa5a879 90 (void) m_SPI.write(reg & 0x7E);
mavix14 0:161f7fa5a879 91 (void) m_SPI.write(value);
mavix14 0:161f7fa5a879 92
mavix14 0:161f7fa5a879 93 m_CS = 1; /* Release SPI Chip MFRC522 */
mavix14 0:161f7fa5a879 94 } // End PCD_WriteRegister()
mavix14 0:161f7fa5a879 95
mavix14 0:161f7fa5a879 96 /**
mavix14 0:161f7fa5a879 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
mavix14 0:161f7fa5a879 98 * The interface is described in the datasheet section 8.1.2.
mavix14 0:161f7fa5a879 99 */
mavix14 0:161f7fa5a879 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
mavix14 0:161f7fa5a879 101 {
mavix14 0:161f7fa5a879 102 m_CS = 0; /* Select SPI Chip MFRC522 */
mavix14 0:161f7fa5a879 103
mavix14 0:161f7fa5a879 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
mavix14 0:161f7fa5a879 105 (void) m_SPI.write(reg & 0x7E);
mavix14 0:161f7fa5a879 106 for (uint8_t index = 0; index < count; index++)
mavix14 0:161f7fa5a879 107 {
mavix14 0:161f7fa5a879 108 (void) m_SPI.write(values[index]);
mavix14 0:161f7fa5a879 109 }
mavix14 0:161f7fa5a879 110
mavix14 0:161f7fa5a879 111 m_CS = 1; /* Release SPI Chip MFRC522 */
mavix14 0:161f7fa5a879 112 } // End PCD_WriteRegister()
mavix14 0:161f7fa5a879 113
mavix14 0:161f7fa5a879 114 /**
mavix14 0:161f7fa5a879 115 * Reads a byte from the specified register in the MFRC522 chip.
mavix14 0:161f7fa5a879 116 * The interface is described in the datasheet section 8.1.2.
mavix14 0:161f7fa5a879 117 */
mavix14 0:161f7fa5a879 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
mavix14 0:161f7fa5a879 119 {
mavix14 0:161f7fa5a879 120 uint8_t value;
mavix14 0:161f7fa5a879 121 m_CS = 0; /* Select SPI Chip MFRC522 */
mavix14 0:161f7fa5a879 122
mavix14 0:161f7fa5a879 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
mavix14 0:161f7fa5a879 124 (void) m_SPI.write(0x80 | reg);
mavix14 0:161f7fa5a879 125
mavix14 0:161f7fa5a879 126 // Read the value back. Send 0 to stop reading.
mavix14 0:161f7fa5a879 127 value = m_SPI.write(0);
mavix14 0:161f7fa5a879 128
mavix14 0:161f7fa5a879 129 m_CS = 1; /* Release SPI Chip MFRC522 */
mavix14 0:161f7fa5a879 130
mavix14 0:161f7fa5a879 131 return value;
mavix14 0:161f7fa5a879 132 } // End PCD_ReadRegister()
mavix14 0:161f7fa5a879 133
mavix14 0:161f7fa5a879 134 /**
mavix14 0:161f7fa5a879 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
mavix14 0:161f7fa5a879 136 * The interface is described in the datasheet section 8.1.2.
mavix14 0:161f7fa5a879 137 */
mavix14 0:161f7fa5a879 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
mavix14 0:161f7fa5a879 139 {
mavix14 0:161f7fa5a879 140 if (count == 0) { return; }
mavix14 0:161f7fa5a879 141
mavix14 0:161f7fa5a879 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
mavix14 0:161f7fa5a879 143 uint8_t index = 0; // Index in values array.
mavix14 0:161f7fa5a879 144
mavix14 0:161f7fa5a879 145 m_CS = 0; /* Select SPI Chip MFRC522 */
mavix14 0:161f7fa5a879 146 count--; // One read is performed outside of the loop
mavix14 0:161f7fa5a879 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
mavix14 0:161f7fa5a879 148
mavix14 0:161f7fa5a879 149 while (index < count)
mavix14 0:161f7fa5a879 150 {
mavix14 0:161f7fa5a879 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
mavix14 0:161f7fa5a879 152 {
mavix14 0:161f7fa5a879 153 // Create bit mask for bit positions rxAlign..7
mavix14 0:161f7fa5a879 154 uint8_t mask = 0;
mavix14 0:161f7fa5a879 155 for (uint8_t i = rxAlign; i <= 7; i++)
mavix14 0:161f7fa5a879 156 {
mavix14 0:161f7fa5a879 157 mask |= (1 << i);
mavix14 0:161f7fa5a879 158 }
mavix14 0:161f7fa5a879 159
mavix14 0:161f7fa5a879 160 // Read value and tell that we want to read the same address again.
mavix14 0:161f7fa5a879 161 uint8_t value = m_SPI.write(address);
mavix14 0:161f7fa5a879 162
mavix14 0:161f7fa5a879 163 // Apply mask to both current value of values[0] and the new data in value.
mavix14 0:161f7fa5a879 164 values[0] = (values[index] & ~mask) | (value & mask);
mavix14 0:161f7fa5a879 165 }
mavix14 0:161f7fa5a879 166 else
mavix14 0:161f7fa5a879 167 {
mavix14 0:161f7fa5a879 168 // Read value and tell that we want to read the same address again.
mavix14 0:161f7fa5a879 169 values[index] = m_SPI.write(address);
mavix14 0:161f7fa5a879 170 }
mavix14 0:161f7fa5a879 171
mavix14 0:161f7fa5a879 172 index++;
mavix14 0:161f7fa5a879 173 }
mavix14 0:161f7fa5a879 174
mavix14 0:161f7fa5a879 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
mavix14 0:161f7fa5a879 176
mavix14 0:161f7fa5a879 177 m_CS = 1; /* Release SPI Chip MFRC522 */
mavix14 0:161f7fa5a879 178 } // End PCD_ReadRegister()
mavix14 0:161f7fa5a879 179
mavix14 0:161f7fa5a879 180 /**
mavix14 0:161f7fa5a879 181 * Sets the bits given in mask in register reg.
mavix14 0:161f7fa5a879 182 */
mavix14 0:161f7fa5a879 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
mavix14 0:161f7fa5a879 184 {
mavix14 0:161f7fa5a879 185 uint8_t tmp = PCD_ReadRegister(reg);
mavix14 0:161f7fa5a879 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
mavix14 0:161f7fa5a879 187 } // End PCD_SetRegisterBitMask()
mavix14 0:161f7fa5a879 188
mavix14 0:161f7fa5a879 189 /**
mavix14 0:161f7fa5a879 190 * Clears the bits given in mask from register reg.
mavix14 0:161f7fa5a879 191 */
mavix14 0:161f7fa5a879 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
mavix14 0:161f7fa5a879 193 {
mavix14 0:161f7fa5a879 194 uint8_t tmp = PCD_ReadRegister(reg);
mavix14 0:161f7fa5a879 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
mavix14 0:161f7fa5a879 196 } // End PCD_ClearRegisterBitMask()
mavix14 0:161f7fa5a879 197
mavix14 0:161f7fa5a879 198
mavix14 0:161f7fa5a879 199 /**
mavix14 0:161f7fa5a879 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
mavix14 0:161f7fa5a879 201 */
mavix14 0:161f7fa5a879 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
mavix14 0:161f7fa5a879 203 {
mavix14 0:161f7fa5a879 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
mavix14 0:161f7fa5a879 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
mavix14 0:161f7fa5a879 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
mavix14 0:161f7fa5a879 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
mavix14 0:161f7fa5a879 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
mavix14 0:161f7fa5a879 209
mavix14 0:161f7fa5a879 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
mavix14 0:161f7fa5a879 211 uint16_t i = 5000;
mavix14 0:161f7fa5a879 212 uint8_t n;
mavix14 0:161f7fa5a879 213 while (1)
mavix14 0:161f7fa5a879 214 {
mavix14 0:161f7fa5a879 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
mavix14 0:161f7fa5a879 216 if (n & 0x04)
mavix14 0:161f7fa5a879 217 {
mavix14 0:161f7fa5a879 218 // CRCIRq bit set - calculation done
mavix14 0:161f7fa5a879 219 break;
mavix14 0:161f7fa5a879 220 }
mavix14 0:161f7fa5a879 221
mavix14 0:161f7fa5a879 222 if (--i == 0)
mavix14 0:161f7fa5a879 223 {
mavix14 0:161f7fa5a879 224 // The emergency break. We will eventually terminate on this one after 89ms.
mavix14 0:161f7fa5a879 225 // Communication with the MFRC522 might be down.
mavix14 0:161f7fa5a879 226 return STATUS_TIMEOUT;
mavix14 0:161f7fa5a879 227 }
mavix14 0:161f7fa5a879 228 }
mavix14 0:161f7fa5a879 229
mavix14 0:161f7fa5a879 230 // Stop calculating CRC for new content in the FIFO.
mavix14 0:161f7fa5a879 231 PCD_WriteRegister(CommandReg, PCD_Idle);
mavix14 0:161f7fa5a879 232
mavix14 0:161f7fa5a879 233 // Transfer the result from the registers to the result buffer
mavix14 0:161f7fa5a879 234 result[0] = PCD_ReadRegister(CRCResultRegL);
mavix14 0:161f7fa5a879 235 result[1] = PCD_ReadRegister(CRCResultRegH);
mavix14 0:161f7fa5a879 236 return STATUS_OK;
mavix14 0:161f7fa5a879 237 } // End PCD_CalculateCRC()
mavix14 0:161f7fa5a879 238
mavix14 0:161f7fa5a879 239
mavix14 0:161f7fa5a879 240 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 241 // Functions for manipulating the MFRC522
mavix14 0:161f7fa5a879 242 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 243
mavix14 0:161f7fa5a879 244 /**
mavix14 0:161f7fa5a879 245 * Initializes the MFRC522 chip.
mavix14 0:161f7fa5a879 246 */
mavix14 0:161f7fa5a879 247 void MFRC522::PCD_Init()
mavix14 0:161f7fa5a879 248 {
mavix14 0:161f7fa5a879 249 /* Reset MFRC522 */
mavix14 0:161f7fa5a879 250 m_RESET = 0;
mavix14 0:161f7fa5a879 251 wait_ms(10);
mavix14 0:161f7fa5a879 252 m_RESET = 1;
mavix14 0:161f7fa5a879 253
mavix14 0:161f7fa5a879 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
mavix14 0:161f7fa5a879 255 wait_ms(50);
mavix14 0:161f7fa5a879 256
mavix14 0:161f7fa5a879 257 // When communicating with a PICC we need a timeout if something goes wrong.
mavix14 0:161f7fa5a879 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
mavix14 0:161f7fa5a879 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
mavix14 0:161f7fa5a879 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
mavix14 0:161f7fa5a879 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
mavix14 0:161f7fa5a879 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
mavix14 0:161f7fa5a879 263 PCD_WriteRegister(TReloadRegL, 0xE8);
mavix14 0:161f7fa5a879 264
mavix14 0:161f7fa5a879 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
mavix14 0:161f7fa5a879 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
mavix14 0:161f7fa5a879 267
mavix14 0:161f7fa5a879 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
mavix14 0:161f7fa5a879 269
mavix14 0:161f7fa5a879 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
mavix14 0:161f7fa5a879 271 } // End PCD_Init()
mavix14 0:161f7fa5a879 272
mavix14 0:161f7fa5a879 273 /**
mavix14 0:161f7fa5a879 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
mavix14 0:161f7fa5a879 275 */
mavix14 0:161f7fa5a879 276 void MFRC522::PCD_Reset()
mavix14 0:161f7fa5a879 277 {
mavix14 0:161f7fa5a879 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
mavix14 0:161f7fa5a879 279 // The datasheet does not mention how long the SoftRest command takes to complete.
mavix14 0:161f7fa5a879 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
mavix14 0:161f7fa5a879 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
mavix14 0:161f7fa5a879 282 wait_ms(50);
mavix14 0:161f7fa5a879 283
mavix14 0:161f7fa5a879 284 // Wait for the PowerDown bit in CommandReg to be cleared
mavix14 0:161f7fa5a879 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
mavix14 0:161f7fa5a879 286 {
mavix14 0:161f7fa5a879 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
mavix14 0:161f7fa5a879 288 }
mavix14 0:161f7fa5a879 289 } // End PCD_Reset()
mavix14 0:161f7fa5a879 290
mavix14 0:161f7fa5a879 291 /**
mavix14 0:161f7fa5a879 292 * Turns the antenna on by enabling pins TX1 and TX2.
mavix14 0:161f7fa5a879 293 * After a reset these pins disabled.
mavix14 0:161f7fa5a879 294 */
mavix14 0:161f7fa5a879 295 void MFRC522::PCD_AntennaOn()
mavix14 0:161f7fa5a879 296 {
mavix14 0:161f7fa5a879 297 uint8_t value = PCD_ReadRegister(TxControlReg);
mavix14 0:161f7fa5a879 298 if ((value & 0x03) != 0x03)
mavix14 0:161f7fa5a879 299 {
mavix14 0:161f7fa5a879 300 PCD_WriteRegister(TxControlReg, value | 0x03);
mavix14 0:161f7fa5a879 301 }
mavix14 0:161f7fa5a879 302 } // End PCD_AntennaOn()
mavix14 0:161f7fa5a879 303
mavix14 0:161f7fa5a879 304 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 305 // Functions for communicating with PICCs
mavix14 0:161f7fa5a879 306 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 307
mavix14 0:161f7fa5a879 308 /**
mavix14 0:161f7fa5a879 309 * Executes the Transceive command.
mavix14 0:161f7fa5a879 310 * CRC validation can only be done if backData and backLen are specified.
mavix14 0:161f7fa5a879 311 */
mavix14 0:161f7fa5a879 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
mavix14 0:161f7fa5a879 313 uint8_t sendLen,
mavix14 0:161f7fa5a879 314 uint8_t *backData,
mavix14 0:161f7fa5a879 315 uint8_t *backLen,
mavix14 0:161f7fa5a879 316 uint8_t *validBits,
mavix14 0:161f7fa5a879 317 uint8_t rxAlign,
mavix14 0:161f7fa5a879 318 bool checkCRC)
mavix14 0:161f7fa5a879 319 {
mavix14 0:161f7fa5a879 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
mavix14 0:161f7fa5a879 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
mavix14 0:161f7fa5a879 322 } // End PCD_TransceiveData()
mavix14 0:161f7fa5a879 323
mavix14 0:161f7fa5a879 324 /**
mavix14 0:161f7fa5a879 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
mavix14 0:161f7fa5a879 326 * CRC validation can only be done if backData and backLen are specified.
mavix14 0:161f7fa5a879 327 */
mavix14 0:161f7fa5a879 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
mavix14 0:161f7fa5a879 329 uint8_t waitIRq,
mavix14 0:161f7fa5a879 330 uint8_t *sendData,
mavix14 0:161f7fa5a879 331 uint8_t sendLen,
mavix14 0:161f7fa5a879 332 uint8_t *backData,
mavix14 0:161f7fa5a879 333 uint8_t *backLen,
mavix14 0:161f7fa5a879 334 uint8_t *validBits,
mavix14 0:161f7fa5a879 335 uint8_t rxAlign,
mavix14 0:161f7fa5a879 336 bool checkCRC)
mavix14 0:161f7fa5a879 337 {
mavix14 0:161f7fa5a879 338 uint8_t n, _validBits = 0;
mavix14 0:161f7fa5a879 339 uint32_t i;
mavix14 0:161f7fa5a879 340
mavix14 0:161f7fa5a879 341 // Prepare values for BitFramingReg
mavix14 0:161f7fa5a879 342 uint8_t txLastBits = validBits ? *validBits : 0;
mavix14 0:161f7fa5a879 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
mavix14 0:161f7fa5a879 344
mavix14 0:161f7fa5a879 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
mavix14 0:161f7fa5a879 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
mavix14 0:161f7fa5a879 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
mavix14 0:161f7fa5a879 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
mavix14 0:161f7fa5a879 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
mavix14 0:161f7fa5a879 350 PCD_WriteRegister(CommandReg, command); // Execute the command
mavix14 0:161f7fa5a879 351 if (command == PCD_Transceive)
mavix14 0:161f7fa5a879 352 {
mavix14 0:161f7fa5a879 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
mavix14 0:161f7fa5a879 354 }
mavix14 0:161f7fa5a879 355
mavix14 0:161f7fa5a879 356 // Wait for the command to complete.
mavix14 0:161f7fa5a879 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
mavix14 0:161f7fa5a879 358 // Each iteration of the do-while-loop takes 17.86us.
mavix14 0:161f7fa5a879 359 i = 2000;
mavix14 0:161f7fa5a879 360 while (1)
mavix14 0:161f7fa5a879 361 {
mavix14 0:161f7fa5a879 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
mavix14 0:161f7fa5a879 363 if (n & waitIRq)
mavix14 0:161f7fa5a879 364 { // One of the interrupts that signal success has been set.
mavix14 0:161f7fa5a879 365 break;
mavix14 0:161f7fa5a879 366 }
mavix14 0:161f7fa5a879 367
mavix14 0:161f7fa5a879 368 if (n & 0x01)
mavix14 0:161f7fa5a879 369 { // Timer interrupt - nothing received in 25ms
mavix14 0:161f7fa5a879 370 return STATUS_TIMEOUT;
mavix14 0:161f7fa5a879 371 }
mavix14 0:161f7fa5a879 372
mavix14 0:161f7fa5a879 373 if (--i == 0)
mavix14 0:161f7fa5a879 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
mavix14 0:161f7fa5a879 375 return STATUS_TIMEOUT;
mavix14 0:161f7fa5a879 376 }
mavix14 0:161f7fa5a879 377 }
mavix14 0:161f7fa5a879 378
mavix14 0:161f7fa5a879 379 // Stop now if any errors except collisions were detected.
mavix14 0:161f7fa5a879 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
mavix14 0:161f7fa5a879 381 if (errorRegValue & 0x13)
mavix14 0:161f7fa5a879 382 { // BufferOvfl ParityErr ProtocolErr
mavix14 0:161f7fa5a879 383 return STATUS_ERROR;
mavix14 0:161f7fa5a879 384 }
mavix14 0:161f7fa5a879 385
mavix14 0:161f7fa5a879 386 // If the caller wants data back, get it from the MFRC522.
mavix14 0:161f7fa5a879 387 if (backData && backLen)
mavix14 0:161f7fa5a879 388 {
mavix14 0:161f7fa5a879 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
mavix14 0:161f7fa5a879 390 if (n > *backLen)
mavix14 0:161f7fa5a879 391 {
mavix14 0:161f7fa5a879 392 return STATUS_NO_ROOM;
mavix14 0:161f7fa5a879 393 }
mavix14 0:161f7fa5a879 394
mavix14 0:161f7fa5a879 395 *backLen = n; // Number of bytes returned
mavix14 0:161f7fa5a879 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
mavix14 0:161f7fa5a879 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
mavix14 0:161f7fa5a879 398 if (validBits)
mavix14 0:161f7fa5a879 399 {
mavix14 0:161f7fa5a879 400 *validBits = _validBits;
mavix14 0:161f7fa5a879 401 }
mavix14 0:161f7fa5a879 402 }
mavix14 0:161f7fa5a879 403
mavix14 0:161f7fa5a879 404 // Tell about collisions
mavix14 0:161f7fa5a879 405 if (errorRegValue & 0x08)
mavix14 0:161f7fa5a879 406 { // CollErr
mavix14 0:161f7fa5a879 407 return STATUS_COLLISION;
mavix14 0:161f7fa5a879 408 }
mavix14 0:161f7fa5a879 409
mavix14 0:161f7fa5a879 410 // Perform CRC_A validation if requested.
mavix14 0:161f7fa5a879 411 if (backData && backLen && checkCRC)
mavix14 0:161f7fa5a879 412 {
mavix14 0:161f7fa5a879 413 // In this case a MIFARE Classic NAK is not OK.
mavix14 0:161f7fa5a879 414 if ((*backLen == 1) && (_validBits == 4))
mavix14 0:161f7fa5a879 415 {
mavix14 0:161f7fa5a879 416 return STATUS_MIFARE_NACK;
mavix14 0:161f7fa5a879 417 }
mavix14 0:161f7fa5a879 418
mavix14 0:161f7fa5a879 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
mavix14 0:161f7fa5a879 420 if ((*backLen < 2) || (_validBits != 0))
mavix14 0:161f7fa5a879 421 {
mavix14 0:161f7fa5a879 422 return STATUS_CRC_WRONG;
mavix14 0:161f7fa5a879 423 }
mavix14 0:161f7fa5a879 424
mavix14 0:161f7fa5a879 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
mavix14 0:161f7fa5a879 426 uint8_t controlBuffer[2];
mavix14 0:161f7fa5a879 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
mavix14 0:161f7fa5a879 428 if (n != STATUS_OK)
mavix14 0:161f7fa5a879 429 {
mavix14 0:161f7fa5a879 430 return n;
mavix14 0:161f7fa5a879 431 }
mavix14 0:161f7fa5a879 432
mavix14 0:161f7fa5a879 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
mavix14 0:161f7fa5a879 434 {
mavix14 0:161f7fa5a879 435 return STATUS_CRC_WRONG;
mavix14 0:161f7fa5a879 436 }
mavix14 0:161f7fa5a879 437 }
mavix14 0:161f7fa5a879 438
mavix14 0:161f7fa5a879 439 return STATUS_OK;
mavix14 0:161f7fa5a879 440 } // End PCD_CommunicateWithPICC()
mavix14 0:161f7fa5a879 441
mavix14 0:161f7fa5a879 442 /*
mavix14 0:161f7fa5a879 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
mavix14 0:161f7fa5a879 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mavix14 0:161f7fa5a879 445 */
mavix14 0:161f7fa5a879 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
mavix14 0:161f7fa5a879 447 {
mavix14 0:161f7fa5a879 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
mavix14 0:161f7fa5a879 449 } // End PICC_RequestA()
mavix14 0:161f7fa5a879 450
mavix14 0:161f7fa5a879 451 /**
mavix14 0:161f7fa5a879 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
mavix14 0:161f7fa5a879 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mavix14 0:161f7fa5a879 454 */
mavix14 0:161f7fa5a879 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
mavix14 0:161f7fa5a879 456 {
mavix14 0:161f7fa5a879 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
mavix14 0:161f7fa5a879 458 } // End PICC_WakeupA()
mavix14 0:161f7fa5a879 459
mavix14 0:161f7fa5a879 460 /*
mavix14 0:161f7fa5a879 461 * Transmits REQA or WUPA commands.
mavix14 0:161f7fa5a879 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mavix14 0:161f7fa5a879 463 */
mavix14 0:161f7fa5a879 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
mavix14 0:161f7fa5a879 465 {
mavix14 0:161f7fa5a879 466 uint8_t validBits;
mavix14 0:161f7fa5a879 467 uint8_t status;
mavix14 0:161f7fa5a879 468
mavix14 0:161f7fa5a879 469 if (bufferATQA == NULL || *bufferSize < 2)
mavix14 0:161f7fa5a879 470 { // The ATQA response is 2 bytes long.
mavix14 0:161f7fa5a879 471 return STATUS_NO_ROOM;
mavix14 0:161f7fa5a879 472 }
mavix14 0:161f7fa5a879 473
mavix14 0:161f7fa5a879 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
mavix14 0:161f7fa5a879 475 PCD_ClrRegisterBits(CollReg, 0x80);
mavix14 0:161f7fa5a879 476
mavix14 0:161f7fa5a879 477 // For REQA and WUPA we need the short frame format
mavix14 0:161f7fa5a879 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
mavix14 0:161f7fa5a879 479 validBits = 7;
mavix14 0:161f7fa5a879 480
mavix14 0:161f7fa5a879 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
mavix14 0:161f7fa5a879 482 if (status != STATUS_OK)
mavix14 0:161f7fa5a879 483 {
mavix14 0:161f7fa5a879 484 return status;
mavix14 0:161f7fa5a879 485 }
mavix14 0:161f7fa5a879 486
mavix14 0:161f7fa5a879 487 if ((*bufferSize != 2) || (validBits != 0))
mavix14 0:161f7fa5a879 488 { // ATQA must be exactly 16 bits.
mavix14 0:161f7fa5a879 489 return STATUS_ERROR;
mavix14 0:161f7fa5a879 490 }
mavix14 0:161f7fa5a879 491
mavix14 0:161f7fa5a879 492 return STATUS_OK;
mavix14 0:161f7fa5a879 493 } // End PICC_REQA_or_WUPA()
mavix14 0:161f7fa5a879 494
mavix14 0:161f7fa5a879 495 /*
mavix14 0:161f7fa5a879 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
mavix14 0:161f7fa5a879 497 */
mavix14 0:161f7fa5a879 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
mavix14 0:161f7fa5a879 499 {
mavix14 0:161f7fa5a879 500 bool uidComplete;
mavix14 0:161f7fa5a879 501 bool selectDone;
mavix14 0:161f7fa5a879 502 bool useCascadeTag;
mavix14 0:161f7fa5a879 503 uint8_t cascadeLevel = 1;
mavix14 0:161f7fa5a879 504 uint8_t result;
mavix14 0:161f7fa5a879 505 uint8_t count;
mavix14 0:161f7fa5a879 506 uint8_t index;
mavix14 0:161f7fa5a879 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
mavix14 0:161f7fa5a879 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
mavix14 0:161f7fa5a879 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
mavix14 0:161f7fa5a879 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
mavix14 0:161f7fa5a879 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
mavix14 0:161f7fa5a879 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
mavix14 0:161f7fa5a879 513 uint8_t *responseBuffer;
mavix14 0:161f7fa5a879 514 uint8_t responseLength;
mavix14 0:161f7fa5a879 515
mavix14 0:161f7fa5a879 516 // Description of buffer structure:
mavix14 0:161f7fa5a879 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
mavix14 0:161f7fa5a879 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
mavix14 0:161f7fa5a879 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
mavix14 0:161f7fa5a879 520 // Byte 3: UID-data
mavix14 0:161f7fa5a879 521 // Byte 4: UID-data
mavix14 0:161f7fa5a879 522 // Byte 5: UID-data
mavix14 0:161f7fa5a879 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
mavix14 0:161f7fa5a879 524 // Byte 7: CRC_A
mavix14 0:161f7fa5a879 525 // Byte 8: CRC_A
mavix14 0:161f7fa5a879 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
mavix14 0:161f7fa5a879 527 //
mavix14 0:161f7fa5a879 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
mavix14 0:161f7fa5a879 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
mavix14 0:161f7fa5a879 530 // ======== ============= ===== ===== ===== =====
mavix14 0:161f7fa5a879 531 // 4 bytes 1 uid0 uid1 uid2 uid3
mavix14 0:161f7fa5a879 532 // 7 bytes 1 CT uid0 uid1 uid2
mavix14 0:161f7fa5a879 533 // 2 uid3 uid4 uid5 uid6
mavix14 0:161f7fa5a879 534 // 10 bytes 1 CT uid0 uid1 uid2
mavix14 0:161f7fa5a879 535 // 2 CT uid3 uid4 uid5
mavix14 0:161f7fa5a879 536 // 3 uid6 uid7 uid8 uid9
mavix14 0:161f7fa5a879 537
mavix14 0:161f7fa5a879 538 // Sanity checks
mavix14 0:161f7fa5a879 539 if (validBits > 80)
mavix14 0:161f7fa5a879 540 {
mavix14 0:161f7fa5a879 541 return STATUS_INVALID;
mavix14 0:161f7fa5a879 542 }
mavix14 0:161f7fa5a879 543
mavix14 0:161f7fa5a879 544 // Prepare MFRC522
mavix14 0:161f7fa5a879 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
mavix14 0:161f7fa5a879 546 PCD_ClrRegisterBits(CollReg, 0x80);
mavix14 0:161f7fa5a879 547
mavix14 0:161f7fa5a879 548 // Repeat Cascade Level loop until we have a complete UID.
mavix14 0:161f7fa5a879 549 uidComplete = false;
mavix14 0:161f7fa5a879 550 while ( ! uidComplete)
mavix14 0:161f7fa5a879 551 {
mavix14 0:161f7fa5a879 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
mavix14 0:161f7fa5a879 553 switch (cascadeLevel)
mavix14 0:161f7fa5a879 554 {
mavix14 0:161f7fa5a879 555 case 1:
mavix14 0:161f7fa5a879 556 buffer[0] = PICC_CMD_SEL_CL1;
mavix14 0:161f7fa5a879 557 uidIndex = 0;
mavix14 0:161f7fa5a879 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
mavix14 0:161f7fa5a879 559 break;
mavix14 0:161f7fa5a879 560
mavix14 0:161f7fa5a879 561 case 2:
mavix14 0:161f7fa5a879 562 buffer[0] = PICC_CMD_SEL_CL2;
mavix14 0:161f7fa5a879 563 uidIndex = 3;
mavix14 0:161f7fa5a879 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
mavix14 0:161f7fa5a879 565 break;
mavix14 0:161f7fa5a879 566
mavix14 0:161f7fa5a879 567 case 3:
mavix14 0:161f7fa5a879 568 buffer[0] = PICC_CMD_SEL_CL3;
mavix14 0:161f7fa5a879 569 uidIndex = 6;
mavix14 0:161f7fa5a879 570 useCascadeTag = false; // Never used in CL3.
mavix14 0:161f7fa5a879 571 break;
mavix14 0:161f7fa5a879 572
mavix14 0:161f7fa5a879 573 default:
mavix14 0:161f7fa5a879 574 return STATUS_INTERNAL_ERROR;
mavix14 0:161f7fa5a879 575 //break;
mavix14 0:161f7fa5a879 576 }
mavix14 0:161f7fa5a879 577
mavix14 0:161f7fa5a879 578 // How many UID bits are known in this Cascade Level?
mavix14 0:161f7fa5a879 579 if(validBits > (8 * uidIndex))
mavix14 0:161f7fa5a879 580 {
mavix14 0:161f7fa5a879 581 currentLevelKnownBits = validBits - (8 * uidIndex);
mavix14 0:161f7fa5a879 582 }
mavix14 0:161f7fa5a879 583 else
mavix14 0:161f7fa5a879 584 {
mavix14 0:161f7fa5a879 585 currentLevelKnownBits = 0;
mavix14 0:161f7fa5a879 586 }
mavix14 0:161f7fa5a879 587
mavix14 0:161f7fa5a879 588 // Copy the known bits from uid->uidByte[] to buffer[]
mavix14 0:161f7fa5a879 589 index = 2; // destination index in buffer[]
mavix14 0:161f7fa5a879 590 if (useCascadeTag)
mavix14 0:161f7fa5a879 591 {
mavix14 0:161f7fa5a879 592 buffer[index++] = PICC_CMD_CT;
mavix14 0:161f7fa5a879 593 }
mavix14 0:161f7fa5a879 594
mavix14 0:161f7fa5a879 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
mavix14 0:161f7fa5a879 596 if (bytesToCopy)
mavix14 0:161f7fa5a879 597 {
mavix14 0:161f7fa5a879 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
mavix14 0:161f7fa5a879 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
mavix14 0:161f7fa5a879 600 if (bytesToCopy > maxBytes)
mavix14 0:161f7fa5a879 601 {
mavix14 0:161f7fa5a879 602 bytesToCopy = maxBytes;
mavix14 0:161f7fa5a879 603 }
mavix14 0:161f7fa5a879 604
mavix14 0:161f7fa5a879 605 for (count = 0; count < bytesToCopy; count++)
mavix14 0:161f7fa5a879 606 {
mavix14 0:161f7fa5a879 607 buffer[index++] = uid->uidByte[uidIndex + count];
mavix14 0:161f7fa5a879 608 }
mavix14 0:161f7fa5a879 609 }
mavix14 0:161f7fa5a879 610
mavix14 0:161f7fa5a879 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
mavix14 0:161f7fa5a879 612 if (useCascadeTag)
mavix14 0:161f7fa5a879 613 {
mavix14 0:161f7fa5a879 614 currentLevelKnownBits += 8;
mavix14 0:161f7fa5a879 615 }
mavix14 0:161f7fa5a879 616
mavix14 0:161f7fa5a879 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
mavix14 0:161f7fa5a879 618 selectDone = false;
mavix14 0:161f7fa5a879 619 while ( ! selectDone)
mavix14 0:161f7fa5a879 620 {
mavix14 0:161f7fa5a879 621 // Find out how many bits and bytes to send and receive.
mavix14 0:161f7fa5a879 622 if (currentLevelKnownBits >= 32)
mavix14 0:161f7fa5a879 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
mavix14 0:161f7fa5a879 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
mavix14 0:161f7fa5a879 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
mavix14 0:161f7fa5a879 626
mavix14 0:161f7fa5a879 627 // Calulate BCC - Block Check Character
mavix14 0:161f7fa5a879 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
mavix14 0:161f7fa5a879 629
mavix14 0:161f7fa5a879 630 // Calculate CRC_A
mavix14 0:161f7fa5a879 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
mavix14 0:161f7fa5a879 632 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 633 {
mavix14 0:161f7fa5a879 634 return result;
mavix14 0:161f7fa5a879 635 }
mavix14 0:161f7fa5a879 636
mavix14 0:161f7fa5a879 637 txLastBits = 0; // 0 => All 8 bits are valid.
mavix14 0:161f7fa5a879 638 bufferUsed = 9;
mavix14 0:161f7fa5a879 639
mavix14 0:161f7fa5a879 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
mavix14 0:161f7fa5a879 641 responseBuffer = &buffer[6];
mavix14 0:161f7fa5a879 642 responseLength = 3;
mavix14 0:161f7fa5a879 643 }
mavix14 0:161f7fa5a879 644 else
mavix14 0:161f7fa5a879 645 { // This is an ANTICOLLISION.
mavix14 0:161f7fa5a879 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
mavix14 0:161f7fa5a879 647 txLastBits = currentLevelKnownBits % 8;
mavix14 0:161f7fa5a879 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
mavix14 0:161f7fa5a879 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
mavix14 0:161f7fa5a879 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
mavix14 0:161f7fa5a879 651 bufferUsed = index + (txLastBits ? 1 : 0);
mavix14 0:161f7fa5a879 652
mavix14 0:161f7fa5a879 653 // Store response in the unused part of buffer
mavix14 0:161f7fa5a879 654 responseBuffer = &buffer[index];
mavix14 0:161f7fa5a879 655 responseLength = sizeof(buffer) - index;
mavix14 0:161f7fa5a879 656 }
mavix14 0:161f7fa5a879 657
mavix14 0:161f7fa5a879 658 // Set bit adjustments
mavix14 0:161f7fa5a879 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
mavix14 0:161f7fa5a879 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
mavix14 0:161f7fa5a879 661
mavix14 0:161f7fa5a879 662 // Transmit the buffer and receive the response.
mavix14 0:161f7fa5a879 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
mavix14 0:161f7fa5a879 664 if (result == STATUS_COLLISION)
mavix14 0:161f7fa5a879 665 { // More than one PICC in the field => collision.
mavix14 0:161f7fa5a879 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
mavix14 0:161f7fa5a879 667 if (result & 0x20)
mavix14 0:161f7fa5a879 668 { // CollPosNotValid
mavix14 0:161f7fa5a879 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
mavix14 0:161f7fa5a879 670 }
mavix14 0:161f7fa5a879 671
mavix14 0:161f7fa5a879 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
mavix14 0:161f7fa5a879 673 if (collisionPos == 0)
mavix14 0:161f7fa5a879 674 {
mavix14 0:161f7fa5a879 675 collisionPos = 32;
mavix14 0:161f7fa5a879 676 }
mavix14 0:161f7fa5a879 677
mavix14 0:161f7fa5a879 678 if (collisionPos <= currentLevelKnownBits)
mavix14 0:161f7fa5a879 679 { // No progress - should not happen
mavix14 0:161f7fa5a879 680 return STATUS_INTERNAL_ERROR;
mavix14 0:161f7fa5a879 681 }
mavix14 0:161f7fa5a879 682
mavix14 0:161f7fa5a879 683 // Choose the PICC with the bit set.
mavix14 0:161f7fa5a879 684 currentLevelKnownBits = collisionPos;
mavix14 0:161f7fa5a879 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
mavix14 0:161f7fa5a879 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
mavix14 0:161f7fa5a879 687 buffer[index] |= (1 << count);
mavix14 0:161f7fa5a879 688 }
mavix14 0:161f7fa5a879 689 else if (result != STATUS_OK)
mavix14 0:161f7fa5a879 690 {
mavix14 0:161f7fa5a879 691 return result;
mavix14 0:161f7fa5a879 692 }
mavix14 0:161f7fa5a879 693 else
mavix14 0:161f7fa5a879 694 { // STATUS_OK
mavix14 0:161f7fa5a879 695 if (currentLevelKnownBits >= 32)
mavix14 0:161f7fa5a879 696 { // This was a SELECT.
mavix14 0:161f7fa5a879 697 selectDone = true; // No more anticollision
mavix14 0:161f7fa5a879 698 // We continue below outside the while.
mavix14 0:161f7fa5a879 699 }
mavix14 0:161f7fa5a879 700 else
mavix14 0:161f7fa5a879 701 { // This was an ANTICOLLISION.
mavix14 0:161f7fa5a879 702 // We now have all 32 bits of the UID in this Cascade Level
mavix14 0:161f7fa5a879 703 currentLevelKnownBits = 32;
mavix14 0:161f7fa5a879 704 // Run loop again to do the SELECT.
mavix14 0:161f7fa5a879 705 }
mavix14 0:161f7fa5a879 706 }
mavix14 0:161f7fa5a879 707 } // End of while ( ! selectDone)
mavix14 0:161f7fa5a879 708
mavix14 0:161f7fa5a879 709 // We do not check the CBB - it was constructed by us above.
mavix14 0:161f7fa5a879 710
mavix14 0:161f7fa5a879 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
mavix14 0:161f7fa5a879 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
mavix14 0:161f7fa5a879 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
mavix14 0:161f7fa5a879 714 for (count = 0; count < bytesToCopy; count++)
mavix14 0:161f7fa5a879 715 {
mavix14 0:161f7fa5a879 716 uid->uidByte[uidIndex + count] = buffer[index++];
mavix14 0:161f7fa5a879 717 }
mavix14 0:161f7fa5a879 718
mavix14 0:161f7fa5a879 719 // Check response SAK (Select Acknowledge)
mavix14 0:161f7fa5a879 720 if (responseLength != 3 || txLastBits != 0)
mavix14 0:161f7fa5a879 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
mavix14 0:161f7fa5a879 722 return STATUS_ERROR;
mavix14 0:161f7fa5a879 723 }
mavix14 0:161f7fa5a879 724
mavix14 0:161f7fa5a879 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
mavix14 0:161f7fa5a879 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
mavix14 0:161f7fa5a879 727 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 728 {
mavix14 0:161f7fa5a879 729 return result;
mavix14 0:161f7fa5a879 730 }
mavix14 0:161f7fa5a879 731
mavix14 0:161f7fa5a879 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
mavix14 0:161f7fa5a879 733 {
mavix14 0:161f7fa5a879 734 return STATUS_CRC_WRONG;
mavix14 0:161f7fa5a879 735 }
mavix14 0:161f7fa5a879 736
mavix14 0:161f7fa5a879 737 if (responseBuffer[0] & 0x04)
mavix14 0:161f7fa5a879 738 { // Cascade bit set - UID not complete yes
mavix14 0:161f7fa5a879 739 cascadeLevel++;
mavix14 0:161f7fa5a879 740 }
mavix14 0:161f7fa5a879 741 else
mavix14 0:161f7fa5a879 742 {
mavix14 0:161f7fa5a879 743 uidComplete = true;
mavix14 0:161f7fa5a879 744 uid->sak = responseBuffer[0];
mavix14 0:161f7fa5a879 745 }
mavix14 0:161f7fa5a879 746 } // End of while ( ! uidComplete)
mavix14 0:161f7fa5a879 747
mavix14 0:161f7fa5a879 748 // Set correct uid->size
mavix14 0:161f7fa5a879 749 uid->size = 3 * cascadeLevel + 1;
mavix14 0:161f7fa5a879 750
mavix14 0:161f7fa5a879 751 return STATUS_OK;
mavix14 0:161f7fa5a879 752 } // End PICC_Select()
mavix14 0:161f7fa5a879 753
mavix14 0:161f7fa5a879 754 /*
mavix14 0:161f7fa5a879 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
mavix14 0:161f7fa5a879 756 */
mavix14 0:161f7fa5a879 757 uint8_t MFRC522::PICC_HaltA()
mavix14 0:161f7fa5a879 758 {
mavix14 0:161f7fa5a879 759 uint8_t result;
mavix14 0:161f7fa5a879 760 uint8_t buffer[4];
mavix14 0:161f7fa5a879 761
mavix14 0:161f7fa5a879 762 // Build command buffer
mavix14 0:161f7fa5a879 763 buffer[0] = PICC_CMD_HLTA;
mavix14 0:161f7fa5a879 764 buffer[1] = 0;
mavix14 0:161f7fa5a879 765
mavix14 0:161f7fa5a879 766 // Calculate CRC_A
mavix14 0:161f7fa5a879 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
mavix14 0:161f7fa5a879 768 if (result == STATUS_OK)
mavix14 0:161f7fa5a879 769 {
mavix14 0:161f7fa5a879 770 // Send the command.
mavix14 0:161f7fa5a879 771 // The standard says:
mavix14 0:161f7fa5a879 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
mavix14 0:161f7fa5a879 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
mavix14 0:161f7fa5a879 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
mavix14 0:161f7fa5a879 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
mavix14 0:161f7fa5a879 776 if (result == STATUS_TIMEOUT)
mavix14 0:161f7fa5a879 777 {
mavix14 0:161f7fa5a879 778 result = STATUS_OK;
mavix14 0:161f7fa5a879 779 }
mavix14 0:161f7fa5a879 780 else if (result == STATUS_OK)
mavix14 0:161f7fa5a879 781 { // That is ironically NOT ok in this case ;-)
mavix14 0:161f7fa5a879 782 result = STATUS_ERROR;
mavix14 0:161f7fa5a879 783 }
mavix14 0:161f7fa5a879 784 }
mavix14 0:161f7fa5a879 785
mavix14 0:161f7fa5a879 786 return result;
mavix14 0:161f7fa5a879 787 } // End PICC_HaltA()
mavix14 0:161f7fa5a879 788
mavix14 0:161f7fa5a879 789
mavix14 0:161f7fa5a879 790 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 791 // Functions for communicating with MIFARE PICCs
mavix14 0:161f7fa5a879 792 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 793
mavix14 0:161f7fa5a879 794 /*
mavix14 0:161f7fa5a879 795 * Executes the MFRC522 MFAuthent command.
mavix14 0:161f7fa5a879 796 */
mavix14 0:161f7fa5a879 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
mavix14 0:161f7fa5a879 798 {
mavix14 0:161f7fa5a879 799 uint8_t i, waitIRq = 0x10; // IdleIRq
mavix14 0:161f7fa5a879 800
mavix14 0:161f7fa5a879 801 // Build command buffer
mavix14 0:161f7fa5a879 802 uint8_t sendData[12];
mavix14 0:161f7fa5a879 803 sendData[0] = command;
mavix14 0:161f7fa5a879 804 sendData[1] = blockAddr;
mavix14 0:161f7fa5a879 805
mavix14 0:161f7fa5a879 806 for (i = 0; i < MF_KEY_SIZE; i++)
mavix14 0:161f7fa5a879 807 { // 6 key bytes
mavix14 0:161f7fa5a879 808 sendData[2+i] = key->keyByte[i];
mavix14 0:161f7fa5a879 809 }
mavix14 0:161f7fa5a879 810
mavix14 0:161f7fa5a879 811 for (i = 0; i < 4; i++)
mavix14 0:161f7fa5a879 812 { // The first 4 bytes of the UID
mavix14 0:161f7fa5a879 813 sendData[8+i] = uid->uidByte[i];
mavix14 0:161f7fa5a879 814 }
mavix14 0:161f7fa5a879 815
mavix14 0:161f7fa5a879 816 // Start the authentication.
mavix14 0:161f7fa5a879 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
mavix14 0:161f7fa5a879 818 } // End PCD_Authenticate()
mavix14 0:161f7fa5a879 819
mavix14 0:161f7fa5a879 820 /*
mavix14 0:161f7fa5a879 821 * Used to exit the PCD from its authenticated state.
mavix14 0:161f7fa5a879 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
mavix14 0:161f7fa5a879 823 */
mavix14 0:161f7fa5a879 824 void MFRC522::PCD_StopCrypto1()
mavix14 0:161f7fa5a879 825 {
mavix14 0:161f7fa5a879 826 // Clear MFCrypto1On bit
mavix14 0:161f7fa5a879 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
mavix14 0:161f7fa5a879 828 } // End PCD_StopCrypto1()
mavix14 0:161f7fa5a879 829
mavix14 0:161f7fa5a879 830 /*
mavix14 0:161f7fa5a879 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
mavix14 0:161f7fa5a879 832 */
mavix14 0:161f7fa5a879 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
mavix14 0:161f7fa5a879 834 {
mavix14 0:161f7fa5a879 835 uint8_t result = STATUS_NO_ROOM;
mavix14 0:161f7fa5a879 836
mavix14 0:161f7fa5a879 837 // Sanity check
mavix14 0:161f7fa5a879 838 if ((buffer == NULL) || (*bufferSize < 18))
mavix14 0:161f7fa5a879 839 {
mavix14 0:161f7fa5a879 840 return result;
mavix14 0:161f7fa5a879 841 }
mavix14 0:161f7fa5a879 842
mavix14 0:161f7fa5a879 843 // Build command buffer
mavix14 0:161f7fa5a879 844 buffer[0] = PICC_CMD_MF_READ;
mavix14 0:161f7fa5a879 845 buffer[1] = blockAddr;
mavix14 0:161f7fa5a879 846
mavix14 0:161f7fa5a879 847 // Calculate CRC_A
mavix14 0:161f7fa5a879 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
mavix14 0:161f7fa5a879 849 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 850 {
mavix14 0:161f7fa5a879 851 return result;
mavix14 0:161f7fa5a879 852 }
mavix14 0:161f7fa5a879 853
mavix14 0:161f7fa5a879 854 // Transmit the buffer and receive the response, validate CRC_A.
mavix14 0:161f7fa5a879 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
mavix14 0:161f7fa5a879 856 } // End MIFARE_Read()
mavix14 0:161f7fa5a879 857
mavix14 0:161f7fa5a879 858 /*
mavix14 0:161f7fa5a879 859 * Writes 16 bytes to the active PICC.
mavix14 0:161f7fa5a879 860 */
mavix14 0:161f7fa5a879 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
mavix14 0:161f7fa5a879 862 {
mavix14 0:161f7fa5a879 863 uint8_t result;
mavix14 0:161f7fa5a879 864
mavix14 0:161f7fa5a879 865 // Sanity check
mavix14 0:161f7fa5a879 866 if (buffer == NULL || bufferSize < 16)
mavix14 0:161f7fa5a879 867 {
mavix14 0:161f7fa5a879 868 return STATUS_INVALID;
mavix14 0:161f7fa5a879 869 }
mavix14 0:161f7fa5a879 870
mavix14 0:161f7fa5a879 871 // Mifare Classic protocol requires two communications to perform a write.
mavix14 0:161f7fa5a879 872 // Step 1: Tell the PICC we want to write to block blockAddr.
mavix14 0:161f7fa5a879 873 uint8_t cmdBuffer[2];
mavix14 0:161f7fa5a879 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
mavix14 0:161f7fa5a879 875 cmdBuffer[1] = blockAddr;
mavix14 0:161f7fa5a879 876 // Adds CRC_A and checks that the response is MF_ACK.
mavix14 0:161f7fa5a879 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
mavix14 0:161f7fa5a879 878 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 879 {
mavix14 0:161f7fa5a879 880 return result;
mavix14 0:161f7fa5a879 881 }
mavix14 0:161f7fa5a879 882
mavix14 0:161f7fa5a879 883 // Step 2: Transfer the data
mavix14 0:161f7fa5a879 884 // Adds CRC_A and checks that the response is MF_ACK.
mavix14 0:161f7fa5a879 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
mavix14 0:161f7fa5a879 886 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 887 {
mavix14 0:161f7fa5a879 888 return result;
mavix14 0:161f7fa5a879 889 }
mavix14 0:161f7fa5a879 890
mavix14 0:161f7fa5a879 891 return STATUS_OK;
mavix14 0:161f7fa5a879 892 } // End MIFARE_Write()
mavix14 0:161f7fa5a879 893
mavix14 0:161f7fa5a879 894 /*
mavix14 0:161f7fa5a879 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
mavix14 0:161f7fa5a879 896 */
mavix14 0:161f7fa5a879 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
mavix14 0:161f7fa5a879 898 {
mavix14 0:161f7fa5a879 899 uint8_t result;
mavix14 0:161f7fa5a879 900
mavix14 0:161f7fa5a879 901 // Sanity check
mavix14 0:161f7fa5a879 902 if (buffer == NULL || bufferSize < 4)
mavix14 0:161f7fa5a879 903 {
mavix14 0:161f7fa5a879 904 return STATUS_INVALID;
mavix14 0:161f7fa5a879 905 }
mavix14 0:161f7fa5a879 906
mavix14 0:161f7fa5a879 907 // Build commmand buffer
mavix14 0:161f7fa5a879 908 uint8_t cmdBuffer[6];
mavix14 0:161f7fa5a879 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
mavix14 0:161f7fa5a879 910 cmdBuffer[1] = page;
mavix14 0:161f7fa5a879 911 memcpy(&cmdBuffer[2], buffer, 4);
mavix14 0:161f7fa5a879 912
mavix14 0:161f7fa5a879 913 // Perform the write
mavix14 0:161f7fa5a879 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
mavix14 0:161f7fa5a879 915 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 916 {
mavix14 0:161f7fa5a879 917 return result;
mavix14 0:161f7fa5a879 918 }
mavix14 0:161f7fa5a879 919
mavix14 0:161f7fa5a879 920 return STATUS_OK;
mavix14 0:161f7fa5a879 921 } // End MIFARE_Ultralight_Write()
mavix14 0:161f7fa5a879 922
mavix14 0:161f7fa5a879 923 /*
mavix14 0:161f7fa5a879 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
mavix14 0:161f7fa5a879 925 */
mavix14 0:161f7fa5a879 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
mavix14 0:161f7fa5a879 927 {
mavix14 0:161f7fa5a879 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
mavix14 0:161f7fa5a879 929 } // End MIFARE_Decrement()
mavix14 0:161f7fa5a879 930
mavix14 0:161f7fa5a879 931 /*
mavix14 0:161f7fa5a879 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
mavix14 0:161f7fa5a879 933 */
mavix14 0:161f7fa5a879 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
mavix14 0:161f7fa5a879 935 {
mavix14 0:161f7fa5a879 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
mavix14 0:161f7fa5a879 937 } // End MIFARE_Increment()
mavix14 0:161f7fa5a879 938
mavix14 0:161f7fa5a879 939 /**
mavix14 0:161f7fa5a879 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
mavix14 0:161f7fa5a879 941 */
mavix14 0:161f7fa5a879 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
mavix14 0:161f7fa5a879 943 {
mavix14 0:161f7fa5a879 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
mavix14 0:161f7fa5a879 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
mavix14 0:161f7fa5a879 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
mavix14 0:161f7fa5a879 947 } // End MIFARE_Restore()
mavix14 0:161f7fa5a879 948
mavix14 0:161f7fa5a879 949 /*
mavix14 0:161f7fa5a879 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
mavix14 0:161f7fa5a879 951 */
mavix14 0:161f7fa5a879 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
mavix14 0:161f7fa5a879 953 {
mavix14 0:161f7fa5a879 954 uint8_t result;
mavix14 0:161f7fa5a879 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
mavix14 0:161f7fa5a879 956
mavix14 0:161f7fa5a879 957 // Step 1: Tell the PICC the command and block address
mavix14 0:161f7fa5a879 958 cmdBuffer[0] = command;
mavix14 0:161f7fa5a879 959 cmdBuffer[1] = blockAddr;
mavix14 0:161f7fa5a879 960
mavix14 0:161f7fa5a879 961 // Adds CRC_A and checks that the response is MF_ACK.
mavix14 0:161f7fa5a879 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
mavix14 0:161f7fa5a879 963 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 964 {
mavix14 0:161f7fa5a879 965 return result;
mavix14 0:161f7fa5a879 966 }
mavix14 0:161f7fa5a879 967
mavix14 0:161f7fa5a879 968 // Step 2: Transfer the data
mavix14 0:161f7fa5a879 969 // Adds CRC_A and accept timeout as success.
mavix14 0:161f7fa5a879 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
mavix14 0:161f7fa5a879 971 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 972 {
mavix14 0:161f7fa5a879 973 return result;
mavix14 0:161f7fa5a879 974 }
mavix14 0:161f7fa5a879 975
mavix14 0:161f7fa5a879 976 return STATUS_OK;
mavix14 0:161f7fa5a879 977 } // End MIFARE_TwoStepHelper()
mavix14 0:161f7fa5a879 978
mavix14 0:161f7fa5a879 979 /*
mavix14 0:161f7fa5a879 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
mavix14 0:161f7fa5a879 981 */
mavix14 0:161f7fa5a879 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
mavix14 0:161f7fa5a879 983 {
mavix14 0:161f7fa5a879 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
mavix14 0:161f7fa5a879 985
mavix14 0:161f7fa5a879 986 // Tell the PICC we want to transfer the result into block blockAddr.
mavix14 0:161f7fa5a879 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
mavix14 0:161f7fa5a879 988 cmdBuffer[1] = blockAddr;
mavix14 0:161f7fa5a879 989
mavix14 0:161f7fa5a879 990 // Adds CRC_A and checks that the response is MF_ACK.
mavix14 0:161f7fa5a879 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
mavix14 0:161f7fa5a879 992 } // End MIFARE_Transfer()
mavix14 0:161f7fa5a879 993
mavix14 0:161f7fa5a879 994
mavix14 0:161f7fa5a879 995 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 996 // Support functions
mavix14 0:161f7fa5a879 997 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 998
mavix14 0:161f7fa5a879 999 /*
mavix14 0:161f7fa5a879 1000 * Wrapper for MIFARE protocol communication.
mavix14 0:161f7fa5a879 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
mavix14 0:161f7fa5a879 1002 */
mavix14 0:161f7fa5a879 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
mavix14 0:161f7fa5a879 1004 {
mavix14 0:161f7fa5a879 1005 uint8_t result;
mavix14 0:161f7fa5a879 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
mavix14 0:161f7fa5a879 1007
mavix14 0:161f7fa5a879 1008 // Sanity check
mavix14 0:161f7fa5a879 1009 if (sendData == NULL || sendLen > 16)
mavix14 0:161f7fa5a879 1010 {
mavix14 0:161f7fa5a879 1011 return STATUS_INVALID;
mavix14 0:161f7fa5a879 1012 }
mavix14 0:161f7fa5a879 1013
mavix14 0:161f7fa5a879 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
mavix14 0:161f7fa5a879 1015 memcpy(cmdBuffer, sendData, sendLen);
mavix14 0:161f7fa5a879 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
mavix14 0:161f7fa5a879 1017 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 1018 {
mavix14 0:161f7fa5a879 1019 return result;
mavix14 0:161f7fa5a879 1020 }
mavix14 0:161f7fa5a879 1021
mavix14 0:161f7fa5a879 1022 sendLen += 2;
mavix14 0:161f7fa5a879 1023
mavix14 0:161f7fa5a879 1024 // Transceive the data, store the reply in cmdBuffer[]
mavix14 0:161f7fa5a879 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
mavix14 0:161f7fa5a879 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
mavix14 0:161f7fa5a879 1027 uint8_t validBits = 0;
mavix14 0:161f7fa5a879 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
mavix14 0:161f7fa5a879 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
mavix14 0:161f7fa5a879 1030 {
mavix14 0:161f7fa5a879 1031 return STATUS_OK;
mavix14 0:161f7fa5a879 1032 }
mavix14 0:161f7fa5a879 1033
mavix14 0:161f7fa5a879 1034 if (result != STATUS_OK)
mavix14 0:161f7fa5a879 1035 {
mavix14 0:161f7fa5a879 1036 return result;
mavix14 0:161f7fa5a879 1037 }
mavix14 0:161f7fa5a879 1038
mavix14 0:161f7fa5a879 1039 // The PICC must reply with a 4 bit ACK
mavix14 0:161f7fa5a879 1040 if (cmdBufferSize != 1 || validBits != 4)
mavix14 0:161f7fa5a879 1041 {
mavix14 0:161f7fa5a879 1042 return STATUS_ERROR;
mavix14 0:161f7fa5a879 1043 }
mavix14 0:161f7fa5a879 1044
mavix14 0:161f7fa5a879 1045 if (cmdBuffer[0] != MF_ACK)
mavix14 0:161f7fa5a879 1046 {
mavix14 0:161f7fa5a879 1047 return STATUS_MIFARE_NACK;
mavix14 0:161f7fa5a879 1048 }
mavix14 0:161f7fa5a879 1049
mavix14 0:161f7fa5a879 1050 return STATUS_OK;
mavix14 0:161f7fa5a879 1051 } // End PCD_MIFARE_Transceive()
mavix14 0:161f7fa5a879 1052
mavix14 0:161f7fa5a879 1053
mavix14 0:161f7fa5a879 1054 /*
mavix14 0:161f7fa5a879 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
mavix14 0:161f7fa5a879 1056 */
mavix14 0:161f7fa5a879 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
mavix14 0:161f7fa5a879 1058 {
mavix14 0:161f7fa5a879 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
mavix14 0:161f7fa5a879 1060
mavix14 0:161f7fa5a879 1061 if (sak & 0x04)
mavix14 0:161f7fa5a879 1062 { // UID not complete
mavix14 0:161f7fa5a879 1063 retType = PICC_TYPE_NOT_COMPLETE;
mavix14 0:161f7fa5a879 1064 }
mavix14 0:161f7fa5a879 1065 else
mavix14 0:161f7fa5a879 1066 {
mavix14 0:161f7fa5a879 1067 switch (sak)
mavix14 0:161f7fa5a879 1068 {
mavix14 0:161f7fa5a879 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
mavix14 0:161f7fa5a879 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
mavix14 0:161f7fa5a879 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
mavix14 0:161f7fa5a879 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
mavix14 0:161f7fa5a879 1073 case 0x10:
mavix14 0:161f7fa5a879 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
mavix14 0:161f7fa5a879 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
mavix14 0:161f7fa5a879 1076 default:
mavix14 0:161f7fa5a879 1077 if (sak & 0x20)
mavix14 0:161f7fa5a879 1078 {
mavix14 0:161f7fa5a879 1079 retType = PICC_TYPE_ISO_14443_4;
mavix14 0:161f7fa5a879 1080 }
mavix14 0:161f7fa5a879 1081 else if (sak & 0x40)
mavix14 0:161f7fa5a879 1082 {
mavix14 0:161f7fa5a879 1083 retType = PICC_TYPE_ISO_18092;
mavix14 0:161f7fa5a879 1084 }
mavix14 0:161f7fa5a879 1085 break;
mavix14 0:161f7fa5a879 1086 }
mavix14 0:161f7fa5a879 1087 }
mavix14 0:161f7fa5a879 1088
mavix14 0:161f7fa5a879 1089 return (retType);
mavix14 0:161f7fa5a879 1090 } // End PICC_GetType()
mavix14 0:161f7fa5a879 1091
mavix14 0:161f7fa5a879 1092 /*
mavix14 0:161f7fa5a879 1093 * Returns a string pointer to the PICC type name.
mavix14 0:161f7fa5a879 1094 */
mavix14 0:161f7fa5a879 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
mavix14 0:161f7fa5a879 1096 {
mavix14 0:161f7fa5a879 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
mavix14 0:161f7fa5a879 1098 {
mavix14 0:161f7fa5a879 1099 piccType = MFRC522_MaxPICCs - 1;
mavix14 0:161f7fa5a879 1100 }
mavix14 0:161f7fa5a879 1101
mavix14 0:161f7fa5a879 1102 return((char *) _TypeNamePICC[piccType]);
mavix14 0:161f7fa5a879 1103 } // End PICC_GetTypeName()
mavix14 0:161f7fa5a879 1104
mavix14 0:161f7fa5a879 1105 /*
mavix14 0:161f7fa5a879 1106 * Returns a string pointer to a status code name.
mavix14 0:161f7fa5a879 1107 */
mavix14 0:161f7fa5a879 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
mavix14 0:161f7fa5a879 1109 {
mavix14 0:161f7fa5a879 1110 return((char *) _ErrorMessage[code]);
mavix14 0:161f7fa5a879 1111 } // End GetStatusCodeName()
mavix14 0:161f7fa5a879 1112
mavix14 0:161f7fa5a879 1113 /*
mavix14 0:161f7fa5a879 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
mavix14 0:161f7fa5a879 1115 */
mavix14 0:161f7fa5a879 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
mavix14 0:161f7fa5a879 1117 uint8_t g0,
mavix14 0:161f7fa5a879 1118 uint8_t g1,
mavix14 0:161f7fa5a879 1119 uint8_t g2,
mavix14 0:161f7fa5a879 1120 uint8_t g3)
mavix14 0:161f7fa5a879 1121 {
mavix14 0:161f7fa5a879 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
mavix14 0:161f7fa5a879 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
mavix14 0:161f7fa5a879 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
mavix14 0:161f7fa5a879 1125
mavix14 0:161f7fa5a879 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
mavix14 0:161f7fa5a879 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
mavix14 0:161f7fa5a879 1128 accessBitBuffer[2] = c3 << 4 | c2;
mavix14 0:161f7fa5a879 1129 } // End MIFARE_SetAccessBits()
mavix14 0:161f7fa5a879 1130
mavix14 0:161f7fa5a879 1131 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 1132 // Convenience functions - does not add extra functionality
mavix14 0:161f7fa5a879 1133 /////////////////////////////////////////////////////////////////////////////////////
mavix14 0:161f7fa5a879 1134
mavix14 0:161f7fa5a879 1135 /*
mavix14 0:161f7fa5a879 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
mavix14 0:161f7fa5a879 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
mavix14 0:161f7fa5a879 1138 */
mavix14 0:161f7fa5a879 1139 bool MFRC522::PICC_IsNewCardPresent(void)
mavix14 0:161f7fa5a879 1140 {
mavix14 0:161f7fa5a879 1141 uint8_t bufferATQA[2];
mavix14 0:161f7fa5a879 1142 uint8_t bufferSize = sizeof(bufferATQA);
mavix14 0:161f7fa5a879 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
mavix14 0:161f7fa5a879 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
mavix14 0:161f7fa5a879 1145 } // End PICC_IsNewCardPresent()
mavix14 0:161f7fa5a879 1146
mavix14 0:161f7fa5a879 1147 /*
mavix14 0:161f7fa5a879 1148 * Simple wrapper around PICC_Select.
mavix14 0:161f7fa5a879 1149 */
mavix14 0:161f7fa5a879 1150 bool MFRC522::PICC_ReadCardSerial(void)
mavix14 0:161f7fa5a879 1151 {
mavix14 0:161f7fa5a879 1152 uint8_t result = PICC_Select(&uid);
mavix14 0:161f7fa5a879 1153 return (result == STATUS_OK);
mavix14 0:161f7fa5a879 1154 } // End PICC_ReadCardSerial()