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LPC2368/LPC23xx.h@40:976df7c37ad5, 2012-06-12 (annotated)

Committer:
emilmont
Date:
Tue Jun 12 18:23:44 2012 +0100
Revision:
40:976df7c37ad5
First build for the new build system

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 40:976df7c37ad5 1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
emilmont 40:976df7c37ad5 2 * Copyright (C) 2009 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 3 *
emilmont 40:976df7c37ad5 4 * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
emilmont 40:976df7c37ad5 5 */
emilmont 40:976df7c37ad5 6
emilmont 40:976df7c37ad5 7 #ifndef __LPC23xx_H
emilmont 40:976df7c37ad5 8 #define __LPC23xx_H
emilmont 40:976df7c37ad5 9
emilmont 40:976df7c37ad5 10 #ifdef __cplusplus
emilmont 40:976df7c37ad5 11 extern "C" {
emilmont 40:976df7c37ad5 12 #endif
emilmont 40:976df7c37ad5 13
emilmont 40:976df7c37ad5 14 /*
emilmont 40:976df7c37ad5 15 * ==========================================================================
emilmont 40:976df7c37ad5 16 * ---------- Interrupt Number Definition -----------------------------------
emilmont 40:976df7c37ad5 17 * ==========================================================================
emilmont 40:976df7c37ad5 18 */
emilmont 40:976df7c37ad5 19
emilmont 40:976df7c37ad5 20 typedef enum IRQn
emilmont 40:976df7c37ad5 21 {
emilmont 40:976df7c37ad5 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
emilmont 40:976df7c37ad5 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
emilmont 40:976df7c37ad5 24
emilmont 40:976df7c37ad5 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
emilmont 40:976df7c37ad5 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
emilmont 40:976df7c37ad5 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
emilmont 40:976df7c37ad5 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
emilmont 40:976df7c37ad5 29 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
emilmont 40:976df7c37ad5 30 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
emilmont 40:976df7c37ad5 31 SPI_IRQn = 10, /*!< SPI Interrupt */
emilmont 40:976df7c37ad5 32 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
emilmont 40:976df7c37ad5 33 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
emilmont 40:976df7c37ad5 34 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
emilmont 40:976df7c37ad5 35 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
emilmont 40:976df7c37ad5 36 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
emilmont 40:976df7c37ad5 37 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
emilmont 40:976df7c37ad5 38 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
emilmont 40:976df7c37ad5 39 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
emilmont 40:976df7c37ad5 40 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
emilmont 40:976df7c37ad5 41 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
emilmont 40:976df7c37ad5 42 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
emilmont 40:976df7c37ad5 43 ENET_IRQn = 21, /*!< Ethernet Interrupt */
emilmont 40:976df7c37ad5 44 USB_IRQn = 22, /*!< USB Interrupt */
emilmont 40:976df7c37ad5 45 CAN_IRQn = 23, /*!< CAN Interrupt */
emilmont 40:976df7c37ad5 46 MIC_IRQn = 24, /*!< Multimedia Interface Controler */
emilmont 40:976df7c37ad5 47 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
emilmont 40:976df7c37ad5 48 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
emilmont 40:976df7c37ad5 49 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
emilmont 40:976df7c37ad5 50 UART2_IRQn = 28, /*!< UART2 Interrupt */
emilmont 40:976df7c37ad5 51 UART3_IRQn = 29, /*!< UART3 Interrupt */
emilmont 40:976df7c37ad5 52 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
emilmont 40:976df7c37ad5 53 I2S_IRQn = 31, /*!< I2S Interrupt */
emilmont 40:976df7c37ad5 54 } IRQn_Type;
emilmont 40:976df7c37ad5 55
emilmont 40:976df7c37ad5 56 /*
emilmont 40:976df7c37ad5 57 * ==========================================================================
emilmont 40:976df7c37ad5 58 * ----------- Processor and Core Peripheral Section ------------------------
emilmont 40:976df7c37ad5 59 * ==========================================================================
emilmont 40:976df7c37ad5 60 */
emilmont 40:976df7c37ad5 61
emilmont 40:976df7c37ad5 62 /* Configuration of the ARM7 Processor and Core Peripherals */
emilmont 40:976df7c37ad5 63 #define __MPU_PRESENT 0 /*!< MPU present or not */
emilmont 40:976df7c37ad5 64 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
emilmont 40:976df7c37ad5 65 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 40:976df7c37ad5 66
emilmont 40:976df7c37ad5 67
emilmont 40:976df7c37ad5 68 #include <core_arm7.h>
emilmont 40:976df7c37ad5 69 #include "system_LPC23xx.h" /* System Header */
emilmont 40:976df7c37ad5 70
emilmont 40:976df7c37ad5 71
emilmont 40:976df7c37ad5 72 /******************************************************************************/
emilmont 40:976df7c37ad5 73 /* Device Specific Peripheral registers structures */
emilmont 40:976df7c37ad5 74 /******************************************************************************/
emilmont 40:976df7c37ad5 75 #if defined ( __CC_ARM )
emilmont 40:976df7c37ad5 76 #pragma anon_unions
emilmont 40:976df7c37ad5 77 #endif
emilmont 40:976df7c37ad5 78
emilmont 40:976df7c37ad5 79 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
emilmont 40:976df7c37ad5 80 typedef struct
emilmont 40:976df7c37ad5 81 {
emilmont 40:976df7c37ad5 82 __I uint32_t IRQStatus;
emilmont 40:976df7c37ad5 83 __I uint32_t FIQStatus;
emilmont 40:976df7c37ad5 84 __I uint32_t RawIntr;
emilmont 40:976df7c37ad5 85 __IO uint32_t IntSelect;
emilmont 40:976df7c37ad5 86 __IO uint32_t IntEnable;
emilmont 40:976df7c37ad5 87 __O uint32_t IntEnClr;
emilmont 40:976df7c37ad5 88 __IO uint32_t SoftInt;
emilmont 40:976df7c37ad5 89 __O uint32_t SoftIntClr;
emilmont 40:976df7c37ad5 90 __IO uint32_t Protection;
emilmont 40:976df7c37ad5 91 __IO uint32_t SWPriorityMask;
emilmont 40:976df7c37ad5 92 __IO uint32_t RESERVED0[54];
emilmont 40:976df7c37ad5 93 __IO uint32_t VectAddr[32];
emilmont 40:976df7c37ad5 94 __IO uint32_t RESERVED1[32];
emilmont 40:976df7c37ad5 95 __IO uint32_t VectPriority[32];
emilmont 40:976df7c37ad5 96 __IO uint32_t RESERVED2[800];
emilmont 40:976df7c37ad5 97 __IO uint32_t Address;
emilmont 40:976df7c37ad5 98 } LPC_VIC_TypeDef;
emilmont 40:976df7c37ad5 99
emilmont 40:976df7c37ad5 100 /*------------- System Control (SC) ------------------------------------------*/
emilmont 40:976df7c37ad5 101 typedef struct
emilmont 40:976df7c37ad5 102 {
emilmont 40:976df7c37ad5 103 __IO uint32_t MAMCR;
emilmont 40:976df7c37ad5 104 __IO uint32_t MAMTIM;
emilmont 40:976df7c37ad5 105 uint32_t RESERVED0[14];
emilmont 40:976df7c37ad5 106 __IO uint32_t MEMMAP;
emilmont 40:976df7c37ad5 107 uint32_t RESERVED1[15];
emilmont 40:976df7c37ad5 108 __IO uint32_t PLL0CON; /* Clocking and Power Control */
emilmont 40:976df7c37ad5 109 __IO uint32_t PLL0CFG;
emilmont 40:976df7c37ad5 110 __I uint32_t PLL0STAT;
emilmont 40:976df7c37ad5 111 __O uint32_t PLL0FEED;
emilmont 40:976df7c37ad5 112 uint32_t RESERVED2[12];
emilmont 40:976df7c37ad5 113 __IO uint32_t PCON;
emilmont 40:976df7c37ad5 114 __IO uint32_t PCONP;
emilmont 40:976df7c37ad5 115 uint32_t RESERVED3[15];
emilmont 40:976df7c37ad5 116 __IO uint32_t CCLKCFG;
emilmont 40:976df7c37ad5 117 __IO uint32_t USBCLKCFG;
emilmont 40:976df7c37ad5 118 __IO uint32_t CLKSRCSEL;
emilmont 40:976df7c37ad5 119 uint32_t RESERVED4[12];
emilmont 40:976df7c37ad5 120 __IO uint32_t EXTINT; /* External Interrupts */
emilmont 40:976df7c37ad5 121 __IO uint32_t INTWAKE;
emilmont 40:976df7c37ad5 122 __IO uint32_t EXTMODE;
emilmont 40:976df7c37ad5 123 __IO uint32_t EXTPOLAR;
emilmont 40:976df7c37ad5 124 uint32_t RESERVED6[12];
emilmont 40:976df7c37ad5 125 __IO uint32_t RSID; /* Reset */
emilmont 40:976df7c37ad5 126 __IO uint32_t CSPR;
emilmont 40:976df7c37ad5 127 __IO uint32_t AHBCFG1;
emilmont 40:976df7c37ad5 128 __IO uint32_t AHBCFG2;
emilmont 40:976df7c37ad5 129 uint32_t RESERVED7[4];
emilmont 40:976df7c37ad5 130 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
emilmont 40:976df7c37ad5 131 __IO uint32_t IRCTRIM; /* Clock Dividers */
emilmont 40:976df7c37ad5 132 __IO uint32_t PCLKSEL0;
emilmont 40:976df7c37ad5 133 __IO uint32_t PCLKSEL1;
emilmont 40:976df7c37ad5 134 uint32_t RESERVED8[4];
emilmont 40:976df7c37ad5 135 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
emilmont 40:976df7c37ad5 136 uint32_t RESERVED9;
emilmont 40:976df7c37ad5 137 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
emilmont 40:976df7c37ad5 138 } LPC_SC_TypeDef;
emilmont 40:976df7c37ad5 139
emilmont 40:976df7c37ad5 140 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
emilmont 40:976df7c37ad5 141 typedef struct
emilmont 40:976df7c37ad5 142 {
emilmont 40:976df7c37ad5 143 __IO uint32_t PINSEL0;
emilmont 40:976df7c37ad5 144 __IO uint32_t PINSEL1;
emilmont 40:976df7c37ad5 145 __IO uint32_t PINSEL2;
emilmont 40:976df7c37ad5 146 __IO uint32_t PINSEL3;
emilmont 40:976df7c37ad5 147 __IO uint32_t PINSEL4;
emilmont 40:976df7c37ad5 148 __IO uint32_t PINSEL5;
emilmont 40:976df7c37ad5 149 __IO uint32_t PINSEL6;
emilmont 40:976df7c37ad5 150 __IO uint32_t PINSEL7;
emilmont 40:976df7c37ad5 151 __IO uint32_t PINSEL8;
emilmont 40:976df7c37ad5 152 __IO uint32_t PINSEL9;
emilmont 40:976df7c37ad5 153 __IO uint32_t PINSEL10;
emilmont 40:976df7c37ad5 154 uint32_t RESERVED0[5];
emilmont 40:976df7c37ad5 155 __IO uint32_t PINMODE0;
emilmont 40:976df7c37ad5 156 __IO uint32_t PINMODE1;
emilmont 40:976df7c37ad5 157 __IO uint32_t PINMODE2;
emilmont 40:976df7c37ad5 158 __IO uint32_t PINMODE3;
emilmont 40:976df7c37ad5 159 __IO uint32_t PINMODE4;
emilmont 40:976df7c37ad5 160 __IO uint32_t PINMODE5;
emilmont 40:976df7c37ad5 161 __IO uint32_t PINMODE6;
emilmont 40:976df7c37ad5 162 __IO uint32_t PINMODE7;
emilmont 40:976df7c37ad5 163 __IO uint32_t PINMODE8;
emilmont 40:976df7c37ad5 164 __IO uint32_t PINMODE9;
emilmont 40:976df7c37ad5 165 __IO uint32_t PINMODE_OD0;
emilmont 40:976df7c37ad5 166 __IO uint32_t PINMODE_OD1;
emilmont 40:976df7c37ad5 167 __IO uint32_t PINMODE_OD2;
emilmont 40:976df7c37ad5 168 __IO uint32_t PINMODE_OD3;
emilmont 40:976df7c37ad5 169 __IO uint32_t PINMODE_OD4;
emilmont 40:976df7c37ad5 170 } LPC_PINCON_TypeDef;
emilmont 40:976df7c37ad5 171
emilmont 40:976df7c37ad5 172 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
emilmont 40:976df7c37ad5 173 typedef struct
emilmont 40:976df7c37ad5 174 {
emilmont 40:976df7c37ad5 175 __IO uint32_t FIODIR;
emilmont 40:976df7c37ad5 176 uint32_t RESERVED0[3];
emilmont 40:976df7c37ad5 177 __IO uint32_t FIOMASK;
emilmont 40:976df7c37ad5 178 __IO uint32_t FIOPIN;
emilmont 40:976df7c37ad5 179 __IO uint32_t FIOSET;
emilmont 40:976df7c37ad5 180 __O uint32_t FIOCLR;
emilmont 40:976df7c37ad5 181 } LPC_GPIO_TypeDef;
emilmont 40:976df7c37ad5 182
emilmont 40:976df7c37ad5 183 typedef struct
emilmont 40:976df7c37ad5 184 {
emilmont 40:976df7c37ad5 185 __I uint32_t IntStatus;
emilmont 40:976df7c37ad5 186 __I uint32_t IO0IntStatR;
emilmont 40:976df7c37ad5 187 __I uint32_t IO0IntStatF;
emilmont 40:976df7c37ad5 188 __O uint32_t IO0IntClr;
emilmont 40:976df7c37ad5 189 __IO uint32_t IO0IntEnR;
emilmont 40:976df7c37ad5 190 __IO uint32_t IO0IntEnF;
emilmont 40:976df7c37ad5 191 uint32_t RESERVED0[3];
emilmont 40:976df7c37ad5 192 __I uint32_t IO2IntStatR;
emilmont 40:976df7c37ad5 193 __I uint32_t IO2IntStatF;
emilmont 40:976df7c37ad5 194 __O uint32_t IO2IntClr;
emilmont 40:976df7c37ad5 195 __IO uint32_t IO2IntEnR;
emilmont 40:976df7c37ad5 196 __IO uint32_t IO2IntEnF;
emilmont 40:976df7c37ad5 197 } LPC_GPIOINT_TypeDef;
emilmont 40:976df7c37ad5 198
emilmont 40:976df7c37ad5 199 /*------------- Timer (TIM) --------------------------------------------------*/
emilmont 40:976df7c37ad5 200 typedef struct
emilmont 40:976df7c37ad5 201 {
emilmont 40:976df7c37ad5 202 __IO uint32_t IR;
emilmont 40:976df7c37ad5 203 __IO uint32_t TCR;
emilmont 40:976df7c37ad5 204 __IO uint32_t TC;
emilmont 40:976df7c37ad5 205 __IO uint32_t PR;
emilmont 40:976df7c37ad5 206 __IO uint32_t PC;
emilmont 40:976df7c37ad5 207 __IO uint32_t MCR;
emilmont 40:976df7c37ad5 208 __IO uint32_t MR0;
emilmont 40:976df7c37ad5 209 __IO uint32_t MR1;
emilmont 40:976df7c37ad5 210 __IO uint32_t MR2;
emilmont 40:976df7c37ad5 211 __IO uint32_t MR3;
emilmont 40:976df7c37ad5 212 __IO uint32_t CCR;
emilmont 40:976df7c37ad5 213 __I uint32_t CR0;
emilmont 40:976df7c37ad5 214 __I uint32_t CR1;
emilmont 40:976df7c37ad5 215 uint32_t RESERVED0[2];
emilmont 40:976df7c37ad5 216 __IO uint32_t EMR;
emilmont 40:976df7c37ad5 217 uint32_t RESERVED1[12];
emilmont 40:976df7c37ad5 218 __IO uint32_t CTCR;
emilmont 40:976df7c37ad5 219 } LPC_TIM_TypeDef;
emilmont 40:976df7c37ad5 220
emilmont 40:976df7c37ad5 221 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
emilmont 40:976df7c37ad5 222 typedef struct
emilmont 40:976df7c37ad5 223 {
emilmont 40:976df7c37ad5 224 __IO uint32_t IR;
emilmont 40:976df7c37ad5 225 __IO uint32_t TCR;
emilmont 40:976df7c37ad5 226 __IO uint32_t TC;
emilmont 40:976df7c37ad5 227 __IO uint32_t PR;
emilmont 40:976df7c37ad5 228 __IO uint32_t PC;
emilmont 40:976df7c37ad5 229 __IO uint32_t MCR;
emilmont 40:976df7c37ad5 230 __IO uint32_t MR0;
emilmont 40:976df7c37ad5 231 __IO uint32_t MR1;
emilmont 40:976df7c37ad5 232 __IO uint32_t MR2;
emilmont 40:976df7c37ad5 233 __IO uint32_t MR3;
emilmont 40:976df7c37ad5 234 __IO uint32_t CCR;
emilmont 40:976df7c37ad5 235 __I uint32_t CR0;
emilmont 40:976df7c37ad5 236 __I uint32_t CR1;
emilmont 40:976df7c37ad5 237 __I uint32_t CR2;
emilmont 40:976df7c37ad5 238 __I uint32_t CR3;
emilmont 40:976df7c37ad5 239 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 240 __IO uint32_t MR4;
emilmont 40:976df7c37ad5 241 __IO uint32_t MR5;
emilmont 40:976df7c37ad5 242 __IO uint32_t MR6;
emilmont 40:976df7c37ad5 243 __IO uint32_t PCR;
emilmont 40:976df7c37ad5 244 __IO uint32_t LER;
emilmont 40:976df7c37ad5 245 uint32_t RESERVED1[7];
emilmont 40:976df7c37ad5 246 __IO uint32_t CTCR;
emilmont 40:976df7c37ad5 247 } LPC_PWM_TypeDef;
emilmont 40:976df7c37ad5 248
emilmont 40:976df7c37ad5 249 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
emilmont 40:976df7c37ad5 250 typedef struct
emilmont 40:976df7c37ad5 251 {
emilmont 40:976df7c37ad5 252 union {
emilmont 40:976df7c37ad5 253 __I uint8_t RBR;
emilmont 40:976df7c37ad5 254 __O uint8_t THR;
emilmont 40:976df7c37ad5 255 __IO uint8_t DLL;
emilmont 40:976df7c37ad5 256 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 257 };
emilmont 40:976df7c37ad5 258 union {
emilmont 40:976df7c37ad5 259 __IO uint8_t DLM;
emilmont 40:976df7c37ad5 260 __IO uint32_t IER;
emilmont 40:976df7c37ad5 261 };
emilmont 40:976df7c37ad5 262 union {
emilmont 40:976df7c37ad5 263 __I uint32_t IIR;
emilmont 40:976df7c37ad5 264 __O uint8_t FCR;
emilmont 40:976df7c37ad5 265 };
emilmont 40:976df7c37ad5 266 __IO uint8_t LCR;
emilmont 40:976df7c37ad5 267 uint8_t RESERVED1[7];
emilmont 40:976df7c37ad5 268 __IO uint8_t LSR;
emilmont 40:976df7c37ad5 269 uint8_t RESERVED2[7];
emilmont 40:976df7c37ad5 270 __IO uint8_t SCR;
emilmont 40:976df7c37ad5 271 uint8_t RESERVED3[3];
emilmont 40:976df7c37ad5 272 __IO uint32_t ACR;
emilmont 40:976df7c37ad5 273 __IO uint8_t ICR;
emilmont 40:976df7c37ad5 274 uint8_t RESERVED4[3];
emilmont 40:976df7c37ad5 275 __IO uint8_t FDR;
emilmont 40:976df7c37ad5 276 uint8_t RESERVED5[7];
emilmont 40:976df7c37ad5 277 __IO uint8_t TER;
emilmont 40:976df7c37ad5 278 uint8_t RESERVED6[27];
emilmont 40:976df7c37ad5 279 __IO uint8_t RS485CTRL;
emilmont 40:976df7c37ad5 280 uint8_t RESERVED7[3];
emilmont 40:976df7c37ad5 281 __IO uint8_t ADRMATCH;
emilmont 40:976df7c37ad5 282 } LPC_UART_TypeDef;
emilmont 40:976df7c37ad5 283
emilmont 40:976df7c37ad5 284 typedef struct
emilmont 40:976df7c37ad5 285 {
emilmont 40:976df7c37ad5 286 union {
emilmont 40:976df7c37ad5 287 __I uint8_t RBR;
emilmont 40:976df7c37ad5 288 __O uint8_t THR;
emilmont 40:976df7c37ad5 289 __IO uint8_t DLL;
emilmont 40:976df7c37ad5 290 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 291 };
emilmont 40:976df7c37ad5 292 union {
emilmont 40:976df7c37ad5 293 __IO uint8_t DLM;
emilmont 40:976df7c37ad5 294 __IO uint32_t IER;
emilmont 40:976df7c37ad5 295 };
emilmont 40:976df7c37ad5 296 union {
emilmont 40:976df7c37ad5 297 __I uint32_t IIR;
emilmont 40:976df7c37ad5 298 __O uint8_t FCR;
emilmont 40:976df7c37ad5 299 };
emilmont 40:976df7c37ad5 300 __IO uint8_t LCR;
emilmont 40:976df7c37ad5 301 uint8_t RESERVED1[3];
emilmont 40:976df7c37ad5 302 __IO uint8_t MCR;
emilmont 40:976df7c37ad5 303 uint8_t RESERVED2[3];
emilmont 40:976df7c37ad5 304 __IO uint8_t LSR;
emilmont 40:976df7c37ad5 305 uint8_t RESERVED3[3];
emilmont 40:976df7c37ad5 306 __IO uint8_t MSR;
emilmont 40:976df7c37ad5 307 uint8_t RESERVED4[3];
emilmont 40:976df7c37ad5 308 __IO uint8_t SCR;
emilmont 40:976df7c37ad5 309 uint8_t RESERVED5[3];
emilmont 40:976df7c37ad5 310 __IO uint32_t ACR;
emilmont 40:976df7c37ad5 311 uint32_t RESERVED6;
emilmont 40:976df7c37ad5 312 __IO uint32_t FDR;
emilmont 40:976df7c37ad5 313 uint32_t RESERVED7;
emilmont 40:976df7c37ad5 314 __IO uint8_t TER;
emilmont 40:976df7c37ad5 315 uint8_t RESERVED8[27];
emilmont 40:976df7c37ad5 316 __IO uint8_t RS485CTRL;
emilmont 40:976df7c37ad5 317 uint8_t RESERVED9[3];
emilmont 40:976df7c37ad5 318 __IO uint8_t ADRMATCH;
emilmont 40:976df7c37ad5 319 uint8_t RESERVED10[3];
emilmont 40:976df7c37ad5 320 __IO uint8_t RS485DLY;
emilmont 40:976df7c37ad5 321 } LPC_UART1_TypeDef;
emilmont 40:976df7c37ad5 322
emilmont 40:976df7c37ad5 323 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
emilmont 40:976df7c37ad5 324 typedef struct
emilmont 40:976df7c37ad5 325 {
emilmont 40:976df7c37ad5 326 __IO uint32_t SPCR;
emilmont 40:976df7c37ad5 327 __I uint32_t SPSR;
emilmont 40:976df7c37ad5 328 __IO uint32_t SPDR;
emilmont 40:976df7c37ad5 329 __IO uint32_t SPCCR;
emilmont 40:976df7c37ad5 330 uint32_t RESERVED0[3];
emilmont 40:976df7c37ad5 331 __IO uint32_t SPINT;
emilmont 40:976df7c37ad5 332 } LPC_SPI_TypeDef;
emilmont 40:976df7c37ad5 333
emilmont 40:976df7c37ad5 334 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
emilmont 40:976df7c37ad5 335 typedef struct
emilmont 40:976df7c37ad5 336 {
emilmont 40:976df7c37ad5 337 __IO uint32_t CR0;
emilmont 40:976df7c37ad5 338 __IO uint32_t CR1;
emilmont 40:976df7c37ad5 339 __IO uint32_t DR;
emilmont 40:976df7c37ad5 340 __I uint32_t SR;
emilmont 40:976df7c37ad5 341 __IO uint32_t CPSR;
emilmont 40:976df7c37ad5 342 __IO uint32_t IMSC;
emilmont 40:976df7c37ad5 343 __IO uint32_t RIS;
emilmont 40:976df7c37ad5 344 __IO uint32_t MIS;
emilmont 40:976df7c37ad5 345 __IO uint32_t ICR;
emilmont 40:976df7c37ad5 346 __IO uint32_t DMACR;
emilmont 40:976df7c37ad5 347 } LPC_SSP_TypeDef;
emilmont 40:976df7c37ad5 348
emilmont 40:976df7c37ad5 349 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
emilmont 40:976df7c37ad5 350 typedef struct
emilmont 40:976df7c37ad5 351 {
emilmont 40:976df7c37ad5 352 __IO uint32_t I2CONSET;
emilmont 40:976df7c37ad5 353 __I uint32_t I2STAT;
emilmont 40:976df7c37ad5 354 __IO uint32_t I2DAT;
emilmont 40:976df7c37ad5 355 __IO uint32_t I2ADR0;
emilmont 40:976df7c37ad5 356 __IO uint32_t I2SCLH;
emilmont 40:976df7c37ad5 357 __IO uint32_t I2SCLL;
emilmont 40:976df7c37ad5 358 __O uint32_t I2CONCLR;
emilmont 40:976df7c37ad5 359 __IO uint32_t MMCTRL;
emilmont 40:976df7c37ad5 360 __IO uint32_t I2ADR1;
emilmont 40:976df7c37ad5 361 __IO uint32_t I2ADR2;
emilmont 40:976df7c37ad5 362 __IO uint32_t I2ADR3;
emilmont 40:976df7c37ad5 363 __I uint32_t I2DATA_BUFFER;
emilmont 40:976df7c37ad5 364 __IO uint32_t I2MASK0;
emilmont 40:976df7c37ad5 365 __IO uint32_t I2MASK1;
emilmont 40:976df7c37ad5 366 __IO uint32_t I2MASK2;
emilmont 40:976df7c37ad5 367 __IO uint32_t I2MASK3;
emilmont 40:976df7c37ad5 368 } LPC_I2C_TypeDef;
emilmont 40:976df7c37ad5 369
emilmont 40:976df7c37ad5 370 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
emilmont 40:976df7c37ad5 371 typedef struct
emilmont 40:976df7c37ad5 372 {
emilmont 40:976df7c37ad5 373 __IO uint32_t I2SDAO;
emilmont 40:976df7c37ad5 374 __I uint32_t I2SDAI;
emilmont 40:976df7c37ad5 375 __O uint32_t I2STXFIFO;
emilmont 40:976df7c37ad5 376 __I uint32_t I2SRXFIFO;
emilmont 40:976df7c37ad5 377 __I uint32_t I2SSTATE;
emilmont 40:976df7c37ad5 378 __IO uint32_t I2SDMA1;
emilmont 40:976df7c37ad5 379 __IO uint32_t I2SDMA2;
emilmont 40:976df7c37ad5 380 __IO uint32_t I2SIRQ;
emilmont 40:976df7c37ad5 381 __IO uint32_t I2STXRATE;
emilmont 40:976df7c37ad5 382 __IO uint32_t I2SRXRATE;
emilmont 40:976df7c37ad5 383 __IO uint32_t I2STXBITRATE;
emilmont 40:976df7c37ad5 384 __IO uint32_t I2SRXBITRATE;
emilmont 40:976df7c37ad5 385 __IO uint32_t I2STXMODE;
emilmont 40:976df7c37ad5 386 __IO uint32_t I2SRXMODE;
emilmont 40:976df7c37ad5 387 } LPC_I2S_TypeDef;
emilmont 40:976df7c37ad5 388
emilmont 40:976df7c37ad5 389 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
emilmont 40:976df7c37ad5 390 typedef struct
emilmont 40:976df7c37ad5 391 {
emilmont 40:976df7c37ad5 392 __IO uint8_t ILR;
emilmont 40:976df7c37ad5 393 uint8_t RESERVED0[3];
emilmont 40:976df7c37ad5 394 __IO uint8_t CTC;
emilmont 40:976df7c37ad5 395 uint8_t RESERVED1[3];
emilmont 40:976df7c37ad5 396 __IO uint8_t CCR;
emilmont 40:976df7c37ad5 397 uint8_t RESERVED2[3];
emilmont 40:976df7c37ad5 398 __IO uint8_t CIIR;
emilmont 40:976df7c37ad5 399 uint8_t RESERVED3[3];
emilmont 40:976df7c37ad5 400 __IO uint8_t AMR;
emilmont 40:976df7c37ad5 401 uint8_t RESERVED4[3];
emilmont 40:976df7c37ad5 402 __I uint32_t CTIME0;
emilmont 40:976df7c37ad5 403 __I uint32_t CTIME1;
emilmont 40:976df7c37ad5 404 __I uint32_t CTIME2;
emilmont 40:976df7c37ad5 405 __IO uint8_t SEC;
emilmont 40:976df7c37ad5 406 uint8_t RESERVED5[3];
emilmont 40:976df7c37ad5 407 __IO uint8_t MIN;
emilmont 40:976df7c37ad5 408 uint8_t RESERVED6[3];
emilmont 40:976df7c37ad5 409 __IO uint8_t HOUR;
emilmont 40:976df7c37ad5 410 uint8_t RESERVED7[3];
emilmont 40:976df7c37ad5 411 __IO uint8_t DOM;
emilmont 40:976df7c37ad5 412 uint8_t RESERVED8[3];
emilmont 40:976df7c37ad5 413 __IO uint8_t DOW;
emilmont 40:976df7c37ad5 414 uint8_t RESERVED9[3];
emilmont 40:976df7c37ad5 415 __IO uint16_t DOY;
emilmont 40:976df7c37ad5 416 uint16_t RESERVED10;
emilmont 40:976df7c37ad5 417 __IO uint8_t MONTH;
emilmont 40:976df7c37ad5 418 uint8_t RESERVED11[3];
emilmont 40:976df7c37ad5 419 __IO uint16_t YEAR;
emilmont 40:976df7c37ad5 420 uint16_t RESERVED12;
emilmont 40:976df7c37ad5 421 __IO uint32_t CALIBRATION;
emilmont 40:976df7c37ad5 422 __IO uint32_t GPREG0;
emilmont 40:976df7c37ad5 423 __IO uint32_t GPREG1;
emilmont 40:976df7c37ad5 424 __IO uint32_t GPREG2;
emilmont 40:976df7c37ad5 425 __IO uint32_t GPREG3;
emilmont 40:976df7c37ad5 426 __IO uint32_t GPREG4;
emilmont 40:976df7c37ad5 427 __IO uint8_t WAKEUPDIS;
emilmont 40:976df7c37ad5 428 uint8_t RESERVED13[3];
emilmont 40:976df7c37ad5 429 __IO uint8_t PWRCTRL;
emilmont 40:976df7c37ad5 430 uint8_t RESERVED14[3];
emilmont 40:976df7c37ad5 431 __IO uint8_t ALSEC;
emilmont 40:976df7c37ad5 432 uint8_t RESERVED15[3];
emilmont 40:976df7c37ad5 433 __IO uint8_t ALMIN;
emilmont 40:976df7c37ad5 434 uint8_t RESERVED16[3];
emilmont 40:976df7c37ad5 435 __IO uint8_t ALHOUR;
emilmont 40:976df7c37ad5 436 uint8_t RESERVED17[3];
emilmont 40:976df7c37ad5 437 __IO uint8_t ALDOM;
emilmont 40:976df7c37ad5 438 uint8_t RESERVED18[3];
emilmont 40:976df7c37ad5 439 __IO uint8_t ALDOW;
emilmont 40:976df7c37ad5 440 uint8_t RESERVED19[3];
emilmont 40:976df7c37ad5 441 __IO uint16_t ALDOY;
emilmont 40:976df7c37ad5 442 uint16_t RESERVED20;
emilmont 40:976df7c37ad5 443 __IO uint8_t ALMON;
emilmont 40:976df7c37ad5 444 uint8_t RESERVED21[3];
emilmont 40:976df7c37ad5 445 __IO uint16_t ALYEAR;
emilmont 40:976df7c37ad5 446 uint16_t RESERVED22;
emilmont 40:976df7c37ad5 447 } LPC_RTC_TypeDef;
emilmont 40:976df7c37ad5 448
emilmont 40:976df7c37ad5 449 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
emilmont 40:976df7c37ad5 450 typedef struct
emilmont 40:976df7c37ad5 451 {
emilmont 40:976df7c37ad5 452 __IO uint8_t WDMOD;
emilmont 40:976df7c37ad5 453 uint8_t RESERVED0[3];
emilmont 40:976df7c37ad5 454 __IO uint32_t WDTC;
emilmont 40:976df7c37ad5 455 __O uint8_t WDFEED;
emilmont 40:976df7c37ad5 456 uint8_t RESERVED1[3];
emilmont 40:976df7c37ad5 457 __I uint32_t WDTV;
emilmont 40:976df7c37ad5 458 __IO uint32_t WDCLKSEL;
emilmont 40:976df7c37ad5 459 } LPC_WDT_TypeDef;
emilmont 40:976df7c37ad5 460
emilmont 40:976df7c37ad5 461 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
emilmont 40:976df7c37ad5 462 typedef struct
emilmont 40:976df7c37ad5 463 {
emilmont 40:976df7c37ad5 464 __IO uint32_t ADCR;
emilmont 40:976df7c37ad5 465 __IO uint32_t ADGDR;
emilmont 40:976df7c37ad5 466 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 467 __IO uint32_t ADINTEN;
emilmont 40:976df7c37ad5 468 __I uint32_t ADDR0;
emilmont 40:976df7c37ad5 469 __I uint32_t ADDR1;
emilmont 40:976df7c37ad5 470 __I uint32_t ADDR2;
emilmont 40:976df7c37ad5 471 __I uint32_t ADDR3;
emilmont 40:976df7c37ad5 472 __I uint32_t ADDR4;
emilmont 40:976df7c37ad5 473 __I uint32_t ADDR5;
emilmont 40:976df7c37ad5 474 __I uint32_t ADDR6;
emilmont 40:976df7c37ad5 475 __I uint32_t ADDR7;
emilmont 40:976df7c37ad5 476 __I uint32_t ADSTAT;
emilmont 40:976df7c37ad5 477 __IO uint32_t ADTRM;
emilmont 40:976df7c37ad5 478 } LPC_ADC_TypeDef;
emilmont 40:976df7c37ad5 479
emilmont 40:976df7c37ad5 480 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
emilmont 40:976df7c37ad5 481 typedef struct
emilmont 40:976df7c37ad5 482 {
emilmont 40:976df7c37ad5 483 __IO uint32_t DACR;
emilmont 40:976df7c37ad5 484 __IO uint32_t DACCTRL;
emilmont 40:976df7c37ad5 485 __IO uint16_t DACCNTVAL;
emilmont 40:976df7c37ad5 486 } LPC_DAC_TypeDef;
emilmont 40:976df7c37ad5 487
emilmont 40:976df7c37ad5 488 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
emilmont 40:976df7c37ad5 489 typedef struct
emilmont 40:976df7c37ad5 490 {
emilmont 40:976df7c37ad5 491 __IO uint32_t MCIPower; /* Power control */
emilmont 40:976df7c37ad5 492 __IO uint32_t MCIClock; /* Clock control */
emilmont 40:976df7c37ad5 493 __IO uint32_t MCIArgument;
emilmont 40:976df7c37ad5 494 __IO uint32_t MMCCommand;
emilmont 40:976df7c37ad5 495 __I uint32_t MCIRespCmd;
emilmont 40:976df7c37ad5 496 __I uint32_t MCIResponse0;
emilmont 40:976df7c37ad5 497 __I uint32_t MCIResponse1;
emilmont 40:976df7c37ad5 498 __I uint32_t MCIResponse2;
emilmont 40:976df7c37ad5 499 __I uint32_t MCIResponse3;
emilmont 40:976df7c37ad5 500 __IO uint32_t MCIDataTimer;
emilmont 40:976df7c37ad5 501 __IO uint32_t MCIDataLength;
emilmont 40:976df7c37ad5 502 __IO uint32_t MCIDataCtrl;
emilmont 40:976df7c37ad5 503 __I uint32_t MCIDataCnt;
emilmont 40:976df7c37ad5 504 } LPC_MCI_TypeDef;
emilmont 40:976df7c37ad5 505
emilmont 40:976df7c37ad5 506 /*------------- Controller Area Network (CAN) --------------------------------*/
emilmont 40:976df7c37ad5 507 typedef struct
emilmont 40:976df7c37ad5 508 {
emilmont 40:976df7c37ad5 509 __IO uint32_t mask[512]; /* ID Masks */
emilmont 40:976df7c37ad5 510 } LPC_CANAF_RAM_TypeDef;
emilmont 40:976df7c37ad5 511
emilmont 40:976df7c37ad5 512 typedef struct /* Acceptance Filter Registers */
emilmont 40:976df7c37ad5 513 {
emilmont 40:976df7c37ad5 514 __IO uint32_t AFMR;
emilmont 40:976df7c37ad5 515 __IO uint32_t SFF_sa;
emilmont 40:976df7c37ad5 516 __IO uint32_t SFF_GRP_sa;
emilmont 40:976df7c37ad5 517 __IO uint32_t EFF_sa;
emilmont 40:976df7c37ad5 518 __IO uint32_t EFF_GRP_sa;
emilmont 40:976df7c37ad5 519 __IO uint32_t ENDofTable;
emilmont 40:976df7c37ad5 520 __I uint32_t LUTerrAd;
emilmont 40:976df7c37ad5 521 __I uint32_t LUTerr;
emilmont 40:976df7c37ad5 522 } LPC_CANAF_TypeDef;
emilmont 40:976df7c37ad5 523
emilmont 40:976df7c37ad5 524 typedef struct /* Central Registers */
emilmont 40:976df7c37ad5 525 {
emilmont 40:976df7c37ad5 526 __I uint32_t CANTxSR;
emilmont 40:976df7c37ad5 527 __I uint32_t CANRxSR;
emilmont 40:976df7c37ad5 528 __I uint32_t CANMSR;
emilmont 40:976df7c37ad5 529 } LPC_CANCR_TypeDef;
emilmont 40:976df7c37ad5 530
emilmont 40:976df7c37ad5 531 typedef struct /* Controller Registers */
emilmont 40:976df7c37ad5 532 {
emilmont 40:976df7c37ad5 533 __IO uint32_t MOD;
emilmont 40:976df7c37ad5 534 __O uint32_t CMR;
emilmont 40:976df7c37ad5 535 __IO uint32_t GSR;
emilmont 40:976df7c37ad5 536 __I uint32_t ICR;
emilmont 40:976df7c37ad5 537 __IO uint32_t IER;
emilmont 40:976df7c37ad5 538 __IO uint32_t BTR;
emilmont 40:976df7c37ad5 539 __IO uint32_t EWL;
emilmont 40:976df7c37ad5 540 __I uint32_t SR;
emilmont 40:976df7c37ad5 541 __IO uint32_t RFS;
emilmont 40:976df7c37ad5 542 __IO uint32_t RID;
emilmont 40:976df7c37ad5 543 __IO uint32_t RDA;
emilmont 40:976df7c37ad5 544 __IO uint32_t RDB;
emilmont 40:976df7c37ad5 545 __IO uint32_t TFI1;
emilmont 40:976df7c37ad5 546 __IO uint32_t TID1;
emilmont 40:976df7c37ad5 547 __IO uint32_t TDA1;
emilmont 40:976df7c37ad5 548 __IO uint32_t TDB1;
emilmont 40:976df7c37ad5 549 __IO uint32_t TFI2;
emilmont 40:976df7c37ad5 550 __IO uint32_t TID2;
emilmont 40:976df7c37ad5 551 __IO uint32_t TDA2;
emilmont 40:976df7c37ad5 552 __IO uint32_t TDB2;
emilmont 40:976df7c37ad5 553 __IO uint32_t TFI3;
emilmont 40:976df7c37ad5 554 __IO uint32_t TID3;
emilmont 40:976df7c37ad5 555 __IO uint32_t TDA3;
emilmont 40:976df7c37ad5 556 __IO uint32_t TDB3;
emilmont 40:976df7c37ad5 557 } LPC_CAN_TypeDef;
emilmont 40:976df7c37ad5 558
emilmont 40:976df7c37ad5 559 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
emilmont 40:976df7c37ad5 560 typedef struct /* Common Registers */
emilmont 40:976df7c37ad5 561 {
emilmont 40:976df7c37ad5 562 __I uint32_t DMACIntStat;
emilmont 40:976df7c37ad5 563 __I uint32_t DMACIntTCStat;
emilmont 40:976df7c37ad5 564 __O uint32_t DMACIntTCClear;
emilmont 40:976df7c37ad5 565 __I uint32_t DMACIntErrStat;
emilmont 40:976df7c37ad5 566 __O uint32_t DMACIntErrClr;
emilmont 40:976df7c37ad5 567 __I uint32_t DMACRawIntTCStat;
emilmont 40:976df7c37ad5 568 __I uint32_t DMACRawIntErrStat;
emilmont 40:976df7c37ad5 569 __I uint32_t DMACEnbldChns;
emilmont 40:976df7c37ad5 570 __IO uint32_t DMACSoftBReq;
emilmont 40:976df7c37ad5 571 __IO uint32_t DMACSoftSReq;
emilmont 40:976df7c37ad5 572 __IO uint32_t DMACSoftLBReq;
emilmont 40:976df7c37ad5 573 __IO uint32_t DMACSoftLSReq;
emilmont 40:976df7c37ad5 574 __IO uint32_t DMACConfig;
emilmont 40:976df7c37ad5 575 __IO uint32_t DMACSync;
emilmont 40:976df7c37ad5 576 } LPC_GPDMA_TypeDef;
emilmont 40:976df7c37ad5 577
emilmont 40:976df7c37ad5 578 typedef struct /* Channel Registers */
emilmont 40:976df7c37ad5 579 {
emilmont 40:976df7c37ad5 580 __IO uint32_t DMACCSrcAddr;
emilmont 40:976df7c37ad5 581 __IO uint32_t DMACCDestAddr;
emilmont 40:976df7c37ad5 582 __IO uint32_t DMACCLLI;
emilmont 40:976df7c37ad5 583 __IO uint32_t DMACCControl;
emilmont 40:976df7c37ad5 584 __IO uint32_t DMACCConfig;
emilmont 40:976df7c37ad5 585 } LPC_GPDMACH_TypeDef;
emilmont 40:976df7c37ad5 586
emilmont 40:976df7c37ad5 587 /*------------- Universal Serial Bus (USB) -----------------------------------*/
emilmont 40:976df7c37ad5 588 typedef struct
emilmont 40:976df7c37ad5 589 {
emilmont 40:976df7c37ad5 590 __I uint32_t HcRevision; /* USB Host Registers */
emilmont 40:976df7c37ad5 591 __IO uint32_t HcControl;
emilmont 40:976df7c37ad5 592 __IO uint32_t HcCommandStatus;
emilmont 40:976df7c37ad5 593 __IO uint32_t HcInterruptStatus;
emilmont 40:976df7c37ad5 594 __IO uint32_t HcInterruptEnable;
emilmont 40:976df7c37ad5 595 __IO uint32_t HcInterruptDisable;
emilmont 40:976df7c37ad5 596 __IO uint32_t HcHCCA;
emilmont 40:976df7c37ad5 597 __I uint32_t HcPeriodCurrentED;
emilmont 40:976df7c37ad5 598 __IO uint32_t HcControlHeadED;
emilmont 40:976df7c37ad5 599 __IO uint32_t HcControlCurrentED;
emilmont 40:976df7c37ad5 600 __IO uint32_t HcBulkHeadED;
emilmont 40:976df7c37ad5 601 __IO uint32_t HcBulkCurrentED;
emilmont 40:976df7c37ad5 602 __I uint32_t HcDoneHead;
emilmont 40:976df7c37ad5 603 __IO uint32_t HcFmInterval;
emilmont 40:976df7c37ad5 604 __I uint32_t HcFmRemaining;
emilmont 40:976df7c37ad5 605 __I uint32_t HcFmNumber;
emilmont 40:976df7c37ad5 606 __IO uint32_t HcPeriodicStart;
emilmont 40:976df7c37ad5 607 __IO uint32_t HcLSTreshold;
emilmont 40:976df7c37ad5 608 __IO uint32_t HcRhDescriptorA;
emilmont 40:976df7c37ad5 609 __IO uint32_t HcRhDescriptorB;
emilmont 40:976df7c37ad5 610 __IO uint32_t HcRhStatus;
emilmont 40:976df7c37ad5 611 __IO uint32_t HcRhPortStatus1;
emilmont 40:976df7c37ad5 612 __IO uint32_t HcRhPortStatus2;
emilmont 40:976df7c37ad5 613 uint32_t RESERVED0[40];
emilmont 40:976df7c37ad5 614 __I uint32_t Module_ID;
emilmont 40:976df7c37ad5 615
emilmont 40:976df7c37ad5 616 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
emilmont 40:976df7c37ad5 617 __IO uint32_t OTGIntEn;
emilmont 40:976df7c37ad5 618 __O uint32_t OTGIntSet;
emilmont 40:976df7c37ad5 619 __O uint32_t OTGIntClr;
emilmont 40:976df7c37ad5 620 __IO uint32_t OTGStCtrl;
emilmont 40:976df7c37ad5 621 __IO uint32_t OTGTmr;
emilmont 40:976df7c37ad5 622 uint32_t RESERVED1[58];
emilmont 40:976df7c37ad5 623
emilmont 40:976df7c37ad5 624 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
emilmont 40:976df7c37ad5 625 __IO uint32_t USBDevIntEn;
emilmont 40:976df7c37ad5 626 __O uint32_t USBDevIntClr;
emilmont 40:976df7c37ad5 627 __O uint32_t USBDevIntSet;
emilmont 40:976df7c37ad5 628
emilmont 40:976df7c37ad5 629 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
emilmont 40:976df7c37ad5 630 __I uint32_t USBCmdData;
emilmont 40:976df7c37ad5 631
emilmont 40:976df7c37ad5 632 __I uint32_t USBRxData; /* USB Device Transfer Registers */
emilmont 40:976df7c37ad5 633 __O uint32_t USBTxData;
emilmont 40:976df7c37ad5 634 __I uint32_t USBRxPLen;
emilmont 40:976df7c37ad5 635 __O uint32_t USBTxPLen;
emilmont 40:976df7c37ad5 636 __IO uint32_t USBCtrl;
emilmont 40:976df7c37ad5 637 __O uint32_t USBDevIntPri;
emilmont 40:976df7c37ad5 638
emilmont 40:976df7c37ad5 639 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
emilmont 40:976df7c37ad5 640 __IO uint32_t USBEpIntEn;
emilmont 40:976df7c37ad5 641 __O uint32_t USBEpIntClr;
emilmont 40:976df7c37ad5 642 __O uint32_t USBEpIntSet;
emilmont 40:976df7c37ad5 643 __O uint32_t USBEpIntPri;
emilmont 40:976df7c37ad5 644
emilmont 40:976df7c37ad5 645 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
emilmont 40:976df7c37ad5 646 __O uint32_t USBEpInd;
emilmont 40:976df7c37ad5 647 __IO uint32_t USBMaxPSize;
emilmont 40:976df7c37ad5 648
emilmont 40:976df7c37ad5 649 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
emilmont 40:976df7c37ad5 650 __O uint32_t USBDMARClr;
emilmont 40:976df7c37ad5 651 __O uint32_t USBDMARSet;
emilmont 40:976df7c37ad5 652 uint32_t RESERVED2[9];
emilmont 40:976df7c37ad5 653 __IO uint32_t USBUDCAH;
emilmont 40:976df7c37ad5 654 __I uint32_t USBEpDMASt;
emilmont 40:976df7c37ad5 655 __O uint32_t USBEpDMAEn;
emilmont 40:976df7c37ad5 656 __O uint32_t USBEpDMADis;
emilmont 40:976df7c37ad5 657 __I uint32_t USBDMAIntSt;
emilmont 40:976df7c37ad5 658 __IO uint32_t USBDMAIntEn;
emilmont 40:976df7c37ad5 659 uint32_t RESERVED3[2];
emilmont 40:976df7c37ad5 660 __I uint32_t USBEoTIntSt;
emilmont 40:976df7c37ad5 661 __O uint32_t USBEoTIntClr;
emilmont 40:976df7c37ad5 662 __O uint32_t USBEoTIntSet;
emilmont 40:976df7c37ad5 663 __I uint32_t USBNDDRIntSt;
emilmont 40:976df7c37ad5 664 __O uint32_t USBNDDRIntClr;
emilmont 40:976df7c37ad5 665 __O uint32_t USBNDDRIntSet;
emilmont 40:976df7c37ad5 666 __I uint32_t USBSysErrIntSt;
emilmont 40:976df7c37ad5 667 __O uint32_t USBSysErrIntClr;
emilmont 40:976df7c37ad5 668 __O uint32_t USBSysErrIntSet;
emilmont 40:976df7c37ad5 669 uint32_t RESERVED4[15];
emilmont 40:976df7c37ad5 670
emilmont 40:976df7c37ad5 671 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
emilmont 40:976df7c37ad5 672 __O uint32_t I2C_WO;
emilmont 40:976df7c37ad5 673 __I uint32_t I2C_STS;
emilmont 40:976df7c37ad5 674 __IO uint32_t I2C_CTL;
emilmont 40:976df7c37ad5 675 __IO uint32_t I2C_CLKHI;
emilmont 40:976df7c37ad5 676 __O uint32_t I2C_CLKLO;
emilmont 40:976df7c37ad5 677 uint32_t RESERVED5[823];
emilmont 40:976df7c37ad5 678
emilmont 40:976df7c37ad5 679 union {
emilmont 40:976df7c37ad5 680 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
emilmont 40:976df7c37ad5 681 __IO uint32_t OTGClkCtrl;
emilmont 40:976df7c37ad5 682 };
emilmont 40:976df7c37ad5 683 union {
emilmont 40:976df7c37ad5 684 __I uint32_t USBClkSt;
emilmont 40:976df7c37ad5 685 __I uint32_t OTGClkSt;
emilmont 40:976df7c37ad5 686 };
emilmont 40:976df7c37ad5 687 } LPC_USB_TypeDef;
emilmont 40:976df7c37ad5 688
emilmont 40:976df7c37ad5 689 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
emilmont 40:976df7c37ad5 690 typedef struct
emilmont 40:976df7c37ad5 691 {
emilmont 40:976df7c37ad5 692 __IO uint32_t MAC1; /* MAC Registers */
emilmont 40:976df7c37ad5 693 __IO uint32_t MAC2;
emilmont 40:976df7c37ad5 694 __IO uint32_t IPGT;
emilmont 40:976df7c37ad5 695 __IO uint32_t IPGR;
emilmont 40:976df7c37ad5 696 __IO uint32_t CLRT;
emilmont 40:976df7c37ad5 697 __IO uint32_t MAXF;
emilmont 40:976df7c37ad5 698 __IO uint32_t SUPP;
emilmont 40:976df7c37ad5 699 __IO uint32_t TEST;
emilmont 40:976df7c37ad5 700 __IO uint32_t MCFG;
emilmont 40:976df7c37ad5 701 __IO uint32_t MCMD;
emilmont 40:976df7c37ad5 702 __IO uint32_t MADR;
emilmont 40:976df7c37ad5 703 __O uint32_t MWTD;
emilmont 40:976df7c37ad5 704 __I uint32_t MRDD;
emilmont 40:976df7c37ad5 705 __I uint32_t MIND;
emilmont 40:976df7c37ad5 706 uint32_t RESERVED0[2];
emilmont 40:976df7c37ad5 707 __IO uint32_t SA0;
emilmont 40:976df7c37ad5 708 __IO uint32_t SA1;
emilmont 40:976df7c37ad5 709 __IO uint32_t SA2;
emilmont 40:976df7c37ad5 710 uint32_t RESERVED1[45];
emilmont 40:976df7c37ad5 711 __IO uint32_t Command; /* Control Registers */
emilmont 40:976df7c37ad5 712 __I uint32_t Status;
emilmont 40:976df7c37ad5 713 __IO uint32_t RxDescriptor;
emilmont 40:976df7c37ad5 714 __IO uint32_t RxStatus;
emilmont 40:976df7c37ad5 715 __IO uint32_t RxDescriptorNumber;
emilmont 40:976df7c37ad5 716 __I uint32_t RxProduceIndex;
emilmont 40:976df7c37ad5 717 __IO uint32_t RxConsumeIndex;
emilmont 40:976df7c37ad5 718 __IO uint32_t TxDescriptor;
emilmont 40:976df7c37ad5 719 __IO uint32_t TxStatus;
emilmont 40:976df7c37ad5 720 __IO uint32_t TxDescriptorNumber;
emilmont 40:976df7c37ad5 721 __IO uint32_t TxProduceIndex;
emilmont 40:976df7c37ad5 722 __I uint32_t TxConsumeIndex;
emilmont 40:976df7c37ad5 723 uint32_t RESERVED2[10];
emilmont 40:976df7c37ad5 724 __I uint32_t TSV0;
emilmont 40:976df7c37ad5 725 __I uint32_t TSV1;
emilmont 40:976df7c37ad5 726 __I uint32_t RSV;
emilmont 40:976df7c37ad5 727 uint32_t RESERVED3[3];
emilmont 40:976df7c37ad5 728 __IO uint32_t FlowControlCounter;
emilmont 40:976df7c37ad5 729 __I uint32_t FlowControlStatus;
emilmont 40:976df7c37ad5 730 uint32_t RESERVED4[34];
emilmont 40:976df7c37ad5 731 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
emilmont 40:976df7c37ad5 732 __IO uint32_t RxFilterWoLStatus;
emilmont 40:976df7c37ad5 733 __IO uint32_t RxFilterWoLClear;
emilmont 40:976df7c37ad5 734 uint32_t RESERVED5;
emilmont 40:976df7c37ad5 735 __IO uint32_t HashFilterL;
emilmont 40:976df7c37ad5 736 __IO uint32_t HashFilterH;
emilmont 40:976df7c37ad5 737 uint32_t RESERVED6[882];
emilmont 40:976df7c37ad5 738 __I uint32_t IntStatus; /* Module Control Registers */
emilmont 40:976df7c37ad5 739 __IO uint32_t IntEnable;
emilmont 40:976df7c37ad5 740 __O uint32_t IntClear;
emilmont 40:976df7c37ad5 741 __O uint32_t IntSet;
emilmont 40:976df7c37ad5 742 uint32_t RESERVED7;
emilmont 40:976df7c37ad5 743 __IO uint32_t PowerDown;
emilmont 40:976df7c37ad5 744 uint32_t RESERVED8;
emilmont 40:976df7c37ad5 745 __IO uint32_t Module_ID;
emilmont 40:976df7c37ad5 746 } LPC_EMAC_TypeDef;
emilmont 40:976df7c37ad5 747
emilmont 40:976df7c37ad5 748 #if defined ( __CC_ARM )
emilmont 40:976df7c37ad5 749 #pragma no_anon_unions
emilmont 40:976df7c37ad5 750 #endif
emilmont 40:976df7c37ad5 751
emilmont 40:976df7c37ad5 752 /******************************************************************************/
emilmont 40:976df7c37ad5 753 /* Peripheral memory map */
emilmont 40:976df7c37ad5 754 /******************************************************************************/
emilmont 40:976df7c37ad5 755 /* Base addresses */
emilmont 40:976df7c37ad5 756
emilmont 40:976df7c37ad5 757 /* AHB Peripheral # 0 */
emilmont 40:976df7c37ad5 758
emilmont 40:976df7c37ad5 759 /*
emilmont 40:976df7c37ad5 760 #define FLASH_BASE (0x00000000UL)
emilmont 40:976df7c37ad5 761 #define RAM_BASE (0x10000000UL)
emilmont 40:976df7c37ad5 762 #define GPIO_BASE (0x2009C000UL)
emilmont 40:976df7c37ad5 763 #define APB0_BASE (0x40000000UL)
emilmont 40:976df7c37ad5 764 #define APB1_BASE (0x40080000UL)
emilmont 40:976df7c37ad5 765 #define AHB_BASE (0x50000000UL)
emilmont 40:976df7c37ad5 766 #define CM3_BASE (0xE0000000UL)
emilmont 40:976df7c37ad5 767 */
emilmont 40:976df7c37ad5 768
emilmont 40:976df7c37ad5 769 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
emilmont 40:976df7c37ad5 770
emilmont 40:976df7c37ad5 771 #define LPC_WDT_BASE (0xE0000000)
emilmont 40:976df7c37ad5 772 #define LPC_TIM0_BASE (0xE0004000)
emilmont 40:976df7c37ad5 773 #define LPC_TIM1_BASE (0xE0008000)
emilmont 40:976df7c37ad5 774 #define LPC_UART0_BASE (0xE000C000)
emilmont 40:976df7c37ad5 775 #define LPC_UART1_BASE (0xE0010000)
emilmont 40:976df7c37ad5 776 #define LPC_PWM1_BASE (0xE0018000)
emilmont 40:976df7c37ad5 777 #define LPC_I2C0_BASE (0xE001C000)
emilmont 40:976df7c37ad5 778 #define LPC_SPI_BASE (0xE0020000)
emilmont 40:976df7c37ad5 779 #define LPC_RTC_BASE (0xE0024000)
emilmont 40:976df7c37ad5 780 #define LPC_GPIOINT_BASE (0xE0028080)
emilmont 40:976df7c37ad5 781 #define LPC_PINCON_BASE (0xE002C000)
emilmont 40:976df7c37ad5 782 #define LPC_SSP1_BASE (0xE0030000)
emilmont 40:976df7c37ad5 783 #define LPC_ADC_BASE (0xE0034000)
emilmont 40:976df7c37ad5 784 #define LPC_CANAF_RAM_BASE (0xE0038000)
emilmont 40:976df7c37ad5 785 #define LPC_CANAF_BASE (0xE003C000)
emilmont 40:976df7c37ad5 786 #define LPC_CANCR_BASE (0xE0040000)
emilmont 40:976df7c37ad5 787 #define LPC_CAN1_BASE (0xE0044000)
emilmont 40:976df7c37ad5 788 #define LPC_CAN2_BASE (0xE0048000)
emilmont 40:976df7c37ad5 789 #define LPC_I2C1_BASE (0xE005C000)
emilmont 40:976df7c37ad5 790 #define LPC_SSP0_BASE (0xE0068000)
emilmont 40:976df7c37ad5 791 #define LPC_DAC_BASE (0xE006C000)
emilmont 40:976df7c37ad5 792 #define LPC_TIM2_BASE (0xE0070000)
emilmont 40:976df7c37ad5 793 #define LPC_TIM3_BASE (0xE0074000)
emilmont 40:976df7c37ad5 794 #define LPC_UART2_BASE (0xE0078000)
emilmont 40:976df7c37ad5 795 #define LPC_UART3_BASE (0xE007C000)
emilmont 40:976df7c37ad5 796 #define LPC_I2C2_BASE (0xE0080000)
emilmont 40:976df7c37ad5 797 #define LPC_I2S_BASE (0xE0088000)
emilmont 40:976df7c37ad5 798 #define LPC_MCI_BASE (0xE008C000)
emilmont 40:976df7c37ad5 799 #define LPC_SC_BASE (0xE01FC000)
emilmont 40:976df7c37ad5 800 #define LPC_EMAC_BASE (0xFFE00000)
emilmont 40:976df7c37ad5 801 #define LPC_GPDMA_BASE (0xFFE04000)
emilmont 40:976df7c37ad5 802 #define LPC_GPDMACH0_BASE (0xFFE04100)
emilmont 40:976df7c37ad5 803 #define LPC_GPDMACH1_BASE (0xFFE04120)
emilmont 40:976df7c37ad5 804 #define LPC_USB_BASE (0xFFE0C000)
emilmont 40:976df7c37ad5 805 #define LPC_VIC_BASE (0xFFFFF000)
emilmont 40:976df7c37ad5 806
emilmont 40:976df7c37ad5 807 /* GPIOs */
emilmont 40:976df7c37ad5 808 #define LPC_GPIO0_BASE (0x3FFFC000)
emilmont 40:976df7c37ad5 809 #define LPC_GPIO1_BASE (0x3FFFC020)
emilmont 40:976df7c37ad5 810 #define LPC_GPIO2_BASE (0x3FFFC040)
emilmont 40:976df7c37ad5 811 #define LPC_GPIO3_BASE (0x3FFFC060)
emilmont 40:976df7c37ad5 812 #define LPC_GPIO4_BASE (0x3FFFC080)
emilmont 40:976df7c37ad5 813
emilmont 40:976df7c37ad5 814
emilmont 40:976df7c37ad5 815 /******************************************************************************/
emilmont 40:976df7c37ad5 816 /* Peripheral declaration */
emilmont 40:976df7c37ad5 817 /******************************************************************************/
emilmont 40:976df7c37ad5 818 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
emilmont 40:976df7c37ad5 819 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
emilmont 40:976df7c37ad5 820 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
emilmont 40:976df7c37ad5 821 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
emilmont 40:976df7c37ad5 822 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
emilmont 40:976df7c37ad5 823 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
emilmont 40:976df7c37ad5 824 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
emilmont 40:976df7c37ad5 825 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
emilmont 40:976df7c37ad5 826 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
emilmont 40:976df7c37ad5 827 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
emilmont 40:976df7c37ad5 828 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
emilmont 40:976df7c37ad5 829 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
emilmont 40:976df7c37ad5 830 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
emilmont 40:976df7c37ad5 831 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
emilmont 40:976df7c37ad5 832 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
emilmont 40:976df7c37ad5 833 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
emilmont 40:976df7c37ad5 834 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
emilmont 40:976df7c37ad5 835 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
emilmont 40:976df7c37ad5 836 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
emilmont 40:976df7c37ad5 837 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
emilmont 40:976df7c37ad5 838 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
emilmont 40:976df7c37ad5 839 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
emilmont 40:976df7c37ad5 840 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
emilmont 40:976df7c37ad5 841 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
emilmont 40:976df7c37ad5 842 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
emilmont 40:976df7c37ad5 843 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
emilmont 40:976df7c37ad5 844 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
emilmont 40:976df7c37ad5 845 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
emilmont 40:976df7c37ad5 846 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
emilmont 40:976df7c37ad5 847 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
emilmont 40:976df7c37ad5 848 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
emilmont 40:976df7c37ad5 849 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
emilmont 40:976df7c37ad5 850 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
emilmont 40:976df7c37ad5 851 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
emilmont 40:976df7c37ad5 852 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
emilmont 40:976df7c37ad5 853 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
emilmont 40:976df7c37ad5 854 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
emilmont 40:976df7c37ad5 855 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
emilmont 40:976df7c37ad5 856 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
emilmont 40:976df7c37ad5 857 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
emilmont 40:976df7c37ad5 858
emilmont 40:976df7c37ad5 859 #ifdef __cplusplus
emilmont 40:976df7c37ad5 860 }
emilmont 40:976df7c37ad5 861 #endif
emilmont 40:976df7c37ad5 862
emilmont 40:976df7c37ad5 863 #endif // __LPC23xx_H
emilmont 40:976df7c37ad5 864