Matthew Sims / mbed

Lab 1 Program C

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LPC11U24/core_cmInstr.h@44:1c5f591fce58, 2015-09-29 (annotated)

Committer:
mattsims12
Date:
Tue Sep 29 03:04:58 2015 +0000
Revision:
44:1c5f591fce58
Parent:
40:976df7c37ad5 
Lab 1 Program C

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UserRevisionLine numberNew contents of line
emilmont 40:976df7c37ad5 1 /**************************************************************************//**
emilmont 40:976df7c37ad5 2 * @file core_cmInstr.h
emilmont 40:976df7c37ad5 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 40:976df7c37ad5 4 * @version V3.00
emilmont 40:976df7c37ad5 5 * @date 09. December 2011
emilmont 40:976df7c37ad5 6 *
emilmont 40:976df7c37ad5 7 * @note
emilmont 40:976df7c37ad5 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 9 *
emilmont 40:976df7c37ad5 10 * @par
emilmont 40:976df7c37ad5 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 40:976df7c37ad5 12 * processor based microcontrollers. This file can be freely distributed
emilmont 40:976df7c37ad5 13 * within development tools that are supporting such ARM based processors.
emilmont 40:976df7c37ad5 14 *
emilmont 40:976df7c37ad5 15 * @par
emilmont 40:976df7c37ad5 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 40:976df7c37ad5 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 40:976df7c37ad5 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 40:976df7c37ad5 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 40:976df7c37ad5 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 40:976df7c37ad5 21 *
emilmont 40:976df7c37ad5 22 ******************************************************************************/
emilmont 40:976df7c37ad5 23
emilmont 40:976df7c37ad5 24 #ifndef __CORE_CMINSTR_H
emilmont 40:976df7c37ad5 25 #define __CORE_CMINSTR_H
emilmont 40:976df7c37ad5 26
emilmont 40:976df7c37ad5 27
emilmont 40:976df7c37ad5 28 /* ########################## Core Instruction Access ######################### */
emilmont 40:976df7c37ad5 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 40:976df7c37ad5 30 Access to dedicated instructions
emilmont 40:976df7c37ad5 31 @{
emilmont 40:976df7c37ad5 32 */
emilmont 40:976df7c37ad5 33
emilmont 40:976df7c37ad5 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 40:976df7c37ad5 35 /* ARM armcc specific functions */
emilmont 40:976df7c37ad5 36
emilmont 40:976df7c37ad5 37 #if (__ARMCC_VERSION < 400677)
emilmont 40:976df7c37ad5 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 40:976df7c37ad5 39 #endif
emilmont 40:976df7c37ad5 40
emilmont 40:976df7c37ad5 41
emilmont 40:976df7c37ad5 42 /** \brief No Operation
emilmont 40:976df7c37ad5 43
emilmont 40:976df7c37ad5 44 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 40:976df7c37ad5 45 */
emilmont 40:976df7c37ad5 46 #define __NOP __nop
emilmont 40:976df7c37ad5 47
emilmont 40:976df7c37ad5 48
emilmont 40:976df7c37ad5 49 /** \brief Wait For Interrupt
emilmont 40:976df7c37ad5 50
emilmont 40:976df7c37ad5 51 Wait For Interrupt is a hint instruction that suspends execution
emilmont 40:976df7c37ad5 52 until one of a number of events occurs.
emilmont 40:976df7c37ad5 53 */
emilmont 40:976df7c37ad5 54 #define __WFI __wfi
emilmont 40:976df7c37ad5 55
emilmont 40:976df7c37ad5 56
emilmont 40:976df7c37ad5 57 /** \brief Wait For Event
emilmont 40:976df7c37ad5 58
emilmont 40:976df7c37ad5 59 Wait For Event is a hint instruction that permits the processor to enter
emilmont 40:976df7c37ad5 60 a low-power state until one of a number of events occurs.
emilmont 40:976df7c37ad5 61 */
emilmont 40:976df7c37ad5 62 #define __WFE __wfe
emilmont 40:976df7c37ad5 63
emilmont 40:976df7c37ad5 64
emilmont 40:976df7c37ad5 65 /** \brief Send Event
emilmont 40:976df7c37ad5 66
emilmont 40:976df7c37ad5 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 40:976df7c37ad5 68 */
emilmont 40:976df7c37ad5 69 #define __SEV __sev
emilmont 40:976df7c37ad5 70
emilmont 40:976df7c37ad5 71
emilmont 40:976df7c37ad5 72 /** \brief Instruction Synchronization Barrier
emilmont 40:976df7c37ad5 73
emilmont 40:976df7c37ad5 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 40:976df7c37ad5 75 so that all instructions following the ISB are fetched from cache or
emilmont 40:976df7c37ad5 76 memory, after the instruction has been completed.
emilmont 40:976df7c37ad5 77 */
emilmont 40:976df7c37ad5 78 #define __ISB() __isb(0xF)
emilmont 40:976df7c37ad5 79
emilmont 40:976df7c37ad5 80
emilmont 40:976df7c37ad5 81 /** \brief Data Synchronization Barrier
emilmont 40:976df7c37ad5 82
emilmont 40:976df7c37ad5 83 This function acts as a special kind of Data Memory Barrier.
emilmont 40:976df7c37ad5 84 It completes when all explicit memory accesses before this instruction complete.
emilmont 40:976df7c37ad5 85 */
emilmont 40:976df7c37ad5 86 #define __DSB() __dsb(0xF)
emilmont 40:976df7c37ad5 87
emilmont 40:976df7c37ad5 88
emilmont 40:976df7c37ad5 89 /** \brief Data Memory Barrier
emilmont 40:976df7c37ad5 90
emilmont 40:976df7c37ad5 91 This function ensures the apparent order of the explicit memory operations before
emilmont 40:976df7c37ad5 92 and after the instruction, without ensuring their completion.
emilmont 40:976df7c37ad5 93 */
emilmont 40:976df7c37ad5 94 #define __DMB() __dmb(0xF)
emilmont 40:976df7c37ad5 95
emilmont 40:976df7c37ad5 96
emilmont 40:976df7c37ad5 97 /** \brief Reverse byte order (32 bit)
emilmont 40:976df7c37ad5 98
emilmont 40:976df7c37ad5 99 This function reverses the byte order in integer value.
emilmont 40:976df7c37ad5 100
emilmont 40:976df7c37ad5 101 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 102 \return Reversed value
emilmont 40:976df7c37ad5 103 */
emilmont 40:976df7c37ad5 104 #define __REV __rev
emilmont 40:976df7c37ad5 105
emilmont 40:976df7c37ad5 106
emilmont 40:976df7c37ad5 107 /** \brief Reverse byte order (16 bit)
emilmont 40:976df7c37ad5 108
emilmont 40:976df7c37ad5 109 This function reverses the byte order in two unsigned short values.
emilmont 40:976df7c37ad5 110
emilmont 40:976df7c37ad5 111 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 112 \return Reversed value
emilmont 40:976df7c37ad5 113 */
emilmont 40:976df7c37ad5 114 static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 40:976df7c37ad5 115 {
emilmont 40:976df7c37ad5 116 rev16 r0, r0
emilmont 40:976df7c37ad5 117 bx lr
emilmont 40:976df7c37ad5 118 }
emilmont 40:976df7c37ad5 119
emilmont 40:976df7c37ad5 120
emilmont 40:976df7c37ad5 121 /** \brief Reverse byte order in signed short value
emilmont 40:976df7c37ad5 122
emilmont 40:976df7c37ad5 123 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 40:976df7c37ad5 124
emilmont 40:976df7c37ad5 125 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 126 \return Reversed value
emilmont 40:976df7c37ad5 127 */
emilmont 40:976df7c37ad5 128 static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 40:976df7c37ad5 129 {
emilmont 40:976df7c37ad5 130 revsh r0, r0
emilmont 40:976df7c37ad5 131 bx lr
emilmont 40:976df7c37ad5 132 }
emilmont 40:976df7c37ad5 133
emilmont 40:976df7c37ad5 134
emilmont 40:976df7c37ad5 135 #if (__CORTEX_M >= 0x03)
emilmont 40:976df7c37ad5 136
emilmont 40:976df7c37ad5 137 /** \brief Reverse bit order of value
emilmont 40:976df7c37ad5 138
emilmont 40:976df7c37ad5 139 This function reverses the bit order of the given value.
emilmont 40:976df7c37ad5 140
emilmont 40:976df7c37ad5 141 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 142 \return Reversed value
emilmont 40:976df7c37ad5 143 */
emilmont 40:976df7c37ad5 144 #define __RBIT __rbit
emilmont 40:976df7c37ad5 145
emilmont 40:976df7c37ad5 146
emilmont 40:976df7c37ad5 147 /** \brief LDR Exclusive (8 bit)
emilmont 40:976df7c37ad5 148
emilmont 40:976df7c37ad5 149 This function performs a exclusive LDR command for 8 bit value.
emilmont 40:976df7c37ad5 150
emilmont 40:976df7c37ad5 151 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 152 \return value of type uint8_t at (*ptr)
emilmont 40:976df7c37ad5 153 */
emilmont 40:976df7c37ad5 154 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 40:976df7c37ad5 155
emilmont 40:976df7c37ad5 156
emilmont 40:976df7c37ad5 157 /** \brief LDR Exclusive (16 bit)
emilmont 40:976df7c37ad5 158
emilmont 40:976df7c37ad5 159 This function performs a exclusive LDR command for 16 bit values.
emilmont 40:976df7c37ad5 160
emilmont 40:976df7c37ad5 161 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 162 \return value of type uint16_t at (*ptr)
emilmont 40:976df7c37ad5 163 */
emilmont 40:976df7c37ad5 164 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 40:976df7c37ad5 165
emilmont 40:976df7c37ad5 166
emilmont 40:976df7c37ad5 167 /** \brief LDR Exclusive (32 bit)
emilmont 40:976df7c37ad5 168
emilmont 40:976df7c37ad5 169 This function performs a exclusive LDR command for 32 bit values.
emilmont 40:976df7c37ad5 170
emilmont 40:976df7c37ad5 171 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 172 \return value of type uint32_t at (*ptr)
emilmont 40:976df7c37ad5 173 */
emilmont 40:976df7c37ad5 174 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 40:976df7c37ad5 175
emilmont 40:976df7c37ad5 176
emilmont 40:976df7c37ad5 177 /** \brief STR Exclusive (8 bit)
emilmont 40:976df7c37ad5 178
emilmont 40:976df7c37ad5 179 This function performs a exclusive STR command for 8 bit values.
emilmont 40:976df7c37ad5 180
emilmont 40:976df7c37ad5 181 \param [in] value Value to store
emilmont 40:976df7c37ad5 182 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 183 \return 0 Function succeeded
emilmont 40:976df7c37ad5 184 \return 1 Function failed
emilmont 40:976df7c37ad5 185 */
emilmont 40:976df7c37ad5 186 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 40:976df7c37ad5 187
emilmont 40:976df7c37ad5 188
emilmont 40:976df7c37ad5 189 /** \brief STR Exclusive (16 bit)
emilmont 40:976df7c37ad5 190
emilmont 40:976df7c37ad5 191 This function performs a exclusive STR command for 16 bit values.
emilmont 40:976df7c37ad5 192
emilmont 40:976df7c37ad5 193 \param [in] value Value to store
emilmont 40:976df7c37ad5 194 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 195 \return 0 Function succeeded
emilmont 40:976df7c37ad5 196 \return 1 Function failed
emilmont 40:976df7c37ad5 197 */
emilmont 40:976df7c37ad5 198 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 40:976df7c37ad5 199
emilmont 40:976df7c37ad5 200
emilmont 40:976df7c37ad5 201 /** \brief STR Exclusive (32 bit)
emilmont 40:976df7c37ad5 202
emilmont 40:976df7c37ad5 203 This function performs a exclusive STR command for 32 bit values.
emilmont 40:976df7c37ad5 204
emilmont 40:976df7c37ad5 205 \param [in] value Value to store
emilmont 40:976df7c37ad5 206 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 207 \return 0 Function succeeded
emilmont 40:976df7c37ad5 208 \return 1 Function failed
emilmont 40:976df7c37ad5 209 */
emilmont 40:976df7c37ad5 210 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 40:976df7c37ad5 211
emilmont 40:976df7c37ad5 212
emilmont 40:976df7c37ad5 213 /** \brief Remove the exclusive lock
emilmont 40:976df7c37ad5 214
emilmont 40:976df7c37ad5 215 This function removes the exclusive lock which is created by LDREX.
emilmont 40:976df7c37ad5 216
emilmont 40:976df7c37ad5 217 */
emilmont 40:976df7c37ad5 218 #define __CLREX __clrex
emilmont 40:976df7c37ad5 219
emilmont 40:976df7c37ad5 220
emilmont 40:976df7c37ad5 221 /** \brief Signed Saturate
emilmont 40:976df7c37ad5 222
emilmont 40:976df7c37ad5 223 This function saturates a signed value.
emilmont 40:976df7c37ad5 224
emilmont 40:976df7c37ad5 225 \param [in] value Value to be saturated
emilmont 40:976df7c37ad5 226 \param [in] sat Bit position to saturate to (1..32)
emilmont 40:976df7c37ad5 227 \return Saturated value
emilmont 40:976df7c37ad5 228 */
emilmont 40:976df7c37ad5 229 #define __SSAT __ssat
emilmont 40:976df7c37ad5 230
emilmont 40:976df7c37ad5 231
emilmont 40:976df7c37ad5 232 /** \brief Unsigned Saturate
emilmont 40:976df7c37ad5 233
emilmont 40:976df7c37ad5 234 This function saturates an unsigned value.
emilmont 40:976df7c37ad5 235
emilmont 40:976df7c37ad5 236 \param [in] value Value to be saturated
emilmont 40:976df7c37ad5 237 \param [in] sat Bit position to saturate to (0..31)
emilmont 40:976df7c37ad5 238 \return Saturated value
emilmont 40:976df7c37ad5 239 */
emilmont 40:976df7c37ad5 240 #define __USAT __usat
emilmont 40:976df7c37ad5 241
emilmont 40:976df7c37ad5 242
emilmont 40:976df7c37ad5 243 /** \brief Count leading zeros
emilmont 40:976df7c37ad5 244
emilmont 40:976df7c37ad5 245 This function counts the number of leading zeros of a data value.
emilmont 40:976df7c37ad5 246
emilmont 40:976df7c37ad5 247 \param [in] value Value to count the leading zeros
emilmont 40:976df7c37ad5 248 \return number of leading zeros in value
emilmont 40:976df7c37ad5 249 */
emilmont 40:976df7c37ad5 250 #define __CLZ __clz
emilmont 40:976df7c37ad5 251
emilmont 40:976df7c37ad5 252 #endif /* (__CORTEX_M >= 0x03) */
emilmont 40:976df7c37ad5 253
emilmont 40:976df7c37ad5 254
emilmont 40:976df7c37ad5 255
emilmont 40:976df7c37ad5 256 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 40:976df7c37ad5 257 /* IAR iccarm specific functions */
emilmont 40:976df7c37ad5 258
emilmont 40:976df7c37ad5 259 #include <cmsis_iar.h>
emilmont 40:976df7c37ad5 260
emilmont 40:976df7c37ad5 261
emilmont 40:976df7c37ad5 262 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 40:976df7c37ad5 263 /* GNU gcc specific functions */
emilmont 40:976df7c37ad5 264
emilmont 40:976df7c37ad5 265 /** \brief No Operation
emilmont 40:976df7c37ad5 266
emilmont 40:976df7c37ad5 267 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 40:976df7c37ad5 268 */
emilmont 40:976df7c37ad5 269 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
emilmont 40:976df7c37ad5 270 {
emilmont 40:976df7c37ad5 271 __ASM volatile ("nop");
emilmont 40:976df7c37ad5 272 }
emilmont 40:976df7c37ad5 273
emilmont 40:976df7c37ad5 274
emilmont 40:976df7c37ad5 275 /** \brief Wait For Interrupt
emilmont 40:976df7c37ad5 276
emilmont 40:976df7c37ad5 277 Wait For Interrupt is a hint instruction that suspends execution
emilmont 40:976df7c37ad5 278 until one of a number of events occurs.
emilmont 40:976df7c37ad5 279 */
emilmont 40:976df7c37ad5 280 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
emilmont 40:976df7c37ad5 281 {
emilmont 40:976df7c37ad5 282 __ASM volatile ("wfi");
emilmont 40:976df7c37ad5 283 }
emilmont 40:976df7c37ad5 284
emilmont 40:976df7c37ad5 285
emilmont 40:976df7c37ad5 286 /** \brief Wait For Event
emilmont 40:976df7c37ad5 287
emilmont 40:976df7c37ad5 288 Wait For Event is a hint instruction that permits the processor to enter
emilmont 40:976df7c37ad5 289 a low-power state until one of a number of events occurs.
emilmont 40:976df7c37ad5 290 */
emilmont 40:976df7c37ad5 291 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
emilmont 40:976df7c37ad5 292 {
emilmont 40:976df7c37ad5 293 __ASM volatile ("wfe");
emilmont 40:976df7c37ad5 294 }
emilmont 40:976df7c37ad5 295
emilmont 40:976df7c37ad5 296
emilmont 40:976df7c37ad5 297 /** \brief Send Event
emilmont 40:976df7c37ad5 298
emilmont 40:976df7c37ad5 299 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 40:976df7c37ad5 300 */
emilmont 40:976df7c37ad5 301 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
emilmont 40:976df7c37ad5 302 {
emilmont 40:976df7c37ad5 303 __ASM volatile ("sev");
emilmont 40:976df7c37ad5 304 }
emilmont 40:976df7c37ad5 305
emilmont 40:976df7c37ad5 306
emilmont 40:976df7c37ad5 307 /** \brief Instruction Synchronization Barrier
emilmont 40:976df7c37ad5 308
emilmont 40:976df7c37ad5 309 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 40:976df7c37ad5 310 so that all instructions following the ISB are fetched from cache or
emilmont 40:976df7c37ad5 311 memory, after the instruction has been completed.
emilmont 40:976df7c37ad5 312 */
emilmont 40:976df7c37ad5 313 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
emilmont 40:976df7c37ad5 314 {
emilmont 40:976df7c37ad5 315 __ASM volatile ("isb");
emilmont 40:976df7c37ad5 316 }
emilmont 40:976df7c37ad5 317
emilmont 40:976df7c37ad5 318
emilmont 40:976df7c37ad5 319 /** \brief Data Synchronization Barrier
emilmont 40:976df7c37ad5 320
emilmont 40:976df7c37ad5 321 This function acts as a special kind of Data Memory Barrier.
emilmont 40:976df7c37ad5 322 It completes when all explicit memory accesses before this instruction complete.
emilmont 40:976df7c37ad5 323 */
emilmont 40:976df7c37ad5 324 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
emilmont 40:976df7c37ad5 325 {
emilmont 40:976df7c37ad5 326 __ASM volatile ("dsb");
emilmont 40:976df7c37ad5 327 }
emilmont 40:976df7c37ad5 328
emilmont 40:976df7c37ad5 329
emilmont 40:976df7c37ad5 330 /** \brief Data Memory Barrier
emilmont 40:976df7c37ad5 331
emilmont 40:976df7c37ad5 332 This function ensures the apparent order of the explicit memory operations before
emilmont 40:976df7c37ad5 333 and after the instruction, without ensuring their completion.
emilmont 40:976df7c37ad5 334 */
emilmont 40:976df7c37ad5 335 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
emilmont 40:976df7c37ad5 336 {
emilmont 40:976df7c37ad5 337 __ASM volatile ("dmb");
emilmont 40:976df7c37ad5 338 }
emilmont 40:976df7c37ad5 339
emilmont 40:976df7c37ad5 340
emilmont 40:976df7c37ad5 341 /** \brief Reverse byte order (32 bit)
emilmont 40:976df7c37ad5 342
emilmont 40:976df7c37ad5 343 This function reverses the byte order in integer value.
emilmont 40:976df7c37ad5 344
emilmont 40:976df7c37ad5 345 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 346 \return Reversed value
emilmont 40:976df7c37ad5 347 */
emilmont 40:976df7c37ad5 348 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
emilmont 40:976df7c37ad5 349 {
emilmont 40:976df7c37ad5 350 uint32_t result;
emilmont 40:976df7c37ad5 351
emilmont 40:976df7c37ad5 352 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 353 return(result);
emilmont 40:976df7c37ad5 354 }
emilmont 40:976df7c37ad5 355
emilmont 40:976df7c37ad5 356
emilmont 40:976df7c37ad5 357 /** \brief Reverse byte order (16 bit)
emilmont 40:976df7c37ad5 358
emilmont 40:976df7c37ad5 359 This function reverses the byte order in two unsigned short values.
emilmont 40:976df7c37ad5 360
emilmont 40:976df7c37ad5 361 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 362 \return Reversed value
emilmont 40:976df7c37ad5 363 */
emilmont 40:976df7c37ad5 364 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
emilmont 40:976df7c37ad5 365 {
emilmont 40:976df7c37ad5 366 uint32_t result;
emilmont 40:976df7c37ad5 367
emilmont 40:976df7c37ad5 368 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 369 return(result);
emilmont 40:976df7c37ad5 370 }
emilmont 40:976df7c37ad5 371
emilmont 40:976df7c37ad5 372
emilmont 40:976df7c37ad5 373 /** \brief Reverse byte order in signed short value
emilmont 40:976df7c37ad5 374
emilmont 40:976df7c37ad5 375 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 40:976df7c37ad5 376
emilmont 40:976df7c37ad5 377 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 378 \return Reversed value
emilmont 40:976df7c37ad5 379 */
emilmont 40:976df7c37ad5 380 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
emilmont 40:976df7c37ad5 381 {
emilmont 40:976df7c37ad5 382 uint32_t result;
emilmont 40:976df7c37ad5 383
emilmont 40:976df7c37ad5 384 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 385 return(result);
emilmont 40:976df7c37ad5 386 }
emilmont 40:976df7c37ad5 387
emilmont 40:976df7c37ad5 388
emilmont 40:976df7c37ad5 389 #if (__CORTEX_M >= 0x03)
emilmont 40:976df7c37ad5 390
emilmont 40:976df7c37ad5 391 /** \brief Reverse bit order of value
emilmont 40:976df7c37ad5 392
emilmont 40:976df7c37ad5 393 This function reverses the bit order of the given value.
emilmont 40:976df7c37ad5 394
emilmont 40:976df7c37ad5 395 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 396 \return Reversed value
emilmont 40:976df7c37ad5 397 */
emilmont 40:976df7c37ad5 398 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
emilmont 40:976df7c37ad5 399 {
emilmont 40:976df7c37ad5 400 uint32_t result;
emilmont 40:976df7c37ad5 401
emilmont 40:976df7c37ad5 402 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 403 return(result);
emilmont 40:976df7c37ad5 404 }
emilmont 40:976df7c37ad5 405
emilmont 40:976df7c37ad5 406
emilmont 40:976df7c37ad5 407 /** \brief LDR Exclusive (8 bit)
emilmont 40:976df7c37ad5 408
emilmont 40:976df7c37ad5 409 This function performs a exclusive LDR command for 8 bit value.
emilmont 40:976df7c37ad5 410
emilmont 40:976df7c37ad5 411 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 412 \return value of type uint8_t at (*ptr)
emilmont 40:976df7c37ad5 413 */
emilmont 40:976df7c37ad5 414 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 40:976df7c37ad5 415 {
emilmont 40:976df7c37ad5 416 uint8_t result;
emilmont 40:976df7c37ad5 417
emilmont 40:976df7c37ad5 418 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 40:976df7c37ad5 419 return(result);
emilmont 40:976df7c37ad5 420 }
emilmont 40:976df7c37ad5 421
emilmont 40:976df7c37ad5 422
emilmont 40:976df7c37ad5 423 /** \brief LDR Exclusive (16 bit)
emilmont 40:976df7c37ad5 424
emilmont 40:976df7c37ad5 425 This function performs a exclusive LDR command for 16 bit values.
emilmont 40:976df7c37ad5 426
emilmont 40:976df7c37ad5 427 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 428 \return value of type uint16_t at (*ptr)
emilmont 40:976df7c37ad5 429 */
emilmont 40:976df7c37ad5 430 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 40:976df7c37ad5 431 {
emilmont 40:976df7c37ad5 432 uint16_t result;
emilmont 40:976df7c37ad5 433
emilmont 40:976df7c37ad5 434 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 40:976df7c37ad5 435 return(result);
emilmont 40:976df7c37ad5 436 }
emilmont 40:976df7c37ad5 437
emilmont 40:976df7c37ad5 438
emilmont 40:976df7c37ad5 439 /** \brief LDR Exclusive (32 bit)
emilmont 40:976df7c37ad5 440
emilmont 40:976df7c37ad5 441 This function performs a exclusive LDR command for 32 bit values.
emilmont 40:976df7c37ad5 442
emilmont 40:976df7c37ad5 443 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 444 \return value of type uint32_t at (*ptr)
emilmont 40:976df7c37ad5 445 */
emilmont 40:976df7c37ad5 446 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 40:976df7c37ad5 447 {
emilmont 40:976df7c37ad5 448 uint32_t result;
emilmont 40:976df7c37ad5 449
emilmont 40:976df7c37ad5 450 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 40:976df7c37ad5 451 return(result);
emilmont 40:976df7c37ad5 452 }
emilmont 40:976df7c37ad5 453
emilmont 40:976df7c37ad5 454
emilmont 40:976df7c37ad5 455 /** \brief STR Exclusive (8 bit)
emilmont 40:976df7c37ad5 456
emilmont 40:976df7c37ad5 457 This function performs a exclusive STR command for 8 bit values.
emilmont 40:976df7c37ad5 458
emilmont 40:976df7c37ad5 459 \param [in] value Value to store
emilmont 40:976df7c37ad5 460 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 461 \return 0 Function succeeded
emilmont 40:976df7c37ad5 462 \return 1 Function failed
emilmont 40:976df7c37ad5 463 */
emilmont 40:976df7c37ad5 464 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 40:976df7c37ad5 465 {
emilmont 40:976df7c37ad5 466 uint32_t result;
emilmont 40:976df7c37ad5 467
emilmont 40:976df7c37ad5 468 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 40:976df7c37ad5 469 return(result);
emilmont 40:976df7c37ad5 470 }
emilmont 40:976df7c37ad5 471
emilmont 40:976df7c37ad5 472
emilmont 40:976df7c37ad5 473 /** \brief STR Exclusive (16 bit)
emilmont 40:976df7c37ad5 474
emilmont 40:976df7c37ad5 475 This function performs a exclusive STR command for 16 bit values.
emilmont 40:976df7c37ad5 476
emilmont 40:976df7c37ad5 477 \param [in] value Value to store
emilmont 40:976df7c37ad5 478 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 479 \return 0 Function succeeded
emilmont 40:976df7c37ad5 480 \return 1 Function failed
emilmont 40:976df7c37ad5 481 */
emilmont 40:976df7c37ad5 482 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 40:976df7c37ad5 483 {
emilmont 40:976df7c37ad5 484 uint32_t result;
emilmont 40:976df7c37ad5 485
emilmont 40:976df7c37ad5 486 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 40:976df7c37ad5 487 return(result);
emilmont 40:976df7c37ad5 488 }
emilmont 40:976df7c37ad5 489
emilmont 40:976df7c37ad5 490
emilmont 40:976df7c37ad5 491 /** \brief STR Exclusive (32 bit)
emilmont 40:976df7c37ad5 492
emilmont 40:976df7c37ad5 493 This function performs a exclusive STR command for 32 bit values.
emilmont 40:976df7c37ad5 494
emilmont 40:976df7c37ad5 495 \param [in] value Value to store
emilmont 40:976df7c37ad5 496 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 497 \return 0 Function succeeded
emilmont 40:976df7c37ad5 498 \return 1 Function failed
emilmont 40:976df7c37ad5 499 */
emilmont 40:976df7c37ad5 500 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 40:976df7c37ad5 501 {
emilmont 40:976df7c37ad5 502 uint32_t result;
emilmont 40:976df7c37ad5 503
emilmont 40:976df7c37ad5 504 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 40:976df7c37ad5 505 return(result);
emilmont 40:976df7c37ad5 506 }
emilmont 40:976df7c37ad5 507
emilmont 40:976df7c37ad5 508
emilmont 40:976df7c37ad5 509 /** \brief Remove the exclusive lock
emilmont 40:976df7c37ad5 510
emilmont 40:976df7c37ad5 511 This function removes the exclusive lock which is created by LDREX.
emilmont 40:976df7c37ad5 512
emilmont 40:976df7c37ad5 513 */
emilmont 40:976df7c37ad5 514 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
emilmont 40:976df7c37ad5 515 {
emilmont 40:976df7c37ad5 516 __ASM volatile ("clrex");
emilmont 40:976df7c37ad5 517 }
emilmont 40:976df7c37ad5 518
emilmont 40:976df7c37ad5 519
emilmont 40:976df7c37ad5 520 /** \brief Signed Saturate
emilmont 40:976df7c37ad5 521
emilmont 40:976df7c37ad5 522 This function saturates a signed value.
emilmont 40:976df7c37ad5 523
emilmont 40:976df7c37ad5 524 \param [in] value Value to be saturated
emilmont 40:976df7c37ad5 525 \param [in] sat Bit position to saturate to (1..32)
emilmont 40:976df7c37ad5 526 \return Saturated value
emilmont 40:976df7c37ad5 527 */
emilmont 40:976df7c37ad5 528 #define __SSAT(ARG1,ARG2) \
emilmont 40:976df7c37ad5 529 ({ \
emilmont 40:976df7c37ad5 530 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 40:976df7c37ad5 531 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 40:976df7c37ad5 532 __RES; \
emilmont 40:976df7c37ad5 533 })
emilmont 40:976df7c37ad5 534
emilmont 40:976df7c37ad5 535
emilmont 40:976df7c37ad5 536 /** \brief Unsigned Saturate
emilmont 40:976df7c37ad5 537
emilmont 40:976df7c37ad5 538 This function saturates an unsigned value.
emilmont 40:976df7c37ad5 539
emilmont 40:976df7c37ad5 540 \param [in] value Value to be saturated
emilmont 40:976df7c37ad5 541 \param [in] sat Bit position to saturate to (0..31)
emilmont 40:976df7c37ad5 542 \return Saturated value
emilmont 40:976df7c37ad5 543 */
emilmont 40:976df7c37ad5 544 #define __USAT(ARG1,ARG2) \
emilmont 40:976df7c37ad5 545 ({ \
emilmont 40:976df7c37ad5 546 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 40:976df7c37ad5 547 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 40:976df7c37ad5 548 __RES; \
emilmont 40:976df7c37ad5 549 })
emilmont 40:976df7c37ad5 550
emilmont 40:976df7c37ad5 551
emilmont 40:976df7c37ad5 552 /** \brief Count leading zeros
emilmont 40:976df7c37ad5 553
emilmont 40:976df7c37ad5 554 This function counts the number of leading zeros of a data value.
emilmont 40:976df7c37ad5 555
emilmont 40:976df7c37ad5 556 \param [in] value Value to count the leading zeros
emilmont 40:976df7c37ad5 557 \return number of leading zeros in value
emilmont 40:976df7c37ad5 558 */
emilmont 40:976df7c37ad5 559 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
emilmont 40:976df7c37ad5 560 {
emilmont 40:976df7c37ad5 561 uint8_t result;
emilmont 40:976df7c37ad5 562
emilmont 40:976df7c37ad5 563 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 564 return(result);
emilmont 40:976df7c37ad5 565 }
emilmont 40:976df7c37ad5 566
emilmont 40:976df7c37ad5 567 #endif /* (__CORTEX_M >= 0x03) */
emilmont 40:976df7c37ad5 568
emilmont 40:976df7c37ad5 569
emilmont 40:976df7c37ad5 570
emilmont 40:976df7c37ad5 571
emilmont 40:976df7c37ad5 572 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 40:976df7c37ad5 573 /* TASKING carm specific functions */
emilmont 40:976df7c37ad5 574
emilmont 40:976df7c37ad5 575 /*
emilmont 40:976df7c37ad5 576 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 40:976df7c37ad5 577 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 40:976df7c37ad5 578 * Including the CMSIS ones.
emilmont 40:976df7c37ad5 579 */
emilmont 40:976df7c37ad5 580
emilmont 40:976df7c37ad5 581 #endif
emilmont 40:976df7c37ad5 582
emilmont 40:976df7c37ad5 583 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 40:976df7c37ad5 584
emilmont 40:976df7c37ad5 585 #endif /* __CORE_CMINSTR_H */