mbed - Lab 1 Program C

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Lab 1 Program C

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LPC1768/core_cm3.h@40:976df7c37ad5, 2012-06-12 (annotated)

Committer:: emilmont
Date:: Tue Jun 12 18:23:44 2012 +0100
Revision:: 40:976df7c37ad5

First build for the new build system

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	40:976df7c37ad5	1	/************************************************************************//
emilmont	40:976df7c37ad5	2	* @file core_cm3.h
emilmont	40:976df7c37ad5	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
emilmont	40:976df7c37ad5	4	* @version V3.01
emilmont	40:976df7c37ad5	5	* @date 06. March 2012
emilmont	40:976df7c37ad5	6	*
emilmont	40:976df7c37ad5	7	* @note
emilmont	40:976df7c37ad5	8	* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont	40:976df7c37ad5	9	*
emilmont	40:976df7c37ad5	10	* @par
emilmont	40:976df7c37ad5	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont	40:976df7c37ad5	12	* processor based microcontrollers. This file can be freely distributed
emilmont	40:976df7c37ad5	13	* within development tools that are supporting such ARM based processors.
emilmont	40:976df7c37ad5	14	*
emilmont	40:976df7c37ad5	15	* @par
emilmont	40:976df7c37ad5	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont	40:976df7c37ad5	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont	40:976df7c37ad5	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont	40:976df7c37ad5	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont	40:976df7c37ad5	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont	40:976df7c37ad5	21	*
emilmont	40:976df7c37ad5	22	******************************************************************************/
emilmont	40:976df7c37ad5	23	#if defined ( __ICCARM__ )
emilmont	40:976df7c37ad5	24	#pragma system_include /* treat file as system include file for MISRA check */
emilmont	40:976df7c37ad5	25	#endif
emilmont	40:976df7c37ad5	26
emilmont	40:976df7c37ad5	27	#ifdef __cplusplus
emilmont	40:976df7c37ad5	28	extern "C" {
emilmont	40:976df7c37ad5	29	#endif
emilmont	40:976df7c37ad5	30
emilmont	40:976df7c37ad5	31	#ifndef __CORE_CM3_H_GENERIC
emilmont	40:976df7c37ad5	32	#define __CORE_CM3_H_GENERIC
emilmont	40:976df7c37ad5	33
emilmont	40:976df7c37ad5	34	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont	40:976df7c37ad5	35	CMSIS violates the following MISRA-C:2004 rules:
emilmont	40:976df7c37ad5	36
emilmont	40:976df7c37ad5	37	\li Required Rule 8.5, object/function definition in header file.<br>
emilmont	40:976df7c37ad5	38	Function definitions in header files are used to allow 'inlining'.
emilmont	40:976df7c37ad5	39
emilmont	40:976df7c37ad5	40	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont	40:976df7c37ad5	41	Unions are used for effective representation of core registers.
emilmont	40:976df7c37ad5	42
emilmont	40:976df7c37ad5	43	\li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont	40:976df7c37ad5	44	Function-like macros are used to allow more efficient code.
emilmont	40:976df7c37ad5	45	*/
emilmont	40:976df7c37ad5	46
emilmont	40:976df7c37ad5	47
emilmont	40:976df7c37ad5	48	/*******************************************************************************
emilmont	40:976df7c37ad5	49	* CMSIS definitions
emilmont	40:976df7c37ad5	50	******************************************************************************/
emilmont	40:976df7c37ad5	51	/** \ingroup Cortex_M3
emilmont	40:976df7c37ad5	52	@{
emilmont	40:976df7c37ad5	53	*/
emilmont	40:976df7c37ad5	54
emilmont	40:976df7c37ad5	55	/* CMSIS CM3 definitions */
emilmont	40:976df7c37ad5	56	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
emilmont	40:976df7c37ad5	57	#define __CM3_CMSIS_VERSION_SUB (0x01) /!< [15:0] CMSIS HAL sub version /
emilmont	40:976df7c37ad5	58	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
emilmont	40:976df7c37ad5	59	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
emilmont	40:976df7c37ad5	60
emilmont	40:976df7c37ad5	61	#define __CORTEX_M (0x03) /!< Cortex-M Core /
emilmont	40:976df7c37ad5	62
emilmont	40:976df7c37ad5	63
emilmont	40:976df7c37ad5	64	#if defined ( __CC_ARM )
emilmont	40:976df7c37ad5	65	#define __ASM __asm /!< asm keyword for ARM Compiler /
emilmont	40:976df7c37ad5	66	#define __INLINE __inline /!< inline keyword for ARM Compiler /
emilmont	40:976df7c37ad5	67	#define __STATIC_INLINE static __inline
emilmont	40:976df7c37ad5	68
emilmont	40:976df7c37ad5	69	#elif defined ( __ICCARM__ )
emilmont	40:976df7c37ad5	70	#define __ASM __asm /!< asm keyword for IAR Compiler /
emilmont	40:976df7c37ad5	71	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
emilmont	40:976df7c37ad5	72	#define __STATIC_INLINE static inline
emilmont	40:976df7c37ad5	73
emilmont	40:976df7c37ad5	74	#elif defined ( __TMS470__ )
emilmont	40:976df7c37ad5	75	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
emilmont	40:976df7c37ad5	76	#define __STATIC_INLINE static inline
emilmont	40:976df7c37ad5	77
emilmont	40:976df7c37ad5	78	#elif defined ( __GNUC__ )
emilmont	40:976df7c37ad5	79	#define __ASM __asm /!< asm keyword for GNU Compiler /
emilmont	40:976df7c37ad5	80	#define __INLINE inline /!< inline keyword for GNU Compiler /
emilmont	40:976df7c37ad5	81	#define __STATIC_INLINE static inline
emilmont	40:976df7c37ad5	82
emilmont	40:976df7c37ad5	83	#elif defined ( __TASKING__ )
emilmont	40:976df7c37ad5	84	#define __ASM __asm /!< asm keyword for TASKING Compiler /
emilmont	40:976df7c37ad5	85	#define __INLINE inline /!< inline keyword for TASKING Compiler /
emilmont	40:976df7c37ad5	86	#define __STATIC_INLINE static inline
emilmont	40:976df7c37ad5	87
emilmont	40:976df7c37ad5	88	#endif
emilmont	40:976df7c37ad5	89
emilmont	40:976df7c37ad5	90	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont	40:976df7c37ad5	91	*/
emilmont	40:976df7c37ad5	92	#define __FPU_USED 0
emilmont	40:976df7c37ad5	93
emilmont	40:976df7c37ad5	94	#if defined ( __CC_ARM )
emilmont	40:976df7c37ad5	95	#if defined __TARGET_FPU_VFP
emilmont	40:976df7c37ad5	96	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	40:976df7c37ad5	97	#endif
emilmont	40:976df7c37ad5	98
emilmont	40:976df7c37ad5	99	#elif defined ( __ICCARM__ )
emilmont	40:976df7c37ad5	100	#if defined __ARMVFP__
emilmont	40:976df7c37ad5	101	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	40:976df7c37ad5	102	#endif
emilmont	40:976df7c37ad5	103
emilmont	40:976df7c37ad5	104	#elif defined ( __TMS470__ )
emilmont	40:976df7c37ad5	105	#if defined __TI__VFP_SUPPORT____
emilmont	40:976df7c37ad5	106	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	40:976df7c37ad5	107	#endif
emilmont	40:976df7c37ad5	108
emilmont	40:976df7c37ad5	109	#elif defined ( __GNUC__ )
emilmont	40:976df7c37ad5	110	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont	40:976df7c37ad5	111	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	40:976df7c37ad5	112	#endif
emilmont	40:976df7c37ad5	113
emilmont	40:976df7c37ad5	114	#elif defined ( __TASKING__ )
emilmont	40:976df7c37ad5	115	/* add preprocessor checks */
emilmont	40:976df7c37ad5	116	#endif
emilmont	40:976df7c37ad5	117
emilmont	40:976df7c37ad5	118	#include <stdint.h> /* standard types definitions */
emilmont	40:976df7c37ad5	119	#include <core_cmInstr.h> /* Core Instruction Access */
emilmont	40:976df7c37ad5	120	#include <core_cmFunc.h> /* Core Function Access */
emilmont	40:976df7c37ad5	121
emilmont	40:976df7c37ad5	122	#endif /* __CORE_CM3_H_GENERIC */
emilmont	40:976df7c37ad5	123
emilmont	40:976df7c37ad5	124	#ifndef __CMSIS_GENERIC
emilmont	40:976df7c37ad5	125
emilmont	40:976df7c37ad5	126	#ifndef __CORE_CM3_H_DEPENDANT
emilmont	40:976df7c37ad5	127	#define __CORE_CM3_H_DEPENDANT
emilmont	40:976df7c37ad5	128
emilmont	40:976df7c37ad5	129	/* check device defines and use defaults */
emilmont	40:976df7c37ad5	130	#if defined __CHECK_DEVICE_DEFINES
emilmont	40:976df7c37ad5	131	#ifndef __CM3_REV
emilmont	40:976df7c37ad5	132	#define __CM3_REV 0x0200
emilmont	40:976df7c37ad5	133	#warning "__CM3_REV not defined in device header file; using default!"
emilmont	40:976df7c37ad5	134	#endif
emilmont	40:976df7c37ad5	135
emilmont	40:976df7c37ad5	136	#ifndef __MPU_PRESENT
emilmont	40:976df7c37ad5	137	#define __MPU_PRESENT 0
emilmont	40:976df7c37ad5	138	#warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont	40:976df7c37ad5	139	#endif
emilmont	40:976df7c37ad5	140
emilmont	40:976df7c37ad5	141	#ifndef __NVIC_PRIO_BITS
emilmont	40:976df7c37ad5	142	#define __NVIC_PRIO_BITS 4
emilmont	40:976df7c37ad5	143	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont	40:976df7c37ad5	144	#endif
emilmont	40:976df7c37ad5	145
emilmont	40:976df7c37ad5	146	#ifndef __Vendor_SysTickConfig
emilmont	40:976df7c37ad5	147	#define __Vendor_SysTickConfig 0
emilmont	40:976df7c37ad5	148	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont	40:976df7c37ad5	149	#endif
emilmont	40:976df7c37ad5	150	#endif
emilmont	40:976df7c37ad5	151
emilmont	40:976df7c37ad5	152	/* IO definitions (access restrictions to peripheral registers) */
emilmont	40:976df7c37ad5	153	/**
emilmont	40:976df7c37ad5	154	\defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont	40:976df7c37ad5	155
emilmont	40:976df7c37ad5	156	<strong>IO Type Qualifiers</strong> are used
emilmont	40:976df7c37ad5	157	\li to specify the access to peripheral variables.
emilmont	40:976df7c37ad5	158	\li for automatic generation of peripheral register debug information.
emilmont	40:976df7c37ad5	159	*/
emilmont	40:976df7c37ad5	160	#ifdef __cplusplus
emilmont	40:976df7c37ad5	161	#define __I volatile /!< Defines 'read only' permissions /
emilmont	40:976df7c37ad5	162	#else
emilmont	40:976df7c37ad5	163	#define __I volatile const /!< Defines 'read only' permissions /
emilmont	40:976df7c37ad5	164	#endif
emilmont	40:976df7c37ad5	165	#define __O volatile /!< Defines 'write only' permissions /
emilmont	40:976df7c37ad5	166	#define __IO volatile /!< Defines 'read / write' permissions /
emilmont	40:976df7c37ad5	167
emilmont	40:976df7c37ad5	168	/@} end of group Cortex_M3 /
emilmont	40:976df7c37ad5	169
emilmont	40:976df7c37ad5	170
emilmont	40:976df7c37ad5	171
emilmont	40:976df7c37ad5	172	/*******************************************************************************
emilmont	40:976df7c37ad5	173	* Register Abstraction
emilmont	40:976df7c37ad5	174	Core Register contain:
emilmont	40:976df7c37ad5	175	- Core Register
emilmont	40:976df7c37ad5	176	- Core NVIC Register
emilmont	40:976df7c37ad5	177	- Core SCB Register
emilmont	40:976df7c37ad5	178	- Core SysTick Register
emilmont	40:976df7c37ad5	179	- Core Debug Register
emilmont	40:976df7c37ad5	180	- Core MPU Register
emilmont	40:976df7c37ad5	181	******************************************************************************/
emilmont	40:976df7c37ad5	182	/** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont	40:976df7c37ad5	183	\brief Type definitions and defines for Cortex-M processor based devices.
emilmont	40:976df7c37ad5	184	*/
emilmont	40:976df7c37ad5	185
emilmont	40:976df7c37ad5	186	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	187	\defgroup CMSIS_CORE Status and Control Registers
emilmont	40:976df7c37ad5	188	\brief Core Register type definitions.
emilmont	40:976df7c37ad5	189	@{
emilmont	40:976df7c37ad5	190	*/
emilmont	40:976df7c37ad5	191
emilmont	40:976df7c37ad5	192	/** \brief Union type to access the Application Program Status Register (APSR).
emilmont	40:976df7c37ad5	193	*/
emilmont	40:976df7c37ad5	194	typedef union
emilmont	40:976df7c37ad5	195	{
emilmont	40:976df7c37ad5	196	struct
emilmont	40:976df7c37ad5	197	{
emilmont	40:976df7c37ad5	198	#if (__CORTEX_M != 0x04)
emilmont	40:976df7c37ad5	199	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
emilmont	40:976df7c37ad5	200	#else
emilmont	40:976df7c37ad5	201	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
emilmont	40:976df7c37ad5	202	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	40:976df7c37ad5	203	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
emilmont	40:976df7c37ad5	204	#endif
emilmont	40:976df7c37ad5	205	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	40:976df7c37ad5	206	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	40:976df7c37ad5	207	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	40:976df7c37ad5	208	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	40:976df7c37ad5	209	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	40:976df7c37ad5	210	} b; /!< Structure used for bit access /
emilmont	40:976df7c37ad5	211	uint32_t w; /!< Type used for word access /
emilmont	40:976df7c37ad5	212	} APSR_Type;
emilmont	40:976df7c37ad5	213
emilmont	40:976df7c37ad5	214
emilmont	40:976df7c37ad5	215	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont	40:976df7c37ad5	216	*/
emilmont	40:976df7c37ad5	217	typedef union
emilmont	40:976df7c37ad5	218	{
emilmont	40:976df7c37ad5	219	struct
emilmont	40:976df7c37ad5	220	{
emilmont	40:976df7c37ad5	221	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	40:976df7c37ad5	222	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
emilmont	40:976df7c37ad5	223	} b; /!< Structure used for bit access /
emilmont	40:976df7c37ad5	224	uint32_t w; /!< Type used for word access /
emilmont	40:976df7c37ad5	225	} IPSR_Type;
emilmont	40:976df7c37ad5	226
emilmont	40:976df7c37ad5	227
emilmont	40:976df7c37ad5	228	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont	40:976df7c37ad5	229	*/
emilmont	40:976df7c37ad5	230	typedef union
emilmont	40:976df7c37ad5	231	{
emilmont	40:976df7c37ad5	232	struct
emilmont	40:976df7c37ad5	233	{
emilmont	40:976df7c37ad5	234	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	40:976df7c37ad5	235	#if (__CORTEX_M != 0x04)
emilmont	40:976df7c37ad5	236	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
emilmont	40:976df7c37ad5	237	#else
emilmont	40:976df7c37ad5	238	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
emilmont	40:976df7c37ad5	239	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	40:976df7c37ad5	240	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
emilmont	40:976df7c37ad5	241	#endif
emilmont	40:976df7c37ad5	242	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
emilmont	40:976df7c37ad5	243	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
emilmont	40:976df7c37ad5	244	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	40:976df7c37ad5	245	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	40:976df7c37ad5	246	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	40:976df7c37ad5	247	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	40:976df7c37ad5	248	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	40:976df7c37ad5	249	} b; /!< Structure used for bit access /
emilmont	40:976df7c37ad5	250	uint32_t w; /!< Type used for word access /
emilmont	40:976df7c37ad5	251	} xPSR_Type;
emilmont	40:976df7c37ad5	252
emilmont	40:976df7c37ad5	253
emilmont	40:976df7c37ad5	254	/** \brief Union type to access the Control Registers (CONTROL).
emilmont	40:976df7c37ad5	255	*/
emilmont	40:976df7c37ad5	256	typedef union
emilmont	40:976df7c37ad5	257	{
emilmont	40:976df7c37ad5	258	struct
emilmont	40:976df7c37ad5	259	{
emilmont	40:976df7c37ad5	260	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
emilmont	40:976df7c37ad5	261	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
emilmont	40:976df7c37ad5	262	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
emilmont	40:976df7c37ad5	263	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
emilmont	40:976df7c37ad5	264	} b; /!< Structure used for bit access /
emilmont	40:976df7c37ad5	265	uint32_t w; /!< Type used for word access /
emilmont	40:976df7c37ad5	266	} CONTROL_Type;
emilmont	40:976df7c37ad5	267
emilmont	40:976df7c37ad5	268	/@} end of group CMSIS_CORE /
emilmont	40:976df7c37ad5	269
emilmont	40:976df7c37ad5	270
emilmont	40:976df7c37ad5	271	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	272	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont	40:976df7c37ad5	273	\brief Type definitions for the NVIC Registers
emilmont	40:976df7c37ad5	274	@{
emilmont	40:976df7c37ad5	275	*/
emilmont	40:976df7c37ad5	276
emilmont	40:976df7c37ad5	277	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont	40:976df7c37ad5	278	*/
emilmont	40:976df7c37ad5	279	typedef struct
emilmont	40:976df7c37ad5	280	{
emilmont	40:976df7c37ad5	281	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
emilmont	40:976df7c37ad5	282	uint32_t RESERVED0[24];
emilmont	40:976df7c37ad5	283	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
emilmont	40:976df7c37ad5	284	uint32_t RSERVED1[24];
emilmont	40:976df7c37ad5	285	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
emilmont	40:976df7c37ad5	286	uint32_t RESERVED2[24];
emilmont	40:976df7c37ad5	287	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
emilmont	40:976df7c37ad5	288	uint32_t RESERVED3[24];
emilmont	40:976df7c37ad5	289	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
emilmont	40:976df7c37ad5	290	uint32_t RESERVED4[56];
emilmont	40:976df7c37ad5	291	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
emilmont	40:976df7c37ad5	292	uint32_t RESERVED5[644];
emilmont	40:976df7c37ad5	293	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
emilmont	40:976df7c37ad5	294	} NVIC_Type;
emilmont	40:976df7c37ad5	295
emilmont	40:976df7c37ad5	296	/* Software Triggered Interrupt Register Definitions */
emilmont	40:976df7c37ad5	297	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
emilmont	40:976df7c37ad5	298	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
emilmont	40:976df7c37ad5	299
emilmont	40:976df7c37ad5	300	/@} end of group CMSIS_NVIC /
emilmont	40:976df7c37ad5	301
emilmont	40:976df7c37ad5	302
emilmont	40:976df7c37ad5	303	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	304	\defgroup CMSIS_SCB System Control Block (SCB)
emilmont	40:976df7c37ad5	305	\brief Type definitions for the System Control Block Registers
emilmont	40:976df7c37ad5	306	@{
emilmont	40:976df7c37ad5	307	*/
emilmont	40:976df7c37ad5	308
emilmont	40:976df7c37ad5	309	/** \brief Structure type to access the System Control Block (SCB).
emilmont	40:976df7c37ad5	310	*/
emilmont	40:976df7c37ad5	311	typedef struct
emilmont	40:976df7c37ad5	312	{
emilmont	40:976df7c37ad5	313	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
emilmont	40:976df7c37ad5	314	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
emilmont	40:976df7c37ad5	315	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
emilmont	40:976df7c37ad5	316	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
emilmont	40:976df7c37ad5	317	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
emilmont	40:976df7c37ad5	318	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
emilmont	40:976df7c37ad5	319	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
emilmont	40:976df7c37ad5	320	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
emilmont	40:976df7c37ad5	321	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
emilmont	40:976df7c37ad5	322	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
emilmont	40:976df7c37ad5	323	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
emilmont	40:976df7c37ad5	324	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
emilmont	40:976df7c37ad5	325	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
emilmont	40:976df7c37ad5	326	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
emilmont	40:976df7c37ad5	327	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
emilmont	40:976df7c37ad5	328	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
emilmont	40:976df7c37ad5	329	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
emilmont	40:976df7c37ad5	330	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
emilmont	40:976df7c37ad5	331	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
emilmont	40:976df7c37ad5	332	uint32_t RESERVED0[5];
emilmont	40:976df7c37ad5	333	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
emilmont	40:976df7c37ad5	334	} SCB_Type;
emilmont	40:976df7c37ad5	335
emilmont	40:976df7c37ad5	336	/* SCB CPUID Register Definitions */
emilmont	40:976df7c37ad5	337	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
emilmont	40:976df7c37ad5	338	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
emilmont	40:976df7c37ad5	339
emilmont	40:976df7c37ad5	340	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
emilmont	40:976df7c37ad5	341	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
emilmont	40:976df7c37ad5	342
emilmont	40:976df7c37ad5	343	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
emilmont	40:976df7c37ad5	344	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
emilmont	40:976df7c37ad5	345
emilmont	40:976df7c37ad5	346	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
emilmont	40:976df7c37ad5	347	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
emilmont	40:976df7c37ad5	348
emilmont	40:976df7c37ad5	349	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
emilmont	40:976df7c37ad5	350	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
emilmont	40:976df7c37ad5	351
emilmont	40:976df7c37ad5	352	/* SCB Interrupt Control State Register Definitions */
emilmont	40:976df7c37ad5	353	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
emilmont	40:976df7c37ad5	354	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
emilmont	40:976df7c37ad5	355
emilmont	40:976df7c37ad5	356	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
emilmont	40:976df7c37ad5	357	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
emilmont	40:976df7c37ad5	358
emilmont	40:976df7c37ad5	359	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
emilmont	40:976df7c37ad5	360	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
emilmont	40:976df7c37ad5	361
emilmont	40:976df7c37ad5	362	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
emilmont	40:976df7c37ad5	363	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
emilmont	40:976df7c37ad5	364
emilmont	40:976df7c37ad5	365	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
emilmont	40:976df7c37ad5	366	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
emilmont	40:976df7c37ad5	367
emilmont	40:976df7c37ad5	368	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
emilmont	40:976df7c37ad5	369	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
emilmont	40:976df7c37ad5	370
emilmont	40:976df7c37ad5	371	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
emilmont	40:976df7c37ad5	372	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
emilmont	40:976df7c37ad5	373
emilmont	40:976df7c37ad5	374	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
emilmont	40:976df7c37ad5	375	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
emilmont	40:976df7c37ad5	376
emilmont	40:976df7c37ad5	377	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
emilmont	40:976df7c37ad5	378	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
emilmont	40:976df7c37ad5	379
emilmont	40:976df7c37ad5	380	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
emilmont	40:976df7c37ad5	381	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
emilmont	40:976df7c37ad5	382
emilmont	40:976df7c37ad5	383	/* SCB Vector Table Offset Register Definitions */
emilmont	40:976df7c37ad5	384	#if (__CM3_REV < 0x0201) /* core r2p1 */
emilmont	40:976df7c37ad5	385	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
emilmont	40:976df7c37ad5	386	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
emilmont	40:976df7c37ad5	387
emilmont	40:976df7c37ad5	388	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	40:976df7c37ad5	389	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	40:976df7c37ad5	390	#else
emilmont	40:976df7c37ad5	391	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	40:976df7c37ad5	392	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	40:976df7c37ad5	393	#endif
emilmont	40:976df7c37ad5	394
emilmont	40:976df7c37ad5	395	/* SCB Application Interrupt and Reset Control Register Definitions */
emilmont	40:976df7c37ad5	396	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
emilmont	40:976df7c37ad5	397	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
emilmont	40:976df7c37ad5	398
emilmont	40:976df7c37ad5	399	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
emilmont	40:976df7c37ad5	400	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
emilmont	40:976df7c37ad5	401
emilmont	40:976df7c37ad5	402	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
emilmont	40:976df7c37ad5	403	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
emilmont	40:976df7c37ad5	404
emilmont	40:976df7c37ad5	405	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
emilmont	40:976df7c37ad5	406	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
emilmont	40:976df7c37ad5	407
emilmont	40:976df7c37ad5	408	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
emilmont	40:976df7c37ad5	409	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
emilmont	40:976df7c37ad5	410
emilmont	40:976df7c37ad5	411	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
emilmont	40:976df7c37ad5	412	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
emilmont	40:976df7c37ad5	413
emilmont	40:976df7c37ad5	414	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
emilmont	40:976df7c37ad5	415	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
emilmont	40:976df7c37ad5	416
emilmont	40:976df7c37ad5	417	/* SCB System Control Register Definitions */
emilmont	40:976df7c37ad5	418	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
emilmont	40:976df7c37ad5	419	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
emilmont	40:976df7c37ad5	420
emilmont	40:976df7c37ad5	421	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
emilmont	40:976df7c37ad5	422	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
emilmont	40:976df7c37ad5	423
emilmont	40:976df7c37ad5	424	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
emilmont	40:976df7c37ad5	425	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
emilmont	40:976df7c37ad5	426
emilmont	40:976df7c37ad5	427	/* SCB Configuration Control Register Definitions */
emilmont	40:976df7c37ad5	428	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
emilmont	40:976df7c37ad5	429	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
emilmont	40:976df7c37ad5	430
emilmont	40:976df7c37ad5	431	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
emilmont	40:976df7c37ad5	432	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
emilmont	40:976df7c37ad5	433
emilmont	40:976df7c37ad5	434	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
emilmont	40:976df7c37ad5	435	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
emilmont	40:976df7c37ad5	436
emilmont	40:976df7c37ad5	437	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
emilmont	40:976df7c37ad5	438	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
emilmont	40:976df7c37ad5	439
emilmont	40:976df7c37ad5	440	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
emilmont	40:976df7c37ad5	441	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
emilmont	40:976df7c37ad5	442
emilmont	40:976df7c37ad5	443	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
emilmont	40:976df7c37ad5	444	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
emilmont	40:976df7c37ad5	445
emilmont	40:976df7c37ad5	446	/* SCB System Handler Control and State Register Definitions */
emilmont	40:976df7c37ad5	447	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
emilmont	40:976df7c37ad5	448	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
emilmont	40:976df7c37ad5	449
emilmont	40:976df7c37ad5	450	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
emilmont	40:976df7c37ad5	451	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
emilmont	40:976df7c37ad5	452
emilmont	40:976df7c37ad5	453	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
emilmont	40:976df7c37ad5	454	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
emilmont	40:976df7c37ad5	455
emilmont	40:976df7c37ad5	456	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
emilmont	40:976df7c37ad5	457	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
emilmont	40:976df7c37ad5	458
emilmont	40:976df7c37ad5	459	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
emilmont	40:976df7c37ad5	460	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
emilmont	40:976df7c37ad5	461
emilmont	40:976df7c37ad5	462	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
emilmont	40:976df7c37ad5	463	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
emilmont	40:976df7c37ad5	464
emilmont	40:976df7c37ad5	465	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
emilmont	40:976df7c37ad5	466	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
emilmont	40:976df7c37ad5	467
emilmont	40:976df7c37ad5	468	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
emilmont	40:976df7c37ad5	469	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
emilmont	40:976df7c37ad5	470
emilmont	40:976df7c37ad5	471	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
emilmont	40:976df7c37ad5	472	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
emilmont	40:976df7c37ad5	473
emilmont	40:976df7c37ad5	474	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
emilmont	40:976df7c37ad5	475	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
emilmont	40:976df7c37ad5	476
emilmont	40:976df7c37ad5	477	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
emilmont	40:976df7c37ad5	478	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
emilmont	40:976df7c37ad5	479
emilmont	40:976df7c37ad5	480	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
emilmont	40:976df7c37ad5	481	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
emilmont	40:976df7c37ad5	482
emilmont	40:976df7c37ad5	483	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
emilmont	40:976df7c37ad5	484	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
emilmont	40:976df7c37ad5	485
emilmont	40:976df7c37ad5	486	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
emilmont	40:976df7c37ad5	487	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
emilmont	40:976df7c37ad5	488
emilmont	40:976df7c37ad5	489	/* SCB Configurable Fault Status Registers Definitions */
emilmont	40:976df7c37ad5	490	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
emilmont	40:976df7c37ad5	491	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
emilmont	40:976df7c37ad5	492
emilmont	40:976df7c37ad5	493	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
emilmont	40:976df7c37ad5	494	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
emilmont	40:976df7c37ad5	495
emilmont	40:976df7c37ad5	496	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
emilmont	40:976df7c37ad5	497	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
emilmont	40:976df7c37ad5	498
emilmont	40:976df7c37ad5	499	/* SCB Hard Fault Status Registers Definitions */
emilmont	40:976df7c37ad5	500	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
emilmont	40:976df7c37ad5	501	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
emilmont	40:976df7c37ad5	502
emilmont	40:976df7c37ad5	503	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
emilmont	40:976df7c37ad5	504	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
emilmont	40:976df7c37ad5	505
emilmont	40:976df7c37ad5	506	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
emilmont	40:976df7c37ad5	507	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
emilmont	40:976df7c37ad5	508
emilmont	40:976df7c37ad5	509	/* SCB Debug Fault Status Register Definitions */
emilmont	40:976df7c37ad5	510	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
emilmont	40:976df7c37ad5	511	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
emilmont	40:976df7c37ad5	512
emilmont	40:976df7c37ad5	513	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
emilmont	40:976df7c37ad5	514	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
emilmont	40:976df7c37ad5	515
emilmont	40:976df7c37ad5	516	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
emilmont	40:976df7c37ad5	517	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
emilmont	40:976df7c37ad5	518
emilmont	40:976df7c37ad5	519	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
emilmont	40:976df7c37ad5	520	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
emilmont	40:976df7c37ad5	521
emilmont	40:976df7c37ad5	522	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
emilmont	40:976df7c37ad5	523	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
emilmont	40:976df7c37ad5	524
emilmont	40:976df7c37ad5	525	/@} end of group CMSIS_SCB /
emilmont	40:976df7c37ad5	526
emilmont	40:976df7c37ad5	527
emilmont	40:976df7c37ad5	528	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	529	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont	40:976df7c37ad5	530	\brief Type definitions for the System Control and ID Register not in the SCB
emilmont	40:976df7c37ad5	531	@{
emilmont	40:976df7c37ad5	532	*/
emilmont	40:976df7c37ad5	533
emilmont	40:976df7c37ad5	534	/** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont	40:976df7c37ad5	535	*/
emilmont	40:976df7c37ad5	536	typedef struct
emilmont	40:976df7c37ad5	537	{
emilmont	40:976df7c37ad5	538	uint32_t RESERVED0[1];
emilmont	40:976df7c37ad5	539	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
emilmont	40:976df7c37ad5	540	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
emilmont	40:976df7c37ad5	541	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
emilmont	40:976df7c37ad5	542	#else
emilmont	40:976df7c37ad5	543	uint32_t RESERVED1[1];
emilmont	40:976df7c37ad5	544	#endif
emilmont	40:976df7c37ad5	545	} SCnSCB_Type;
emilmont	40:976df7c37ad5	546
emilmont	40:976df7c37ad5	547	/* Interrupt Controller Type Register Definitions */
emilmont	40:976df7c37ad5	548	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
emilmont	40:976df7c37ad5	549	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
emilmont	40:976df7c37ad5	550
emilmont	40:976df7c37ad5	551	/* Auxiliary Control Register Definitions */
emilmont	40:976df7c37ad5	552
emilmont	40:976df7c37ad5	553	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
emilmont	40:976df7c37ad5	554	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
emilmont	40:976df7c37ad5	555
emilmont	40:976df7c37ad5	556	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
emilmont	40:976df7c37ad5	557	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
emilmont	40:976df7c37ad5	558
emilmont	40:976df7c37ad5	559	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
emilmont	40:976df7c37ad5	560	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
emilmont	40:976df7c37ad5	561
emilmont	40:976df7c37ad5	562	/@} end of group CMSIS_SCnotSCB /
emilmont	40:976df7c37ad5	563
emilmont	40:976df7c37ad5	564
emilmont	40:976df7c37ad5	565	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	566	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont	40:976df7c37ad5	567	\brief Type definitions for the System Timer Registers.
emilmont	40:976df7c37ad5	568	@{
emilmont	40:976df7c37ad5	569	*/
emilmont	40:976df7c37ad5	570
emilmont	40:976df7c37ad5	571	/** \brief Structure type to access the System Timer (SysTick).
emilmont	40:976df7c37ad5	572	*/
emilmont	40:976df7c37ad5	573	typedef struct
emilmont	40:976df7c37ad5	574	{
emilmont	40:976df7c37ad5	575	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
emilmont	40:976df7c37ad5	576	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
emilmont	40:976df7c37ad5	577	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
emilmont	40:976df7c37ad5	578	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
emilmont	40:976df7c37ad5	579	} SysTick_Type;
emilmont	40:976df7c37ad5	580
emilmont	40:976df7c37ad5	581	/* SysTick Control / Status Register Definitions */
emilmont	40:976df7c37ad5	582	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
emilmont	40:976df7c37ad5	583	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
emilmont	40:976df7c37ad5	584
emilmont	40:976df7c37ad5	585	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
emilmont	40:976df7c37ad5	586	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
emilmont	40:976df7c37ad5	587
emilmont	40:976df7c37ad5	588	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
emilmont	40:976df7c37ad5	589	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
emilmont	40:976df7c37ad5	590
emilmont	40:976df7c37ad5	591	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
emilmont	40:976df7c37ad5	592	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
emilmont	40:976df7c37ad5	593
emilmont	40:976df7c37ad5	594	/* SysTick Reload Register Definitions */
emilmont	40:976df7c37ad5	595	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
emilmont	40:976df7c37ad5	596	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
emilmont	40:976df7c37ad5	597
emilmont	40:976df7c37ad5	598	/* SysTick Current Register Definitions */
emilmont	40:976df7c37ad5	599	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
emilmont	40:976df7c37ad5	600	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
emilmont	40:976df7c37ad5	601
emilmont	40:976df7c37ad5	602	/* SysTick Calibration Register Definitions */
emilmont	40:976df7c37ad5	603	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
emilmont	40:976df7c37ad5	604	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
emilmont	40:976df7c37ad5	605
emilmont	40:976df7c37ad5	606	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
emilmont	40:976df7c37ad5	607	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
emilmont	40:976df7c37ad5	608
emilmont	40:976df7c37ad5	609	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
emilmont	40:976df7c37ad5	610	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
emilmont	40:976df7c37ad5	611
emilmont	40:976df7c37ad5	612	/@} end of group CMSIS_SysTick /
emilmont	40:976df7c37ad5	613
emilmont	40:976df7c37ad5	614
emilmont	40:976df7c37ad5	615	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	616	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont	40:976df7c37ad5	617	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont	40:976df7c37ad5	618	@{
emilmont	40:976df7c37ad5	619	*/
emilmont	40:976df7c37ad5	620
emilmont	40:976df7c37ad5	621	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont	40:976df7c37ad5	622	*/
emilmont	40:976df7c37ad5	623	typedef struct
emilmont	40:976df7c37ad5	624	{
emilmont	40:976df7c37ad5	625	__O union
emilmont	40:976df7c37ad5	626	{
emilmont	40:976df7c37ad5	627	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
emilmont	40:976df7c37ad5	628	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
emilmont	40:976df7c37ad5	629	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
emilmont	40:976df7c37ad5	630	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
emilmont	40:976df7c37ad5	631	uint32_t RESERVED0[864];
emilmont	40:976df7c37ad5	632	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
emilmont	40:976df7c37ad5	633	uint32_t RESERVED1[15];
emilmont	40:976df7c37ad5	634	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
emilmont	40:976df7c37ad5	635	uint32_t RESERVED2[15];
emilmont	40:976df7c37ad5	636	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
emilmont	40:976df7c37ad5	637	} ITM_Type;
emilmont	40:976df7c37ad5	638
emilmont	40:976df7c37ad5	639	/* ITM Trace Privilege Register Definitions */
emilmont	40:976df7c37ad5	640	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
emilmont	40:976df7c37ad5	641	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
emilmont	40:976df7c37ad5	642
emilmont	40:976df7c37ad5	643	/* ITM Trace Control Register Definitions */
emilmont	40:976df7c37ad5	644	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
emilmont	40:976df7c37ad5	645	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
emilmont	40:976df7c37ad5	646
emilmont	40:976df7c37ad5	647	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
emilmont	40:976df7c37ad5	648	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
emilmont	40:976df7c37ad5	649
emilmont	40:976df7c37ad5	650	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
emilmont	40:976df7c37ad5	651	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
emilmont	40:976df7c37ad5	652
emilmont	40:976df7c37ad5	653	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
emilmont	40:976df7c37ad5	654	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
emilmont	40:976df7c37ad5	655
emilmont	40:976df7c37ad5	656	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
emilmont	40:976df7c37ad5	657	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
emilmont	40:976df7c37ad5	658
emilmont	40:976df7c37ad5	659	#define ITM_TCR_TXENA_Pos 3 /!< ITM TCR: TXENA Position /
emilmont	40:976df7c37ad5	660	#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /!< ITM TCR: TXENA Mask /
emilmont	40:976df7c37ad5	661
emilmont	40:976df7c37ad5	662	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
emilmont	40:976df7c37ad5	663	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
emilmont	40:976df7c37ad5	664
emilmont	40:976df7c37ad5	665	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
emilmont	40:976df7c37ad5	666	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
emilmont	40:976df7c37ad5	667
emilmont	40:976df7c37ad5	668	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
emilmont	40:976df7c37ad5	669	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
emilmont	40:976df7c37ad5	670
emilmont	40:976df7c37ad5	671	/@}/ /* end of group CMSIS_ITM */
emilmont	40:976df7c37ad5	672
emilmont	40:976df7c37ad5	673
emilmont	40:976df7c37ad5	674	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	675	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
emilmont	40:976df7c37ad5	676	\brief Type definitions for the Data Watchpoint and Trace (DWT)
emilmont	40:976df7c37ad5	677	@{
emilmont	40:976df7c37ad5	678	*/
emilmont	40:976df7c37ad5	679
emilmont	40:976df7c37ad5	680	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
emilmont	40:976df7c37ad5	681	*/
emilmont	40:976df7c37ad5	682	typedef struct
emilmont	40:976df7c37ad5	683	{
emilmont	40:976df7c37ad5	684	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
emilmont	40:976df7c37ad5	685	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
emilmont	40:976df7c37ad5	686	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
emilmont	40:976df7c37ad5	687	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
emilmont	40:976df7c37ad5	688	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
emilmont	40:976df7c37ad5	689	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
emilmont	40:976df7c37ad5	690	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
emilmont	40:976df7c37ad5	691	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
emilmont	40:976df7c37ad5	692	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
emilmont	40:976df7c37ad5	693	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
emilmont	40:976df7c37ad5	694	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
emilmont	40:976df7c37ad5	695	uint32_t RESERVED0[1];
emilmont	40:976df7c37ad5	696	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
emilmont	40:976df7c37ad5	697	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
emilmont	40:976df7c37ad5	698	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
emilmont	40:976df7c37ad5	699	uint32_t RESERVED1[1];
emilmont	40:976df7c37ad5	700	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
emilmont	40:976df7c37ad5	701	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
emilmont	40:976df7c37ad5	702	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
emilmont	40:976df7c37ad5	703	uint32_t RESERVED2[1];
emilmont	40:976df7c37ad5	704	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
emilmont	40:976df7c37ad5	705	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
emilmont	40:976df7c37ad5	706	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
emilmont	40:976df7c37ad5	707	} DWT_Type;
emilmont	40:976df7c37ad5	708
emilmont	40:976df7c37ad5	709	/* DWT Control Register Definitions */
emilmont	40:976df7c37ad5	710	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
emilmont	40:976df7c37ad5	711	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
emilmont	40:976df7c37ad5	712
emilmont	40:976df7c37ad5	713	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
emilmont	40:976df7c37ad5	714	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
emilmont	40:976df7c37ad5	715
emilmont	40:976df7c37ad5	716	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
emilmont	40:976df7c37ad5	717	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
emilmont	40:976df7c37ad5	718
emilmont	40:976df7c37ad5	719	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
emilmont	40:976df7c37ad5	720	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
emilmont	40:976df7c37ad5	721
emilmont	40:976df7c37ad5	722	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
emilmont	40:976df7c37ad5	723	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
emilmont	40:976df7c37ad5	724
emilmont	40:976df7c37ad5	725	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
emilmont	40:976df7c37ad5	726	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
emilmont	40:976df7c37ad5	727
emilmont	40:976df7c37ad5	728	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
emilmont	40:976df7c37ad5	729	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
emilmont	40:976df7c37ad5	730
emilmont	40:976df7c37ad5	731	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
emilmont	40:976df7c37ad5	732	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
emilmont	40:976df7c37ad5	733
emilmont	40:976df7c37ad5	734	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
emilmont	40:976df7c37ad5	735	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
emilmont	40:976df7c37ad5	736
emilmont	40:976df7c37ad5	737	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
emilmont	40:976df7c37ad5	738	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
emilmont	40:976df7c37ad5	739
emilmont	40:976df7c37ad5	740	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
emilmont	40:976df7c37ad5	741	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
emilmont	40:976df7c37ad5	742
emilmont	40:976df7c37ad5	743	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
emilmont	40:976df7c37ad5	744	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
emilmont	40:976df7c37ad5	745
emilmont	40:976df7c37ad5	746	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
emilmont	40:976df7c37ad5	747	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
emilmont	40:976df7c37ad5	748
emilmont	40:976df7c37ad5	749	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
emilmont	40:976df7c37ad5	750	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
emilmont	40:976df7c37ad5	751
emilmont	40:976df7c37ad5	752	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
emilmont	40:976df7c37ad5	753	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
emilmont	40:976df7c37ad5	754
emilmont	40:976df7c37ad5	755	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
emilmont	40:976df7c37ad5	756	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
emilmont	40:976df7c37ad5	757
emilmont	40:976df7c37ad5	758	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
emilmont	40:976df7c37ad5	759	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
emilmont	40:976df7c37ad5	760
emilmont	40:976df7c37ad5	761	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
emilmont	40:976df7c37ad5	762	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
emilmont	40:976df7c37ad5	763
emilmont	40:976df7c37ad5	764	/* DWT CPI Count Register Definitions */
emilmont	40:976df7c37ad5	765	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
emilmont	40:976df7c37ad5	766	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
emilmont	40:976df7c37ad5	767
emilmont	40:976df7c37ad5	768	/* DWT Exception Overhead Count Register Definitions */
emilmont	40:976df7c37ad5	769	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
emilmont	40:976df7c37ad5	770	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
emilmont	40:976df7c37ad5	771
emilmont	40:976df7c37ad5	772	/* DWT Sleep Count Register Definitions */
emilmont	40:976df7c37ad5	773	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
emilmont	40:976df7c37ad5	774	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
emilmont	40:976df7c37ad5	775
emilmont	40:976df7c37ad5	776	/* DWT LSU Count Register Definitions */
emilmont	40:976df7c37ad5	777	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
emilmont	40:976df7c37ad5	778	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
emilmont	40:976df7c37ad5	779
emilmont	40:976df7c37ad5	780	/* DWT Folded-instruction Count Register Definitions */
emilmont	40:976df7c37ad5	781	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
emilmont	40:976df7c37ad5	782	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
emilmont	40:976df7c37ad5	783
emilmont	40:976df7c37ad5	784	/* DWT Comparator Mask Register Definitions */
emilmont	40:976df7c37ad5	785	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
emilmont	40:976df7c37ad5	786	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
emilmont	40:976df7c37ad5	787
emilmont	40:976df7c37ad5	788	/* DWT Comparator Function Register Definitions */
emilmont	40:976df7c37ad5	789	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
emilmont	40:976df7c37ad5	790	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
emilmont	40:976df7c37ad5	791
emilmont	40:976df7c37ad5	792	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
emilmont	40:976df7c37ad5	793	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
emilmont	40:976df7c37ad5	794
emilmont	40:976df7c37ad5	795	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
emilmont	40:976df7c37ad5	796	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
emilmont	40:976df7c37ad5	797
emilmont	40:976df7c37ad5	798	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
emilmont	40:976df7c37ad5	799	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
emilmont	40:976df7c37ad5	800
emilmont	40:976df7c37ad5	801	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
emilmont	40:976df7c37ad5	802	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
emilmont	40:976df7c37ad5	803
emilmont	40:976df7c37ad5	804	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
emilmont	40:976df7c37ad5	805	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
emilmont	40:976df7c37ad5	806
emilmont	40:976df7c37ad5	807	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
emilmont	40:976df7c37ad5	808	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
emilmont	40:976df7c37ad5	809
emilmont	40:976df7c37ad5	810	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
emilmont	40:976df7c37ad5	811	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
emilmont	40:976df7c37ad5	812
emilmont	40:976df7c37ad5	813	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
emilmont	40:976df7c37ad5	814	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
emilmont	40:976df7c37ad5	815
emilmont	40:976df7c37ad5	816	/@}/ /* end of group CMSIS_DWT */
emilmont	40:976df7c37ad5	817
emilmont	40:976df7c37ad5	818
emilmont	40:976df7c37ad5	819	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	820	\defgroup CMSIS_TPI Trace Port Interface (TPI)
emilmont	40:976df7c37ad5	821	\brief Type definitions for the Trace Port Interface (TPI)
emilmont	40:976df7c37ad5	822	@{
emilmont	40:976df7c37ad5	823	*/
emilmont	40:976df7c37ad5	824
emilmont	40:976df7c37ad5	825	/** \brief Structure type to access the Trace Port Interface Register (TPI).
emilmont	40:976df7c37ad5	826	*/
emilmont	40:976df7c37ad5	827	typedef struct
emilmont	40:976df7c37ad5	828	{
emilmont	40:976df7c37ad5	829	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
emilmont	40:976df7c37ad5	830	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
emilmont	40:976df7c37ad5	831	uint32_t RESERVED0[2];
emilmont	40:976df7c37ad5	832	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
emilmont	40:976df7c37ad5	833	uint32_t RESERVED1[55];
emilmont	40:976df7c37ad5	834	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
emilmont	40:976df7c37ad5	835	uint32_t RESERVED2[131];
emilmont	40:976df7c37ad5	836	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
emilmont	40:976df7c37ad5	837	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
emilmont	40:976df7c37ad5	838	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
emilmont	40:976df7c37ad5	839	uint32_t RESERVED3[759];
emilmont	40:976df7c37ad5	840	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
emilmont	40:976df7c37ad5	841	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
emilmont	40:976df7c37ad5	842	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
emilmont	40:976df7c37ad5	843	uint32_t RESERVED4[1];
emilmont	40:976df7c37ad5	844	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
emilmont	40:976df7c37ad5	845	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
emilmont	40:976df7c37ad5	846	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
emilmont	40:976df7c37ad5	847	uint32_t RESERVED5[39];
emilmont	40:976df7c37ad5	848	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
emilmont	40:976df7c37ad5	849	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
emilmont	40:976df7c37ad5	850	uint32_t RESERVED7[8];
emilmont	40:976df7c37ad5	851	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
emilmont	40:976df7c37ad5	852	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
emilmont	40:976df7c37ad5	853	} TPI_Type;
emilmont	40:976df7c37ad5	854
emilmont	40:976df7c37ad5	855	/* TPI Asynchronous Clock Prescaler Register Definitions */
emilmont	40:976df7c37ad5	856	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
emilmont	40:976df7c37ad5	857	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
emilmont	40:976df7c37ad5	858
emilmont	40:976df7c37ad5	859	/* TPI Selected Pin Protocol Register Definitions */
emilmont	40:976df7c37ad5	860	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
emilmont	40:976df7c37ad5	861	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
emilmont	40:976df7c37ad5	862
emilmont	40:976df7c37ad5	863	/* TPI Formatter and Flush Status Register Definitions */
emilmont	40:976df7c37ad5	864	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
emilmont	40:976df7c37ad5	865	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
emilmont	40:976df7c37ad5	866
emilmont	40:976df7c37ad5	867	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
emilmont	40:976df7c37ad5	868	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
emilmont	40:976df7c37ad5	869
emilmont	40:976df7c37ad5	870	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
emilmont	40:976df7c37ad5	871	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
emilmont	40:976df7c37ad5	872
emilmont	40:976df7c37ad5	873	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
emilmont	40:976df7c37ad5	874	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
emilmont	40:976df7c37ad5	875
emilmont	40:976df7c37ad5	876	/* TPI Formatter and Flush Control Register Definitions */
emilmont	40:976df7c37ad5	877	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
emilmont	40:976df7c37ad5	878	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
emilmont	40:976df7c37ad5	879
emilmont	40:976df7c37ad5	880	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
emilmont	40:976df7c37ad5	881	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
emilmont	40:976df7c37ad5	882
emilmont	40:976df7c37ad5	883	/* TPI TRIGGER Register Definitions */
emilmont	40:976df7c37ad5	884	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
emilmont	40:976df7c37ad5	885	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
emilmont	40:976df7c37ad5	886
emilmont	40:976df7c37ad5	887	/* TPI Integration ETM Data Register Definitions (FIFO0) */
emilmont	40:976df7c37ad5	888	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
emilmont	40:976df7c37ad5	889	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
emilmont	40:976df7c37ad5	890
emilmont	40:976df7c37ad5	891	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
emilmont	40:976df7c37ad5	892	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
emilmont	40:976df7c37ad5	893
emilmont	40:976df7c37ad5	894	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
emilmont	40:976df7c37ad5	895	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
emilmont	40:976df7c37ad5	896
emilmont	40:976df7c37ad5	897	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
emilmont	40:976df7c37ad5	898	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
emilmont	40:976df7c37ad5	899
emilmont	40:976df7c37ad5	900	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
emilmont	40:976df7c37ad5	901	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
emilmont	40:976df7c37ad5	902
emilmont	40:976df7c37ad5	903	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
emilmont	40:976df7c37ad5	904	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
emilmont	40:976df7c37ad5	905
emilmont	40:976df7c37ad5	906	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
emilmont	40:976df7c37ad5	907	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
emilmont	40:976df7c37ad5	908
emilmont	40:976df7c37ad5	909	/* TPI ITATBCTR2 Register Definitions */
emilmont	40:976df7c37ad5	910	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
emilmont	40:976df7c37ad5	911	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
emilmont	40:976df7c37ad5	912
emilmont	40:976df7c37ad5	913	/* TPI Integration ITM Data Register Definitions (FIFO1) */
emilmont	40:976df7c37ad5	914	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
emilmont	40:976df7c37ad5	915	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
emilmont	40:976df7c37ad5	916
emilmont	40:976df7c37ad5	917	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
emilmont	40:976df7c37ad5	918	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
emilmont	40:976df7c37ad5	919
emilmont	40:976df7c37ad5	920	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
emilmont	40:976df7c37ad5	921	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
emilmont	40:976df7c37ad5	922
emilmont	40:976df7c37ad5	923	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
emilmont	40:976df7c37ad5	924	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
emilmont	40:976df7c37ad5	925
emilmont	40:976df7c37ad5	926	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
emilmont	40:976df7c37ad5	927	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
emilmont	40:976df7c37ad5	928
emilmont	40:976df7c37ad5	929	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
emilmont	40:976df7c37ad5	930	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
emilmont	40:976df7c37ad5	931
emilmont	40:976df7c37ad5	932	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
emilmont	40:976df7c37ad5	933	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
emilmont	40:976df7c37ad5	934
emilmont	40:976df7c37ad5	935	/* TPI ITATBCTR0 Register Definitions */
emilmont	40:976df7c37ad5	936	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
emilmont	40:976df7c37ad5	937	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
emilmont	40:976df7c37ad5	938
emilmont	40:976df7c37ad5	939	/* TPI Integration Mode Control Register Definitions */
emilmont	40:976df7c37ad5	940	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
emilmont	40:976df7c37ad5	941	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
emilmont	40:976df7c37ad5	942
emilmont	40:976df7c37ad5	943	/* TPI DEVID Register Definitions */
emilmont	40:976df7c37ad5	944	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
emilmont	40:976df7c37ad5	945	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
emilmont	40:976df7c37ad5	946
emilmont	40:976df7c37ad5	947	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
emilmont	40:976df7c37ad5	948	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
emilmont	40:976df7c37ad5	949
emilmont	40:976df7c37ad5	950	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
emilmont	40:976df7c37ad5	951	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
emilmont	40:976df7c37ad5	952
emilmont	40:976df7c37ad5	953	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
emilmont	40:976df7c37ad5	954	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
emilmont	40:976df7c37ad5	955
emilmont	40:976df7c37ad5	956	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
emilmont	40:976df7c37ad5	957	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
emilmont	40:976df7c37ad5	958
emilmont	40:976df7c37ad5	959	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
emilmont	40:976df7c37ad5	960	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
emilmont	40:976df7c37ad5	961
emilmont	40:976df7c37ad5	962	/* TPI DEVTYPE Register Definitions */
emilmont	40:976df7c37ad5	963	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
emilmont	40:976df7c37ad5	964	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
emilmont	40:976df7c37ad5	965
emilmont	40:976df7c37ad5	966	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
emilmont	40:976df7c37ad5	967	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
emilmont	40:976df7c37ad5	968
emilmont	40:976df7c37ad5	969	/@}/ /* end of group CMSIS_TPI */
emilmont	40:976df7c37ad5	970
emilmont	40:976df7c37ad5	971
emilmont	40:976df7c37ad5	972	#if (__MPU_PRESENT == 1)
emilmont	40:976df7c37ad5	973	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	974	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont	40:976df7c37ad5	975	\brief Type definitions for the Memory Protection Unit (MPU)
emilmont	40:976df7c37ad5	976	@{
emilmont	40:976df7c37ad5	977	*/
emilmont	40:976df7c37ad5	978
emilmont	40:976df7c37ad5	979	/** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont	40:976df7c37ad5	980	*/
emilmont	40:976df7c37ad5	981	typedef struct
emilmont	40:976df7c37ad5	982	{
emilmont	40:976df7c37ad5	983	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
emilmont	40:976df7c37ad5	984	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
emilmont	40:976df7c37ad5	985	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
emilmont	40:976df7c37ad5	986	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
emilmont	40:976df7c37ad5	987	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
emilmont	40:976df7c37ad5	988	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
emilmont	40:976df7c37ad5	989	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
emilmont	40:976df7c37ad5	990	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
emilmont	40:976df7c37ad5	991	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
emilmont	40:976df7c37ad5	992	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
emilmont	40:976df7c37ad5	993	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
emilmont	40:976df7c37ad5	994	} MPU_Type;
emilmont	40:976df7c37ad5	995
emilmont	40:976df7c37ad5	996	/* MPU Type Register */
emilmont	40:976df7c37ad5	997	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
emilmont	40:976df7c37ad5	998	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
emilmont	40:976df7c37ad5	999
emilmont	40:976df7c37ad5	1000	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
emilmont	40:976df7c37ad5	1001	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
emilmont	40:976df7c37ad5	1002
emilmont	40:976df7c37ad5	1003	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
emilmont	40:976df7c37ad5	1004	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
emilmont	40:976df7c37ad5	1005
emilmont	40:976df7c37ad5	1006	/* MPU Control Register */
emilmont	40:976df7c37ad5	1007	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
emilmont	40:976df7c37ad5	1008	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
emilmont	40:976df7c37ad5	1009
emilmont	40:976df7c37ad5	1010	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
emilmont	40:976df7c37ad5	1011	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
emilmont	40:976df7c37ad5	1012
emilmont	40:976df7c37ad5	1013	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
emilmont	40:976df7c37ad5	1014	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
emilmont	40:976df7c37ad5	1015
emilmont	40:976df7c37ad5	1016	/* MPU Region Number Register */
emilmont	40:976df7c37ad5	1017	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
emilmont	40:976df7c37ad5	1018	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
emilmont	40:976df7c37ad5	1019
emilmont	40:976df7c37ad5	1020	/* MPU Region Base Address Register */
emilmont	40:976df7c37ad5	1021	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
emilmont	40:976df7c37ad5	1022	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
emilmont	40:976df7c37ad5	1023
emilmont	40:976df7c37ad5	1024	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
emilmont	40:976df7c37ad5	1025	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
emilmont	40:976df7c37ad5	1026
emilmont	40:976df7c37ad5	1027	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
emilmont	40:976df7c37ad5	1028	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
emilmont	40:976df7c37ad5	1029
emilmont	40:976df7c37ad5	1030	/* MPU Region Attribute and Size Register */
emilmont	40:976df7c37ad5	1031	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
emilmont	40:976df7c37ad5	1032	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
emilmont	40:976df7c37ad5	1033
emilmont	40:976df7c37ad5	1034	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
emilmont	40:976df7c37ad5	1035	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
emilmont	40:976df7c37ad5	1036
emilmont	40:976df7c37ad5	1037	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
emilmont	40:976df7c37ad5	1038	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
emilmont	40:976df7c37ad5	1039
emilmont	40:976df7c37ad5	1040	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
emilmont	40:976df7c37ad5	1041	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
emilmont	40:976df7c37ad5	1042
emilmont	40:976df7c37ad5	1043	/@} end of group CMSIS_MPU /
emilmont	40:976df7c37ad5	1044	#endif
emilmont	40:976df7c37ad5	1045
emilmont	40:976df7c37ad5	1046
emilmont	40:976df7c37ad5	1047	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	1048	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont	40:976df7c37ad5	1049	\brief Type definitions for the Core Debug Registers
emilmont	40:976df7c37ad5	1050	@{
emilmont	40:976df7c37ad5	1051	*/
emilmont	40:976df7c37ad5	1052
emilmont	40:976df7c37ad5	1053	/** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont	40:976df7c37ad5	1054	*/
emilmont	40:976df7c37ad5	1055	typedef struct
emilmont	40:976df7c37ad5	1056	{
emilmont	40:976df7c37ad5	1057	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
emilmont	40:976df7c37ad5	1058	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
emilmont	40:976df7c37ad5	1059	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
emilmont	40:976df7c37ad5	1060	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
emilmont	40:976df7c37ad5	1061	} CoreDebug_Type;
emilmont	40:976df7c37ad5	1062
emilmont	40:976df7c37ad5	1063	/* Debug Halting Control and Status Register */
emilmont	40:976df7c37ad5	1064	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
emilmont	40:976df7c37ad5	1065	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
emilmont	40:976df7c37ad5	1066
emilmont	40:976df7c37ad5	1067	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
emilmont	40:976df7c37ad5	1068	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
emilmont	40:976df7c37ad5	1069
emilmont	40:976df7c37ad5	1070	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
emilmont	40:976df7c37ad5	1071	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
emilmont	40:976df7c37ad5	1072
emilmont	40:976df7c37ad5	1073	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
emilmont	40:976df7c37ad5	1074	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
emilmont	40:976df7c37ad5	1075
emilmont	40:976df7c37ad5	1076	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
emilmont	40:976df7c37ad5	1077	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
emilmont	40:976df7c37ad5	1078
emilmont	40:976df7c37ad5	1079	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
emilmont	40:976df7c37ad5	1080	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
emilmont	40:976df7c37ad5	1081
emilmont	40:976df7c37ad5	1082	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
emilmont	40:976df7c37ad5	1083	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
emilmont	40:976df7c37ad5	1084
emilmont	40:976df7c37ad5	1085	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
emilmont	40:976df7c37ad5	1086	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
emilmont	40:976df7c37ad5	1087
emilmont	40:976df7c37ad5	1088	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
emilmont	40:976df7c37ad5	1089	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
emilmont	40:976df7c37ad5	1090
emilmont	40:976df7c37ad5	1091	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
emilmont	40:976df7c37ad5	1092	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
emilmont	40:976df7c37ad5	1093
emilmont	40:976df7c37ad5	1094	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
emilmont	40:976df7c37ad5	1095	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
emilmont	40:976df7c37ad5	1096
emilmont	40:976df7c37ad5	1097	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
emilmont	40:976df7c37ad5	1098	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
emilmont	40:976df7c37ad5	1099
emilmont	40:976df7c37ad5	1100	/* Debug Core Register Selector Register */
emilmont	40:976df7c37ad5	1101	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
emilmont	40:976df7c37ad5	1102	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
emilmont	40:976df7c37ad5	1103
emilmont	40:976df7c37ad5	1104	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
emilmont	40:976df7c37ad5	1105	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
emilmont	40:976df7c37ad5	1106
emilmont	40:976df7c37ad5	1107	/* Debug Exception and Monitor Control Register */
emilmont	40:976df7c37ad5	1108	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
emilmont	40:976df7c37ad5	1109	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
emilmont	40:976df7c37ad5	1110
emilmont	40:976df7c37ad5	1111	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
emilmont	40:976df7c37ad5	1112	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
emilmont	40:976df7c37ad5	1113
emilmont	40:976df7c37ad5	1114	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
emilmont	40:976df7c37ad5	1115	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
emilmont	40:976df7c37ad5	1116
emilmont	40:976df7c37ad5	1117	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
emilmont	40:976df7c37ad5	1118	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
emilmont	40:976df7c37ad5	1119
emilmont	40:976df7c37ad5	1120	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
emilmont	40:976df7c37ad5	1121	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
emilmont	40:976df7c37ad5	1122
emilmont	40:976df7c37ad5	1123	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
emilmont	40:976df7c37ad5	1124	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
emilmont	40:976df7c37ad5	1125
emilmont	40:976df7c37ad5	1126	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
emilmont	40:976df7c37ad5	1127	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
emilmont	40:976df7c37ad5	1128
emilmont	40:976df7c37ad5	1129	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
emilmont	40:976df7c37ad5	1130	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
emilmont	40:976df7c37ad5	1131
emilmont	40:976df7c37ad5	1132	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
emilmont	40:976df7c37ad5	1133	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
emilmont	40:976df7c37ad5	1134
emilmont	40:976df7c37ad5	1135	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
emilmont	40:976df7c37ad5	1136	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
emilmont	40:976df7c37ad5	1137
emilmont	40:976df7c37ad5	1138	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
emilmont	40:976df7c37ad5	1139	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
emilmont	40:976df7c37ad5	1140
emilmont	40:976df7c37ad5	1141	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
emilmont	40:976df7c37ad5	1142	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
emilmont	40:976df7c37ad5	1143
emilmont	40:976df7c37ad5	1144	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
emilmont	40:976df7c37ad5	1145	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
emilmont	40:976df7c37ad5	1146
emilmont	40:976df7c37ad5	1147	/@} end of group CMSIS_CoreDebug /
emilmont	40:976df7c37ad5	1148
emilmont	40:976df7c37ad5	1149
emilmont	40:976df7c37ad5	1150	/** \ingroup CMSIS_core_register
emilmont	40:976df7c37ad5	1151	\defgroup CMSIS_core_base Core Definitions
emilmont	40:976df7c37ad5	1152	\brief Definitions for base addresses, unions, and structures.
emilmont	40:976df7c37ad5	1153	@{
emilmont	40:976df7c37ad5	1154	*/
emilmont	40:976df7c37ad5	1155
emilmont	40:976df7c37ad5	1156	/* Memory mapping of Cortex-M3 Hardware */
emilmont	40:976df7c37ad5	1157	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
emilmont	40:976df7c37ad5	1158	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
emilmont	40:976df7c37ad5	1159	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
emilmont	40:976df7c37ad5	1160	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
emilmont	40:976df7c37ad5	1161	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
emilmont	40:976df7c37ad5	1162	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
emilmont	40:976df7c37ad5	1163	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
emilmont	40:976df7c37ad5	1164	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
emilmont	40:976df7c37ad5	1165
emilmont	40:976df7c37ad5	1166	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
emilmont	40:976df7c37ad5	1167	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
emilmont	40:976df7c37ad5	1168	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
emilmont	40:976df7c37ad5	1169	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
emilmont	40:976df7c37ad5	1170	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
emilmont	40:976df7c37ad5	1171	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
emilmont	40:976df7c37ad5	1172	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
emilmont	40:976df7c37ad5	1173	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
emilmont	40:976df7c37ad5	1174
emilmont	40:976df7c37ad5	1175	#if (__MPU_PRESENT == 1)
emilmont	40:976df7c37ad5	1176	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
emilmont	40:976df7c37ad5	1177	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
emilmont	40:976df7c37ad5	1178	#endif
emilmont	40:976df7c37ad5	1179
emilmont	40:976df7c37ad5	1180	/@} /
emilmont	40:976df7c37ad5	1181
emilmont	40:976df7c37ad5	1182
emilmont	40:976df7c37ad5	1183
emilmont	40:976df7c37ad5	1184	/*******************************************************************************
emilmont	40:976df7c37ad5	1185	* Hardware Abstraction Layer
emilmont	40:976df7c37ad5	1186	Core Function Interface contains:
emilmont	40:976df7c37ad5	1187	- Core NVIC Functions
emilmont	40:976df7c37ad5	1188	- Core SysTick Functions
emilmont	40:976df7c37ad5	1189	- Core Debug Functions
emilmont	40:976df7c37ad5	1190	- Core Register Access Functions
emilmont	40:976df7c37ad5	1191	******************************************************************************/
emilmont	40:976df7c37ad5	1192	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont	40:976df7c37ad5	1193	*/
emilmont	40:976df7c37ad5	1194
emilmont	40:976df7c37ad5	1195
emilmont	40:976df7c37ad5	1196
emilmont	40:976df7c37ad5	1197	/* ########################## NVIC functions #################################### */
emilmont	40:976df7c37ad5	1198	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	40:976df7c37ad5	1199	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont	40:976df7c37ad5	1200	\brief Functions that manage interrupts and exceptions via the NVIC.
emilmont	40:976df7c37ad5	1201	@{
emilmont	40:976df7c37ad5	1202	*/
emilmont	40:976df7c37ad5	1203
emilmont	40:976df7c37ad5	1204	/** \brief Set Priority Grouping
emilmont	40:976df7c37ad5	1205
emilmont	40:976df7c37ad5	1206	The function sets the priority grouping field using the required unlock sequence.
emilmont	40:976df7c37ad5	1207	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont	40:976df7c37ad5	1208	Only values from 0..7 are used.
emilmont	40:976df7c37ad5	1209	In case of a conflict between priority grouping and available
emilmont	40:976df7c37ad5	1210	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont	40:976df7c37ad5	1211
emilmont	40:976df7c37ad5	1212	\param [in] PriorityGroup Priority grouping field.
emilmont	40:976df7c37ad5	1213	*/
emilmont	40:976df7c37ad5	1214	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont	40:976df7c37ad5	1215	{
emilmont	40:976df7c37ad5	1216	uint32_t reg_value;
emilmont	40:976df7c37ad5	1217	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
emilmont	40:976df7c37ad5	1218
emilmont	40:976df7c37ad5	1219	reg_value = SCB->AIRCR; /* read old register configuration */
emilmont	40:976df7c37ad5	1220	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
emilmont	40:976df7c37ad5	1221	reg_value = (reg_value \|
emilmont	40:976df7c37ad5	1222	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
emilmont	40:976df7c37ad5	1223	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
emilmont	40:976df7c37ad5	1224	SCB->AIRCR = reg_value;
emilmont	40:976df7c37ad5	1225	}
emilmont	40:976df7c37ad5	1226
emilmont	40:976df7c37ad5	1227
emilmont	40:976df7c37ad5	1228	/** \brief Get Priority Grouping
emilmont	40:976df7c37ad5	1229
emilmont	40:976df7c37ad5	1230	The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont	40:976df7c37ad5	1231
emilmont	40:976df7c37ad5	1232	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont	40:976df7c37ad5	1233	*/
emilmont	40:976df7c37ad5	1234	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
emilmont	40:976df7c37ad5	1235	{
emilmont	40:976df7c37ad5	1236	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
emilmont	40:976df7c37ad5	1237	}
emilmont	40:976df7c37ad5	1238
emilmont	40:976df7c37ad5	1239
emilmont	40:976df7c37ad5	1240	/** \brief Enable External Interrupt
emilmont	40:976df7c37ad5	1241
emilmont	40:976df7c37ad5	1242	The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont	40:976df7c37ad5	1243
emilmont	40:976df7c37ad5	1244	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	40:976df7c37ad5	1245	*/
emilmont	40:976df7c37ad5	1246	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont	40:976df7c37ad5	1247	{
emilmont	40:976df7c37ad5	1248	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
emilmont	40:976df7c37ad5	1249	}
emilmont	40:976df7c37ad5	1250
emilmont	40:976df7c37ad5	1251
emilmont	40:976df7c37ad5	1252	/** \brief Disable External Interrupt
emilmont	40:976df7c37ad5	1253
emilmont	40:976df7c37ad5	1254	The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont	40:976df7c37ad5	1255
emilmont	40:976df7c37ad5	1256	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	40:976df7c37ad5	1257	*/
emilmont	40:976df7c37ad5	1258	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont	40:976df7c37ad5	1259	{
emilmont	40:976df7c37ad5	1260	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
emilmont	40:976df7c37ad5	1261	}
emilmont	40:976df7c37ad5	1262
emilmont	40:976df7c37ad5	1263
emilmont	40:976df7c37ad5	1264	/** \brief Get Pending Interrupt
emilmont	40:976df7c37ad5	1265
emilmont	40:976df7c37ad5	1266	The function reads the pending register in the NVIC and returns the pending bit
emilmont	40:976df7c37ad5	1267	for the specified interrupt.
emilmont	40:976df7c37ad5	1268
emilmont	40:976df7c37ad5	1269	\param [in] IRQn Interrupt number.
emilmont	40:976df7c37ad5	1270
emilmont	40:976df7c37ad5	1271	\return 0 Interrupt status is not pending.
emilmont	40:976df7c37ad5	1272	\return 1 Interrupt status is pending.
emilmont	40:976df7c37ad5	1273	*/
emilmont	40:976df7c37ad5	1274	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont	40:976df7c37ad5	1275	{
emilmont	40:976df7c37ad5	1276	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
emilmont	40:976df7c37ad5	1277	}
emilmont	40:976df7c37ad5	1278
emilmont	40:976df7c37ad5	1279
emilmont	40:976df7c37ad5	1280	/** \brief Set Pending Interrupt
emilmont	40:976df7c37ad5	1281
emilmont	40:976df7c37ad5	1282	The function sets the pending bit of an external interrupt.
emilmont	40:976df7c37ad5	1283
emilmont	40:976df7c37ad5	1284	\param [in] IRQn Interrupt number. Value cannot be negative.
emilmont	40:976df7c37ad5	1285	*/
emilmont	40:976df7c37ad5	1286	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont	40:976df7c37ad5	1287	{
emilmont	40:976df7c37ad5	1288	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
emilmont	40:976df7c37ad5	1289	}
emilmont	40:976df7c37ad5	1290
emilmont	40:976df7c37ad5	1291
emilmont	40:976df7c37ad5	1292	/** \brief Clear Pending Interrupt
emilmont	40:976df7c37ad5	1293
emilmont	40:976df7c37ad5	1294	The function clears the pending bit of an external interrupt.
emilmont	40:976df7c37ad5	1295
emilmont	40:976df7c37ad5	1296	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	40:976df7c37ad5	1297	*/
emilmont	40:976df7c37ad5	1298	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont	40:976df7c37ad5	1299	{
emilmont	40:976df7c37ad5	1300	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont	40:976df7c37ad5	1301	}
emilmont	40:976df7c37ad5	1302
emilmont	40:976df7c37ad5	1303
emilmont	40:976df7c37ad5	1304	/** \brief Get Active Interrupt
emilmont	40:976df7c37ad5	1305
emilmont	40:976df7c37ad5	1306	The function reads the active register in NVIC and returns the active bit.
emilmont	40:976df7c37ad5	1307
emilmont	40:976df7c37ad5	1308	\param [in] IRQn Interrupt number.
emilmont	40:976df7c37ad5	1309
emilmont	40:976df7c37ad5	1310	\return 0 Interrupt status is not active.
emilmont	40:976df7c37ad5	1311	\return 1 Interrupt status is active.
emilmont	40:976df7c37ad5	1312	*/
emilmont	40:976df7c37ad5	1313	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
emilmont	40:976df7c37ad5	1314	{
emilmont	40:976df7c37ad5	1315	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
emilmont	40:976df7c37ad5	1316	}
emilmont	40:976df7c37ad5	1317
emilmont	40:976df7c37ad5	1318
emilmont	40:976df7c37ad5	1319	/** \brief Set Interrupt Priority
emilmont	40:976df7c37ad5	1320
emilmont	40:976df7c37ad5	1321	The function sets the priority of an interrupt.
emilmont	40:976df7c37ad5	1322
emilmont	40:976df7c37ad5	1323	\note The priority cannot be set for every core interrupt.
emilmont	40:976df7c37ad5	1324
emilmont	40:976df7c37ad5	1325	\param [in] IRQn Interrupt number.
emilmont	40:976df7c37ad5	1326	\param [in] priority Priority to set.
emilmont	40:976df7c37ad5	1327	*/
emilmont	40:976df7c37ad5	1328	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont	40:976df7c37ad5	1329	{
emilmont	40:976df7c37ad5	1330	if(IRQn < 0) {
emilmont	40:976df7c37ad5	1331	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
emilmont	40:976df7c37ad5	1332	else {
emilmont	40:976df7c37ad5	1333	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
emilmont	40:976df7c37ad5	1334	}
emilmont	40:976df7c37ad5	1335
emilmont	40:976df7c37ad5	1336
emilmont	40:976df7c37ad5	1337	/** \brief Get Interrupt Priority
emilmont	40:976df7c37ad5	1338
emilmont	40:976df7c37ad5	1339	The function reads the priority of an interrupt. The interrupt
emilmont	40:976df7c37ad5	1340	number can be positive to specify an external (device specific)
emilmont	40:976df7c37ad5	1341	interrupt, or negative to specify an internal (core) interrupt.
emilmont	40:976df7c37ad5	1342
emilmont	40:976df7c37ad5	1343
emilmont	40:976df7c37ad5	1344	\param [in] IRQn Interrupt number.
emilmont	40:976df7c37ad5	1345	\return Interrupt Priority. Value is aligned automatically to the implemented
emilmont	40:976df7c37ad5	1346	priority bits of the microcontroller.
emilmont	40:976df7c37ad5	1347	*/
emilmont	40:976df7c37ad5	1348	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont	40:976df7c37ad5	1349	{
emilmont	40:976df7c37ad5	1350
emilmont	40:976df7c37ad5	1351	if(IRQn < 0) {
emilmont	40:976df7c37ad5	1352	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
emilmont	40:976df7c37ad5	1353	else {
emilmont	40:976df7c37ad5	1354	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont	40:976df7c37ad5	1355	}
emilmont	40:976df7c37ad5	1356
emilmont	40:976df7c37ad5	1357
emilmont	40:976df7c37ad5	1358	/** \brief Encode Priority
emilmont	40:976df7c37ad5	1359
emilmont	40:976df7c37ad5	1360	The function encodes the priority for an interrupt with the given priority group,
emilmont	40:976df7c37ad5	1361	preemptive priority value, and subpriority value.
emilmont	40:976df7c37ad5	1362	In case of a conflict between priority grouping and available
emilmont	40:976df7c37ad5	1363	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
emilmont	40:976df7c37ad5	1364
emilmont	40:976df7c37ad5	1365	\param [in] PriorityGroup Used priority group.
emilmont	40:976df7c37ad5	1366	\param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont	40:976df7c37ad5	1367	\param [in] SubPriority Subpriority value (starting from 0).
emilmont	40:976df7c37ad5	1368	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont	40:976df7c37ad5	1369	*/
emilmont	40:976df7c37ad5	1370	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont	40:976df7c37ad5	1371	{
emilmont	40:976df7c37ad5	1372	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	40:976df7c37ad5	1373	uint32_t PreemptPriorityBits;
emilmont	40:976df7c37ad5	1374	uint32_t SubPriorityBits;
emilmont	40:976df7c37ad5	1375
emilmont	40:976df7c37ad5	1376	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont	40:976df7c37ad5	1377	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont	40:976df7c37ad5	1378
emilmont	40:976df7c37ad5	1379	return (
emilmont	40:976df7c37ad5	1380	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
emilmont	40:976df7c37ad5	1381	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
emilmont	40:976df7c37ad5	1382	);
emilmont	40:976df7c37ad5	1383	}
emilmont	40:976df7c37ad5	1384
emilmont	40:976df7c37ad5	1385
emilmont	40:976df7c37ad5	1386	/** \brief Decode Priority
emilmont	40:976df7c37ad5	1387
emilmont	40:976df7c37ad5	1388	The function decodes an interrupt priority value with a given priority group to
emilmont	40:976df7c37ad5	1389	preemptive priority value and subpriority value.
emilmont	40:976df7c37ad5	1390	In case of a conflict between priority grouping and available
emilmont	40:976df7c37ad5	1391	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
emilmont	40:976df7c37ad5	1392
emilmont	40:976df7c37ad5	1393	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont	40:976df7c37ad5	1394	\param [in] PriorityGroup Used priority group.
emilmont	40:976df7c37ad5	1395	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont	40:976df7c37ad5	1396	\param [out] pSubPriority Subpriority value (starting from 0).
emilmont	40:976df7c37ad5	1397	*/
emilmont	40:976df7c37ad5	1398	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont	40:976df7c37ad5	1399	{
emilmont	40:976df7c37ad5	1400	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	40:976df7c37ad5	1401	uint32_t PreemptPriorityBits;
emilmont	40:976df7c37ad5	1402	uint32_t SubPriorityBits;
emilmont	40:976df7c37ad5	1403
emilmont	40:976df7c37ad5	1404	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont	40:976df7c37ad5	1405	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont	40:976df7c37ad5	1406
emilmont	40:976df7c37ad5	1407	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
emilmont	40:976df7c37ad5	1408	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
emilmont	40:976df7c37ad5	1409	}
emilmont	40:976df7c37ad5	1410
emilmont	40:976df7c37ad5	1411
emilmont	40:976df7c37ad5	1412	/** \brief System Reset
emilmont	40:976df7c37ad5	1413
emilmont	40:976df7c37ad5	1414	The function initiates a system reset request to reset the MCU.
emilmont	40:976df7c37ad5	1415	*/
emilmont	40:976df7c37ad5	1416	__STATIC_INLINE void NVIC_SystemReset(void)
emilmont	40:976df7c37ad5	1417	{
emilmont	40:976df7c37ad5	1418	__DSB(); /* Ensure all outstanding memory accesses included
emilmont	40:976df7c37ad5	1419	buffered write are completed before reset */
emilmont	40:976df7c37ad5	1420	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
emilmont	40:976df7c37ad5	1421	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
emilmont	40:976df7c37ad5	1422	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
emilmont	40:976df7c37ad5	1423	__DSB(); /* Ensure completion of memory access */
emilmont	40:976df7c37ad5	1424	while(1); /* wait until reset */
emilmont	40:976df7c37ad5	1425	}
emilmont	40:976df7c37ad5	1426
emilmont	40:976df7c37ad5	1427	/@} end of CMSIS_Core_NVICFunctions /
emilmont	40:976df7c37ad5	1428
emilmont	40:976df7c37ad5	1429
emilmont	40:976df7c37ad5	1430
emilmont	40:976df7c37ad5	1431	/* ################################## SysTick function ############################################ */
emilmont	40:976df7c37ad5	1432	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	40:976df7c37ad5	1433	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont	40:976df7c37ad5	1434	\brief Functions that configure the System.
emilmont	40:976df7c37ad5	1435	@{
emilmont	40:976df7c37ad5	1436	*/
emilmont	40:976df7c37ad5	1437
emilmont	40:976df7c37ad5	1438	#if (__Vendor_SysTickConfig == 0)
emilmont	40:976df7c37ad5	1439
emilmont	40:976df7c37ad5	1440	/** \brief System Tick Configuration
emilmont	40:976df7c37ad5	1441
emilmont	40:976df7c37ad5	1442	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont	40:976df7c37ad5	1443	Counter is in free running mode to generate periodic interrupts.
emilmont	40:976df7c37ad5	1444
emilmont	40:976df7c37ad5	1445	\param [in] ticks Number of ticks between two interrupts.
emilmont	40:976df7c37ad5	1446
emilmont	40:976df7c37ad5	1447	\return 0 Function succeeded.
emilmont	40:976df7c37ad5	1448	\return 1 Function failed.
emilmont	40:976df7c37ad5	1449
emilmont	40:976df7c37ad5	1450	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont	40:976df7c37ad5	1451	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont	40:976df7c37ad5	1452	must contain a vendor-specific implementation of this function.
emilmont	40:976df7c37ad5	1453
emilmont	40:976df7c37ad5	1454	*/
emilmont	40:976df7c37ad5	1455	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont	40:976df7c37ad5	1456	{
emilmont	40:976df7c37ad5	1457	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont	40:976df7c37ad5	1458
emilmont	40:976df7c37ad5	1459	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
emilmont	40:976df7c37ad5	1460	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont	40:976df7c37ad5	1461	SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont	40:976df7c37ad5	1462	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
emilmont	40:976df7c37ad5	1463	SysTick_CTRL_TICKINT_Msk \|
emilmont	40:976df7c37ad5	1464	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont	40:976df7c37ad5	1465	return (0); /* Function successful */
emilmont	40:976df7c37ad5	1466	}
emilmont	40:976df7c37ad5	1467
emilmont	40:976df7c37ad5	1468	#endif
emilmont	40:976df7c37ad5	1469
emilmont	40:976df7c37ad5	1470	/@} end of CMSIS_Core_SysTickFunctions /
emilmont	40:976df7c37ad5	1471
emilmont	40:976df7c37ad5	1472
emilmont	40:976df7c37ad5	1473
emilmont	40:976df7c37ad5	1474	/* ##################################### Debug In/Output function ########################################### */
emilmont	40:976df7c37ad5	1475	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	40:976df7c37ad5	1476	\defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont	40:976df7c37ad5	1477	\brief Functions that access the ITM debug interface.
emilmont	40:976df7c37ad5	1478	@{
emilmont	40:976df7c37ad5	1479	*/
emilmont	40:976df7c37ad5	1480
emilmont	40:976df7c37ad5	1481	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
emilmont	40:976df7c37ad5	1482	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
emilmont	40:976df7c37ad5	1483
emilmont	40:976df7c37ad5	1484
emilmont	40:976df7c37ad5	1485	/** \brief ITM Send Character
emilmont	40:976df7c37ad5	1486
emilmont	40:976df7c37ad5	1487	The function transmits a character via the ITM channel 0, and
emilmont	40:976df7c37ad5	1488	\li Just returns when no debugger is connected that has booked the output.
emilmont	40:976df7c37ad5	1489	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont	40:976df7c37ad5	1490
emilmont	40:976df7c37ad5	1491	\param [in] ch Character to transmit.
emilmont	40:976df7c37ad5	1492
emilmont	40:976df7c37ad5	1493	\returns Character to transmit.
emilmont	40:976df7c37ad5	1494	*/
emilmont	40:976df7c37ad5	1495	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont	40:976df7c37ad5	1496	{
emilmont	40:976df7c37ad5	1497	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
emilmont	40:976df7c37ad5	1498	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
emilmont	40:976df7c37ad5	1499	{
emilmont	40:976df7c37ad5	1500	while (ITM->PORT[0].u32 == 0);
emilmont	40:976df7c37ad5	1501	ITM->PORT[0].u8 = (uint8_t) ch;
emilmont	40:976df7c37ad5	1502	}
emilmont	40:976df7c37ad5	1503	return (ch);
emilmont	40:976df7c37ad5	1504	}
emilmont	40:976df7c37ad5	1505
emilmont	40:976df7c37ad5	1506
emilmont	40:976df7c37ad5	1507	/** \brief ITM Receive Character
emilmont	40:976df7c37ad5	1508
emilmont	40:976df7c37ad5	1509	The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont	40:976df7c37ad5	1510
emilmont	40:976df7c37ad5	1511	\return Received character.
emilmont	40:976df7c37ad5	1512	\return -1 No character pending.
emilmont	40:976df7c37ad5	1513	*/
emilmont	40:976df7c37ad5	1514	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
emilmont	40:976df7c37ad5	1515	int32_t ch = -1; /* no character available */
emilmont	40:976df7c37ad5	1516
emilmont	40:976df7c37ad5	1517	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont	40:976df7c37ad5	1518	ch = ITM_RxBuffer;
emilmont	40:976df7c37ad5	1519	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont	40:976df7c37ad5	1520	}
emilmont	40:976df7c37ad5	1521
emilmont	40:976df7c37ad5	1522	return (ch);
emilmont	40:976df7c37ad5	1523	}
emilmont	40:976df7c37ad5	1524
emilmont	40:976df7c37ad5	1525
emilmont	40:976df7c37ad5	1526	/** \brief ITM Check Character
emilmont	40:976df7c37ad5	1527
emilmont	40:976df7c37ad5	1528	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont	40:976df7c37ad5	1529
emilmont	40:976df7c37ad5	1530	\return 0 No character available.
emilmont	40:976df7c37ad5	1531	\return 1 Character available.
emilmont	40:976df7c37ad5	1532	*/
emilmont	40:976df7c37ad5	1533	__STATIC_INLINE int32_t ITM_CheckChar (void) {
emilmont	40:976df7c37ad5	1534
emilmont	40:976df7c37ad5	1535	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont	40:976df7c37ad5	1536	return (0); /* no character available */
emilmont	40:976df7c37ad5	1537	} else {
emilmont	40:976df7c37ad5	1538	return (1); /* character available */
emilmont	40:976df7c37ad5	1539	}
emilmont	40:976df7c37ad5	1540	}
emilmont	40:976df7c37ad5	1541
emilmont	40:976df7c37ad5	1542	/@} end of CMSIS_core_DebugFunctions /
emilmont	40:976df7c37ad5	1543
emilmont	40:976df7c37ad5	1544	#endif /* __CORE_CM3_H_DEPENDANT */
emilmont	40:976df7c37ad5	1545
emilmont	40:976df7c37ad5	1546	#endif /* __CMSIS_GENERIC */
emilmont	40:976df7c37ad5	1547
emilmont	40:976df7c37ad5	1548	#ifdef __cplusplus
emilmont	40:976df7c37ad5	1549	}
emilmont	40:976df7c37ad5	1550	#endif

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Type:	Library
Created:	29 Sep 2015
Imports:	2
Forks:	0
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LPC1768/core_cm3.h@40:976df7c37ad5, 2012-06-12 (annotated)

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